Semiconductor device, preparation method and electronic equipment

Abstract

The invention relates to a semiconductor device, a preparation method and electronic equipment. The semiconductor device comprises a substrate, a barrier layer, a compensation layer and a plurality of contact holes, the substrate comprises a gate structure and an active region, the barrier layer covers the top surfaces of the gate structure and the active region, the compensation layer is located on the top surface, away from the gate structure, of the barrier layer, and the contact holes penetrate through the barrier layer and the compensation layer in the direction perpendicular to the top surface of the substrate. A portion of the top surface of the substrate is exposed. A compensation layer is formed on the top surface, far away from a gate structure, of a barrier layer, and the compensation layer can compensate the thickness of the barrier layer on the top surface of the gate structure, so that the thickness of a film layer on the top of the gate structure is equal to that of a film layer on the top surface of an active region, and therefore, under the condition that multiple contact holes are formed, in the process that the contact holes expose the top surface of the active region, the thickness of the active region is reduced. Therefore, the top surface of the gate structure is ensured not to be etched, the problem that the contact resistance in the contact hole is increased due to the height difference caused by etching of the top surface of the gate structure can be avoided, and the electrical property and the reliability of the semiconductor device are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a preparation method and an electronic device. Background Art

[0002] In the process of forming metal contact holes in semiconductors, it is necessary to create through holes in the insulating layer on the wafer and fill them with metal to achieve electrical connections between semiconductor structures at different levels, so that current can be conducted from one level of semiconductor structure to another level of semiconductor structure, thereby realizing complex circuit functions.

[0003] However, in conventional technology, when forming a contact hole, the top of the gate structure will be over-etched, resulting in a groove formed on the top of the gate structure, which in turn causes a height difference on the top of the gate structure, further increasing the contact resistance in the contact hole and reducing the electrical properties and reliability of the semiconductor device. Summary of the invention

[0004] The purpose of the present application is to provide a semiconductor device, a preparation method and an electronic device, which can avoid etching damage to the top of the gate structure in the semiconductor device and the problem of height difference when forming a contact hole in the semiconductor device, thereby improving the electrical properties and reliability of the semiconductor device. To achieve the purpose of the present application, the present application provides the following technical solutions:

[0005] In a first aspect, the present application provides a semiconductor device, comprising:

[0006] a substrate including a gate structure and an active region;

[0007] A barrier layer covering the gate structure and the top surface of the active area;

[0008] A compensation layer, located on a top surface of the barrier layer away from the gate structure;

[0009] A plurality of contact holes penetrate the barrier layer and the compensation layer in a direction perpendicular to the top surface of the substrate and expose a portion of the top surface of the substrate.

[0010] The semiconductor device of the present application includes a substrate, a barrier layer, a compensation layer and a plurality of contact holes, wherein the substrate includes a gate structure and an active area, and the barrier layer covers the top surfaces of the gate structure and the active area, wherein the thickness of the barrier layer on the top surface of the gate structure is less than the thickness of the barrier layer on the top surface of the active area, and by forming a compensation layer on the barrier layer away from the top surface of the gate structure, the compensation layer can compensate for the thickness of the barrier layer on the top surface of the gate structure, so that the thickness of the film layer on the top of the gate structure is equal to the thickness of the film layer on the top surface of the active area, and thus, when forming a plurality of contact holes, in the process of exposing the top surface of the active area through the contact holes, it is ensured that the top surface of the gate structure is not etched, and the height difference on the top surface of the gate structure caused by etching can be avoided, thereby avoiding the problem of increased contact resistance in the contact holes, and improving the electrical properties and reliability of the semiconductor device.

[0011] In one embodiment, the barrier layer includes a first barrier layer, a second barrier layer and a third barrier layer stacked in sequence parallel to the top surface of the substrate, wherein the material of the first barrier layer is different from the material of the second barrier layer; and the material of the second barrier layer is different from the material of the third barrier layer.

[0012] In one of the embodiments, the compensation layer is used to compensate for the height difference formed on the top surface of the gate structure when the barrier layer is etched.

[0013] In one embodiment, the semiconductor device further comprises:

[0014] A dielectric layer covers the barrier layer and the compensation layer.

[0015] In one embodiment, the substrate further comprises:

[0016] A metal silicide layer covers the gate structure and the exposed surface of the active area.

[0017] In a second aspect, the present application further provides an electronic device, including:

[0018] A semiconductor device as described in any of the above.

[0019] The electronic device of the present application comprises any of the semiconductor devices described above, wherein the substrate comprises a gate structure and an active area, and a barrier layer covers the top surfaces of the gate structure and the active area, wherein the thickness of the barrier layer on the top surface of the gate structure is less than the thickness of the barrier layer on the top surface of the active area, and a compensation layer is formed on the barrier layer away from the top surface of the gate structure, so that the thickness of the film layer on the top of the gate structure is equal to the thickness of the film layer on the top surface of the active area, thereby ensuring that the top surface of the gate structure is not etched when the contact holes expose the top surface of the active area during the process of forming multiple contact holes, thereby avoiding the problem of height difference on the top surface of the gate structure caused by etching, thereby causing the contact resistance in the contact holes to increase, and thereby improving the electrical properties and reliability of the semiconductor device.

[0020] In a third aspect, the present application further provides a method for preparing a semiconductor device, comprising:

[0021] Providing a substrate, the substrate comprising a gate structure and an active area;

[0022] forming a barrier layer and a compensation material layer on the top surfaces of the gate structure and the active area, wherein the barrier layer covers the top surfaces of the gate structure and the active area, and the compensation material layer is located on the barrier layer away from the top surface of the gate structure;

[0023] Etching the compensation material layer to form a compensation layer, wherein the compensation layer is located on a top surface of the barrier layer away from the gate structure;

[0024] A plurality of contact holes are formed, wherein the plurality of contact holes penetrate the barrier layer and the compensation layer in a direction perpendicular to the top surface of the substrate and expose a portion of the top surface of the substrate.

[0025] The preparation method of the semiconductor device of the present application includes providing a substrate, the substrate including a gate structure and an active area, and then forming a barrier layer and a compensation material layer on the top surface of the gate structure and the active area, wherein the barrier layer covers the top surface of the gate structure and the active area, and the compensation material layer is located on the top surface of the barrier layer away from the gate structure, and further etching the compensation material layer to form a compensation layer, wherein the compensation layer is located on the top surface of the barrier layer away from the gate structure, and finally forming a plurality of contact holes, wherein the plurality of contact holes penetrate the barrier layer and the compensation layer in a direction perpendicular to the top surface of the substrate and expose a portion of the top surface of the substrate. A barrier layer and a compensation material layer are formed on the top surfaces of the gate structure and the active area, wherein the thickness of the barrier layer on the top surface of the gate structure is less than the thickness of the barrier layer on the top surface of the active area, and the compensation layer is obtained by etching the compensation material layer. The compensation layer can compensate for the thickness of the barrier layer on the top surface of the gate structure, so that the thickness of the film layer on the top of the gate structure is equal to the thickness of the film layer on the top surface of the active area. In the process of forming multiple contact holes, when the contact holes expose the top surface of the active area, it is ensured that the top surface of the gate structure is not etched, and the height difference of the top surface of the gate structure caused by etching, which in turn causes the problem of increased contact resistance in the contact holes, can be avoided, and the electrical properties and reliability of the semiconductor device can be improved.

[0026] In one embodiment, the barrier layer includes a first barrier layer, a second barrier layer and a third barrier layer stacked in sequence parallel to the top surface of the substrate, wherein the material of the first barrier layer is different from the material of the second barrier layer; and the material of the second barrier layer is different from the material of the third barrier layer.

[0027] In one embodiment, after etching the compensation material layer to form the compensation layer and before forming the plurality of contact holes, the method further includes:

[0028] A dielectric layer is formed, wherein the dielectric layer covers the barrier layer and the compensation layer.

[0029] In one embodiment, the substrate further comprises:

[0030] A metal silicide layer covers the gate structure and the exposed surface of the active area. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 is a schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment;

[0033] Figure 2 is a flow chart of a method for preparing a semiconductor device provided in another embodiment;

[0034] Figure 3 is a schematic cross-sectional view of a structure obtained from step S11 to step S12 in a method for preparing a semiconductor device provided in another embodiment;

[0035] Figure 4 is a schematic cross-sectional view of a structure obtained in step S13 of a method for preparing a semiconductor device provided in another embodiment;

[0036] Figure 5 It is a schematic cross-sectional structural diagram of a structure obtained from step S14 to step S15 in a method for preparing a semiconductor device provided in another embodiment.

[0037] Description of Reference Numerals

[0038] 10. Substrate; 101. Gate structure; 102. Active region; 20. Barrier layer; 201. First barrier layer; 202. Second barrier layer; 203. Third barrier layer; 30. Compensation layer; 301. Compensation material layer; 40. Contact hole; 50. Dielectric layer; 60. Metal silicide layer. DETAILED DESCRIPTION

[0039] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0041] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0042] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0043] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0045] In the process of forming metal contact holes in semiconductors, it is necessary to create through holes in the insulating layer on the wafer and fill them with metal to achieve electrical connections between semiconductor structures at different levels, so that current can be conducted from one level of semiconductor structure to another level of semiconductor structure, thereby realizing complex circuit functions.

[0046] However, in conventional technology, the top surface of the gate structure is higher than the top surface of the active area, so that the film thickness on the top surface of the gate structure is smaller than the film thickness on the top of the active area. As a result, when a contact hole is formed, the top of the gate structure will be over-etched, resulting in a groove formed on the top of the gate structure, which will lead to a height difference at the top of the gate structure, further causing the contact resistance in the contact hole to increase, thereby reducing the electrical properties and reliability of the semiconductor device.

[0047] The present application embodiment provides a semiconductor device. Figure 1 The semiconductor device may include: a substrate 10, a barrier layer 20, a compensation layer 30 and contact holes 40. The substrate 10 includes a gate structure 101 and an active area 102, the barrier layer 20 covers the top surfaces of the gate structure 101 and the active area 102, the compensation layer 30 is located on the top surface of the barrier layer 20 away from the gate structure 101, and a plurality of contact holes 40 penetrate the barrier layer 20 and the compensation layer 30 in a direction perpendicular to the top surface of the substrate 10, and expose a portion of the top surface of the substrate 10.

[0048] Exemplarily, the substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate deposited on a silicon germanium wafer.

[0049] Exemplarily, the gate structure 101 may include a gate conductive layer, a gate oxide layer and a gate electrode. The gate conductive layer, the material of the gate conductive layer may include but is not limited to a conductive layer, such as a doped polysilicon gate conductive layer or a metal gate conductive layer, etc., the gate oxide layer may include but is not limited to an oxide layer, such as a silicon dioxide layer, and the gate electrode may include but is not limited to a metal gate electrode.

[0050] Exemplarily, the active region 102 may be a source region or a drain region. It should be noted that, when the active region 102 is a source region, the semiconductor device further includes a source electrode, which covers the top surface of the source region. When the active region 102 is a drain region, the semiconductor device may further include a drain electrode, which is located on the top surface of the drain region.

[0051] It should be noted that in the semiconductor device, the top surface of the gate structure 101 is higher than the top surface of the active area 102. When the barrier layer 20 is deposited, due to the height difference between the gate structure 101 and the active area 102, the thickness of the barrier layer 20 on the top surface of the active area 102 is greater than the thickness of the barrier layer 20 on the top surface of the gate structure 101.

[0052] By way of example, the material of the compensation layer 30 may include, but is not limited to, silicon nitride (SiN) material.

[0053] Exemplarily, the contact hole 40 can be arranged in one-to-one correspondence with the gate structure 101 and the active area 102 to achieve electrical connectivity between the circuit line and the active device. The size of the contact hole 40 parallel to the top surface of the substrate can be set according to the size of the metal layer, gate structure 101, and active area 102 in the semiconductor device. The size and shape of the contact hole 40 can also be set according to electrical performance parameters such as resistance and capacitance, thereby achieving interconnection between different functional layers to form a complete circuit. Specifically, in this embodiment, the longitudinal section of the contact hole is a quadrilateral.

[0054] The semiconductor device of the present application includes a substrate 10, a barrier layer 20, a compensation layer 30 and a plurality of contact holes 40. The substrate 10 includes a gate structure 101 and an active area 102. The barrier layer 20 covers the top surfaces of the gate structure 101 and the active area 102. The thickness of the barrier layer 20 on the top surface of the gate structure 101 is less than the thickness of the barrier layer 20 on the top surface of the active area 102. By forming the compensation layer 30 on the top surface of the barrier layer 20 away from the gate structure 101, the compensation layer 30 can compensate for the thickness of the barrier layer 20 on the top surface of the gate structure 101, so that the film thickness on the top of the gate structure 101 is equal to the film thickness on the top surface of the active area 102. In addition, in the process of forming the plurality of contact holes 40, when the contact holes 40 expose the top surface of the active area 102, it is ensured that the top surface of the gate structure 101 is not etched, so that the height difference caused by etching on the top surface of the gate structure 101 can be avoided, thereby avoiding the problem of increased contact resistance in the contact holes 40, and improving the electrical properties and reliability of the semiconductor device.

[0055] In some embodiments, please refer to Figure 1 The barrier layer 20 includes a first barrier layer 201, a second barrier layer 202 and a third barrier layer 203 which are stacked in sequence on the top surface parallel to the substrate 10, wherein the material of the first barrier layer 201 is different from the material of the second barrier layer 202; the material of the second barrier layer 202 is different from the material of the third barrier layer 203.

[0056] As an example, the material of the first barrier layer 201 may include but is not limited to a silicon oxynitride layer. The first barrier layer 201 has good etching selectivity with the substrate 10, and can be quickly stopped when etching reaches the top surface of the substrate 10 during the etching process to prevent the top surface of the substrate 10 from being etched. The material of the second barrier layer 202 may include but is not limited to a silicon nitride layer. The second barrier layer 202 has good etching selectivity with the first barrier layer 201. When etching reaches the top surface of the first barrier layer 201 during the etching process, the etching rate may change to control the progress of etching. The material of the third barrier layer 203 may include but is not limited to an oxide layer. The third barrier layer 203 has good etching selectivity with the second barrier layer 202. When etching reaches the top surface of the second barrier layer 202 during the etching process, the etching rate may change to further control the progress of etching.

[0057] The semiconductor device in the embodiment of the present application, by providing a stacked combination of a first barrier layer 201, a second barrier layer 202 and a third barrier layer 203, can protect the unexposed portion of the top surface of the substrate 10 when the contact hole 40 is subsequently formed, thereby preventing the unexposed portion of the top surface of the substrate 10 from being etched. In addition, the first barrier layer 201, the second barrier layer 202 and the third barrier layer 203 are made of different materials, so that different etching rates can be achieved during the etching process to provide a clear etching interface, and the etching progress can be controlled according to the etching rate to prevent the top surface of the substrate 10 from being damaged by etching.

[0058] In some embodiments, please refer to Figure 1 The compensation layer 30 is used to compensate for the height difference formed on the top surface of the gate structure 101 when the stop layer 20 is etched.

[0059] As an example, the thickness of the compensation layer 30 can be set according to the height difference between the barrier layer 20 at the top of the gate structure 101 and the barrier layer 20 at the top of the active area 102, so as to compensate for the fact that the thickness of the barrier layer 20 at the top of the gate structure 101 is less than the thickness of the barrier layer 20 at the top of the active area 102. This can ensure that when the contact hole 40 is subsequently formed, excessive etching is avoided at the top of the gate structure 101 due to the excessively small thickness of the barrier layer 20.

[0060] The semiconductor device in the embodiment of the present application can compensate for the height difference formed on the top surface of the gate structure 101 when the blocking layer 20 is etched by the compensation layer 30, so that in the process of forming multiple contact holes 40, when the contact holes 40 expose the top surface of the active area 102, it can ensure that the top surface of the gate structure 101 is not etched, and the height difference of the top surface of the gate structure 101 caused by etching, which in turn causes the problem of increased contact resistance in the contact hole 40, and the thickness of the compensation layer 30 can be set according to the height difference between the blocking layer 20 at the top of the gate structure 101 and the blocking layer 20 at the top of the active area 102, so that it can be freely set in different semiconductor devices, thereby improving the applicability of the semiconductor device.

[0061] In some embodiments, please refer to Figure 1 The semiconductor device further includes: a dielectric layer 50 covering the barrier layer 20 and the compensation layer 30 .

[0062] As an example, the material of the dielectric layer 50 may include but is not limited to silicon oxide (SiO2), silicon nitride (SiNx), aluminum oxide (Al2O3), low dielectric constant (Low-k) material, high dielectric constant (High-k) material, etc.

[0063] The semiconductor device provided in the embodiment of the present application can separate the metal layer from the substrate 10 by forming a dielectric layer 50 to cover the barrier layer 20 and the compensation layer 30, so as to achieve electrical isolation of the semiconductor device and realize efficient transmission of signals in the multi-layer interconnection structure.

[0064] In some embodiments, please refer to Figure 1 The substrate 10 further includes: a metal silicide layer 60 covering the exposed surface of the gate structure 101 and the active area 102 .

[0065] As an example, the material of the metal silicide layer 60 may include, but is not limited to, at least one of titanium silicide (TiSi 2 ), cobalt silicide (CoSi 2 ), nickel silicide (NiSi), and platinum silicide (PtSi).

[0066] The semiconductor device provided in the embodiment of the present application can reduce the contact resistance between the conductor in the contact hole 40 and the active area 102 and the gate structure 101 by forming a metal silicide to cover the exposed surface of the gate structure 101 and the active area 102, thereby improving the signal transmission efficiency.

[0067] An embodiment of the present application provides an electronic device, comprising the semiconductor device in any one of the above embodiments.

[0068] The electronic device of the present application includes the semiconductor device in any of the above embodiments, the substrate 10 includes a gate structure 101 and an active area 102, the barrier layer 20 covers the top surfaces of the gate structure 101 and the active area 102, wherein the thickness of the barrier layer 20 on the top surface of the gate structure 101 is less than the thickness of the barrier layer 20 on the top surface of the active area 102, and by forming a compensation layer 30 on the barrier layer 20 away from the top surface of the gate structure 101, the compensation layer 30 can compensate for the thickness of the barrier layer 20 on the top surface of the gate structure 101, so that the film thickness on the top of the gate structure 101 is equal to the film thickness on the top surface of the active area 102, and then in the process of forming a plurality of contact holes 40, when the contact holes 40 expose the top surface of the active area 102, it is ensured that the top surface of the gate structure 101 is not etched, and the height difference caused by etching on the top surface of the gate structure 101 can be avoided, thereby avoiding the problem of increased contact resistance in the contact holes 40, and improving the electrical properties and reliability of the semiconductor device.

[0069] The present invention provides a method for preparing a semiconductor device. Figure 2 , the method for preparing the semiconductor device may include:

[0070] S11: providing a substrate, wherein the substrate includes a gate structure and an active region.

[0071] As an example, see Figure 1The substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate deposited on a silicon germanium wafer.

[0072] As an example, see Figure 3 The gate structure 101 may include a gate conductive layer, a gate oxide layer and a gate electrode. The gate conductive layer, the material of the gate conductive layer may include but is not limited to a conductive layer, such as a doped polysilicon gate conductive layer or a metal gate conductive layer, etc. The gate oxide layer may include but is not limited to an oxide layer, such as a silicon dioxide layer, and the gate electrode may include but is not limited to a metal gate electrode.

[0073] As an example, the active region 102 may be a source region or a drain region, and the active region 102 may be formed by, but not limited to, ion implantation. It should be noted that, when the active region 102 is a source region, the semiconductor device further includes a source electrode, which covers the top surface of the source region, and when the active region 102 is a drain region, the semiconductor device may further include a drain electrode, which is located on the top surface of the drain region.

[0074] S12: forming a barrier layer and a compensation material layer on the top surfaces of the gate structure and the active area, wherein the barrier layer covers the top surfaces of the gate structure and the active area, and the compensation material layer is located on the top surface of the barrier layer away from the gate structure.

[0075] As an example, see Figure 3 The barrier layer 20 and the compensation material layer 301 may be formed on the top surface of the gate structure 101 and the active area 102 by, but not limited to, a molecular beam epitaxy process (MBE), a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), or an atomic layer deposition process (ALD). The material of the compensation material layer 301 may include, but not limited to, a silicon nitride (SiN) material.

[0076] It should be noted that in the semiconductor device, the top surface of the gate structure 101 is higher than the top surface of the active area 102. When the barrier layer 20 is deposited, due to the height difference between the gate structure 101 and the active area 102, the thickness of the barrier layer 20 on the top surface of the active area 102 is greater than the thickness of the barrier layer 20 on the top surface of the gate structure 101.

[0077] S13: etching the compensation material layer to form a compensation layer, wherein the compensation layer is located on a top surface of the barrier layer away from the gate structure.

[0078] As an example, see Figure 4 , the compensation material layer 301 may be etched by, but not limited to, a photolithography process to form a compensation layer 30. The thickness of the compensation layer 30 may be set according to the height difference between the barrier layer 20 at the top of the gate structure 101 and the barrier layer 20 at the top of the active region 102, so as to compensate for the fact that the thickness of the barrier layer 20 at the top of the gate structure 101 is less than the thickness of the barrier layer 20 at the top of the active region 102, and to ensure that when the contact hole 40 is subsequently formed, the top of the gate structure 101 is prevented from being over-etched due to the small thickness of the barrier layer 20.

[0079] S15: forming a plurality of contact holes, wherein the plurality of contact holes penetrate the barrier layer and the compensation layer in a direction perpendicular to the top surface of the substrate and expose a portion of the top surface of the substrate.

[0080] As an example, see Figure 1 , a plurality of contact holes 40 may be formed by, but not limited to, a dry etching process or a wet etching process. The contact holes 40 may be arranged one-to-one with the gate structure 101 and the active area 102 to achieve electrical connectivity between the circuit line and the active device. The size of the contact hole 40 parallel to the top surface of the substrate 10 may be set according to the size of the metal layer, the gate structure 101, and the active area 102 in the semiconductor device. The size and shape of the contact hole 40 may also be set according to electrical performance parameters such as resistance and capacitance, thereby achieving interconnection between different functional layers to form a complete circuit. Specifically, in this embodiment, the longitudinal section of the contact hole 40 is a quadrilateral.

[0081] The preparation method of the semiconductor device of the present application includes providing a substrate, the substrate including a gate structure and an active area, and then forming a barrier layer and a compensation material layer on the top surface of the gate structure and the active area, wherein the barrier layer covers the top surface of the gate structure and the active area, and the compensation material layer is located on the top surface of the barrier layer away from the gate structure, and further etching the compensation material layer to form a compensation layer, wherein the compensation layer is located on the top surface of the barrier layer away from the gate structure, and finally forming a plurality of contact holes, wherein the plurality of contact holes penetrate the barrier layer and the compensation layer in a direction perpendicular to the top surface of the substrate and expose a portion of the top surface of the substrate. By forming a barrier layer and a compensation material layer on the top surface of the gate structure and the active area, wherein the thickness of the barrier layer on the top surface of the gate structure is less than the thickness of the barrier layer on the top surface of the active area, and etching the compensation material layer to obtain a compensation layer, the compensation layer can compensate for the thickness of the barrier layer on the top surface of the gate structure, so that the thickness of the film layer on the top of the gate structure is equal to the thickness of the film layer on the top surface of the active area, and then in the process of forming multiple contact holes, when the contact holes expose the top surface of the active area, it can be ensured that the top surface of the gate structure is not etched, and the height difference caused by etching on the top surface of the gate structure, which in turn causes the problem of increased contact resistance in the contact hole, can be avoided, and the electrical properties and reliability of the semiconductor device can be improved. .

[0082] In some embodiments, see Figure 3 The barrier layer 20 includes a first barrier layer 201, a second barrier layer 202 and a third barrier layer 203 which are stacked in sequence on the top surface parallel to the substrate 10, wherein the material of the first barrier layer 201 is different from the material of the second barrier layer 202; the material of the second barrier layer 202 is different from the material of the third barrier layer 203.

[0083] As an example, the first barrier layer 201, the second barrier layer 202 and the third barrier layer 203 may be formed by, but not limited to, a molecular beam epitaxy process, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process. The material of the first barrier layer 201 may include, but not limited to, a silicon oxynitride layer. The first barrier layer 201 has a good etching selectivity with the substrate 10. When the etching reaches the top surface of the substrate 10 during the etching process, the etching can be stopped quickly to prevent the top surface of the substrate 10 from being etched. The material of the second barrier layer 202 may include, but not limited to, a silicon nitride layer. The second barrier layer 202 has a good etching selectivity with the first barrier layer 201. When the etching reaches the top surface of the first barrier layer 201 during the etching process, the etching rate may change to control the progress of the etching. The material of the third barrier layer 203 may include, but not limited to, an oxide layer. The third barrier layer 203 has a good etching selectivity with the second barrier layer 202. When the etching reaches the top surface of the second barrier layer 202 during the etching process, the etching rate may change to further control the progress of the etching.

[0084] The method for preparing a semiconductor device in the embodiment of the present application, by forming a stacked combination of a first barrier layer 201, a second barrier layer 202 and a third barrier layer 203, can protect the unexposed portion of the top surface of the substrate 10 when a contact hole 40 is subsequently formed, thereby preventing the unexposed portion of the top surface of the substrate 10 from being etched. In addition, the first barrier layer 201, the second barrier layer 202 and the third barrier layer 203 are made of different materials, so different etching rates can be achieved during the etching process to provide a clear etching interface, and the etching progress can be controlled according to the etching rate to prevent the top surface of the substrate 10 from being damaged by etching.

[0085] In some embodiments, after etching the compensation material layer to form the compensation layer and before forming the plurality of contact holes, the process further includes: step S14.

[0086] Step S14: forming a dielectric layer, wherein the dielectric layer covers the barrier layer and the compensation layer.

[0087] As an example, see Figure 5 The dielectric layer 50 may be formed by, but not limited to, a molecular beam epitaxy process, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. The material of the dielectric layer 50 may include, but not limited to, silicon oxide (SiO2), silicon nitride (SiNx), aluminum oxide (Al2O3), a low dielectric constant (Low-k) material, a high dielectric constant (High-k) material, etc.

[0088] The method for preparing a semiconductor device provided in an embodiment of the present application can separate the metal layer from the substrate 10 by forming a dielectric layer 50 to cover the barrier layer 20 and the compensation layer 30, so as to achieve electrical isolation of the semiconductor device and realize efficient transmission of signals in a multi-layer interconnection structure.

[0089] In some embodiments, the substrate 10 further includes a metal silicide layer 60 covering the exposed surfaces of the gate structure 101 and the active region 102 .

[0090] As an example, see Figure 5 The metal silicide layer 60 may be formed by, but is not limited to, depositing a metal layer and then performing an annealing process. The material of the metal silicide layer 60 may include, but is not limited to, at least one of titanium silicide (TiSi2), cobalt silicide (CoSi2), nickel silicide (NiSi) and platinum silicide (PtSi).

[0091] The semiconductor device provided in the embodiment of the present application can reduce the contact resistance between the conductor in the contact hole 40 and the active area 102 and the gate structure 101 by forming a metal silicide to cover the exposed surface of the gate structure 101 and the active area 102, thereby improving the signal transmission efficiency.

[0092] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0093] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: include: a substrate including a gate structure and an active region; A barrier layer covering the gate structure and the top surface of the active area; A compensation layer, located on a top surface of the barrier layer away from the gate structure; A plurality of contact holes penetrate the barrier layer and the compensation layer in a direction perpendicular to the top surface of the substrate and expose a portion of the top surface of the substrate.

2. The semiconductor device according to claim 1, wherein: The barrier layer includes a first barrier layer, a second barrier layer and a third barrier layer stacked in sequence parallel to the top surface of the substrate, wherein the material of the first barrier layer is different from the material of the second barrier layer; the material of the second barrier layer is different from the material of the third barrier layer.

3. The semiconductor device according to claim 1, wherein: The compensation layer is used to compensate for the height difference formed on the top surface of the gate structure when the barrier layer is etched.

4. The semiconductor device according to claim 1, wherein: Also includes: A dielectric layer covers the barrier layer and the compensation layer.

5. The semiconductor device according to claim 1, wherein: The substrate further comprises: A metal silicide layer covers the gate structure and the exposed surface of the active area.

6. An electronic device, characterized in that: include: A semiconductor device as claimed in any one of claims 1 to 5.

7. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising a gate structure and an active area; forming a barrier layer and a compensation material layer on the top surfaces of the gate structure and the active area, wherein the barrier layer covers the top surfaces of the gate structure and the active area, and the compensation material layer is located on the barrier layer away from the top surface of the gate structure; Etching the compensation material layer to form a compensation layer, wherein the compensation layer is located on a top surface of the barrier layer away from the gate structure; A plurality of contact holes are formed, wherein the plurality of contact holes penetrate the barrier layer and the compensation layer in a direction perpendicular to the top surface of the substrate and expose a portion of the top surface of the substrate.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: The barrier layer includes a first barrier layer, a second barrier layer and a third barrier layer stacked in sequence parallel to the top surface of the substrate, wherein the material of the first barrier layer is different from the material of the second barrier layer; the material of the second barrier layer is different from the material of the third barrier layer.

9. The method for preparing a semiconductor device according to claim 7, characterized in that: After etching the compensation material layer to form the compensation layer and before forming a plurality of contact holes, the method further includes: A dielectric layer is formed, wherein the dielectric layer covers the barrier layer and the compensation layer.

10. The method for preparing a semiconductor device according to claim 7, characterized in that: The substrate further comprises: A metal silicide layer covers the gate structure and the exposed surface of the active area.

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