Semiconductor device, semiconductor package and semiconductor packaging method

Abstract

The invention relates to the field of semiconductor packaging, and provides a semiconductor device, a semiconductor package and a semiconductor packaging method, the semiconductor device is applied to the semiconductor package, the semiconductor device comprises a plurality of stacked semiconductor chips, and the current semiconductor chip is stacked on the lower semiconductor chip; the substrate of the current semiconductor chip is provided with a first surface and a second surface which are oppositely arranged; the first surface is used for providing an attachment surface of an interconnection layer; the second surface is used for abutting against an interconnection layer at the top end of the lower semiconductor chip. The structure is used for reducing interlayer gaps and layer height fluctuation so as to reduce gap filling process steps, and ensures that short circuit is avoided after packaging so as to ensure the performance of the device. Compared with a silicon through hole process, the method does not need to accurately etch the internal structure of a silicon wafer, and reduces the process difficulty of semiconductor device stacking.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and in particular to a semiconductor device, a semiconductor packaging and a semiconductor packaging method. Background Art

[0002] Semiconductor devices usually use different semiconductor materials, different processes and geometric structures, and have developed a wide variety of devices with different functions and uses. It is often necessary to electrically connect the conductive materials of each layer to realize the interconnection of devices to achieve the required performance. Semiconductor devices are constantly developing in the direction of being smaller, faster and more efficient, which requires continuous innovation and optimization of the manufacturing process of the device. However, in the manufacturing process of semiconductor devices, there are a series of technical problems that need to be solved. In the traditional scheme, the interconnection layer is physically deposited, and silicon through-holes are usually used when interconnecting inter-layer devices across layers. However, this requires control of inter-layer alignment and drilling accuracy. If the accuracy is too low, it is easy to cause device failure, and the use of insulating layers to fill it is easy to block cross-layer conduction, further affecting the performance of the device. Therefore, there is an urgent need for a semiconductor device, semiconductor package and semiconductor packaging method to improve the above problems. Summary of the invention

[0003] An object of the present invention is to provide a semiconductor device, a semiconductor package and a semiconductor packaging method, which are used to reduce layer height fluctuations in a multi-layer chip to ensure the performance of the semiconductor device.

[0004] In the first aspect, the present invention provides a semiconductor device for use inside a semiconductor package, comprising: a plurality of stacked semiconductor chips, wherein the current semiconductor chip is stacked on a lower semiconductor chip; each semiconductor chip has a plurality of interconnection layers, a plurality of insulating layers and a substrate; the interconnection layers are used to provide a first conductive region and a second conductive region; the contours of adjacent etched grooves in N layers of interconnection layers do not intersect each other in the stacking direction, and N is a positive integer greater than 2; the insulating layer is located between adjacent interconnection layers and is used to provide an insulating dielectric; the substrate of the current semiconductor chip has a first surface and a second surface arranged opposite to each other; the first surface is used to provide an attachment surface for the interconnection layer; and the second surface is used to abut the interconnection layer on the top of the lower semiconductor chip.

[0005] Optionally, the interconnection layer in each semiconductor chip is set to M layers, where M is greater than or equal to N; when M is equal to N, the contours of the etched grooves in the N layers of the interconnection layer do not intersect each other in the stacking direction.

[0006] Optionally, when M is greater than N, contours of the etched grooves in the interconnection layer within the N layers intersect with contours of the etched grooves in the interconnection layer outside the N layers.

[0007] Optionally, the interconnect layer in each semiconductor chip has a first edge and a second edge opposite to each other, and the etching grooves in two adjacent interconnect layers are respectively close to the first edge and the second edge, so that the first areas and the second areas in adjacent interconnect layers overlap alternately.

[0008] In a second aspect, the present invention provides a semiconductor package, comprising: a semiconductor device as described in any one of the first aspects, and: a first conductive sealing end portion, used to connect a first region of an interconnection layer in each semiconductor chip; a second conductive sealing end portion, used to connect a second region in an interconnection layer in each semiconductor chip; the first conductive sealing end portion and the second conductive sealing end portion are isolated from each other.

[0009] In a third aspect, the present invention provides a semiconductor packaging method for forming a semiconductor device described in any one of the first aspects, comprising: S1, providing a substrate, forming an interconnection area in a portion where a conductor needs to be led out; S2, performing an etching process on a non-interconnection area on the surface where a conductor does not need to be led out, so that the non-interconnection area is blocked by an etching groove into a first area and a second area; S3, forming an insulating layer on the surface of the interconnection layer; forming an interconnection layer on the upper surface of the insulating layer; S4, after repeating S2-S3 several times, executing S2 once again to form a semiconductor chip; the contours of adjacent etching grooves in N layers of interconnection layers do not intersect each other in the stacking direction, N is a positive integer greater than 2; S5, repeating S1-S4 L times, L is a positive integer greater than 1; stacking L layers of semiconductor chips to form a semiconductor device.

[0010] Optionally, the semiconductor chip is thinned, and L layers of thinned semiconductor chips are stacked to form a semiconductor device.

[0011] Optionally, edges of the stacked interconnection layers are cut or polished to expose the first region and the second region of the interconnection layers in the semiconductor chip.

[0012] Optionally, a first conductive sealing end portion is formed for connecting the first region in each interconnect layer, and a second conductive sealing end portion is formed for connecting the second region in each interconnect layer.

[0013] Optionally, the interconnect layer and the insulating layer are respectively formed by at least one of atomic layer deposition and chemical vapor deposition processes; and the first conductive sealing end portion and the second conductive sealing end portion are formed by an electroplating process.

[0014] The beneficial effects of the present invention are as follows: the semiconductor device is applied to semiconductor packaging, comprising: a plurality of semiconductor chips arranged in a stack, wherein the current semiconductor chip is stacked on the lower semiconductor chip; the substrate of the current semiconductor chip has a first surface and a second surface arranged oppositely; the first surface is used to provide an attachment surface for the interconnection layer; the second surface is used to abut the interconnection layer on the top of the lower semiconductor chip. The structure is used to reduce the gap between layers and the fluctuation of layer height, thereby reducing the process steps of filling the gap, ensuring that there will be no short circuit after packaging, so as to ensure the performance of the device. Compared with the through silicon via process, there is no need to accurately etch the internal structure of the silicon wafer, which reduces the process difficulty of stacking semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of a semiconductor device provided by the present invention; Figure 2 A schematic diagram of the structure of a semiconductor package provided by the present invention; Figure 3 A schematic flow chart of a semiconductor packaging method provided by the present invention; Figure 4 A schematic diagram of a structure in which an odd-numbered first interconnection layer is formed on a substrate provided by the present invention; Figure 5 A schematic diagram of a structure in which an odd-numbered first interconnection layer etching groove is formed in an odd-numbered first interconnection layer provided by the present invention; Figure 6 A schematic diagram of a structure in which a first insulating layer is formed on an odd-numbered first interconnection layer provided by the present invention; Figure 7 A schematic diagram of a structure in which an odd-numbered second interconnection layer is formed on a first insulating layer provided by the present invention; Figure 8 A schematic diagram of a structure in which an odd-numbered second interconnection layer etching groove is formed in an odd-numbered second interconnection layer provided by the present invention; Fig. 9 A schematic diagram of a structure in which a second insulating layer is formed on an odd-numbered second interconnection layer provided by the present invention; Fig.10 A schematic structural diagram of a semiconductor package provided with a conductive sealing end portion provided by the present invention.

[0016] Description of reference numerals in the figures: 1. Substrate; 6. Chip unit; 21, odd-numbered first interconnection layer; 22, even-numbered first interconnection layer; 31, odd-numbered second interconnection layer; 32, even-numbered second interconnection layer; 41, first insulating layer; 42, second insulating layer; 43, third insulating layer; 51, first conductive sealing end; 52, second conductive sealing end; 201, odd-numbered first interconnection layer etching groove; 202, even-numbered first interconnection layer etching groove; 211, odd-numbered first interconnection layer high potential region; 212, odd-numbered first interconnection layer low potential region; 221, even-numbered first interconnection layer high potential region; 222, even-numbered first interconnection layer low potential region; 301, etching grooves of the second interconnection layer of odd-numbered digits; 302, etching grooves of the second interconnection layer of even-numbered digits; 311, high potential area of ​​the second interconnection layer of odd-numbered digits; 312, low potential area of ​​the second interconnection layer of odd-numbered digits; 321, high potential area of ​​the second interconnection layer of even-numbered digits; 322, low potential area of ​​the second interconnection layer of even-numbered digits. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0018] At present, the existing technology usually adopts silicon through-hole technology to realize 3D packaging. However, the existing through-hole etching process, including laser etching and deep reactive ion etching, requires high-precision process to realize the preparation of micro-holes with high aspect ratio structure, and requires matching high-precision etching equipment. These advanced equipment are usually expensive, which increases the cost of mass production and is not conducive to the promotion of high-integration packaging.

[0019] In view of the problems existing in the existing technology, such as Figure 1As shown, the first embodiment of the present invention provides a semiconductor device, which is applied to the inside of a semiconductor package, including: a plurality of semiconductor chips arranged in a stack, wherein the current semiconductor chip is stacked on the lower semiconductor chip; each semiconductor chip has a plurality of interconnection layers, a plurality of insulation layers and a substrate; the interconnection layer is used to provide a first conductive area and a second conductive area; the contours of adjacent etching grooves in the N layers of interconnection layers do not intersect each other in the stacking direction, and N is a positive integer greater than 2; the insulation layer is located between adjacent interconnection layers and is used to provide an insulating dielectric; the substrate of the current semiconductor chip has a first surface and a second surface arranged oppositely; the first surface is used to provide an attachment surface for the interconnection layer; and the second surface is used to abut the interconnection layer at the top of the lower semiconductor chip. In this embodiment, by making the contours of adjacent etching grooves in the N layers of interconnection layers do not intersect each other in the stacking direction, the height difference of the etching grooves arranged in the multiple layers of interconnection layers is avoided to accumulate and form layer height fluctuations, which can increase the actual effective conductive area, keep the electric field between the interconnection layers uniform, avoid excessive local electric field strength, thereby reducing leakage current, improving the insulation performance of the insulation layer, avoiding breakdown, and being conducive to improving the performance of the semiconductor device.

[0020] In some other specific embodiments, the stacking direction of the N layers of interconnection layers is along the vertical direction Z, and the extension direction of the substrate 1, the interconnection layer and the insulating layer is along the horizontal plane. The etched groove is configured to gradually penetrate into the interconnection layer along the vertical direction Z until it contacts the substrate 1 or the insulating layer. The stacking structure of this embodiment can disperse stress, reduce the pressure of the monolithic structure, and improve the mechanical stability of the semiconductor device.

[0021] In some other specific embodiments, the substrate 1 in each semiconductor chip is made of silicon, silicon oxide, zirconium oxide, hafnium oxide, germanium, silicon nitride, aluminum oxide or gallium oxide. The interconnection layer is set to a conductive material. The insulating layer is set to an insulating material. The insulating layer is also used to fill the etched groove of the interconnection layer thereunder, so that the first area and the second area are separated by the insulating material.

[0022] In some embodiments, the interconnection layer is set to be M layers, where M is greater than or equal to N; when M is equal to N, the profiles of the etched grooves in the N layers of the interconnection layer do not intersect each other in the stacking direction.

[0023] In some specific embodiments, M=N=4, and an odd-numbered first interconnection layer 21 is connected to the attachment surface provided by the substrate 1. A first insulating layer 41 is connected to the odd-numbered first interconnection layer 21. An odd-numbered second interconnection layer 31 is connected to the first insulating layer 41. A second insulating layer 42 is connected to the odd-numbered second interconnection layer 31. An even-numbered first interconnection layer 22 is connected to the second insulating layer 42. A third insulating layer 43 is connected to the even-numbered first interconnection layer 22. The third insulating layer 43 is connected to the even-numbered second interconnection layer 32. In this embodiment, by setting the etching grooves in the N-layer interconnection layer not to intersect each other in the Z direction, the accumulation of etching groove height differences is avoided, and the step difference can be fundamentally eliminated. The actual effective conductive area of ​​the chip is increased, so that the electric field between the interconnection layers remains uniform, and the local electric field strength is avoided from being too high, thereby reducing leakage current, improving the insulation performance of the insulating layer, and avoiding breakdown, which is conducive to improving the performance of semiconductor devices.

[0024] In some examples, the odd-numbered first interconnection layer 21 is provided with an odd-numbered first interconnection layer etching groove 201 close to the reverse direction of X, and the even-numbered first interconnection layer 22 is provided with an even-numbered first interconnection layer etching groove 202 close to the reverse direction of X. The odd-numbered first interconnection layer etching groove 201 and the even-numbered first interconnection layer etching groove 202 are adjacent to each other, and the profiles of the two in the Z direction do not intersect each other.

[0025] In some other examples, the odd-numbered second interconnection layer 31 is provided with an odd-numbered second interconnection layer etching groove 301 close to the X direction, and the even-numbered second interconnection layer 32 is provided with an even-numbered second interconnection layer etching groove 302 close to the X direction. The odd-numbered second interconnection layer etching groove 301 and the even-numbered second interconnection layer etching groove 302 are adjacent to each other, and the profiles of the two in the Z direction do not intersect each other.

[0026] It is worth noting that the micro-displacement fine trench patterning (MDFTP) is used to define the position of the etching grooves of adjacent interconnection layers. It can achieve sub-micron or even nanometer-level positioning accuracy, which is conducive to improving the integration of integrated circuits.

[0027] In some embodiments, when M is greater than N, the contours of the etched grooves in the interconnection layer within the N layers intersect with the contours of the etched grooves in the interconnection layer outside the N layers.

[0028] In some specific embodiments, M=20, N=10, 20 interconnection layers and 20 insulation layers are stacked on the substrate 1 along the Z direction, and the etched grooves in the interconnection layer at the 1st layer intersect with the outlines of the etched grooves in the interconnection layer at the 401st layer in the Z direction; the etched grooves in the interconnection layer at the 2nd layer intersect with the outlines of the etched grooves in the interconnection layer at the 402nd layer in the Z direction; the etched grooves in the interconnection layer at the 10th layer intersect with the outlines of the etched grooves in the interconnection layer at the 20th layer in the Z direction. This embodiment reuses the etched groove positions after spacing N layers of interconnection layers, which can minimize the local accumulation of etched groove height differences, so that the semiconductor device can reach a higher number of layers to meet the design of large-capacity semiconductor packaging. On the other hand, this embodiment can further increase the effective conductive area by increasing the number of interconnection layers to M layers, thereby improving the overall working efficiency of the semiconductor device.

[0029] In some embodiments, the interconnect layer in each semiconductor chip has a first edge and a second edge opposite to each other, and the etching grooves in two adjacent interconnect layers are respectively close to the first edge and the second edge so that the first areas and the second areas in adjacent interconnect layers overlap alternately.

[0030] In some specific embodiments, the first edge is located in the opposite direction of X, and the second edge is located in the X direction. In some examples, the odd-numbered first interconnection layer low potential area 212, the odd-numbered second interconnection layer high potential area 311, the even-numbered first interconnection layer low potential area 222, and the even-numbered second interconnection layer high potential area 321 overlap alternately from bottom to top. In other specific embodiments, the first edge is located in the X direction, and the second edge is located in the opposite direction of X. In this embodiment, by making the etching grooves in the two adjacent interconnection layers close to the first edge and the second edge respectively, the space can be better utilized, the effective conductive area can be further increased, and the work efficiency can be improved.

[0031] In some embodiments, the semiconductor device includes a chip unit 6, which is located in the center of the semiconductor device, and the odd-numbered first interconnection layer etching grooves 201 are located in the X-reverse direction of the chip unit 6; the odd-numbered second interconnection layer etching grooves 301 are located in the X-direction of the chip unit 6.

[0032] In some specific embodiments, the chip unit 6 is configured as a memory chip unit, which includes a static random access memory (SRAM), a dynamic random access memory (DRAM), or other types of non-volatile memory.

[0033] In some other specific embodiments, the chip unit 6 is configured as a logic chip unit. The logic chip unit includes an arithmetic logic unit (ALU), a microprocessor core, a digital signal processor (DSP), or an application-specific integrated circuit (ASIC) for executing a specific algorithm.

[0034] like Figure 2 As shown, the second embodiment provides a semiconductor package, comprising: a semiconductor device inside the semiconductor device described in any one of the above embodiments, and: a first conductive sealing end 51, used to connect the first area of ​​the interconnection layer in each semiconductor chip; a second conductive sealing end 52, used to connect the second area of ​​the interconnection layer in each semiconductor chip; the first conductive sealing end 51 and the second conductive sealing end 52 are not connected to each other.

[0035] In some specific embodiments, the first conductive sealing end portion 51 is used to connect the high potential terminal, and the second conductive sealing end portion 52 is used to connect the low potential terminal. When there is a potential difference between the high potential terminal and the low potential terminal, an electric field is formed between the first region and the second region. In other specific embodiments, the first conductive sealing end portion 51 is used to connect the low potential terminal, and the second conductive sealing end portion 52 is used to connect the high potential terminal. It is worth noting that this embodiment realizes parallel connection of adjacent interconnection layers by setting the first conductive sealing end portion 51 and the second conductive sealing end portion 52 that are not connected to each other, which is beneficial to increase the area of ​​the terminal. Thanks to the parallel connection of multiple interconnection layers and the effective use of space, the integration of semiconductor devices can be improved.

[0036] In some examples, the number of interconnection layers is an even number, and charges are stored by alternating insulating layers and interconnection layers. In other examples, the number of interconnection layers is an odd number, and the interconnection layer at the top layer is not connected to the first conductive sealing end 51 and the second conductive sealing end 52, which is used to provide shielding. This design can reduce electromagnetic interference between the semiconductor device and other components, especially in high-frequency applications. The shielding effect of the top interconnection layer helps to maintain the stable performance of the semiconductor device and reduce electromagnetic interference to the outside world.

[0037] The third embodiment provides a semiconductor packaging method for forming a semiconductor device inside a semiconductor device described in any one of the above embodiments, comprising: S1, providing a substrate 1, and forming an interconnection layer in a portion where a conductor needs to be led out; S2, performing an etching process on a non-interconnection area on the surface where a conductor does not need to be led out, so that the non-interconnection area is blocked by an etching groove into a first area and a second area; S3, forming an insulating layer on the surface of the interconnection layer; forming an interconnection layer on the upper surface of the insulating layer; S4, after repeating S2-S3 several times, executing S2 once again to form a semiconductor chip; the contours of adjacent etching grooves in N layers of interconnection layers do not intersect each other in the stacking direction, and N is a positive integer greater than 2; S5, repeating S1-S4 L times, and L is a positive integer greater than 1; stacking L layers of semiconductor chips to form a semiconductor device.

[0038] It is worth noting that the interconnection layer and the insulating layer are formed by at least one process of atomic layer deposition (ALD) or chemical vapor deposition (CVD). In this embodiment, by repeatedly executing steps S2 and S3, a new layer is deposited on the basis of the previous layer c and the insulating layer each time, thereby realizing the layer-by-layer alternating accumulation of a multi-layer interconnection layer and an insulating layer structure. This process demonstrates a high degree of repeatability and control accuracy, and supports large-scale industrial production of complex multi-layer structures.

[0039] In some embodiments, S5 further includes: thinning the semiconductor chip, and stacking the L-layer thinned semiconductor chips to form a semiconductor device. It is worth noting that this embodiment resets the local differences in layer heights by stacking semiconductor chips, avoids excessive fluctuations in layer heights that lead to a reduction in the effective conductive area, improves the uniformity of the electric field between interconnected layers, helps reduce leakage current, improves the insulation performance of the insulating layer, avoids the risk of breakdown, and ensures the performance of the semiconductor device group.

[0040] More specifically, when thinning the bottom surface of the substrate of each semiconductor chip, a thinning process is performed on the second surface of the substrate to thin the substrate to 80-100 microns. The thinning process is mechanical grinding, chemical mechanical polishing or etching. In this embodiment, by thinning the substrate in the semiconductor chip, the volume proportion of the substrate in the semiconductor device group is reduced as much as possible, so that the limited on-chip space can accommodate more interconnection layers.

[0041] In the first example, five silicon substrates 1 with a size of 2 cm*2 cm are patterned and etched using a reactive ion etching process. S1 includes: using an atomic layer deposition process to deposit 20 nanometers of titanium nitride (TiN) on the surface of the silicon wafer as an odd-numbered first interconnection layer 21 .

[0042] like Figure 5As shown, when S2 is executed for the first time, it also includes: etching the odd-numbered first interconnect layer 21 at the first edge located in the opposite direction of X to form an odd-numbered first interconnect layer etching groove 201, and dividing the odd-numbered first interconnect layer 21 into an odd-numbered first interconnect layer high potential area 211 and an odd-numbered first interconnect layer low potential area 212.

[0043] like Figure 6 As shown, when S3 is first executed, it also includes: S31, using an atomic layer deposition process to deposit 10 nm of hafnium zirconium oxide (HfZrO) antiferroelectric material on the surface of the odd-numbered first interconnect layer 21 as the first insulating layer 41. Figure 7 As shown, 40 nm of titanium nitride is deposited on the first insulating layer 41 using an atomic layer deposition process as the odd-numbered second interconnection layer 31 .

[0044] like Figure 8 As shown, the second execution of S2 also includes: S41, etching the odd-numbered second interconnect layer 31 at the second edge located in the X direction to form an odd-numbered second interconnect layer etching groove 301, dividing the odd-numbered second interconnect layer 31 into an odd-numbered second interconnect layer high potential area 311 and an odd-numbered second interconnect layer low potential area 312.

[0045] like Fig. 9 As shown, the second execution of S3 further includes: S42, using chemical vapor deposition to deposit 10nm silicon oxide on the surface of the odd-numbered second interconnection layer 31 as the second insulating layer 42. Using atomic layer deposition to deposit 20nm titanium nitride on the second insulating layer 42 as the even-numbered first interconnection layer 22.

[0046] The third execution of S2 also includes: S43, etching the even-numbered first interconnect layer 22 at the first edge located in the X direction to form an even-numbered first interconnect layer etching groove 202, and dividing the even-numbered first interconnect layer 22 into an even-numbered first interconnect layer high potential area 221 and an even-numbered first interconnect layer low potential area 222.

[0047] The third execution of S3 further includes: S44, using an atomic layer deposition process to deposit 10 nm of hafnium zirconium oxide (HfZrO) antiferroelectric material on the surface of the even-numbered first interconnection layer 22 as a third insulating layer 43. Using an atomic layer deposition process to deposit 50 nm of titanium nitride on the third insulating layer 43 as an even-numbered second interconnection layer 32.

[0048] The fourth execution of S2 also includes: S45, etching the even-numbered second interconnect layer 32 at the second edge located in the X direction to form an even-numbered second interconnect layer etching groove 302, and dividing the even-numbered second interconnect layer 32 into an even-numbered second interconnect layer high potential area 321 and an even-numbered second interconnect layer low potential area 322.

[0049] The fourth execution of S3 further includes: S46, using a chemical vapor deposition process to deposit 10 nm of silicon oxide on the surface of the even-numbered second interconnection layer 32 as a fourth insulating layer.

[0050] It is worth noting that the last execution of S2 on the current substrate also includes: etching the interconnection layer located on the surface to form a surface interconnection layer etching groove, dividing the interconnection layer located on the surface into a surface high potential area and a surface low potential area.

[0051] The fourth insulating layer is used as substrate 1, and the above S1-S46 are repeated 10 times to form the semiconductor chip in the first example. The substrate of the five semiconductor chips is thinned to 80 microns, and finally liquid metal slurry is prepared on the substrate to stack the five semiconductor chips to form the semiconductor device.

[0052] This example uses a combination of atomic layer deposition and chemical vapor deposition to precisely control the thickness and quality of the insulating layer (such as zirconium oxide and hafnium oxide), ensuring the effective use of high dielectric constant materials, thereby improving the energy density and efficiency of semiconductor devices. Titanium nitride is selected as the material for the interconnect layer, thanks to its excellent conductivity and thermal stability. In combination with high dielectric constant materials, it significantly improves the high-frequency performance and thermal stability of the device, meeting the needs of high-performance electronic devices.

[0053] In the second example, 20 silicon substrates 1 with a size of 1 cm*1 cm are patterned and etched by using a reactive ion etching process, and 400 nanometers of metal tungsten are deposited on the surface of the silicon wafers by using an atomic layer deposition process as the odd-numbered first interconnection layer 21 .

[0054] like Figure 5 As shown, when S2 is executed for the first time, it also includes: etching the odd-numbered first interconnect layer 21 at the first edge located in the opposite direction of X to form an odd-numbered first interconnect layer etching groove 201, and dividing the odd-numbered first interconnect layer 21 into an odd-numbered first interconnect layer high potential area 211 and an odd-numbered first interconnect layer low potential area 212.

[0055] like Figure 6 As shown, when S3 is performed for the first time, it also includes: S31, using a chemical vapor deposition process to deposit 20nm of silicon oxide on the surface of the odd-numbered first interconnection layer 21 as the first insulating layer 41. Figure 7 As shown, a 200 nm thick metal tungsten is deposited on the first insulating layer 41 using a chemical vapor deposition process as the odd-numbered second interconnection layer 31 .

[0056] like Figure 8As shown, the second execution of S2 also includes: S41, etching the odd-numbered second interconnect layer 31 at the second edge located in the X direction to form an odd-numbered second interconnect layer etching groove 301, dividing the odd-numbered second interconnect layer 31 into an odd-numbered second interconnect layer high potential area 311 and an odd-numbered second interconnect layer low potential area 312.

[0057] like Fig. 9 As shown, the second execution of S3 further includes: S42, using chemical vapor deposition process to deposit 10nm silicon oxide on the surface of the odd-numbered second interconnection layer 31 as the second insulation layer 42. Depositing 400nm of metal tungsten on the second insulation layer 42 as the even-numbered first interconnection layer 22.

[0058] The third execution of S2 also includes: S43, etching the even-numbered first interconnect layer 22 at the first edge located in the X direction to form an even-numbered first interconnect layer etching groove 202, and dividing the even-numbered first interconnect layer 22 into an even-numbered first interconnect layer high potential area 221 and an even-numbered first interconnect layer low potential area 222.

[0059] The third execution of S3 further includes: S44, using chemical vapor deposition to deposit 20 nm silicon oxide as the third insulating layer 43 on the surface of the even-numbered first interconnection layer 22. Using chemical vapor deposition to deposit 200 nm metal tungsten as the even-numbered second interconnection layer 32 on the third insulating layer 43.

[0060] The fourth execution of S2 also includes: S45, etching the even-numbered second interconnect layer 32 at the second edge located in the X direction to form an even-numbered second interconnect layer etching groove 302, and dividing the even-numbered second interconnect layer 32 into an even-numbered second interconnect layer high potential area 321 and an even-numbered second interconnect layer low potential area 322.

[0061] The fourth execution of S3 further includes: S46, using a chemical vapor deposition process to deposit 10 nm of silicon oxide on the surface of the even-numbered second interconnection layer 32 as a fourth insulating layer.

[0062] The fourth insulating layer is used as substrate 1, and the above S1-S46 are repeated 15 times to form the semiconductor chip in the second example. The substrate of 20 semiconductor chips is thinned to 100 microns, and finally inorganic glue is spin-coated on the substrate to stack and fix the 20 semiconductor chips to form the semiconductor device.

[0063] Compared with other metals and alloys, metal tungsten has higher conductivity and better corrosion resistance, which not only enhances the conductivity of the interconnect layer, but also may improve the overall stability and service life of the device. For the first time in S3, 20nm silicon oxide is deposited as the first insulating layer 41 using chemical vapor deposition process, and the subsequent changes in the thickness of the insulating layer (such as 100nm silicon oxide of the second insulating layer 42) can adjust different dielectric materials and thicknesses to optimize chip integration and leakage current, so as to achieve higher integration or lower leakage.

[0064] In some embodiments, S4 further includes S45 , cutting or grinding edges of the stacked interconnection layers to expose the first region and the second region of the interconnection layers.

[0065] In some specific embodiments, the edges of the stacked interconnection layers are first cut and polished so that the first region of the interconnection layer exposes a flat cut surface at the first edge on the side opposite to the X direction, and the second region of the interconnection layer exposes a flat cut surface at the second edge on the side opposite to the X direction. This embodiment ensures that the edges of the first region and the second region on the side opposite to the X direction and the side opposite to the X direction present a flat cut surface by cutting and subsequently polishing the edges of the stacked interconnection layers. This processing method improves the edge neatness of the interconnection layer structure, reduces the risk of electric field concentration or short circuit caused by rough edges, and improves the reliability and electrical performance of the device.

[0066] like Fig.10 As shown, in some embodiments, it also includes S5, forming a first conductive sealing end portion 51 for connecting the first region in each interconnection layer, and forming a second conductive sealing end portion 52 for connecting the second region in each interconnection layer.

[0067] It is worth noting that the filling materials in the prior art need to have good fluidity and wettability, as well as appropriate process conditions. The filling process needs to be efficient and low-cost, while ensuring that there are no voids inside the metal core and that there is no delamination or cracking at the interface with the barrier layer. Depositing a high-quality metal seed layer on the sidewall of the through-silicon via is a difficult task, which directly affects the filling effect and the overall reliability of the through-silicon via. The difficulty is further exacerbated as the aperture decreases and the aspect ratio increases.

[0068] In some comparative examples, copper electroplating can be used to achieve termination. However, copper electroplating is difficult because it is necessary to ensure that the growth rates at the top, middle, and bottom of the hole are consistent. This requires not only a high-quality seed layer, but also a long growth time and complex process conditions, and is susceptible to contamination.

[0069] In some specific embodiments of the present application, the first conductive sealing end 51 and the second conductive sealing end 52 are formed by electroplating using graphite slurry or silver slurry. The conductive sealing end formed by the electroplating process using graphite slurry or silver slurry in this embodiment can significantly enhance the conductivity of the electrical connection between the interconnection layers, ensure efficient current transmission, and reduce resistance loss, which is particularly critical for improving the overall electrical performance of semiconductor devices. Both graphite and silver materials have good conductivity and stability, and the formed sealing end can effectively resist the influence of environmental factors on the electrical connection part, increasing the long-term stability and durability of the device. The conductive sealing end is formed by deposition using an electroplating process, and the thickness and uniformity of the deposited layer can be accurately controlled, which is suitable for mass production, can simplify the manufacturing process of the conductive sealing end, and improve production efficiency and reduce costs.

[0070] The liquid metal slurry or inorganic glue in the above embodiments are used to bond adjacent semiconductor chips after solidification. In some examples, the liquid metal slurry is defined as an interconnect layer to participate in connecting the first conductive sealing end 51 or the second conductive sealing end 52. This example makes full use of the insulating properties of the substrate and the conductive properties of the liquid metal, increases the effective conductive area, and further improves the working efficiency of the semiconductor package.

[0071] The process flow of the prior art is relatively complicated, involving multiple process steps, including through-hole etching, insulating layer deposition, seed layer deposition, and electroplating filling. These steps need to be closely coordinated, and any mistake in any step may lead to the failure of the entire product. However, the present application uses graphite slurry or silver slurry for electroplating to form a conductive end cap, which not only simplifies the process flow and reduces production costs, but also significantly improves the reliability and electrical performance of semiconductor devices.

[0072] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A semiconductor device, used in a semiconductor package, characterized in that: include: A plurality of semiconductor chips arranged in a stack, wherein a current semiconductor chip is stacked on a lower semiconductor chip; Each semiconductor chip has a number of interconnection layers, a number of insulating layers and a substrate; The interconnection layer is used to provide a conductive first region and a second region; the contours of adjacent etched grooves in the N layers of interconnection layers do not intersect each other in the stacking direction, and N is a positive integer greater than 2; The insulating layer is located between adjacent interconnect layers and is used to provide an insulating dielectric; The substrate of the current semiconductor chip has a first surface and a second surface arranged opposite to each other; the first surface is used to provide an attachment surface for an interconnection layer; and the second surface is used to abut against the interconnection layer on the top of the lower semiconductor chip.

2. The semiconductor device according to claim 1, wherein: The interconnection layer in each semiconductor chip is set to M layers, where M is greater than or equal to N; when M is equal to N, the contours of the etched grooves in the N layers of the interconnection layer do not intersect each other in the stacking direction.

3. The semiconductor device according to claim 2, characterized in that When M is greater than N, the contours of the etched grooves in the interconnection layer within the N layer intersect with the contours of the etched grooves in the interconnection layer outside the N layer.

4. The semiconductor device according to claim 1, wherein: The interconnection layer in each semiconductor chip has a first edge and a second edge opposite to each other, and the etching grooves in two adjacent interconnection layers are respectively close to the first edge and the second edge, so that the first areas and the second areas in the adjacent interconnection layers overlap alternately.

5. A semiconductor package, characterized in that: include: The semiconductor device according to any one of claims 1 to 4, and: A first conductive sealing end portion, used to connect to a first region of an interconnect layer in each semiconductor chip; The second conductive sealing end portion is used to connect the second region in the interconnection layer in each semiconductor chip; the first conductive sealing end portion and the second conductive sealing end portion are isolated from each other.

6. A semiconductor packaging method for forming the semiconductor device according to any one of claims 1 to 4, characterized in that: include: S1, providing a substrate, and forming an interconnection region at a portion where a conductor needs to be led out; S2, performing an etching process on a non-interconnected area on the surface where no conductor is required to be led out, so that the non-interconnected area is blocked by the etching groove into a first area and a second area; S3, forming an insulating layer on the surface of the interconnection layer; forming an interconnection layer on the upper surface of the insulating layer; S4, after repeating S2-S3 several times, S2 is executed again to form a semiconductor chip; the contours of adjacent etched grooves in the N layers of interconnection layers do not intersect each other in the stacking direction, and N is a positive integer greater than 2; S5, repeat S1-S4 L times, where L is a positive integer greater than 1; stack L layers of the semiconductor chips to form a semiconductor device.

7. The semiconductor packaging method according to claim 6, characterized in that: S5 also includes: thinning the semiconductor chips, and stacking L layers of thinned semiconductor chips to form a semiconductor device.

8. The semiconductor packaging method according to claim 6, wherein: S4 further includes: cutting or grinding the edges of the stacked interconnection layers to expose the first region and the second region of the interconnection layers in the semiconductor chip.

9. The semiconductor packaging method according to claim 8, characterized in that: Also includes: A first conductive sealing end portion is formed for connecting the first region in each interconnection layer, and a second conductive sealing end portion is formed for connecting the second region in each interconnection layer.

10. The semiconductor packaging method according to claim 9, characterized in that: The interconnection layer and the insulating layer are respectively formed by at least one of atomic layer deposition and chemical vapor deposition processes; the first conductive sealing end portion and the second conductive sealing end portion are formed by an electroplating process.

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