Overvoltage protection circuit

Abstract

The invention relates to the technical field of circuits, in particular to an overvoltage protection circuit which comprises a sampling module, a reference module, a comparison module, a starting module, a discharge module and a load module. The two ends of the sampling module, the two ends of the reference module, the two ends of the comparison module, the two ends of the starting module, the two ends of the discharge module and the two ends of the load module are connected with VCC power supply voltage and grounded respectively. The circuit structure of the overvoltage protection circuit does not need to use a voltage-regulator tube, the compatibility of the circuit is improved, the application range is large, the overvoltage protection circuit outputs the reference voltage based on the MOS tube and is not affected by the voltage of an external power supply, the reference voltage is stable, the anti-noise capability is high, and the overvoltage protection circuit is suitable for large-scale popularization and application. And when the voltage is judged to be too large, quick response and voltage discharge can be realized, so that the stability and the reliability of an overvoltage protection function are ensured.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to an overvoltage protection circuit. Background Art

[0002] With the development of electronic information technology, the application of various electronic devices and systems is becoming more and more extensive. However, with the increasing complexity of electrical and electronic systems, circuits are also facing various electrical interference and overvoltage problems. For this reason, it is necessary to design an overvoltage protection circuit inside the chip. When the overvoltage protection circuit detects that the external power supply voltage of the chip is higher than the maximum value it has set, the overvoltage protection circuit responds quickly and sends a logic control signal to shut down the chip to protect the entire circuit system.

[0003] like Figure 1 As shown, the reference voltage of the current traditional overvoltage protection circuit is provided by a voltage regulator tube, and the accuracy of the reference voltage is not high. Resistors R1 and R2 sample the power supply voltage VCC, and the sampled voltage is compared with the reference voltage through a comparator. The comparator outputs a signal to control the on and off of the switch tube M1, thereby controlling the discharge of the power supply voltage VCC to the ground. This method has poor anti-interference ability, and since voltage regulator tubes cannot be provided or there are no matching voltage regulator tubes in some processes, the application scope of this overvoltage protection circuit is relatively small. Summary of the invention

[0004] The invention aims to solve the technical problems that the existing overvoltage protection circuit has poor anti-interference ability and a small application range.

[0005] In order to solve the above technical problems, the present invention provides an overvoltage protection circuit, including a sampling module, a reference module, a comparison module, a startup module, a discharge module and a load module, wherein two ends of each of the sampling module, the reference module, the comparison module, the startup module, the discharge module and the load module are connected to a VCC power supply voltage and a ground respectively, wherein:

[0006] The sampling module is used to obtain a sampled voltage Va and send the sampled voltage Va to the comparison module, wherein the sampled voltage Va is positively correlated with the voltage of the VCC power supply voltage;

[0007] The reference module includes the reference module for outputting a reference voltage Vd to the comparison module;

[0008] The comparison module is used to compare the difference between the sampled voltage Va and the reference voltage Vd, and output a comparison voltage Ve;

[0009] The startup module is used to access the reference voltage Vd and feed back the output to the reference module;

[0010] The discharge module is used for comparing and judging the buffer voltage Vb with the comparison voltage Ve, and when the comparison voltage Ve is at a high level and the buffer voltage Vb is at a low level, discharging the voltage of the VCC power supply voltage through the ground terminal.

[0011] Furthermore, the sampling module includes a resistor R1 and a resistor R2, the first end of the resistor R1 is connected to the VCC power supply voltage, the second end of the resistor R1 is connected to the first end of the resistor R2, the second end of the resistor R2 is grounded, the sampling voltage Va is the voltage of the second end of the resistor R1, and the sampling voltage V a =R2*VCC / (R1+R2).

[0012] Furthermore, the reference module includes a MOS tube M5, a MOS tube M6, a MOS tube M7, a MOS tube M8 and a resistor R3, wherein the MOS tube M5 and the MOS tube M6 are NMOS tubes with the same length and width, and the MOS tube M7 and the MOS tube M8 are PMOS tubes with the same length and width;

[0013] The drain of the MOS tube M5 is connected to the drain of the MOS tube M7, the gate of the MOS tube M5 is connected to the drain of the MOS tube M7 and the gate of the MOS tube M6, and the source of the MOS tube M5 is grounded;

[0014] The drain of the MOS tube M6 is connected to the drain of the MOS tube M8 and the gate of the MOS tube M8 at the same time, and the source of the MOS tube M6 is connected to the first end of the resistor R3;

[0015] The second end of the resistor R3 is grounded;

[0016] The source of the MOS tube M7 is connected to the VCC power supply voltage, and the gate of the MOS tube M7 is connected to the gate of the MOS tube M8;

[0017] The source of the MOS tube M8 is connected to the VCC power supply voltage;

[0018] The reference voltage Vd is the voltage of the drain of the MOS tube M6. d =2(R3+r O6 ) / u n C ox (W / L)6R3R3, where r O Indicates the equivalent internal resistance of the MOS tube, u n , C ox They represent the electron mobility and gate oxide capacitance per unit area of ​​the MOS tube respectively, and W and L are the channel width and length of the MOS tube respectively.

[0019] Furthermore, the comparison module includes a MOS tube M10, a MOS tube M11, a MOS tube M12 and a MOS tube M13, wherein the MOS tube M10 and the MOS tube M11 are NMOS tubes, and the MOS tube M12 and the MOS tube M13 are PMOS tubes;

[0020] The gate of the MOS tube M10 is connected to the drain of the MOS tube M6 to access the reference voltage Vd, the source of the MOS tube M10 is grounded, and the drain of the MOS tube M10 is simultaneously connected to the drain of the MOS tube M12 and the gate of the MOS tube M12;

[0021] The gate of the MOS transistor M11 is connected to the second end of the resistor R1 to access the sampling voltage Va, the source of the MOS transistor M11 is grounded, and the drain of the MOS transistor M11 is connected to the drain of the MOS transistor M13;

[0022] The gate of the MOS tube M12 is connected to the gate of the MOS tube M13, and the source of the MOS tube M12 is connected to the VCC power supply voltage;

[0023] The source of the MOS tube M13 is connected to the VCC power supply voltage;

[0024] The comparison voltage Ve is the voltage of the drain of the MOS tube MO11. e =g m11 (r O11 / / r O13 )(V a -V d ), where g m Indicates the transconductance of the MOS tube.

[0025] Furthermore, the startup module includes a MOS tube M4, a MOS tube M2 and a MOS tube M3, wherein the MOS tube M4 is a PMOS tube, and the MOS tube M2 and the MOS tube M3 are NMOS tubes;

[0026] The source of the MOS tube M4 is connected to the VCC power supply voltage, the drain of the MOS tube M4 is connected to the drain and gate of the MOS tube M2, and the gate of the MOS tube M4 is connected to the reference voltage Vd;

[0027] The source of the MOS tube M2 is grounded, and the gate of the MOS tube M2 is connected to the gate of the MOS tube M3;

[0028] The source of the MOS tube M3 is grounded, and the drain of the MOS tube M3 is connected to the gate and drain of the MOS tube M8 at the same time.

[0029] Furthermore, the discharge module includes a MOS tube M9, a MOS tube M14, a MOS tube M15, a MOS tube M16 and a MOS tube M1, wherein the MOS tube M9, the MOS tube M14 and the MOS tube M15 are NMOS tubes, and the MOS tube M16 and the MOS tube M1 are PMOS tubes;

[0030] The source and drain of the MOS tube M9 are both grounded, and the gate of the MOS tube M9 is connected to the drain of the MOS tube MO11 to access the comparison voltage Ve;

[0031] The source of the MOS tube M14 is grounded, and the gate and drain of the MOS tube M14 are connected to the source of the MOS tube M15;

[0032] The gate of the MOS tube M15 is connected to the drain of the MOS tube MO11 to access the comparison voltage Ve, and the drain of the MOS tube M15 is simultaneously connected to the drain and gate of the MOS tube M16;

[0033] The source of the MOS tube 16 is connected to the VCC power supply voltage;

[0034] The gate of the MOS tube M1 is connected to the drain of the MOS tube M15, the drain of the MOS tube M1 is grounded, and the source of the MOS tube M1 is connected to the VCC power supply voltage;

[0035] The buffer voltage Vb is the voltage of the drain of the MOS tube M15.

[0036] The beneficial effect achieved by the present invention is that an overvoltage protection circuit is proposed, and the circuit structure of the overvoltage protection circuit does not need to use a voltage regulator tube, thereby improving the compatibility of the circuit and having a wider range of applications. In addition, the overvoltage protection circuit is based on a MOS tube to output a reference voltage, which is not affected by an external power supply voltage, so that the reference voltage is stable and has strong anti-noise capability. When it is judged that the voltage is too large, it can respond quickly and discharge the voltage, thereby ensuring the stability and reliability of the overvoltage protection function. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a schematic diagram of the structure of a traditional overvoltage protection circuit;

[0038] Figure 2 is a module schematic diagram of an overvoltage protection circuit provided by an embodiment of the present invention;

[0039] Figure 3 It is a structural schematic diagram of an overvoltage protection circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0041] Please refer to Figure 2 , Figure 2 1 is a schematic diagram of a module of an overvoltage protection circuit provided by an embodiment of the present invention. The embodiment of the present invention provides an overvoltage protection circuit 100, including a sampling module 101, a reference module 102, a comparison module 103, a startup module 104, a discharge module 105 and a load module 106. The sampling module 101, the reference module 102, the comparison module 103, the startup module 104, the discharge module 105 and the load module 106 are respectively connected to the VCC power supply voltage and the ground at both ends, wherein:

[0042] The sampling module 101 is used to obtain a sampled voltage Va and send the sampled voltage Va to the comparison module, wherein the sampled voltage Va is positively correlated with the voltage of the VCC power supply voltage;

[0043] The reference module 102 is used to output a reference voltage Vd to the comparison module 103;

[0044] The comparison module 103 is used to compare the difference between the sample voltage Va and the reference voltage Vd, and output a comparison voltage Ve;

[0045] The startup module 104 is used to access the reference voltage Vd and feed back the output to the reference module 102;

[0046] The discharge module 105 is used for comparing the buffer voltage Vb with the comparison voltage Ve, and when the comparison voltage Ve is at a high level and the buffer voltage Vb is at a low level, discharging the voltage of the VCC power supply voltage through the ground terminal.

[0047] The load module 106 is a target circuit structure for providing an overvoltage protection function for the overvoltage protection circuit 100 .

[0048] For details, please refer to Figure 3 , Figure 3 is a structural diagram of an overvoltage protection circuit provided by an embodiment of the present invention. The sampling module 101 includes a resistor R1 and a resistor R2. The first end of the resistor R1 is connected to the VCC power supply voltage, the second end of the resistor R1 is connected to the first end of the resistor R2, and the second end of the resistor R2 is grounded. The sampling voltage Va is the voltage of the second end of the resistor R1. Figure 3In the example, the access point of the sampling voltage Va is equivalent to point a, and the sampling voltage V a＝ R2*VCC / (R1+R2). Based on this relationship, it can be seen that when the VCC voltage increases, the sampling voltage Va at point a will also increase.

[0049] The reference module 102 includes a MOS transistor M5, a MOS transistor M6, a MOS transistor M7, a MOS transistor M8 and a resistor R3, wherein the MOS transistor M5 and the MOS transistor M6 are NMOS transistors with the same length and width, and the MOS transistor M7 and the MOS transistor M8 are PMOS transistors with the same length and width;

[0050] The drain of the MOS tube M5 is connected to the drain of the MOS tube M7, the gate of the MOS tube M5 is connected to the drain of the MOS tube M7 and the gate of the MOS tube M6, and the source of the MOS tube M5 is grounded;

[0051] The drain of the MOS tube M6 is connected to the drain of the MOS tube M8 and the gate of the MOS tube M8 at the same time, and the source of the MOS tube M6 is connected to the first end of the resistor R3;

[0052] The second end of the resistor R3 is grounded;

[0053] The source of the MOS tube M7 is connected to the VCC power supply voltage, and the gate of the MOS tube M7 is connected to the gate of the MOS tube M8;

[0054] The source of the MOS tube M8 is connected to the VCC power supply voltage;

[0055] The reference voltage Vd is the voltage of the drain of the MOS tube M6. Figure 3 In the example, the access point of the reference voltage Vd is equivalent to point d, and the reference voltage V d =2(R3+r O6 ) / u n C ox (W / L)6R3R3, where r O Indicates the equivalent internal resistance of the MOS tube, u n , C ox They represent the electron mobility and gate oxide capacitance per unit area of ​​the MOS tube, respectively, and W and L represent the channel width and length of the MOS tube, respectively. Based on this relationship, it can be seen that the output reference voltage Vd at point d is a fixed value and is not affected by the power supply voltage VCC.

[0056] The comparison module 103 includes a MOS transistor M10, a MOS transistor M11, a MOS transistor M12, and a MOS transistor M13, wherein the MOS transistor M10 and the MOS transistor M11 are NMOS transistors, and the MOS transistor M12 and the MOS transistor M13 are PMOS transistors;

[0057] The gate of the MOS tube M10 is connected to the drain of the MOS tube M6 to access the reference voltage Vd, the source of the MOS tube M10 is grounded, and the drain of the MOS tube M10 is simultaneously connected to the drain of the MOS tube M12 and the gate of the MOS tube M12;

[0058] The gate of the MOS transistor M11 is connected to the second end of the resistor R1 to access the sampling voltage Va, the source of the MOS transistor M11 is grounded, and the drain of the MOS transistor M11 is connected to the drain of the MOS transistor M13;

[0059] The gate of the MOS tube M12 is connected to the gate of the MOS tube M13, and the source of the MOS tube M12 is connected to the VCC power supply voltage;

[0060] The source of the MOS tube M13 is connected to the VCC power supply voltage;

[0061] The comparison voltage Ve is the voltage of the drain of the MOS tube MO11. Figure 3 In the example, the access point of the comparison voltage Ve is equivalent to point e, and the comparison voltage V e =g m11 (r O11 / / r O13 )(V a -V d ), where g m In the above structure, the comparison module 103 is a differential amplifier circuit, which can amplify and output the difference between the gate voltage Va of M11 and the gate voltage Vd of M10 from point e. From the above relationship, it can be seen that when the sampling voltage Va at point a increases, the comparison voltage Ve at point e will also increase.

[0062] The startup module 104 includes a MOS transistor M4, a MOS transistor M2 and a MOS transistor M3, wherein the MOS transistor M4 is a PMOS transistor, and the MOS transistor M2 and the MOS transistor M3 are NMOS transistors;

[0063] The source of the MOS tube M4 is connected to the VCC power supply voltage, the drain of the MOS tube M4 is connected to the drain and gate of the MOS tube M2, and the gate of the MOS tube M4 is connected to the reference voltage Vd;

[0064] The source of the MOS tube M2 is grounded, and the gate of the MOS tube M2 is connected to the gate of the MOS tube M3;

[0065] The source of the MOS tube M3 is grounded, and the drain of the MOS tube M3 is connected to the gate and drain of the MOS tube M8 at the same time.

[0066] Figure 3 In FIG. 1 , the point where the drain of the MOS tube M3 is connected to the reference module 102 is equivalent to point c.

[0067] The discharge module 105 includes a MOS tube M9, a MOS tube M14, a MOS tube M15, a MOS tube M16 and a MOS tube M1, wherein the MOS tube M9, the MOS tube M14 and the MOS tube M15 are NMOS tubes, and the MOS tube M16 and the MOS tube M1 are PMOS tubes;

[0068] The source and drain of the MOS tube M9 are both grounded, and the gate of the MOS tube M9 is connected to the drain of the MOS tube MO11 to access the comparison voltage Ve;

[0069] The source of the MOS tube M14 is grounded, and the gate and drain of the MOS tube M14 are connected to the source of the MOS tube M15;

[0070] The gate of the MOS tube M15 is connected to the drain of the MOS tube MO11 to access the comparison voltage Ve, and the drain of the MOS tube M15 is simultaneously connected to the drain and gate of the MOS tube M16;

[0071] The source of the MOS tube 16 is connected to the VCC power supply voltage;

[0072] The gate of the MOS tube M1 is connected to the drain of the MOS tube M15, the drain of the MOS tube M1 is grounded, and the source of the MOS tube M1 is connected to the VCC power supply voltage;

[0073] The buffer voltage Vb is the voltage of the drain of the MOS tube M15. Figure 3 In the discharge module 105, the drain and source of the NMOS tube M9 are grounded, and the gate is connected to point e, which is used as a capacitor to prevent the instantaneous fluctuation of point e from affecting M15 and causing false triggering; the gates and drains of M14 and M16 are connected, used as diodes, and together with M15 form a buffer stage circuit.

[0074] When the voltage in the overvoltage protection circuit 100 is normal, point e is at a low level, M15 is turned off, the voltage at point b is at a high level, M1 is turned off, and no voltage discharge is performed; when point e becomes a high level, M15 is turned on, the voltage at point b is at a low level, M1 is turned on, and the VCC voltage is directly discharged to the ground.

[0075] Based on the circuit structure of the overvoltage protection circuit 100, when VCC is a normal voltage, the voltage at point a of the sampling module 101 is at a low level, and the output voltage Vd of the reference module 103 is fixed. It can be seen from the expression of the comparison voltage Ve that the voltage at point e is at a low level at this time, that is, the gate voltage of the NOMS tube M15 in the discharge module 105 is at a low level, M15 is in the off state, the discharge module 103 does not work, and normally provides the power supply voltage VCC to the load module 106;

[0076] When VCC rises, the voltage at point a also rises, and the output voltage Vd of the reference module 103 remains unchanged. It can be seen from the expression of the comparison voltage Ve that the voltage Ve at point e, the output voltage of the comparison module 104, also rises. When VCC rises and exceeds the threshold value VCC1, the voltage Ve at point e rises and exceeds the turn-on threshold voltage Vth15+Vth14 of the NMOS tube M15 of the discharge module 105, and the discharge module 105 starts to work, and the voltage Vb at point b becomes a low level, the PMOS tube M1 is turned on, and the VCC voltage is directly discharged to GND, entering the overvoltage lock state, and the power supply voltage VCC does not pass through the load module 106, so as to achieve overvoltage protection;

[0077] When VCC decreases, the voltage at point a also decreases, and the output voltage Vd of the reference module 103 remains unchanged. From the expression of the comparison voltage Ve, it can be seen that the output voltage Ve at point e of the comparison module 104 also decreases. When VCC decreases below the threshold value VCC1, the voltage Ve at point e decreases below the turn-on threshold voltage Vth15+Vth14 of the NMOS tube M15 of the discharge module 105, M15 is turned off, the voltage Vb at point b becomes a high level, the PMOS tube M1 is turned off, the overvoltage lock state is released, and the VCC voltage can supply power to the load module 106 normally.

[0078] The beneficial effect achieved by the present invention is that an overvoltage protection circuit is proposed, and the circuit structure of the overvoltage protection circuit does not need to use a voltage regulator tube, thereby improving the compatibility of the circuit and having a wider range of applications. In addition, the overvoltage protection circuit is based on a MOS tube to output a reference voltage, which is not affected by an external power supply voltage, so that the reference voltage is stable and has strong anti-noise capability. When it is judged that the voltage is too large, it can respond quickly and discharge the voltage, thereby ensuring the stability and reliability of the overvoltage protection function.

[0079] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0080] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. An overvoltage protection circuit, characterized in that: It includes a sampling module, a reference module, a comparison module, a startup module, a discharge module and a load module, wherein two ends of each of the sampling module, the reference module, the comparison module, the startup module, the discharge module and the load module are connected to a VCC power supply voltage and ground respectively, wherein: The sampling module is used to obtain a sampled voltage Va and send the sampled voltage Va to the comparison module, wherein the sampled voltage Va is positively correlated with the voltage of the VCC power supply voltage; The reference module includes the reference module for outputting a reference voltage Vd to the comparison module; The comparison module is used to compare the difference between the sampled voltage Va and the reference voltage Vd, and output a comparison voltage Ve; The startup module is used to access the reference voltage Vd and feed back the output to the reference module; The discharge module is used for comparing and judging the buffer voltage Vb with the comparison voltage Ve, and when the comparison voltage Ve is at a high level and the buffer voltage Vb is at a low level, discharging the voltage of the VCC power supply voltage through the ground terminal.

2. The overvoltage protection circuit according to claim 1, characterized in that: The sampling module includes a resistor R1 and a resistor R2, wherein the first end of the resistor R1 is connected to the VCC power supply voltage, the second end of the resistor R1 is connected to the first end of the resistor R2, and the second end of the resistor R2 is grounded. The sampling voltage Va is the voltage at the second end of the resistor R1. a =R2*VCC / (R1+R2).

3. The overvoltage protection circuit according to claim 2, characterized in that: The reference module includes a MOS tube M5, a MOS tube M6, a MOS tube M7, a MOS tube M8 and a resistor R3, wherein the MOS tube M5 and the MOS tube M6 are NMOS tubes with the same length and width, and the MOS tube M7 and the MOS tube M8 are PMOS tubes with the same length and width; The drain of the MOS tube M5 is connected to the drain of the MOS tube M7, the gate of the MOS tube M5 is connected to the drain of the MOS tube M7 and the gate of the MOS tube M6, and the source of the MOS tube M5 is grounded; The drain of the MOS tube M6 is connected to the drain of the MOS tube M8 and the gate of the MOS tube M8 at the same time, and the source of the MOS tube M6 is connected to the first end of the resistor R3; The second end of the resistor R3 is grounded; The source of the MOS tube M7 is connected to the VCC power supply voltage, and the gate of the MOS tube M7 is connected to the gate of the MOS tube M8; The source of the MOS tube M8 is connected to the VCC power supply voltage; The reference voltage Vd is the voltage of the drain of the MOS tube M6. d =2(R3+r O6 ) / u n C ox (W / L)6R3R3, where r O Indicates the equivalent internal resistance of the MOS tube, u n , C ox They represent the electron mobility and gate oxide capacitance per unit area of ​​the MOS tube respectively, and W and L are the channel width and length of the MOS tube respectively.

4. The overvoltage protection circuit according to claim 3, characterized in that: The comparison module includes a MOS tube M10, a MOS tube M11, a MOS tube M12 and a MOS tube M13, wherein the MOS tube M10 and the MOS tube M11 are NMOS tubes, and the MOS tube M12 and the MOS tube M13 are PMOS tubes; The gate of the MOS tube M10 is connected to the drain of the MOS tube M6 to access the reference voltage Vd, the source of the MOS tube M10 is grounded, and the drain of the MOS tube M10 is simultaneously connected to the drain of the MOS tube M12 and the gate of the MOS tube M12; The gate of the MOS transistor M11 is connected to the second end of the resistor R1 to access the sampling voltage Va, the source of the MOS transistor M11 is grounded, and the drain of the MOS transistor M11 is connected to the drain of the MOS transistor M13; The gate of the MOS tube M12 is connected to the gate of the MOS tube M13, and the source of the MOS tube M12 is connected to the VCC power supply voltage; The source of the MOS tube M13 is connected to the VCC power supply voltage; The comparison voltage Ve is the voltage of the drain of the MOS tube MO11. e =g m11 (r O11 / / r O13 )(V a -V d ), where g m Indicates the transconductance of the MOS tube.

5. The overvoltage protection circuit according to claim 4, characterized in that: The startup module includes a MOS tube M4, a MOS tube M2 and a MOS tube M3, wherein the MOS tube M4 is a PMOS tube, and the MOS tube M2 and the MOS tube M3 are NMOS tubes; The source of the MOS tube M4 is connected to the VCC power supply voltage, the drain of the MOS tube M4 is connected to the drain and gate of the MOS tube M2, and the gate of the MOS tube M4 is connected to the reference voltage Vd; The source of the MOS tube M2 is grounded, and the gate of the MOS tube M2 is connected to the gate of the MOS tube M3; The source of the MOS tube M3 is grounded, and the drain of the MOS tube M3 is connected to the gate and drain of the MOS tube M8 at the same time.

6. The overvoltage protection circuit according to claim 5, characterized in that: The discharge module includes a MOS tube M9, a MOS tube M14, a MOS tube M15, a MOS tube M16 and a MOS tube M1, wherein the MOS tube M9, the MOS tube M14 and the MOS tube M15 are NMOS tubes, and the MOS tube M16 and the MOS tube M1 are PMOS tubes; The source and drain of the MOS tube M9 are both grounded, and the gate of the MOS tube M9 is connected to the drain of the MOS tube MO11 to access the comparison voltage Ve; The source of the MOS tube M14 is grounded, and the gate and drain of the MOS tube M14 are connected to the source of the MOS tube M15; The gate of the MOS tube M15 is connected to the drain of the MOS tube MO11 to access the comparison voltage Ve, and the drain of the MOS tube M15 is simultaneously connected to the drain and gate of the MOS tube M16; The source of the MOS tube 16 is connected to the VCC power supply voltage; The gate of the MOS tube M1 is connected to the drain of the MOS tube M15, the drain of the MOS tube M1 is grounded, and the source of the MOS tube M1 is connected to the VCC power supply voltage; The buffer voltage Vb is the voltage of the drain of the MOS tube M15.

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