A digital IGBT drive circuit based on FPGA and its control method

Abstract

The present invention provides a digital IGBT drive circuit based on FPGA and a control method thereof, wherein the drive circuit comprises an FPGA, an upper and lower bridge arm overcurrent detection protection circuit, an upper and lower bridge arm overvoltage detection protection circuit, and an upper and lower bridge arm optocoupler isolation circuit; the FPGA comprises a filtering module, an error control signal detection module, a logic control module, a fault identification and feedback module, and a mode selection module; the present invention realizes safe and effective overcurrent and overvoltage fault detection and protection through hardware detection of the drive circuit and software control strategy of the FPGA, while ensuring isolation of control signals of the primary and secondary sides, and isolation of high voltage and low voltage, ensuring normal operation of the drive circuit and the host computer on the low voltage side when a fault occurs, and ensuring the safety of the drive circuit; realizing digital drive of the IGBT, intelligent management of drive faults and identification, and flexibility of application scenarios, providing possibility for digital and intelligent large-scale IGBT drive management.

Description

Technical Field

[0001] The present invention belongs to the field of IGBT drive circuits, and specifically relates to a digital IGBT drive circuit based on FPGA and a control method thereof. Background Art

[0002] The IGBT drive circuit is a circuit that controls the on and off of the IGBT. In the fields of aerospace systems, rail transit systems, new energy vehicles, and industry, the reliable drive of the motor is crucial to the normal operation of the system, and the IGBT drive circuit is the key circuit for motor drive, so the reliability of the IGBT drive circuit is also very important.

[0003] In aerospace motor systems, due to the upgrading of application requirements and the increase in motor power levels, the corresponding operating voltage and current also increase accordingly. The bus voltage of the motor system increases from the common 240-270V to 500-600V. In the future, the operating voltage will be further increased to 800-900V, and the phase current will increase from tens of amperes to more than 400A. Therefore, the safety requirements of the drive system and drive circuit also increase accordingly.

[0004] At present, whether in the industrial field or aerospace field, digitalization and intelligence are the major development trends in these fields. At present, the IGBT drive circuit is mainly based on the integrated drive chip. The main advantage of the integrated drive chip is the simple design of the peripheral circuit, but the function type of the drive circuit is limited by the function type of the drive chip. Therefore, the IGBT drive circuit based on the integrated drive chip lacks certain flexibility.

[0005] In the current aerospace motor system applications, IGBT devices are used in parts including aviation static converters, transformer rectifiers, converters, motor drivers, etc., and each device has a corresponding drive circuit. Therefore, the number of drive circuits is relatively large, and it is also a relatively complex task to realize real-time status monitoring and fault management of these drive circuits. Through the identification of fault types, feedback of occurrence frequency and data collection, it is not only possible to evaluate the stability of the entire system, but also to guide the selection of devices and the design improvement of devices. Similarly, in the process of a large number of devices running at the same time, multiple control signals need to be input at the same time. Since the quality of the control signal provided by the host computer cannot be guaranteed or the control signal is interfered, narrow pulses and erroneous control signals may directly act on the IGBT device, causing it to be triggered incorrectly or have high voltage spikes or high-frequency oscillation problems, thereby posing a huge safety threat. Therefore, it is also crucial to carry out an integrated design of the entire drive circuit system, including status monitoring, fault management, and control signal inspection. However, the integrated driver chip cannot identify the fault signal of the subsequent circuit, intelligently feedback, and cannot perform more complex processing on the input signal, so it is impossible to realize intelligent monitoring and digital management of the entire system.

[0006] At the same time, when the motor system is working, the power end voltage is higher and is called the high voltage side, while the drive circuit side voltage is relatively lower and is called the low voltage side. In order to ensure that the control end of the low voltage side can work normally when the motor system is in an abnormal working state, that is, when a high voltage and a large current occur on the high voltage side, the circuit needs to be safely isolated to improve the reliability of the drive circuit. Therefore, there is an urgent need to design a high-reliability IGBT drive circuit that can meet the trend of intelligence and digitalization.

[0007] The Chinese patent with publication number CN 106209040B discloses a high-reliability IGBT driving circuit based on FPGA, which makes the driving circuit output an intermediate level between +14.5V and +7V, such as +9V, for a short period of time instead of directly outputting -8V to shut down after receiving a low-level input, and then outputs -8V to shut down. Since the collector current of the IGBT is proportional to the gate turn-on voltage, the +9V gate level will limit the collector current of the IGBT to a lower value. When the driving circuit then outputs -8V to shut down the IGBT, the current change rate generated will not be too large, that is, the peak voltage is suppressed, protecting the safety of the IGBT; but the disclosed patent has the following defects:

[0008] The defects of the hardware module are as follows: (1) The high-voltage side and the low-voltage side of the drive circuit are not isolated, and the safety and reliability of the drive are not guaranteed. Once a fault occurs on the high-voltage side, it may cause the drive circuit and the input signal end to be completely destroyed and fail, the IGBT control to fail, and cause the machine to explode or other major accidents; (2) It mainly suppresses the high voltage that may appear during the IGBT shutdown process, and does not set up a special circuit to detect and feedback overcurrent, overvoltage and other faults; and does not respond to various faults accordingly;

[0009] The defects of the software module are as follows: (1) There is no fault management function, including fault identification and fault reporting, as well as fault frequency record storage. It is still lacking in the intelligence of the driving circuit and is not suitable for intelligent management in large-scale IGBT application scenarios; (2) It only drives a single IGBT, and the applicable scenarios are limited. The control of half-bridge and full-bridge IGBT modules is more complicated. Therefore, this method is not suitable for the driving circuit of half-bridge and full-bridge IGBT modules; (3) It does not take into account the control failure that may be caused by the quality problem of the input control signal. Summary of the invention

[0010] In order to solve the above technical problems, the present invention provides a digital IGBT driving circuit based on FPGA;

[0011] In order to solve the above technical problems, the present invention provides a control method for a digital IGBT drive circuit based on FPGA.

[0012] The present invention is achieved through the following technical solutions.

[0013] The present invention provides a digital IGBT drive circuit based on FPGA, comprising an FPGA, wherein the FPGA is connected to an upper bridge arm overcurrent detection protection circuit, a lower bridge arm overcurrent detection protection circuit, an upper bridge arm overvoltage detection protection circuit, a lower bridge arm overvoltage detection protection circuit, an upper bridge arm optocoupler isolation circuit, and a lower bridge arm optocoupler isolation circuit; the upper bridge arm optocoupler isolation circuit and the lower bridge arm optocoupler isolation circuit are also connected to an upper bridge arm push-pull circuit and a lower bridge arm push-pull circuit, respectively; the upper bridge arm overvoltage detection protection circuit and the lower bridge arm overvoltage detection protection circuit are also connected to an upper bridge arm push-pull circuit and a lower bridge arm push-pull circuit, respectively;

[0014] The FPGA includes a filtering module, an error control signal detection module, a logic control module, and a fault identification and feedback module which are connected in sequence; the logic control module is also connected to the output end of the mode selection module, the upper bridge arm optocoupler isolation circuit and the lower bridge arm optocoupler isolation circuit; the filtering module is also connected to the upper bridge arm control signal IN_1 and the lower bridge arm control signal IN_2; the fault identification and feedback module is connected to the upper bridge arm overcurrent detection protection circuit, the lower bridge arm overcurrent detection protection circuit, the upper bridge arm overvoltage detection protection circuit, the lower bridge arm overvoltage detection protection circuit and the working state ends of the upper bridge arm and the lower bridge arm of the host computer; the input end of the mode selection module is connected to the mode selection signal end of the external input.

[0015] The upper bridge arm overcurrent detection protection circuit includes a high-voltage diode D1, a resistor R2, a resistor R3, a capacitor C1, a comparator A1 and an optical coupler C2;

[0016] The anode of the high-voltage diode D1 is connected to the resistor R2, the resistor R3, one end of the capacitor C1, and the inverting input end of the comparator A1, and the cathode is connected to the collector C1 of the upper bridge arm IGBT and the bus voltage end; the other end of the resistor R2 is connected to the positive power supply VCC_1, and the other ends of the capacitor C1 and the resistor R3 are connected to the power ground GND_1; the non-inverting input end of the comparator A1 is connected to the reference voltage, and the output end is connected to the cathode of the primary light-emitting diode of the optocoupler C2; the anode of the primary light-emitting diode of the optocoupler C2 is connected to the positive power supply VCC_1, the secondary collector is connected to the positive power supply VCC, the secondary emitter is connected to the power ground GND, and the secondary output end is connected to the fault identification and feedback module.

[0017] The lower bridge arm overcurrent detection protection circuit includes a high-voltage diode D2, a resistor R5, a resistor R6, a capacitor C2, a comparator A2 and an optical coupler C7;

[0018] The anode of the high-voltage diode D2 is connected to the resistor R5, the resistor R6, one end of the capacitor C2, and the inverting input terminal of the comparator A2, and the cathode is connected to the collector C2 of the lower bridge arm IGBT and the emitter E1 of the upper bridge arm IGBT; the other end of the resistor R5 is connected to the positive power supply VCC_2, and the other ends of the capacitor C2 and the resistor R6 are connected to the power ground GND_2; the non-inverting input terminal of the comparator A2 is connected to the reference voltage, and the output terminal is connected to the cathode of the primary light-emitting diode of the optocoupler C7; the anode of the primary light-emitting diode of the optocoupler C7 is connected to the positive power supply VCC_2, the secondary collector is connected to the positive power supply VCC, the secondary emitter is connected to the power ground GND, and the secondary output terminal is connected to the fault identification and feedback module.

[0019] The upper bridge arm overvoltage detection protection circuit includes a transient suppression diode TD1, a fast recovery diode SD1, an N-type transistor N1, a resistor R1 and an optocoupler C1; the anode of the fast recovery diode SD1 is connected to the base of the N-type transistor N1 and the anode of the transient suppression diode TD1, the cathode is connected to the driving resistor R1 and one end of the resistor R4, and the gate of the upper bridge arm IGBT, and the other end of the resistor R4 is connected to the emitter E1 of the upper bridge arm IGBT; the emitter of the N-type transistor N1 is connected to the power ground GND_1, the collector is connected to one end of the resistor R1 and the cathode of the primary light-emitting diode of the optocoupler C1; the other end of the resistor R1 is connected to the positive power supply VCC_1; the cathode of the transient suppression diode TD1 is connected to the collector C1 of the upper bridge arm IGBT; the secondary collector of the optocoupler C1 is connected to the positive power supply VCC, the secondary emitter is connected to the power ground GND, and the secondary output end is connected to the fault identification and feedback module.

[0020] The lower bridge arm overvoltage detection protection circuit includes a transient suppression diode TD2, a fast recovery diode SD2, an N-type transistor N2, a resistor R8 and an optocoupler C8; the anode of the fast recovery diode SD2 is connected to the base of the N-type transistor N2 and the anode of the transient suppression diode TD2, the cathode is connected to the driving resistor R2 and one end of the resistor R7, and the gate of the lower bridge arm IGBT, the other end of the resistor R7 is connected to the emitter E2 of the lower bridge arm IGBT and then to the power ground GND; the emitter of the N-type transistor N2 is connected to the power ground GND_2, the collector is connected to one end of the resistor R8 and the cathode of the primary light emitting diode of the optocoupler C8; the other end of the resistor R8 is connected to the positive power supply VCC_2; the cathode of the transient suppression diode TD2 is connected to the collector C2 of the lower bridge arm IGBT; the secondary collector of the optocoupler C8 is connected to the positive power supply VCC, the secondary emitter is connected to the power ground GND, and the secondary output end is connected to the fault identification and feedback module.

[0021] The upper bridge arm optocoupler isolation circuit includes an N-type MOS tube M1, an N-type MOS tube M2, an optocoupler C3 and an optocoupler C4; the anode of the primary side light emitting diode of the optocoupler C3 is connected to the positive power supply VCC, the cathode is connected to the drain of the N-type MOS tube M1, the gate of the N-type MOS tube M1 is connected to the logic control module, and the source of the N-type MOS tube M1 is connected to the power ground GND; the secondary side collector of the optocoupler C3 is connected to the positive power supply VCC_1, and the emitter is connected to the power ground GND_1; the anode of the primary side light emitting diode of the optocoupler C4 is connected to the positive power supply VCC, the cathode is connected to the drain of the N-type MOS tube M2, the gate of the N-type MOS tube M2 is connected to the logic control module, and the source of the N-type MOS tube M2 is connected to the power ground GND; the secondary side collector of the optocoupler C4 is connected to the positive power supply VCC_1, and the emitter is connected to the negative power supply VEE_1;

[0022] The lower bridge arm optocoupler isolation circuit includes an N-type MOS tube M3, an N-type MOS tube M4, an optocoupler C5 and an optocoupler C6; the anode of the primary side light emitting diode of the optocoupler C5 is connected to the positive power supply VCC, the cathode is connected to the drain of the N-type MOS tube M3, the gate of the N-type MOS tube M3 is connected to the logic control module, and the source of the N-type MOS tube M3 is connected to the power ground GND; the secondary side collector of the optocoupler C5 is connected to the positive power supply VCC_2, and the emitter is connected to the power ground GND_2; the anode of the primary side light emitting diode of the optocoupler C6 is connected to the positive power supply VCC, the cathode is connected to the drain of the N-type MOS tube M4, the gate of the N-type MOS tube M4 is connected to the logic control module, and the source of the N-type MOS tube M4 is connected to the power ground GND; the secondary side collector of the optocoupler C6 is connected to the positive power supply VCC_2, and the emitter is connected to the negative power supply VEE_2.

[0023] The upper bridge arm push-pull circuit includes a P-type MOS tube MP1, an N-type MOS tube M5 and an N-type MOS tube M7; the gate of the P-type MOS tube MP1 is connected to the secondary side output end of the optical coupler C3 and the gate of the N-type MOS tube M7, the source is connected to the +15V power supply, and the drain is connected to the drain of the N-type MOS tube M7, the drain of the N-type MOS tube M5 and the other end of the driving resistor R1; the source of the N-type MOS tube M5 is connected to the -9V power supply, and the gate is connected to the secondary side output end of the optical coupler C4; the source of the N-type MOS tube M7 is connected to the power ground GND_1;

[0024] The lower bridge arm push-pull circuit includes a P-type MOS tube MP2, an N-type MOS tube M6 and an N-type MOS tube M8; the gate of the P-type MOS tube MP2 is connected to the secondary side output end of the optical coupler C5 and the gate of the N-type MOS tube M8, the source is connected to the +15V power supply, and the drain is connected to the drain of the N-type MOS tube M8, the drain of the N-type MOS tube M6 and the other end of the driving resistor R2; the source of the N-type MOS tube M6 is connected to the -9V power supply, and the gate is connected to the secondary side output end of the optical coupler C6; the source of the N-type MOS tube M8 is connected to the power ground GND_2.

[0025] A control method for a digital IGBT drive circuit based on FPGA, including the following modes:

[0026] Mode 1: Independent mode, the upper bridge arm control signal and the lower bridge arm control signal are determined to be independent of each other through the upper bridge arm control signal IN_1 and the lower bridge arm control signal IN_2;

[0027] Mode 2: Complementary mode, the FPGA analyzes the upper bridge arm control signal IN_1 to generate symmetrical and complementary upper bridge arm and lower bridge arm control signals;

[0028] Mode 3: Fault identification mode. The fault identification and feedback module collects the status of the IGBT and analyzes and processes it, then feeds back the fault category to the host computer. At the same time, the logic control module makes a corresponding control signal output to realize the processing of the IGBT fault status.

[0029] The specific steps of Mode 1 are:

[0030] Step 101: The upper bridge arm control signal IN_1 and the lower bridge arm control signal IN_2 are input into the FPGA and filtered by the filtering module to achieve narrow pulse suppression;

[0031] Step 102: The error control signal detection module detects the filtered upper bridge arm control signal IN_1 and the lower bridge arm control signal IN_2, and determines whether the two control signals are correct; specifically:

[0032] Step 1021: When the two control signals detected by the error control signal detection module are both at high levels, the two control signals are error control signals, and the FPGA outputs control signals for shutting down the upper bridge arm IGBT and the lower bridge arm IGBT to ensure the safety of the IGBT and the entire system;

[0033] Step 1022: When the two control signals detected by the error control signal detection module are not both at high levels, the two control signals are correct control signals, which are input to the logic control module for processing and analysis. The two control signals after processing and analysis are converted into four hardware control signals to control the N-type MOS tubes M1, M2, M3, and M4 respectively.

[0034] The specific steps of Mode 2 are:

[0035] Step 201: The upper bridge arm control signal IN_1 is input into the FPGA and filtered by the filtering module to achieve narrow pulse suppression;

[0036] Step 202: The logic control module analyzes the filtered upper bridge arm control signal IN_1 and generates a complementary lower bridge arm control signal IN_2 with a dead zone, and then converts the upper bridge arm control signal IN_1 and the lower bridge arm control signal IN_2 into four hardware control signals through processing and analysis to control the N-type MOS tubes M1, M2, M3, and M4 respectively.

[0037] The specific steps of Mode 3 are:

[0038] Step 301: When the IGBT is in a short circuit or overcurrent state, the voltage at the inverting input terminal of the comparator A1 or A2 is greater than the set reference voltage, and the comparator A1 or A2 outputs a low level, and the optocoupler C2 or C7 outputs a high level. After the high level is collected and analyzed by the fault identification and feedback module, the FPGA feeds back the specific fault type to the upper computer and records the number of faults. At the same time, the logic control module outputs a soft shutdown control signal to turn on the N-type MOS tube M7 or M8 to achieve the safe shutdown function of the IGBT;

[0039] Step 302: When the IGBT is in an overvoltage state, the transient suppression diode TD1 or the transient suppression diode TD2 is first broken down. At this time, the N-type transistor N1 or the N-type transistor N2 is turned on, and the optocoupler C1 or the optocoupler C2 outputs a high level. After the high level is collected and analyzed by the fault identification and feedback module, the FPGA feeds back the specific fault type to the upper computer and records the number of faults. At the same time, the logic control module outputs a direct shutdown control signal to turn on the N-type MOS tube M5 or M6 to achieve the safe shutdown function of the IGBT.

[0040] The beneficial effects of the present invention are as follows: 1) through the hardware detection of the driving circuit and the software control strategy of the FPGA, based on simple triodes, diodes and optocouplers, safe and effective over-current and over-voltage fault detection and protection are achieved, while ensuring the isolation of the primary side and the secondary side, ensuring that the control circuit and the host computer on the low-voltage side work normally when a fault occurs, and avoiding the transmission of the fault on the high-voltage side to the low-voltage side; based on MOS tubes and optocouplers, the isolated transmission of control signals is achieved, ensuring the isolation of the primary side and the secondary side, and ensuring the safety of the control circuit;

[0041] 2) In order to improve the digitization and intelligence of the drive circuit, the FPGA-based digital IGBT drive control method is equipped with an error control signal detection module to filter the possible poor quality of the control signal, that is, the narrow pulse, to improve the quality and stability of the control signal and avoid the wrong control of the IGBT on and off; an error control signal detection module is set to detect the correctness of the control signal to avoid the safety accidents caused by the direct connection of the upper and lower bridge arms of the IGBT; a mode selection module is set to provide two working modes, independent mode and complementary mode, to provide more flexibility for application scenarios; a fault identification and feedback module is set to perform real-time detection of the subsequent circuit, identify the fault type, record the number of faults, and promptly feedback the fault information to the host computer and make control actions set according to the application scenario at the same time;

[0042] 3) The fault category and frequency information fed back by the fault feedback module plays an important role in large-scale IGBT application scenarios. It can be used to evaluate the stability of the entire system and guide the selection of IGBT brands and specifications. At the same time, the collected fault information can also reflect IGBT design defects to a certain extent, and guide the design of IGBT chips and IGBT packages. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a circuit structure principle diagram of the present invention;

[0044] Figure 2 It is a schematic diagram of input and output waveforms of the filter module of the present invention;

[0045] Figure 3 It is a schematic diagram of the dead time of the MOS control signal output by the FPGA of the present invention. DETAILED DESCRIPTION

[0046] The technical solution of the present invention is further described below, but the scope of protection claimed is not limited to the description.

[0047] like Figure 1 The circuit structure principle diagram of the present invention is shown as follows; a digital IGBT drive circuit based on FPGA, comprising an FPGA, wherein the FPGA is connected to an upper bridge arm overcurrent detection protection circuit, a lower bridge arm overcurrent detection protection circuit, an upper bridge arm overvoltage detection protection circuit, a lower bridge arm overvoltage detection protection circuit, an upper bridge arm optocoupler isolation circuit, and a lower bridge arm optocoupler isolation circuit; the upper bridge arm optocoupler isolation circuit and the lower bridge arm optocoupler isolation circuit are also connected to an upper bridge arm push-pull circuit and a lower bridge arm push-pull circuit, respectively; the upper bridge arm overvoltage detection protection circuit and the lower bridge arm overvoltage detection protection circuit are also connected to an upper bridge arm push-pull circuit and a lower bridge arm push-pull circuit, respectively;

[0048] The FPGA includes a filter module, an error control signal detection module, a logic control module, and a fault identification and feedback module connected in sequence; the logic control module is also connected to the output end of the mode selection module, the upper bridge arm optical coupling isolation circuit and the lower bridge arm optical coupling isolation circuit; the filter module is also connected to the upper bridge arm control signal IN_1 and the lower bridge arm control signal IN_2; the fault identification and feedback module is connected to the upper bridge arm overcurrent detection protection circuit, the lower bridge arm overcurrent detection protection circuit, the upper bridge arm overvoltage detection protection circuit, the lower bridge arm overvoltage detection protection circuit and the upper bridge arm and lower bridge arm working state ends of the host computer; the input end of the mode selection module is connected to the mode selection signal end of the external input;

[0049] Specifically, the upper bridge arm control signal IN_1 and the lower bridge arm control signal IN_2 are input to the filter module in the FPGA. The filter module stores a certain length of control signal through a shift register, checks each control signal, and filters the narrow pulse if a narrow pulse narrower than the set width appears. Figure 2 The input and output waveform diagram of the filter module of the present invention shown in the figure has a preferred comparison width of more than several hundred ns, which can be adjusted accordingly according to actual working conditions.

[0050] The upper bridge arm overcurrent detection protection circuit includes a high-voltage diode D1, a resistor R2, a resistor R3, a capacitor C1, a comparator A1 and an optical coupler C2;

[0051] The anode of the high-voltage diode D1 is connected to the resistor R2, the resistor R3, one end of the capacitor C1, and the inverting input end of the comparator A1, and the cathode is connected to the collector C1 of the upper bridge arm IGBT and the bus voltage end; the other end of the resistor R2 is connected to the positive power supply VCC_1, and the other ends of the capacitor C1 and the resistor R3 are connected to the power ground GND_1; the non-inverting input end of the comparator A1 is connected to the reference voltage, and the output end is connected to the cathode of the primary light-emitting diode of the optocoupler C2; the anode of the primary light-emitting diode of the optocoupler C2 is connected to the positive power supply VCC_1, the secondary collector is connected to the positive power supply VCC, the secondary emitter is connected to the power ground GND, and the secondary output end is connected to the fault identification and feedback module;

[0052] The lower bridge arm overcurrent detection protection circuit includes a high-voltage diode D2, a resistor R5, a resistor R6, a capacitor C2, a comparator A2 and an optical coupler C7;

[0053] The anode of the high-voltage diode D2 is connected to the resistor R5, the resistor R6, one end of the capacitor C2, and the inverting input end of the comparator A2, and the cathode is connected to the collector C2 of the lower bridge arm IGBT and the emitter E1 of the upper bridge arm IGBT; the other end of the resistor R5 is connected to the positive power supply VCC_2, and the other ends of the capacitor C2 and the resistor R6 are connected to the power ground GND_2; the non-inverting input end of the comparator A2 is connected to the reference voltage, and the output end is connected to the cathode of the primary light-emitting diode of the optical coupler C7; the anode of the primary light-emitting diode of the optical coupler C7 is connected to the positive power supply VCC_2, the secondary collector is connected to the positive power supply VCC, the secondary emitter is connected to the power ground GND, and the secondary output end is connected to the fault identification and feedback module;

[0054] Specifically, Table 1 shows the FPGA control signal truth table of the present invention:

[0055] Table 1

[0056]

[0057] "10" indicates that the signal output by the FPGA is a soft shutdown control signal; when an overcurrent occurs in the IGBT, the high-voltage diode D1 or D2 is cut off, and the power supply VCC_1 forms a loop through the resistors R2 and R3 to GND_1 or the resistors R5 and R6 to GND_2. The capacitor C1 or C2 is used as a filter capacitor. At this time, the inverting terminal voltage of the comparator A1 or A2 is the voltage on the resistor R3 or the resistor R6. At this time, the inverting terminal voltage is greater than the reference voltage of the non-phase terminal of the comparator A1 or A2. The comparator A1 or A2 outputs a low level, and the primary side of the optocoupler C2 or C7 forms a current loop. The secondary side of the optocoupler C2 or C7 outputs a high level, which is input into the fault identification and feedback module of the FPGA. After receiving the overcurrent fault, the fault identification and feedback module quickly feeds back the overcurrent fault to the upper computer. At the same time, the logic control module immediately outputs a soft shutdown control signal to turn on the soft shutdown N-type MOS tube M7 or M8, control the gate potential at 0V, slow down the current drop rate, and then the FPGA outputs a normal shutdown signal to safely shut down the IGBT. At this time, the FPGA shields the input signal, and any input signal will not generate any output. When the upper computer inputs the control signal to the FPGA for a certain period of time, the drive circuit resumes normal operation. Preferably, the duration is more than 50ms;

[0058] Preferably, the reference voltage is selected to be about 7-8V, and the reference voltage is comprehensively considered according to the actual IGBT performance and safety margin design, because IGBTs of different voltage levels have different parameter characteristics. The insulation withstand voltage level of the optocoupler is preferably above 5000V to ensure safe isolation between the high-voltage side and the low-voltage side.

[0059] The upper bridge arm overvoltage detection protection circuit includes a transient suppression diode TD1, a fast recovery diode SD1, an N-type transistor N1, a resistor R1 and an optocoupler C1; the anode of the fast recovery diode SD1 is connected to the base of the N-type transistor N1 and the anode of the transient suppression diode TD1, the cathode is connected to the driving resistor R1 and one end of the resistor R4, and the gate of the upper bridge arm IGBT, and the other end of the resistor R4 is connected to the emitter E1 of the upper bridge arm IGBT; the emitter of the N-type transistor N1 is connected to the power ground GND_1, the collector is connected to one end of the resistor R1 and the cathode of the primary light emitting diode of the optocoupler C1; the other end of the resistor R1 is connected to the positive power supply VCC_1; the cathode of the transient suppression diode TD1 is connected to the collector C1 of the upper bridge arm IGBT; the secondary collector of the optocoupler C1 is connected to the positive power supply VCC, the secondary emitter is connected to the power ground GND, and the secondary output end is connected to the fault identification and feedback module;

[0060] Specifically, the cathode of the fast recovery diode SD1 is connected to the driving resistor R1 and one end of the resistor R4, serving as the output terminal OUT1 of the FPGA-based digital IGBT driving circuit, and the output terminal OUT1 provides a driving signal for the upper bridge arm of the half-bridge IGBT module;

[0061] The lower bridge arm overvoltage detection protection circuit includes a transient suppression diode TD2, a fast recovery diode SD2, an N-type transistor N2, a resistor R8 and an optocoupler C8; the anode of the fast recovery diode SD2 is connected to the base of the N-type transistor N2 and the anode of the transient suppression diode TD2, the cathode is connected to the driving resistor R2 and one end of the resistor R7, and the gate of the lower bridge arm IGBT, the other end of the resistor R7 is connected to the emitter E2 of the lower bridge arm IGBT and then to the power ground GND; the emitter of the N-type transistor N2 is connected to the power ground GND_2, the collector is connected to one end of the resistor R8 and the cathode of the primary light emitting diode of the optocoupler C8; the other end of the resistor R8 is connected to the positive power supply VCC_2; the cathode of the transient suppression diode TD2 is connected to the collector C2 of the lower bridge arm IGBT; the secondary collector of the optocoupler C8 is connected to the positive power supply VCC, the secondary emitter is connected to the power ground GND, and the secondary output end is connected to the fault identification and feedback module;

[0062] Specifically, the cathode of the fast recovery diode SD2 is connected to the driving resistor R2 and one end of the resistor R7, serving as the output terminal OUT2 of the FPGA-based digital IGBT driving circuit, and the output terminal OUT2 provides a driving signal for the lower bridge arm of the half-bridge IGBT module;

[0063] Specifically, refer to the FPGA control signal truth table of the present invention shown in Table 1; "11" indicates that the signal output by the FPGA is a direct shutdown control signal; when the host computer control signal is a shutdown signal, the FPGA turns on the N-type MOS tube M5 or M6 and turns off the IGBT by outputting a hardware signal; when an overvoltage fault occurs in the IGBT, the transient suppression diode TD1 or TD2 will be broken down, and the fast recovery diode SD1 or SD2 will be turned on, providing current to the gate to slow down the IGBT shutdown and achieve high voltage spike suppression. At the same time, the N-type transistor N1 or N2 is turned on, the primary side of the optocoupler C1 or C8 forms a loop, and the secondary side of the optocoupler C1 or C8 outputs a high potential input to the fault identification and feedback module; after receiving the overcurrent fault, the fault identification and feedback module quickly feeds back the overvoltage fault to the host computer, and at the same time, the logic control module immediately outputs a direct shutdown control signal to turn on the N-type MOS tube M5 or M6, and then outputs a shutdown control signal to safely turn off the IGBT;

[0064] Preferably, the transient suppression diode withstand voltage TD1 or TD2 level is selected according to the IGBT voltage level and actual operating conditions, and the voltage level of the transient suppression diode withstand voltage TD1 or TD2 should be less than or equal to the maximum operating voltage of the IGBT designed according to the design operating conditions.

[0065] The upper bridge arm optocoupler isolation circuit includes an N-type MOS tube M1, an N-type MOS tube M2, an optocoupler C3 and an optocoupler C4; the anode of the primary side light emitting diode of the optocoupler C3 is connected to the positive power supply VCC, the cathode is connected to the drain of the N-type MOS tube M1, the gate of the N-type MOS tube M1 is connected to the logic control module, and the source of the N-type MOS tube M1 is connected to the power ground GND; the secondary side collector of the optocoupler C3 is connected to the positive power supply VCC_1, and the emitter is connected to the power ground GND_1; the anode of the primary side light emitting diode of the optocoupler C4 is connected to the positive power supply VCC, the cathode is connected to the drain of the N-type MOS tube M2, the gate of the N-type MOS tube M2 is connected to the logic control module, and the source of the N-type MOS tube M2 is connected to the power ground GND; the secondary side collector of the optocoupler C4 is connected to the positive power supply VCC_1, and the emitter is connected to the negative power supply VEE_1;

[0066] The lower bridge arm optocoupler isolation circuit includes an N-type MOS tube M3, an N-type MOS tube M4, an optocoupler C5 and an optocoupler C6; the anode of the primary side light emitting diode of the optocoupler C5 is connected to the positive power supply VCC, the cathode is connected to the drain of the N-type MOS tube M3, the gate of the N-type MOS tube M3 is connected to the logic control module, and the source of the N-type MOS tube M3 is connected to the power ground GND; the secondary side collector of the optocoupler C5 is connected to the positive power supply VCC_2, and the emitter is connected to the power ground GND_2; the anode of the primary side light emitting diode of the optocoupler C6 is connected to the positive power supply VCC, the cathode is connected to the drain of the N-type MOS tube M4, the gate of the N-type MOS tube M4 is connected to the logic control module, and the source of the N-type MOS tube M4 is connected to the power ground GND; the secondary side collector of the optocoupler C6 is connected to the positive power supply VCC_2, and the emitter is connected to the negative power supply VEE_2.

[0067] The upper bridge arm push-pull circuit includes a P-type MOS tube MP1, an N-type MOS tube M5 and an N-type MOS tube M7; the gate of the P-type MOS tube MP1 is connected to the secondary side output end of the optical coupler C3 and the gate of the N-type MOS tube M7, the source is connected to the +15V power supply, and the drain is connected to the drain of the N-type MOS tube M7, the drain of the N-type MOS tube M5 and the other end of the driving resistor R1; the source of the N-type MOS tube M5 is connected to the -9V power supply, and the gate is connected to the secondary side output end of the optical coupler C4; the source of the N-type MOS tube M7 is connected to the power ground GND_1;

[0068] The lower bridge arm push-pull circuit includes a P-type MOS tube MP2, an N-type MOS tube M6 and an N-type MOS tube M8; the gate of the P-type MOS tube MP2 is connected to the secondary side output end of the optical coupler C5 and the gate of the N-type MOS tube M8, the source is connected to the +15V power supply, and the drain is connected to the drain of the N-type MOS tube M8, the drain of the N-type MOS tube M6 and the other end of the driving resistor R2; the source of the N-type MOS tube M6 is connected to the -9V power supply, and the gate is connected to the secondary side output end of the optical coupler C6; the source of the N-type MOS tube M8 is connected to the power ground GND_2.

[0069] A control method for a digital IGBT drive circuit based on FPGA, including the following modes:

[0070] Mode 1: Independent mode, the upper bridge arm control signal and the lower bridge arm control signal are determined to be independent of each other through the upper bridge arm control signal IN_1 and the lower bridge arm control signal IN_2;

[0071] Mode 2: Complementary mode, the FPGA analyzes the upper bridge arm control signal IN_1 to generate symmetrical and complementary upper bridge arm and lower bridge arm control signals;

[0072] Mode 3: Fault identification mode. The fault identification and feedback module collects the status of the IGBT and analyzes and processes it, then feeds back the fault category to the host computer. At the same time, the logic control module makes a corresponding control signal output to realize the processing of the IGBT fault status.

[0073] The specific steps of Mode 1 are:

[0074] Step 101: The upper bridge arm control signal IN_1 and the lower bridge arm control signal IN_2 are input into the FPGA and filtered by the filtering module to achieve narrow pulse suppression; specifically, when the width of a high level signal or a low level signal is lower than the set width, the signal will be filtered; the filtering module prevents the narrow pulse generated by the poor quality of the upper computer control signal from affecting the normal operation of the IGBT;

[0075] Step 102: The error control signal detection module detects the filtered upper bridge arm control signal IN_1 and the lower bridge arm control signal IN_2, and determines whether the two control signals are correct; specifically:

[0076] Step 1021: When the two control signals detected by the error control signal detection module are both at high levels, the two control signals are error control signals, and the FPGA outputs control signals for shutting down the upper bridge arm IGBT and the lower bridge arm IGBT to ensure the safety of the IGBT and the entire system; specifically, since the upper and lower bridge arms of the IGBT cannot be turned on at the same time in any application, when the two control signals are both on signals, that is, both at high levels, they are error signals;

[0077] Step 1022: When the two control signals detected by the error control signal detection module are not both at high levels, the two control signals are correct control signals, which are input to the logic control module for processing and analysis. The two control signals after processing and analysis are converted into four hardware control signals to control the N-type MOS tubes M1, M2, M3, and M4 respectively. Specifically, if the two control signals are both low-level control signals or one high and one low control signals, the signals will be input to the logic control module. The logic control module will analyze the input control signals and parse out the control signals for the N-type MOS tubes M1, M2, M3, and M4 respectively in combination with the design of the driving circuit. The corresponding truth table is shown in Table 1. At the same time, in order to avoid direct connection between the P-type MOS tube MP1 and the N-type MOS tube M5 or the P-type MOS tube MP2 and the N-type MOS tube M6, the dead time t of the FPGA output control signal is set, as shown in FIG. Figure 3 The dead time diagram of the MOS control signal output by the FPGA of the present invention is shown. In addition, the dead time t can be set according to the performance of the MOS tube actually used. The preferred dead time is at the level of tens of ns.

[0078] The specific steps of Mode 2 are:

[0079] Step 201: the upper bridge arm control signal IN_1 is input into the FPGA and filtered by the filtering module to achieve narrow pulse suppression; specifically, in the independent mode, the function of the error control signal detection module will be shielded, and the signal will directly enter the logic control module;

[0080] Step 202: The logic control module analyzes the filtered upper bridge arm control signal IN_1 and generates a complementary lower bridge arm control signal IN_2 with a dead zone, and then converts the upper bridge arm control signal IN_1 and the lower bridge arm control signal IN_2 into 4 hardware control signals through processing and analysis to control the N-type MOS tubes M1, M2, M3, and M4 respectively; specifically, the complementary signal generation program in the logic control module will generate complementary control signals with dead zones. Assuming that the upper bridge control signal IN_1 is at a high level, the lower bridge control signal generated by the FPGA is at a low level. At the same time, there is a dead zone time between the two complementary control signals, and the dead zone time is adjustable; then, combined with the design of the driving circuit, the control signals for the N-type MOS tubes M1, M2, M3, and M4 are respectively analyzed, and the corresponding truth tables are as follows: Figure 3 As shown; similarly, in order to avoid direct conduction between the P-type MOS tube MP1 and the N-type MOS tube M5 or the P-type MOS tube MP2 and the N-type MOS tube M6, a dead zone of the FPGA output control signal is set, and the dead zone time can also be set according to the performance of the MOS tube actually used.

[0081] The specific steps of Mode 3 are:

[0082] Step 301: When the IGBT is in a short circuit or overcurrent state, the voltage at the inverting input terminal of the comparator A1 or A2 is greater than the set reference voltage, and the comparator A1 or A2 outputs a low level, and the optocoupler C2 or C7 outputs a high level. After the high level is collected and analyzed by the fault identification and feedback module, the FPGA feeds back the specific fault type to the upper computer and records the number of faults. At the same time, the logic control module outputs a soft shutdown control signal to turn on the N-type MOS tube M7 or M8 to achieve the safe shutdown function of the IGBT;

[0083] Step 302: When the IGBT is in an overvoltage state, the transient suppression diode TD1 or the transient suppression diode TD2 is first broken down. At this time, the N-type transistor N1 or the N-type transistor N2 is turned on, and the optocoupler C1 or the optocoupler C2 outputs a high level. After the high level is collected and analyzed by the fault identification and feedback module, the FPGA feeds back the specific fault type to the upper computer and records the number of faults. At the same time, the logic control module outputs a direct shutdown control signal to turn on the N-type MOS tube M5 or M6 to achieve the safe shutdown function of the IGBT.

[0084] The beneficial effects of the present invention are as follows: 1) through the hardware detection of the driving circuit and the software control strategy of the FPGA, safe and effective over-current and over-voltage fault detection and protection are achieved, while ensuring the isolation of the primary side and the secondary side, ensuring that the control circuit and the host computer on the low-voltage side work normally when a fault occurs, and avoiding the fault on the high-voltage side from being transmitted to the low-voltage side; it also realizes the isolated transmission of the control signal, ensuring the isolation of the primary side and the secondary side, and ensuring the safety of the control circuit;

[0085] 2) In order to improve the digitization and intelligence of the drive circuit, the FPGA-based digital IGBT drive control method is equipped with an error control signal detection module to filter the possible poor quality of the control signal, that is, the narrow pulse, to improve the quality and stability of the control signal and avoid the wrong control of the IGBT on and off; an error control signal detection module is set to detect the correctness of the control signal to avoid the safety accidents caused by the direct connection of the upper and lower bridge arms of the IGBT; a mode selection module is set to provide two working modes, independent mode and complementary mode, to provide more flexibility for application scenarios; a fault identification and feedback module is set to perform real-time detection of the subsequent circuit, identify the fault type, record the number of faults, and promptly feedback the fault information to the host computer and make control actions set according to the application scenario at the same time;

[0086] 3) The fault category and frequency information fed back by the fault feedback module plays an important role in large-scale IGBT application scenarios. It can be used to evaluate the stability of the entire system and guide the selection of IGBT brands and specifications. At the same time, the collected fault information can also reflect IGBT design defects to a certain extent, and guide the design of IGBT chips and IGBT packages.

Claims

1. A digital IGBT drive circuit based on FPGA, characterized in that: It includes an FPGA, and the FPGA is connected to an upper bridge arm overcurrent detection protection circuit, a lower bridge arm overcurrent detection protection circuit, an upper bridge arm overvoltage detection protection circuit, a lower bridge arm overvoltage detection protection circuit, an upper bridge arm optocoupler isolation circuit, and a lower bridge arm optocoupler isolation circuit; the upper bridge arm optocoupler isolation circuit and the lower bridge arm optocoupler isolation circuit are also connected to an upper bridge arm push-pull circuit and a lower bridge arm push-pull circuit respectively; the upper bridge arm overvoltage detection protection circuit and the lower bridge arm overvoltage detection protection circuit are also connected to an upper bridge arm push-pull circuit and a lower bridge arm push-pull circuit respectively; The FPGA includes a filtering module, an error control signal detection module, a logic control module, and a fault identification and feedback module which are connected in sequence; the logic control module is also connected to the output end of the mode selection module, the upper bridge arm optocoupler isolation circuit and the lower bridge arm optocoupler isolation circuit; the filtering module is also connected to the upper bridge arm control signal IN_1 and the lower bridge arm control signal IN_2; the fault identification and feedback module is connected to the upper bridge arm overcurrent detection protection circuit, the lower bridge arm overcurrent detection protection circuit, the upper bridge arm overvoltage detection protection circuit, the lower bridge arm overvoltage detection protection circuit and the working state ends of the upper bridge arm and the lower bridge arm of the host computer; the input end of the mode selection module is connected to the mode selection signal end of the external input.

2. The FPGA-based digital IGBT drive circuit according to claim 1, characterized in that: The upper bridge arm overcurrent detection protection circuit includes a high-voltage diode D1, a resistor R2, a resistor R3, a capacitor C1, a comparator A1 and an optical coupler C2; The anode of the high-voltage diode D1 is connected to the resistor R2, the resistor R3, one end of the capacitor C1, and the inverting input end of the comparator A1, and the cathode is connected to the collector C1 of the upper bridge arm IGBT and the bus voltage end; the other end of the resistor R2 is connected to the positive power supply VCC_1, and the other ends of the capacitor C1 and the resistor R3 are connected to the power ground GND_1; the non-inverting input end of the comparator A1 is connected to the reference voltage, and the output end is connected to the cathode of the primary light-emitting diode of the optocoupler C2; the anode of the primary light-emitting diode of the optocoupler C2 is connected to the positive power supply VCC_1, the secondary collector is connected to the positive power supply VCC, the secondary emitter is connected to the power ground GND, and the secondary output end is connected to the fault identification and feedback module.

3. The FPGA-based digital IGBT driving circuit according to claim 1, characterized in that: The lower bridge arm overcurrent detection protection circuit includes a high-voltage diode D2, a resistor R5, a resistor R6, a capacitor C2, a comparator A2 and an optical coupler C7; The anode of the high-voltage diode D2 is connected to the resistor R5, the resistor R6, one end of the capacitor C2, and the inverting input terminal of the comparator A2, and the cathode is connected to the collector C2 of the lower bridge arm IGBT and the emitter E1 of the upper bridge arm IGBT; the other end of the resistor R5 is connected to the positive power supply VCC_2, and the other ends of the capacitor C2 and the resistor R6 are connected to the power ground GND_2; the non-inverting input terminal of the comparator A2 is connected to the reference voltage, and the output terminal is connected to the cathode of the primary light-emitting diode of the optocoupler C7; the anode of the primary light-emitting diode of the optocoupler C7 is connected to the positive power supply VCC_2, the secondary collector is connected to the positive power supply VCC, the secondary emitter is connected to the power ground GND, and the secondary output terminal is connected to the fault identification and feedback module.

4. The FPGA-based digital IGBT drive circuit according to claim 1, characterized in that: The upper bridge arm overvoltage detection protection circuit includes a transient suppression diode TD1, a fast recovery diode SD1, an N-type transistor N1, a resistor R1 and an optocoupler C1; the anode of the fast recovery diode SD1 is connected to the base of the N-type transistor N1 and the anode of the transient suppression diode TD1, the cathode is connected to the driving resistor R1 and one end of the resistor R4, and the gate of the upper bridge arm IGBT, and the other end of the resistor R4 is connected to the emitter E1 of the upper bridge arm IGBT; the emitter of the N-type transistor N1 is connected to the power ground GND_1, the collector is connected to one end of the resistor R1 and the cathode of the primary light-emitting diode of the optocoupler C1; the other end of the resistor R1 is connected to the positive power supply VCC_1; the cathode of the transient suppression diode TD1 is connected to the collector C1 of the upper bridge arm IGBT; the secondary collector of the optocoupler C1 is connected to the positive power supply VCC, the secondary emitter is connected to the power ground GND, and the secondary output end is connected to the fault identification and feedback module. The lower bridge arm overvoltage detection protection circuit includes a transient suppression diode TD2, a fast recovery diode SD2, an N-type transistor N2, a resistor R8 and an optocoupler C8; the anode of the fast recovery diode SD2 is connected to the base of the N-type transistor N2 and the anode of the transient suppression diode TD2, the cathode is connected to the driving resistor R2 and one end of the resistor R7, and the gate of the lower bridge arm IGBT, the other end of the resistor R7 is connected to the emitter E2 of the lower bridge arm IGBT and the power ground GND; the emitter of the N-type transistor N2 is connected to the power ground GND_2, the collector is connected to one end of the resistor R8 and the cathode of the primary light emitting diode of the optocoupler C8; the other end of the resistor R8 is connected to the positive power supply VCC_2; the cathode of the transient suppression diode TD2 is connected to the collector C2 of the lower bridge arm IGBT; the secondary collector of the optocoupler C8 is connected to the positive power supply VCC, the secondary emitter is connected to the power ground GND, and the secondary output end is connected to the fault identification and feedback module.

5. The FPGA-based digital IGBT drive circuit according to claim 1, characterized in that: The upper bridge arm optocoupler isolation circuit includes an N-type MOS tube M1, an N-type MOS tube M2, an optocoupler C3 and an optocoupler C4; the anode of the primary side light emitting diode of the optocoupler C3 is connected to the positive power supply VCC, the cathode is connected to the drain of the N-type MOS tube M1, the gate of the N-type MOS tube M1 is connected to the logic control module, and the source of the N-type MOS tube M1 is connected to the power ground GND; the secondary side collector of the optocoupler C3 is connected to the positive power supply VCC_1, and the emitter is connected to the power ground GND_1; the anode of the primary side light emitting diode of the optocoupler C4 is connected to the positive power supply VCC, the cathode is connected to the drain of the N-type MOS tube M2, the gate of the N-type MOS tube M2 is connected to the logic control module, and the source of the N-type MOS tube M2 is connected to the power ground GND; the secondary side collector of the optocoupler C4 is connected to the positive power supply VCC_1, and the emitter is connected to the negative power supply VEE_1; The lower bridge arm optocoupler isolation circuit includes an N-type MOS tube M3, an N-type MOS tube M4, an optocoupler C5 and an optocoupler C6; the anode of the primary side light emitting diode of the optocoupler C5 is connected to the positive power supply VCC, the cathode is connected to the drain of the N-type MOS tube M3, the gate of the N-type MOS tube M3 is connected to the logic control module, and the source of the N-type MOS tube M3 is connected to the power ground GND; the secondary side collector of the optocoupler C5 is connected to the positive power supply VCC_2, and the emitter is connected to the power ground GND_2; the anode of the primary side light emitting diode of the optocoupler C6 is connected to the positive power supply VCC, the cathode is connected to the drain of the N-type MOS tube M4, the gate of the N-type MOS tube M4 is connected to the logic control module, and the source of the N-type MOS tube M4 is connected to the power ground GND; the secondary side collector of the optocoupler C6 is connected to the positive power supply VCC_2, and the emitter is connected to the negative power supply VEE_2.

6. The FPGA-based digital IGBT driving circuit according to claim 1, characterized in that: The upper bridge arm push-pull circuit includes a P-type MOS tube MP1, an N-type MOS tube M5 and an N-type MOS tube M7; the gate of the P-type MOS tube MP1 is connected to the secondary side output end of the optical coupler C3 and the gate of the N-type MOS tube M7, the source is connected to the +15V power supply, and the drain is connected to the drain of the N-type MOS tube M7, the drain of the N-type MOS tube M5 and the other end of the driving resistor R1; the source of the N-type MOS tube M5 is connected to the -9V power supply, and the gate is connected to the secondary side output end of the optical coupler C4; the source of the N-type MOS tube M7 is connected to the power ground GND_1; The lower bridge arm push-pull circuit includes a P-type MOS tube MP2, an N-type MOS tube M6 and an N-type MOS tube M8; the gate of the P-type MOS tube MP2 is connected to the secondary side output end of the optical coupler C5 and the gate of the N-type MOS tube M8, the source is connected to the +15V power supply, and the drain is connected to the drain of the N-type MOS tube M8, the drain of the N-type MOS tube M6 and the other end of the driving resistor R2; the source of the N-type MOS tube M6 is connected to the -9V power supply, and the gate is connected to the secondary side output end of the optical coupler C6; the source of the N-type MOS tube M8 is connected to the power ground GND_2.

7. A control method for a digital IGBT drive circuit based on FPGA, applied to a digital IGBT drive circuit based on FPGA as claimed in any one of claims 1 to 7, characterized in that: The following modes are included: Mode 1: Independent mode, the upper bridge arm control signal and the lower bridge arm control signal are determined to be independent of each other through the upper bridge arm control signal IN_1 and the lower bridge arm control signal IN_2; Mode 2: Complementary mode, the FPGA analyzes the upper bridge arm control signal IN_1 to generate symmetrical and complementary upper bridge arm and lower bridge arm control signals; Mode 3: Fault identification mode. The fault identification and feedback module collects the status of the IGBT and analyzes and processes it, then feeds back the fault category to the host computer. At the same time, the logic control module makes a corresponding control signal output to realize the processing of the IGBT fault status.

8. The control method of the digital IGBT driving circuit based on FPGA as claimed in claim 8, characterized in that: The specific steps of Mode 1 are: Step 101: The upper bridge arm control signal IN_1 and the lower bridge arm control signal IN_2 are input into the FPGA and filtered by the filtering module to achieve narrow pulse suppression; Step 102: The error control signal detection module detects the filtered upper bridge arm control signal IN_1 and the lower bridge arm control signal IN_2, and determines whether the two control signals are correct; specifically: Step 1021: When the two control signals detected by the error control signal detection module are both at high levels, the two control signals are error control signals, and the FPGA outputs control signals for shutting down the upper bridge arm IGBT and the lower bridge arm IGBT to ensure the safety of the IGBT and the entire system; Step 1022: When the two control signals detected by the error control signal detection module are not both at high levels, the two control signals are correct control signals, which are input to the logic control module for processing and analysis. The two control signals after processing and analysis are converted into four hardware control signals to control the N-type MOS tubes M1, M2, M3, and M4 respectively.

9. The control method of the digital IGBT driving circuit based on FPGA as claimed in claim 8, characterized in that: The specific steps of Mode 2 are: Step 201: The upper bridge arm control signal IN_1 is input into the FPGA and filtered by the filtering module to achieve narrow pulse suppression; Step 202: The logic control module analyzes the filtered upper bridge arm control signal IN_1 and generates a complementary lower bridge arm control signal IN_2 with a dead zone, and then converts the upper bridge arm control signal IN_1 and the lower bridge arm control signal IN_2 into four hardware control signals through processing and analysis to control the N-type MOS tubes M1, M2, M3, and M4 respectively.

10. The control method of the digital IGBT driving circuit based on FPGA as claimed in claim 8, characterized in that: The specific steps of Mode 3 are: Step 301: When the IGBT is in a short circuit or overcurrent state, the voltage at the inverting input terminal of the comparator A1 or A2 is greater than the set reference voltage, and the comparator A1 or A2 outputs a low level, and the optocoupler C2 or C7 outputs a high level. After the high level is collected and analyzed by the fault identification and feedback module, the FPGA feeds back the specific fault type to the upper computer and records the number of faults. At the same time, the logic control module outputs a soft shutdown control signal to turn on the N-type MOS tube M7 or M8 to achieve the safe shutdown function of the IGBT; Step 302: When the IGBT is in an overvoltage state, the transient suppression diode TD1 or the transient suppression diode TD2 is first broken down. At this time, the N-type transistor N1 or the N-type transistor N2 is turned on, and the optocoupler C1 or the optocoupler C2 outputs a high level. After the high level is collected and analyzed by the fault identification and feedback module, the FPGA feeds back the specific fault type to the upper computer and records the number of faults. At the same time, the logic control module outputs a direct shutdown control signal to turn on the N-type MOS tube M5 or M6 to achieve the safe shutdown function of the IGBT.

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