A low-noise circuit for powering an operational transconductance amplifier (OTA)

Abstract

This application relates to a low-noise circuit for powering an operational transconductance amplifier (OTA). The circuit includes a first switched capacitor circuit and a second switched capacitor circuit. Each of the first and second switched capacitor circuits includes at least four switches and at least one capacitor. When the connection between the capacitor and the OTA is closed, the capacitor powers the OTA. When the connection between the capacitor and the OTA is closed, the capacitor is in a charging state. Each switch closes or opens in response to a clock signal to control the connection between the corresponding capacitor and the OTA. This circuit avoids the noise problems introduced by using a conventional MOSFET current source to power the OTA, achieving a low-noise power supply circuit and saving power consumption.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design, and more particularly to a low-noise circuit for powering an operational transconductance amplifier (OTA). Background Technology

[0002] Currently, the operational transconductance amplifier (OTA) is powered by a current source using a metal-oxide-semiconductor field-effect transistor (MOSFET). Figure 1 This diagram illustrates a traditional high-gain, high-linearity, and high-energy-efficiency OTA, in which... Figure 1 Figure A illustrates a method for achieving high-gain, high-linearity, and high-energy-efficiency over-the-air (OTA) using complementary metal-oxide-semiconductor (CMOS) technology. To conserve voltage headroom, the bias current (i.e., ...) is... Figure 1 A in I B The current does not flow through the resistor R used for source degeneration. d If a conventional MOSFET current source is used to bias this OTA (e.g., Figure 1 As shown in B), due to this type of current source (i.e. Figure 1 The noise from Mb1, Mb2, Mb3, and Mb4 in component B is non-common-mode noise. This type of current source noise will worsen the input equivalent noise of the OTA. To reduce this type of current source noise while keeping the bias current constant, it is necessary to reduce... Figure 1 The ratio of transconductance to drain current of Mb1-Mb4 in B (i.e., g) m / I d The value of Mb1-Mb4 causes Mb1-Mb4 to require a higher voltage margin, which in turn causes the OTA to require a higher supply voltage and thus results in higher power consumption. Summary of the Invention

[0003] In view of this, this application proposes a low-noise power supply circuit for an operational transconductance amplifier OTA, which can avoid the noise problem introduced by using a conventional MOSFET current source for power supply, realize a low-noise power supply circuit, and save power consumption.

[0004] According to one aspect of this application, a circuit for powering an operational transconductance amplifier (OTA) is provided, comprising: a first switched capacitor circuit and a second switched capacitor circuit; the first switched capacitor circuit and the second switched capacitor circuit each include at least four switches and at least one capacitor; wherein, when the connection between the capacitor and the OTA is turned on, the capacitor is used to power the OTA; when the connection between the capacitor and the OTA is turned off, the capacitor is in a charging state; each of the switches closes or opens in response to a clock signal to control the on / off state of the connection between the corresponding capacitor and the OTA.

[0005] In one possible implementation, the first switched capacitor circuit includes a first capacitor, a first switch, a second switch, a third switch, and a fourth switch; the second switched capacitor circuit includes a second capacitor, a fifth switch, a sixth switch, a seventh switch, and an eighth switch; the first terminal of the first switch, the first terminal of the third switch, the first terminal of the fifth switch, and the first terminal of the seventh switch are respectively connected to the OTA; the second terminal of the first switch and the first terminal of the second switch are connected to the first terminal of the first capacitor; the second terminal of the third switch and the first terminal of the fourth switch are connected to the second terminal of the first capacitor; the second terminal of the fifth switch and the first terminal of the sixth switch are connected to the first terminal of the second capacitor; the second terminal of the seventh switch and the first terminal of the eighth switch are connected to the second terminal of the second capacitor; the second terminal of the second switch and the second terminal of the sixth switch are connected to a first voltage; the second terminal of the fourth switch and the second terminal of the eighth switch are connected to a second voltage; the first switch, the third switch, the fifth switch, the fifth switch, the fifth switch, the sixth switch, the seventh switch, the fifth switch, the sixth switch, the seventh switch, the seventh switch, the eighth ... The seventh switch closes in response to a first level in the first clock signal and opens in response to a second level in the first clock signal; the second switch, the fourth switch, the sixth switch, and the eighth switch close in response to the first level in the second clock signal and open in response to the second level in the second clock signal; wherein the first clock signal and the second clock signal have the same clock period but opposite levels; when the first switch, the third switch, the fifth switch, and the seventh switch close in response to the first clock signal, the second switch, the fourth switch, the sixth switch, and the eighth switch open in response to the second clock signal, and the first capacitor and the second capacitor are used to power the OTA; when the second switch, the fourth switch, the sixth switch, and the eighth switch close in response to the second clock signal, the first switch, the third switch, the fifth switch, and the seventh switch open in response to the first clock signal, and the first capacitor and the second capacitor are in a charging state.

[0006] In one possible implementation, the first switched capacitor circuit further includes a third capacitor, a ninth switch, a tenth switch, an eleventh switch, and a twelfth switch; the second switched capacitor circuit further includes a fourth capacitor, a thirteenth switch, a fourteenth switch, a fifteenth switch, and a sixteenth switch; the first terminal of the ninth switch is connected to the first terminal of the first switch; the first terminal of the eleventh switch is connected to the first terminal of the third switch; the first terminal of the thirteenth switch is connected to the first terminal of the fifth switch; the first terminal of the fifteenth switch is connected to the first terminal of the seventh switch; the second terminals of the ninth switch and the tenth switch are connected to the first terminal of the third capacitor; the second terminals of the eleventh switch and the twelfth switch are connected to the second terminal of the third capacitor; the second terminals of the thirteenth switch and the fourteenth switch are connected to the first terminal of the fourth capacitor; the second terminals of the fifteenth switch and the sixteenth switch are connected to the second terminal of the fourth capacitor; the second terminals of the tenth switch and the fourteenth switch are connected to the first voltage; the second terminal of the twelfth switch and the first terminal of the eleventh switch are connected to the first voltage; the second terminal of the twelfth switch and the first terminal of the eleventh switch are connected to the first voltage; the second terminal of the eleven ... The second terminal of the sixteenth switch is connected to the second voltage; the tenth, twelfth, fourteenth, and sixteenth switches close in response to the first level of the first clock signal and open in response to the second level of the first clock signal; the ninth, eleventh, thirteenth, and fifteenth switches close in response to the first level of the second clock signal and open in response to the second level of the second clock signal; wherein, when the tenth, twelfth, fourteenth, and sixteenth switches close in response to the first clock signal, the ninth, eleventh, thirteenth, and fifteenth switches open in response to the second clock signal, and the third and fourth capacitors are in a charging state; when the ninth, eleventh, thirteenth, and fifteenth switches close in response to the second clock signal, the tenth, twelfth, fourteenth, and sixteenth switches open in response to the first clock signal, and the third and fourth capacitors are used to power the OTA.

[0007] In one possible implementation, the OTA includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first resistor, and a second resistor; the gates of the first PMOS transistor and the second NMOS transistor are connected to form the first input terminal of the OTA; the gates of the third PMOS transistor and the fourth NMOS transistor are connected to form the second input terminal of the OTA; the source of the first PMOS transistor, the first terminal of the first resistor, and the first terminal of the first switch are connected; the drain of the first PMOS transistor is connected to the source of the second PMOS transistor; the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor to form the first output terminal of the OTA; the first NMOS transistor... The source of the first NMOS transistor is connected to the drain of the second NMOS transistor; the source of the second NMOS transistor and the first end of the second resistor are connected to the first end of the third switch; the source of the third PMOS transistor and the second end of the first resistor are connected to the first end of the fifth switch; the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor; the drain of the fourth PMOS transistor is connected to the drain of the third NMOS transistor, forming the second output terminal of the OTA; the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor; the source of the fourth NMOS transistor and the second end of the second resistor are connected to the first end of the seventh switch; the gates of the second PMOS transistor and the fourth PMOS transistor are connected to a first gate voltage; the gates of the first NMOS transistor and the third NMOS transistor are connected to a second gate voltage.

[0008] In one possible implementation, the circuit further includes a fifth capacitor and a sixth capacitor; a first terminal of the fifth capacitor is connected to the source of the first PMOS transistor; a second terminal of the fifth capacitor is connected to the source of the second NMOS transistor; a first terminal of the sixth capacitor is connected to the source of the third PMOS transistor; and a second terminal of the sixth capacitor is connected to the source of the fourth NMOS transistor.

[0009] In one possible implementation, the capacitance values ​​of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are equal.

[0010] In one possible implementation, the duty cycle of the first clock signal and the second clock signal is 50%; the capacitance values ​​C of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are... S =0.5T S ·I B / (V top -V bottom ); where TS Indicates the clock periods of the first clock signal and the second clock signal; I B This represents the bias current required for the OTA to function properly; V top V represents the source voltage of the first PMOS transistor; bottom V represents the source voltage of the second NMOS transistor; top -V bottom The value is equal to the sum of the absolute values ​​of the drain-source voltages of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor.

[0011] In one possible implementation, the first capacitor comprises N capacitors with a capacitance value of N·C. S The first sub-capacitor; N≥2; when the first capacitor is in a charging state, N first sub-capacitors are connected in parallel; when the first capacitor is used to power the OTA, N first sub-capacitors are connected in series; the second capacitor includes N capacitors with a capacitance value of N·C. S The second sub-capacitor; when the second capacitor is in a charging state, N second sub-capacitors are connected in parallel; when the second capacitor is used to power the OTA, N second sub-capacitors are connected in series; the third capacitor includes N capacitors with a capacitance value of N·C. S The third sub-capacitor; when the third capacitor is in a charging state, N third sub-capacitors are connected in parallel; when the third capacitor is used to power the OTA, N third sub-capacitors are connected in series; the fourth capacitor includes N capacitors with a capacitance value of N·C. S The fourth sub-capacitor; when the fourth capacitor is in a charging state, N fourth sub-capacitors are connected in parallel; when the fourth capacitor is used to power the OTA, N fourth sub-capacitors are connected in series.

[0012] In one possible implementation, the first voltage and the second voltage satisfy: V L +(V H -V L ) / 2=V bottom +(V top -V bottom ) / 2 and N·(V H -V L )=2·(V top -V bottom ); where V H V represents the first voltage; L This indicates the second voltage.

[0013] In one possible implementation, the circuit further includes: a fifth PMOS transistor, a sixth PMOS transistor, and a first operational amplifier; the first input terminal of the first operational amplifier receives the output common-mode voltage of the OTA; the second input terminal of the first operational amplifier receives a reference common-mode voltage; the gates of the fifth PMOS transistor and the sixth PMOS transistor are connected to the output terminal of the first operational amplifier; the sources of the fifth PMOS transistor and the sixth PMOS transistor are connected to a third voltage; the drain of the fifth PMOS transistor is connected to the source of the first PMOS transistor; the drain of the sixth PMOS transistor is connected to the source of the third PMOS transistor; wherein, the output common-mode voltage is the sum of the first output voltage output from the first output terminal of the OTA and the second output voltage output from the second output terminal of the OTA divided by 2.

[0014] The circuit for powering OTA in this application uses a switched capacitor instead of a traditional MOSFET current source to power OTA, which avoids the non-common-mode noise introduced by using a traditional MOSFET current source, thus achieving a low-noise power supply circuit and saving power consumption.

[0015] Other features and aspects of this application will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0016] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this application together with the specification and serve to explain the principles of this application.

[0017] Figure 1 A schematic diagram of a traditional high-gain, high-linearity, and high-energy-efficiency OTA is shown.

[0018] Figure 2 This diagram illustrates a low-noise circuit for powering an OTA according to an embodiment of the present application.

[0019] Figure 3 A schematic diagram of a first clock signal and a second clock signal according to an embodiment of this application is shown.

[0020] Figure 4 This diagram illustrates a low-noise circuit for powering an OTA according to an embodiment of the present application.

[0021] Figure 5 This diagram illustrates a low-noise circuit for powering an OTA according to an embodiment of the present application. Detailed Implementation

[0022] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0023] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0024] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0025] Figure 2 This diagram illustrates a low-noise circuit for powering an OTA (Over-The-Air) device according to an embodiment of this application. Figure 2 As shown, the circuit includes a first switched capacitor circuit and a second switched capacitor circuit; the first switched capacitor circuit and the second switched capacitor circuit each include at least four switches and at least one capacitor; wherein, when the connection between the capacitor and the OTA is turned on, the capacitor is used to supply power to the OTA; when the connection between the capacitor and the OTA is turned off, the capacitor is in a charging state; each of the switches closes or opens in response to a clock signal to control the connection between the corresponding capacitor and the OTA.

[0026] In one possible implementation, the first switched capacitor circuit includes a first capacitor C. s,a1 First switch S 1a Second switch S 2a Third switch S 3a and the fourth switch S 4a The second switched capacitor circuit includes a second capacitor C. s,a2 Fifth switch S 1b Sixth switch S 2b Seventh switch S 3b and the eighth switch S 4b .

[0027] Among them, S 1a The first end, S 3a The first end, S 1b The first end, S 3b The first end is connected to the OTA respectively; S 1a The second end, S 2a The first end and C s,a1The first end (i.e., C) s,a1 (Upper plate) connection; S 3a The second end, S 4a The first end and C s,a1 The second end (i.e., C) s,a1 (lower electrode plate) connection; S 1b The second end, S 2b The first end and C s,a2 The first end (i.e., C) s,a2 (Upper plate) connection; S 3b The second end, S 4b The first end and C s,a2 The second end (i.e., C) s,a2 (lower electrode plate) connection; S 2a The second end and S 2b The second terminal is connected to the first voltage V H S 4a The second end and S 4b The second terminal is connected to the second voltage V L .

[0028] For example, S 1a S 3a S 1b and S 3b The signal closes in response to the first level in the first clock signal Φ1, and opens in response to the second level in Φ1; S 2a S 4a S 2b and S 4b The signal closes in response to the first level in the second clock signal Φ2, and opens in response to the second level in Φ2. As an example, the first level can be high, and the second level can be low, i.e., S... 1a S 3a S 1b and S 3b It can be closed when Φ1 is high and opened when Φ1 is low; S 2a S 4a S 2b and S 4b It can be closed when Φ2 is high and opened when Φ2 is low.

[0029] Figure 3 A schematic diagram showing a first clock signal and a second clock signal according to an embodiment of this application is provided, as follows: Figure 3 As shown, Φ1 and Φ2 have the same clock period but opposite voltage levels. Ideally, the duty cycles of Φ1 and Φ2 could be set to 50%, but since the rise and fall times of a real clock generation circuit are not zero, and Φ1 and Φ2 need to be non-overlapping, their duty cycles are actually less than 50%. The clock periods of Φ1 and Φ2 can be denoted as T.S .

[0030] The circuit in this embodiment can be used for... Figure 1 The high-gain, high-linearity, and high-energy-efficiency OTA shown in Figure A is used for power supply. Figure 2 The switched capacitor circuit in the example is equivalent to a switched-capacitor supply. For example... Figure 2 As shown, OTA may include a first PMOS transistor M 1,a The second PMOS transistor M 2,a The third PMOS transistor M 1,b The fourth PMOS transistor M 2,b The first NMOS transistor M 3,a The second NMOS transistor M 4,a The third NMOS transistor M 3,b The fourth NMOS transistor M 4,b First resistor R d1 Second resistor R d2 M 1,a and M 1,b They can be the same, M 2,a and M 2,b They can be the same, M 3,a and M 3,b They can be the same, M 4,a and M 4,b They can be the same.

[0031] Among them, M 1,a The gate and M 4,a The gate connection forms the first input terminal of the OTA, and the input voltage of the first input terminal is V. i+ M 1,b The gate and M 4,b The gate connection forms the second input terminal of the OTA, and the input voltage of the second input terminal is V. i- M 1,a The source, R d1 The first end and S 1a The first end is connected, and the connection point is denoted as S. M1 M 1,a The drain and M 2,a Source connection; M 2,a The drain and M 3,a The drain connection forms the first output terminal of the OTA, and the output voltage of the first output terminal is V. O- M 3,a The source and M 4,a Drain connection; M 4,a The source, R d2 The first end and S 3a The first end is connected, and the connection point is denoted as S.M4 M 1,b The source, R d1 The second end and S 1b The first end is connected, and the connection point is denoted as S. M2 M 1,b The drain and M 2,b Source connection; M 2,b The drain and M 3,b The drain connection forms the second output terminal of the OTA, and the output voltage of the second output terminal is V. O+ M 3,b The source and M 4,b Drain connection; M 4,b The source, R d2 The second end and S 3b The first end is connected, and the connection point is denoted as S. M3 M 2,a The gate and M 2,b The gate is connected to the first gate voltage V bcasp M 3,a The gate and M 3,b The gate is connected to the second gate voltage V bcasn The output differential voltage V of the OTA O =V O+ -V O- Output common-mode voltage V O,cm =(V O+ +V O- ) / 2. The circuit structure of this OTA is similar to... Figure 1 The circuit structure of OTA shown in A is the same.

[0032] In one embodiment, when Φ1 is high and Φ2 is low, S 1a S 3a S 1b and S 3b Closed, S 2a S 4a S 2b and S 4b Disconnect, at this time C s,a1 and C s,a2 The connection with OTA is established, C s,a1 and C s,a2 Charge can be injected into the OTA to power it; when Φ2 is high and Φ1 is low, S 2a S 4a S 2b and S 4b Closed, S 1a S 3a S 1b and S 3b Disconnect, at this time Cs,a1 and C s,a2 The connection with OTA is lost, C s,a1 and C s,a2 The two ends are respectively connected to V H and V L C s,a1 and C s,a2 It is currently charging.

[0033] With both the first and second switched-capacitor circuits containing four switches and one capacitor respectively, continuous power supply to OTA (Over-The-Air) devices cannot be achieved. Adding four switches and one capacitor to both the first and second switched-capacitor circuits can enable continuous power supply to OTA devices.

[0034] Figure 4 This diagram illustrates a low-noise circuit for powering an OTA (Over-The-Air) device according to an embodiment of this application. Figure 4 As shown, the circuit includes a first switched capacitor circuit and a second switched capacitor circuit. The first switched capacitor circuit includes C s,a1 S 1a S 2a S 3a and S 4a The second switched capacitor circuit includes C s,a2 S 1b S 2b S 3b and S 4b C s,a1 C s,a2 S 1a S 2a S 3a S 4a S 1b S 2b S 3b and S 4b Connection method and Figure 3 The connection methods shown are the same. The first switched capacitor circuit also includes a third capacitor C. s,b1 Ninth switch S 5a 10th switch S 6a Eleventh switch S 7a and the twelfth switch S 8a The second switched capacitor circuit also includes a fourth capacitor C. s,b2 13th switch S 5b Fourteenth switch S 6b Fifteenth switch S 7b and the sixteenth switch S 8b .

[0035] Among them, S 5a The first end and S1a The first end is connected; S 7a The first end and S 3a The first end is connected; S 5b The first end and S 1b The first end is connected; S 7b The first end and S 3b The first end is connected; S 5a The second end, S 6a The first end and C s,b1 The first end (i.e., C) s,b1 (Upper plate) connection; S 7a The second end, S 8a The first end and C s,b1 The second end (i.e., C) s,b1 (lower electrode plate) connection; S 5b The second end, S 6b The first end and C s,b2 The first end (i.e., C) s,b2 (Upper plate) connection; S 7b The second end, S 8b The first end and C s,b2 The second end (i.e., C) s,b2 (lower electrode plate) connection; S 6a The second end and S 6b The second end is connected to V H S 8a The second end and S 8b The second end is connected to V L .

[0036] For example, S 6a S 8a S 6b and S 8b The system closes in response to the first level in Φ1 and opens in response to the second level in Φ1; S 5a S 7a S 5b and S 7b The circuit closes in response to the first level in Φ2 and opens in response to the second level in Φ2. As an example, the first level can be high and the second level can be low, i.e., S... 6a S 8a S 6b and S 8b It can be closed when Φ1 is high and opened when Φ1 is low; S 5a S 7a S 5b and S 7b It can be closed when Φ2 is high and opened when Φ2 is low.

[0037] For example, Cs,a1 C s,a2 C s,b1 C s,b2 The capacitance values ​​are equal. C s,a1 C s,a2 C s,b1 C s,b2 It can be called a switched capacitor.

[0038] In one embodiment, to ensure the input MOSFETs (i.e., M) in the OTA 1,a M 1,b M 4,a M 4,b The capacitance seen at the source end of the capacitor remains unchanged. The switched capacitor can supply power to the OTA in a ping-pong manner, that is: when Φ1 is high and Φ2 is low, S 1a S 3a S 6a S 8a S 1b S 3b S 6b and S 8b Closed, S 2a S 4a S 5a S 7a S 2b S 4b S 5b and S 7b Disconnect, at this time C s,a1 and C s,a2 The connection with OTA is established, C s,a1 and C s,a2 Injecting charge into the OTA powers the OTA, while C s,b1 and C s,b2 The two ends are respectively connected to V H and V L C s,b1 and C s,b2 Being charged; when Φ2 is high and Φ1 is low, S 2a S 4a S 5a S 7a S 2b S 4b S 5b and S 7b Closed, S 1a S 3a S 6a S 8a S 1b S 3b S 6b and S 8b Disconnect, at this time Cs,b1 and C s,b2 The connection with OTA is established, C s,b1 and C s,b2 Injecting charge into the OTA powers the OTA, while C s,a1 and C s,a2 The two ends are respectively connected to V H and V L C s,a1 and C s,a2 It is being charged. Thus, the circuit of this embodiment can provide continuous power to the OTA (Over-The-Air) system.

[0039] When powering OTA, C s,a1 / C s,a2 / C s,b1 / C s,b2 The amount of charge injected into OTA each time should be equal to half a clock cycle (i.e., 0.5T). S The charge flowing through OTA will cause C s,a1 C s,a2 C s,b1 C s,b2 The capacitance value is denoted as C. S Then C S ·(V H -V L ) = 0.5T S ·I B , and V H -V L =V top -V bottom C can then be calculated using the following formula. S Value:

[0040] C S =0.5T S ·I B / (V top -V bottom (1)

[0041] Among them, T S Indicates the clock periods of Φ1 and Φ2; I B This represents the bias current required for normal OTA operation. In M... 1,a and M 1,b Same, M 2,a and M 2,b Same, M 3,a and M 3,b Same, M 4,a and M 4,b Under the same conditions, V top M represents 1,a The source voltage and M 1,b The source voltage (i.e., node S)M1 Voltage at point S and node S M2 (V) bottom M represents 4,a The source voltage and M 4,b The source voltage (i.e., node S) M3 Voltage at point S and node S M4 (V) top -V bottom The value is equal to M 1,a M 2,a M 3,a M 4,a The drain-source voltage (i.e., V) ds The sum of the absolute values ​​of V. top and V bottom The value can be determined based on the required OTA output common-mode voltage and M. 1,a M 2,a M 3,a M 4,a The drain-source voltage is set.

[0042] At the moment when the switch transitions between the closed and open states, V top and V bottom It may produce instantaneous peaks, in order to prevent M 1,a M 1,b M 4,a M 4,b The source end (i.e., node S) M1 S M2 S M3 S M4 If you see a large glitch, you can check at node S. M1 S M4 Between and node S M2 S M3 An additional, relatively large capacitor is connected between them.

[0043] like Figure 4 As shown, the circuit in this embodiment of the application further includes a fifth capacitor C. b1 and the sixth capacitor C b2 C b1 The first end (i.e., C) b1 (upper electrode plate) and M 1,a Source connection; C b1 The second end (i.e., C) b1 (lower electrode plate) and M 4,a Source connection; C b2 The first end (i.e., C) b2 (upper electrode plate) and M 1,b Source connection; C b2 The second end (i.e., C)b2 (lower electrode plate) and M 4,b The source connection. Theoretically, C b1 and C b2 The larger the capacitance value, the better the attenuation effect on glitches. However, because the equivalent transconductance of the OTA is source-degenerated, the glitches "seen" by the OTA due to switching operations are also attenuated due to source degeneration. Therefore, C b1 and C b2 The capacitance value can be relatively large, but it does not need to be very large.

[0044] To stabilize the OTA output common-mode voltage at the required output common-mode voltage, a common-mode feedback circuit (CMFB) can be used.

[0045] like Figure 4 As shown, the circuit in this embodiment may further include a fifth PMOS transistor M. P1 The sixth PMOS transistor M P2 and the first operational amplifier OP, M P1 and M P2 They can be the same. Specifically, the first input terminal of the OP receives the common-mode voltage V output by the OTA. O,cm V O,cm =(V O+ +V O- ) / 2; The second input terminal of the OP receives the reference common-mode voltage V. O,cm,ref V O,cm,ref The required output common-mode voltage is determined based on actual needs; M P1 gate, M P2 The gate of the OP is connected to the output terminal; M P1 The source and M P2 The source is connected to the third voltage V DD V DD The value is based on M P1 and M P2 V ds Confirmed; M P1 The drain and M 1,a Source connection; M P2 The drain and M 1,b The source connection. M P1 M P2 Together with the OP, they form a CMFB circuit. The output voltage of the OP is equal to V. O,cm With V O,cm,ref The difference multiplied by the magnification factor, M P1 and M P2 This is equivalent to two current sources, and the current I generated by these two current sources... CMFBControlled by the output voltage of the OP, the V output of the OTA can be converted through this CMFB circuit. O,cm Stabilize at the required V O,cm,ref .

[0046] When C s,a1 / C s,a2 / C s,b1 / C s,b2 When the connection between the two ends of the device and the OTA is broken, a portion of the charge will be carried away. This amount of charge carried away is half of the charge instant before the connection was broken. To compensate for the charge carried away, it is possible to... s,a1 / C s,a2 / C s,b1 / C s,b2 Charge it to 2 (V) when it is in the charging state. top -V bottom Therefore, each time two of the four switched capacitors are connected to the OTA, twice the amount of charge required by the OTA will be injected into the OTA. Half of the charge will be carried away by the other two switched capacitors that are simultaneously disconnected from the OTA, and the remaining half of the charge will be injected into the OTA to provide it with bias current, thus ensuring that the OTA is injected with the required amount of charge in real time. However, in advanced CMOS processes, 2(V top -V bottom This generally exceeds the normal supply voltage of the core transistor. To avoid the charging voltage required for the switching capacitor exceeding the normal supply voltage of the core transistor, 2V can be obtained through capacitor stacking. top -V bottom The voltage of ), i.e., C s,a1 C s,a2 C s,b1 C s,b2 It can be composed of N capacitors with a value of N·C. S This is achieved by connecting sub-capacitors in series.

[0047] In one possible implementation, C s,a1 Includes N capacitors with a value of N·C S The first sub-capacitor; N≥2; C s,a1 When in charging state, N first sub-capacitors are connected in parallel; C s,a1 When used to power OTA, N first sub-capacitors are connected in series; C s,a2 Includes N capacitors with a value of N·C S The second sub-capacitor; C s,a2 When in charging state, N second sub-capacitors are connected in parallel; C s,a2 When used to power OTA (Over-The-Air), N second sub-capacitors are connected in series; C s,b1Includes N capacitors with a value of N·C S The third sub-capacitor; C s,b1 When in the charging state, N of the third sub-capacitors are connected in parallel; C s,b1 When used to power OTA, N of the aforementioned third sub-capacitors are connected in series; C s,b2 Includes N capacitors with a value of N·C S The fourth sub-capacitor; C s,b2 When in the charging state, N of the fourth sub-capacitors are connected in parallel; C s,b2 When used to power OTA, N of the fourth sub-capacitors are connected in series.

[0048] During the charging of the switched capacitor, it is only necessary to charge N parallel capacitors with a capacitance of N·C. S The sub-capacitor is charged to 2 (V) top -V bottom ) / N, i.e., V H and V L The selection of [a] needs to satisfy the following constraints:

[0049] N·(V H -V L )=2·(V top -V bottom (2)

[0050] When using switched capacitors to power OTA, the N capacitors are valued at N·C. S By connecting the sub-capacitors in series, a voltage drop of 2 (V) can be obtained. top -V bottom The capacitance value is C S The equivalent capacitance is used to inject charge into the OTA for power supply. Simultaneously, to ensure the voltage drop of 2 (V) obtained through capacitor stacking... top -V bottom The intermediate potential of ) is equal to the intermediate potential V required by OTA. bottom +(V top -V bottom ) / 2, V H and V L The selection of [a] also needs to satisfy the following constraints:

[0051] V L +(V H -V L ) / 2=V bottom +(V top -V bottom ) / twenty three)

[0052] Thus, in V H and V LProvided that the voltage does not exceed the transistor's core supply voltage, when using the equivalent capacitance to power the OTA, twice the amount of charge required by the OTA will appear at node S. M1 S M4 Location and node S M2 S M3 At this point, half of the charge will be carried away by the equivalent capacitance that is simultaneously disconnected from the OTA, and the remaining half of the charge will be injected into the OTA to generate a current I. B Bias on OTA.

[0053] Preferably, the value of N can be 3. Since the larger the value of N, the more switches are needed in the circuit, and the more complex the corresponding switch control circuit becomes, the smaller the value of N, the better. However, when N=2, a negative voltage may be required to obtain the required intermediate potential. To avoid using a negative voltage and to simplify the switch control circuit as much as possible, N=3 is the preferred value.

[0054] Figure 5 This diagram illustrates a low-noise circuit for powering an OTA (Over-The-Air) device according to an embodiment of this application. Figure 5 As shown, C s,a1 C s,a2 C s,b1 C s,b2 It can be made of 3 capacitors with a value of 3C. S The sub-capacitor is implemented. Figure 5 The light yellow section corresponding to the first switched capacitor circuit shows the use of three capacitors with a value of 3C. S The sub-capacitor realizes C s,a1 The circuit structure diagram shows that the light yellow part corresponding to the second switched capacitor circuit uses three capacitors with a value of 3C. S The sub-capacitor realizes C s,a2 The circuit structure diagram is shown below. As shown in light yellow, the green switch is controlled by Φ1, which closes when Φ1 is high and opens when Φ1 is low; the yellow switch is controlled by Φ2, which closes when Φ2 is high and opens when Φ2 is low. Figure 5 The light blue parts corresponding to the first and second switched capacitor circuits respectively indicate the use of three capacitors with a value of 3C. S The sub-capacitor realizes C s,b1 and C s,b2 The circuit structure diagram shows that the light blue part of the circuit structure is the same as the light yellow part. Figure 5The circuit structure of the light blue section is not shown in the diagram; refer to the circuit structure of the light yellow section. The difference is that the yellow switch in the light blue section is controlled by Φ1, and the green switch is controlled by Φ2. The yellow switch in the light blue section can be closed when Φ1 is high and open when Φ1 is low; the green switch can be closed when Φ2 is high and open when Φ2 is low.

[0055] When Φ1 is high and Φ2 is low, the green switch in the light yellow section is closed and the yellow switch is open; the yellow switch in the light blue section is closed and the green switch is open; in the light yellow section, the value of the three capacitors is 3C. S The sub-capacitors are connected in series to form a voltage drop of 2 (V) top -V bottom The capacitance value is C S The equivalent capacitance is connected to the OTA at both ends, injecting charge into the OTA to supply power; in the light blue part, the three capacitors have a value of 3C. S The sub-capacitors are connected in parallel, and their terminals are respectively connected to V. H and V L Each sub-capacitor will be charged to V H -V L That is, it is charged to 2 (V) top -V bottom ) / 3. When Φ1 is low and Φ2 is high, the yellow switch in the light yellow section is closed and the green switch is open; the green switch in the light blue section is closed and the yellow switch is open; in the light yellow section, the value of the three capacitors is 3C. S The sub-capacitors are connected in parallel, and each sub-capacitor will be charged to 2 (V). top -V bottom ) / 3; In the light blue section, the three capacitors have a value of 3C. S The sub-capacitors are connected in series to form a voltage drop of 2 (V) top -V bottom The capacitance value is C S The equivalent capacitance is used to inject charge into the OTA to supply power. Thus, the circuit in this embodiment uses three capacitors with a value of 3C. S By stacking sub-capacitors, a switched capacitor can be implemented, which can be selected at V... H and V L Under the premise that the voltage does not exceed the core supply voltage of the transistor, ensure that the required charge is injected into the OTA in real time, and ensure that the voltage drop of 2 (V) obtained through capacitor stacking is guaranteed. top -V bottom The intermediate potential of ) is equal to the intermediate potential required by OTA, and at the same time, the use of negative voltage can be avoided.

[0056] Figure 5The purple section in the middle is a CMFB circuit, which uses two real-time output common-mode voltages V controlled by OTA. O,cm and the required output common-mode voltage V O,cm,ref The difference between the current sources and the operational amplifier can be used to implement the V output of the OTA. O,cm Stabilize at the required V O,cm,ref These two current sources can be implemented using MOSFETs, for example, using PMOS transistors (such as...). Figure 4 China via M P1 and M P2 (Implementation). The current I generated by these two current sources. CMFB The value can be much smaller than I. B For example, it can be I B One-tenth or less of the current source, although these two current sources will contribute noise to the OTA, the corresponding current noise is minimal due to their low current. m (k represents the Boltzmann constant, T represents the absolute temperature, γ represents a parameter related to the MOSFET manufacturing process, g) m The transconductance is also very low, so the noise contribution of these two current sources to the OTA can be ignored in a suitable design.

[0057] The circuit in this embodiment uses a switched capacitor to power the OTA, which avoids non-common-mode noise from conventional non-common-mode tail current sources (i.e., traditional MOSFET current sources). Technically, the circuit in this embodiment primarily has the advantage of saving power consumption. If a conventional non-common-mode tail current source is used, under the premise that the bias current of the OTA remains unchanged, reducing the noise of such a current source requires reducing the g-skill of the corresponding transistor. m / I d The value of V necessitates higher drain-source voltages for these transistors. ds This necessitates either increasing the supply voltage of the OTA or compressing its output swing. A higher supply voltage means higher power consumption, while a compressed output swing means a deterioration in the OTA's performance (primarily linearity). The circuit in this embodiment uses a switched capacitor instead of a traditional MOSFET current source, which avoids introducing non-common-mode noise, achieving a low-noise power supply circuit. Furthermore, it eliminates the need to increase the OTA's supply voltage, thereby saving power consumption.

[0058] From an application perspective, the switched-capacitor power supply technology proposed in this application is particularly suitable for high-gain, high-linearity, and low-noise OTA designs using advanced CMOS processes. Compared to older CMOS processes (such as 180nm CMOS processes), transistor noise is higher under advanced CMOS processes. The circuit in the embodiments of this application uses switched capacitors instead of traditional MOSFET current sources for power supply, which can reduce noise and avoid using higher supply voltages, thereby saving power consumption. At the same time, high-speed switching circuits are easier to design under advanced CMOS processes.

[0059] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technological improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A low-noise circuit for powering an operational transconductance amplifier OTA, characterized in that, include: A first switched capacitor circuit and a second switched capacitor circuit; the first switched capacitor circuit and the second switched capacitor circuit each include at least four switches and at least one capacitor; wherein, when the connection between the capacitor and the OTA is turned on, the capacitor is used to supply power to the OTA; when the connection between the capacitor and the OTA is turned off, the capacitor is in a charging state; each of the switches closes or opens in response to a clock signal to control the on / off state of the connection between the corresponding capacitor and the OTA; The first switched capacitor circuit includes a first capacitor, a first switch, a second switch, a third switch, and a fourth switch; the second switched capacitor circuit includes a second capacitor, a fifth switch, a sixth switch, a seventh switch, and an eighth switch. The first terminals of the first switch, the third switch, the fifth switch, and the seventh switch are respectively connected to the OTA; the second terminals of the first switch and the second switch are connected to the first terminal of the first capacitor; the second terminals of the third switch and the fourth switch are connected to the second terminal of the first capacitor; the second terminals of the fifth switch and the sixth switch are connected to the first terminal of the second capacitor; the second terminals of the seventh switch and the eighth switch are connected to the second terminal of the second capacitor; the second terminals of the second switch and the sixth switch are connected to a first voltage; the second terminals of the fourth switch and the eighth switch are connected to a second voltage. The first switch, the third switch, the fifth switch, and the seventh switch close in response to a first level in the first clock signal and open in response to a second level in the first clock signal; the second switch, the fourth switch, the sixth switch, and the eighth switch close in response to the first level in the second clock signal and open in response to the second level in the second clock signal. Wherein, the first clock signal and the second clock signal have the same clock period but opposite levels; when the first switch, the third switch, the fifth switch, and the seventh switch are closed in response to the first clock signal, the second switch, the fourth switch, the sixth switch, and the eighth switch are open in response to the second clock signal, and the first capacitor and the second capacitor are used to power the OTA; when the second switch, the fourth switch, the sixth switch, and the eighth switch are closed in response to the second clock signal, the first switch, the third switch, the fifth switch, and the seventh switch are open in response to the first clock signal, and the first capacitor and the second capacitor are in a charging state; The OTA includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first resistor, and a second resistor. The gate of the first PMOS transistor and the gate of the second NMOS transistor are connected to form the first input terminal of the OTA; the gate of the third PMOS transistor and the gate of the fourth NMOS transistor are connected to form the second input terminal of the OTA; the source of the first PMOS transistor, the first terminal of the first resistor, and the first terminal of the first switch are connected; the drain of the first PMOS transistor and the source of the second PMOS transistor are connected; the drain of the second PMOS transistor and the drain of the first NMOS transistor are connected to form the first output terminal of the OTA; the source of the first NMOS transistor and the drain of the second NMOS transistor are connected; the source of the second NMOS transistor, the first terminal of the second resistor, and the third PMOS transistor are connected to the first input terminal of the OTA. The first terminal of the switch is connected; the source of the third PMOS transistor and the second terminal of the first resistor are connected to the first terminal of the fifth switch; the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor; the drain of the fourth PMOS transistor is connected to the drain of the third NMOS transistor, forming the second output terminal of the OTA; the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor; the source of the fourth NMOS transistor and the second terminal of the second resistor are connected to the first terminal of the seventh switch; the gates of the second PMOS transistor and the fourth PMOS transistor are connected to a first gate voltage; the gates of the first NMOS transistor and the third NMOS transistor are connected to a second gate voltage.

2. The circuit according to claim 1, characterized in that, The first switched capacitor circuit further includes a third capacitor, a ninth switch, a tenth switch, an eleventh switch, and a twelfth switch; the second switched capacitor circuit further includes a fourth capacitor, a thirteenth switch, a fourteenth switch, a fifteenth switch, and a sixteenth switch. The first terminal of the ninth switch is connected to the first terminal of the first switch; the first terminal of the eleventh switch is connected to the first terminal of the third switch; the first terminal of the thirteenth switch is connected to the first terminal of the fifth switch; the first terminal of the fifteenth switch is connected to the first terminal of the seventh switch; the second terminal of the ninth switch and the first terminal of the tenth switch are connected to the first terminal of the third capacitor; the second terminal of the eleventh switch and the first terminal of the twelfth switch are connected to the second terminal of the third capacitor; the second terminal of the thirteenth switch and the first terminal of the fourteenth switch are connected to the first terminal of the fourth capacitor; the second terminal of the fifteenth switch and the first terminal of the sixteenth switch are connected to the second terminal of the fourth capacitor; the second terminal of the tenth switch and the second terminal of the fourteenth switch are connected to the first voltage; the second terminal of the twelfth switch and the second terminal of the sixteenth switch are connected to the second voltage. The tenth switch, the twelfth switch, the fourteenth switch, and the sixteenth switch close in response to a first level in the first clock signal, and open in response to a second level in the first clock signal; The ninth switch, the eleventh switch, the thirteenth switch, and the fifteenth switch close in response to the first level in the second clock signal, and open in response to the second level in the second clock signal; Specifically, when the tenth, twelfth, fourteenth, and sixteenth switches are closed in response to the first clock signal, the ninth, eleventh, thirteenth, and fifteenth switches are open in response to the second clock signal, and the third and fourth capacitors are in a charging state. When the ninth, eleventh, thirteenth, and fifteenth switches close in response to the second clock signal, the tenth, twelfth, fourteenth, and sixteenth switches open in response to the first clock signal, and the third and fourth capacitors are used to power the OTA.

3. The circuit according to claim 1, characterized in that, The circuit also includes a fifth capacitor and a sixth capacitor; The first terminal of the fifth capacitor is connected to the source of the first PMOS transistor; the second terminal of the fifth capacitor is connected to the source of the second NMOS transistor; the first terminal of the sixth capacitor is connected to the source of the third PMOS transistor; and the second terminal of the sixth capacitor is connected to the source of the fourth NMOS transistor.

4. The circuit according to claim 2, characterized in that, The capacitance values ​​of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are equal.

5. The circuit according to claim 4, characterized in that, The duty cycle of the first clock signal and the second clock signal is 50%; the capacitance values ​​of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are... Among them, T S Indicates the clock periods of the first clock signal and the second clock signal; I B This represents the bias current required for the OTA to function properly; V top V represents the source voltage of the first PMOS transistor; bottom V represents the source voltage of the second NMOS transistor; top -V bottom The value is equal to the sum of the absolute values ​​of the drain-source voltages of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor.

6. The circuit according to claim 5, characterized in that, The first capacitor includes N capacitors with capacitance values ​​of The first sub-capacitor; N≥2; when the first capacitor is in the charging state, N first sub-capacitors are connected in parallel; when the first capacitor is used to power the OTA, N first sub-capacitors are connected in series; The second capacitor includes N capacitors with capacitance values ​​of The second sub-capacitor; when the second capacitor is in a charging state, N second sub-capacitors are connected in parallel; when the second capacitor is used to power the OTA, N second sub-capacitors are connected in series; The third capacitor includes N capacitors with capacitance values ​​of... The third sub-capacitor; when the third capacitor is in a charging state, N third sub-capacitors are connected in parallel; when the third capacitor is used to power the OTA, N third sub-capacitors are connected in series. The fourth capacitor includes N capacitors with capacitance values ​​of... The fourth sub-capacitor; when the fourth capacitor is in a charging state, N fourth sub-capacitors are connected in parallel; when the fourth capacitor is used to power the OTA, N fourth sub-capacitors are connected in series.

7. The circuit according to claim 6, characterized in that, The first voltage and the second voltage satisfy: V L +(V H -V L ) / 2=V bottom +(V top -V bottom ) / 2 and ; Among them, V H V represents the first voltage; L This indicates the second voltage.

8. The circuit according to claim 1, characterized in that, The circuit further includes: a fifth PMOS transistor, a sixth PMOS transistor, and a first operational amplifier; the first input terminal of the first operational amplifier receives the output common-mode voltage of the OTA; the second input terminal of the first operational amplifier receives a reference common-mode voltage; the gates of the fifth PMOS transistor and the sixth PMOS transistor are connected to the output terminal of the first operational amplifier; the sources of the fifth PMOS transistor and the sixth PMOS transistor are connected to a third voltage; the drain of the fifth PMOS transistor is connected to the source of the first PMOS transistor; the drain of the sixth PMOS transistor is connected to the source of the third PMOS transistor; wherein, the output common-mode voltage is the sum of the first output voltage output from the first output terminal of the OTA and the second output voltage output from the second output terminal of the OTA divided by 2.

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