Piezoelectric ring peak Lamb wave resonator with parasitic mode suppression and quality factor improvement based on micro-nano processing technology and manufacturing method thereof

Abstract

The invention discloses a piezoelectric ring peak Lamb wave resonator with parasitic mode suppression and quality factor improvement based on a micro-nano processing technology and a manufacturing method of the piezoelectric ring peak Lamb wave resonator. The resonator mainly comprises a metal upper electrode layer, a piezoelectric film layer, a metal bottom electrode layer and a substrate layer. And the upper electrode comprises a plurality of arc-shaped electrode insertion fingers which are uniformly arranged on the piezoelectric film layer at intervals, are used for acoustic-electric conversion, are consistent in width and are concentric. According to the invention, through two different processes, a ring peak resonator adopting a floating potential bottom electrode which is not connected with a positive electrode and a negative electrode, a ring peak resonator adopting a floating potential bottom electrode which is not connected with a positive electrode and a negative electrode, or a ring peak resonator adopting an arc-shaped interdigital bottom electrode which is connected with an upper electrode through opposite polarities can be respectively manufactured. According to the invention, through the micro-nano processing technology, the technology complexity is reduced; the application of the ring peak Lamb wave can effectively suppress the parasitic mode of the device and reduce the energy loss of the device so as to improve the quality factor, and the ring peak Lamb wave can be widely used for manufacturing the piezoelectric Lamb wave resonator.

Description

Technical Field

[0001] The present invention relates to the design and processing technology of a piezoelectric Lamb wave resonator, and in particular to a piezoelectric ring-peak Lamb wave resonator with parasitic mode suppression and quality factor improvement based on micro-nano processing technology and a manufacturing method thereof. Background Art

[0002] Due to the continuous development of wireless communication technology and the trend of miniaturization of communication equipment, traditional piezoelectric acoustic resonators are beginning to face huge challenges. Piezoelectric Lamb wave resonators, as a new type of piezoelectric acoustic resonator, have become one of the strong candidates for the next generation of piezoelectric acoustic resonators due to their small device size, high acoustic wave phase velocity, and low manufacturing process complexity. However, the current piezoelectric Lamb wave resonators face several major problems: traditional piezoelectric Lamb wave resonators usually use square interdigital electrodes to excite straight-peak Lamb waves on piezoelectric films, but because it is difficult to excite straight-peak Lamb waves that propagate only in a specific direction, traditional piezoelectric Lamb wave resonators are often troubled by various parasitic modes; on the other hand, ideally, the displacement amplitude of the straight-peak Lamb wave will not decrease from the center to the edge of the resonator, which makes the traditional piezoelectric Lamb wave resonator leak more acoustic waves to the surrounding structure, the device energy loss is high, and it is difficult to achieve a high quality factor.

[0003] Patent publication number CN111262543A discloses a Lamb wave resonator based on a single crystal grown scandium-doped aluminum nitride piezoelectric layer, which suppresses parasitic modes by setting a through-hole array structure on the piezoelectric layer in the electrode gap. However, this design complicates the design process on the one hand, and has high requirements on processing accuracy on the other.

[0004] Patent publication number CN112688650A discloses a Lamb wave resonator based on a lithium niobate piezoelectric layer on a high acoustic velocity material substrate, which achieves parasitic mode suppression by partially burying the upper electrode in the piezoelectric film layer. However, this design is difficult to accurately control the actual electrode burying ratio in terms of process, has high process requirements, and increases process production costs. Summary of the invention

[0005] The purpose of the present invention is: in view of the problems existing in the existing piezoelectric Lamb wave resonator, the present invention provides a piezoelectric ring-peak Lamb wave resonator and its manufacturing process with parasitic mode suppression and quality factor improvement based on micro-nano processing technology. Its core function is based on the resonator structure formed by the metal upper electrode layer, the piezoelectric film layer, and the metal bottom electrode layer, as well as the substrate layer for support. The ring-peak Lamb wave excited on the circular or annular piezoelectric thin disk by the arc-shaped interdigitated metal upper electrode propagates radially along the resonator, thereby avoiding the possibility of parasitic modes caused by the excitation of Lamb waves propagating in other directions, and effectively suppressing the parasitic mode; at the same time, the displacement amplitude of the ring-peak Lamb wave decreases from the center to the edge of the device, thereby effectively reducing the leakage of acoustic waves and improving the quality factor of the device; moreover, the process scheme adopted by the resonator has low complexity and effectively controls the production cost.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] In a first aspect, the present invention provides a piezoelectric ring-peak Lamb wave resonator with parasitic mode suppression and quality factor improvement based on micro-nano processing technology, which includes a metal upper electrode layer (a), a piezoelectric film layer (b), a metal bottom electrode layer (c), and a substrate layer (d); wherein:

[0008] The metal upper electrode layer (a) comprises a plurality of arc-shaped electrode fingers (1) uniformly spaced and arranged on the piezoelectric film layer (b);

[0009] The piezoelectric film layer (b) comprises a circular or annular piezoelectric thin disk (2) and an unreleased piezoelectric layer (3);

[0010] The metal bottom electrode layer (c) adopts a floating potential bottom electrode that is not connected to the positive and negative electrodes, or an arc-shaped interdigitated bottom electrode (4) that is connected to the upper electrode with opposite polarity;

[0011] The substrate layer (d) comprises a substrate (6) for supporting the piezoelectric film layer (b) and a release cavity (5);

[0012] The piezoelectric thin disk (2) is arranged on the release cavity (5) of the substrate layer (d), and is connected to the unreleased piezoelectric layer (3) by one or more beams obtained by patterning the piezoelectric film layer (b) and made of the same material as the piezoelectric film layer (b).

[0013] Preferably, the substrate (6) is a high-resistance silicon substrate.

[0014] Preferably, when using an arc-shaped interdigitated bottom electrode connected with the upper electrode in opposite polarity, the bottom electrode needs to be led out to the device surface through a through hole (7).

[0015] Preferably, the number of the arc-shaped electrode fingers (1) is multiple, the width is uniform and they are evenly arranged at equal intervals on the surface of the piezoelectric thin film layer (b); at the same time, the arc-shaped electrode fingers share a common center, and the radius of the arc-shaped electrode fingers is larger as they are closer to the edge of the piezoelectric thin disk.

[0016] Preferably, the arc-shaped electrode fingers (8) are alternately connected to the positive electrode or the negative electrode from the center to the edge of the piezoelectric thin disk (2), and the connection method is to design one or more openings on the arc-shaped electrode fingers to be connected to the positive electrode, design one or more metal electrodes (9) to pass through the openings, connect the arc-shaped electrode fingers to be connected to the negative electrode, and then connect the arc-shaped electrode fingers to be connected to the positive electrode in the same way.

[0017] In a second aspect, the present invention further provides a method for manufacturing the piezoelectric ring-peak Lamb wave resonator according to the first aspect, wherein the manufacturing method is selected from any one of method one and method two, wherein:

[0018] The method 1 comprises the following steps:

[0019] Step 1: growing a piezoelectric layer on a high-resistance silicon substrate;

[0020] Step 2: Making a metal upper electrode on the piezoelectric layer;

[0021] Step 3: Deposit a layer of silicon oxide, and pattern the silicon oxide layer by applying a resin, photolithography, developing, and then etching;

[0022] Step 4: After removing the remaining photoresist in step 3, the piezoelectric layer is etched;

[0023] Step 5: Thinning the high-resistance silicon substrate from the back side through a wafer thinning process;

[0024] Step 6: Apply glue, photolithography, and development on the back of the thinned high-resistance silicon substrate, and then use the xenon difluoride dry etching process to etch the back silicon substrate of the device area; the purpose is to release the piezoelectric layer in the device area so that the device can work normally after completion;

[0025] Step 7: depositing a bottom electrode metal on the back of the piezoelectric layer in the device area to form a bottom electrode;

[0026] Step 8: Remove the front silicon oxide layer to complete the device fabrication.

[0027] The second method comprises the following steps:

[0028] Step S1: preparing a metal bottom electrode on a high-resistance silicon substrate;

[0029] Step S2: growing a piezoelectric layer;

[0030] Step S3: depositing a layer of silicon oxide, and patterning the silicon oxide layer by coating, photolithography, development, and etching;

[0031] Step S4: After removing the remaining photoresist in step S3, the piezoelectric layer is etched to define release holes and upper and lower electrode holes. The etching process can adopt various methods such as ICP-RIE, RIE, wet etching, IBE, etc.

[0032] Step S5: removing the front silicon oxide layer;

[0033] Step S6: depositing the upper electrode metal through a lift-off process and patterning it. The thickness of the photoresist used in the spin coating should be greater than the thickness of the electrode metal;

[0034] Step S7: Use xenon difluoride dry etching process to etch the substrate silicon to release the device, completing the device manufacturing.

[0035] Preferably, the piezoelectric layer is grown in step 1 and step S2 by magnetron sputtering, epitaxial molecular beam growth (MBE) or substrate transfer process; the material of the piezoelectric layer is one or more of aluminum nitride, scandium-doped aluminum nitride and zinc oxide.

[0036] Preferably, the metal upper electrode in step 2 is prepared in the same manner as the metal bottom electrode in step S1, and the metal upper electrode or the metal bottom electrode is prepared by depositing electrode metal and coating, photolithography, development, and then etching, or depositing electrode metal and patterning by a lift-off process, and the thickness of the photoresist spin coating used at this time should be greater than the thickness of the electrode metal;

[0037] Before depositing the electrode metal, titanium metal is first deposited as an adhesion layer; the deposition is performed by thermal evaporation, electron beam evaporation or magnetron sputtering;

[0038] The electrode metal is selected from one or more of aluminum, platinum, gold and molybdenum.

[0039] Preferably, the etching process involved in the method 1 and the method 2 adopts inductively coupled reactive ion etching (ICP-RIE), ion beam etching (IBE), hydrogen fluoride dry vapor etching or wet etching.

[0040] Preferably, titanium metal is first deposited as an adhesion layer before depositing the bottom electrode metal in step 7; the bottom electrode metal is selected from one or more of aluminum, platinum, gold and molybdenum, and the deposition is performed by thermal evaporation, electron beam evaporation or magnetron sputtering process.

[0041] Preferably, titanium metal is first deposited as an adhesion layer before depositing the upper electrode metal in step S6; the upper electrode metal is selected from one or more of aluminum, platinum, gold and molybdenum, and the deposition is performed by thermal evaporation, electron beam evaporation or magnetron sputtering.

[0042] More preferably, the material of the piezoelectric layer is Al 0.8 Sc 0.2 N, its thickness is 0.1 to 10.0 microns.

[0043] More preferably, the thickness of the adhesion layer is 1 to 200 nm.

[0044] Compared with the prior art, the present invention has the following beneficial effects:

[0045] The present invention uses an arc-shaped interdigitated metal upper electrode to excite a ring-peak Lamb wave on a circular or annular piezoelectric thin disk, which propagates radially along the resonator, thereby avoiding the possibility of generating parasitic modes due to the excitation of Lamb waves propagating in other directions, and effectively suppressing parasitic modes; at the same time, the displacement amplitude of the ring-peak Lamb wave decreases from the center to the edge of the device, thereby effectively reducing acoustic wave leakage and improving the quality factor of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A 3D cross-sectional view of a piezoelectric ring-peak Lamb wave resonator using a floating potential bottom electrode not connected to a positive or negative electrode, manufactured using the first process (Example 1) of the present invention;

[0047] Figure 2 A 3D cross-sectional view of a piezoelectric ring-peak Lamb wave resonator using an arc-shaped interdigitated bottom electrode connected to an upper electrode with opposite polarity, manufactured using the second process (Example 2) of the present invention;

[0048] Figure 3 2D schematic diagram of a metal upper electrode formed by arc-shaped metal fingers used in the present invention;

[0049] Figure 4 It is a 3D schematic diagram of a piezoelectric ring-peak Lamb wave resonator using a floating potential bottom electrode not connected to a positive or negative electrode and a circular piezoelectric thin disk, which is manufactured using the first process (Example 1) of the present invention;

[0050] Figure 5 It is a 3D schematic diagram of a piezoelectric ring-peak Lamb wave resonator using a floating potential bottom electrode not connected to a positive or negative electrode and an annular piezoelectric thin disk, which is manufactured using the first process (Example 1) of the present invention;

[0051] Figure 6 A 3D cross-sectional view of a piezoelectric ring-peak Lamb wave resonator using an arc-shaped interdigitated bottom electrode connected to an upper electrode with opposite polarity and a circular piezoelectric thin disk, manufactured using the second process (Example 2) of the present invention;

[0052] Figure 7A 3D cross-sectional view of a piezoelectric ring-peak Lamb wave resonator using an arc-shaped interdigitated bottom electrode connected to an upper electrode with opposite polarity and an annular piezoelectric thin disk, manufactured using the second process (Example 2) of the present invention;

[0053] Figure 8 This is a process flow chart of the first manufacturing process (Example 1) of the method of the present invention; (1) to (8) in the figure represent steps 1 to 8 of the manufacturing process;

[0054] Fig. 9 This is a process flow chart of the second manufacturing process (Example 2) of the method of the present invention; (1) to (7) in the figure respectively represent steps 1 to 7 of the manufacturing process;

[0055] Fig.10 It is a schematic diagram of the structure obtained after a piezoelectric layer is deposited on a high-resistance silicon substrate in the first manufacturing process (Example 1) of the present invention;

[0056] Fig.11 For Fig.10 A schematic diagram of a structure obtained by depositing and patterning a metal layer on the basis of the arc-shaped interdigitated metal upper electrode;

[0057] Fig.12 For Fig.11 Schematic diagram of the structure obtained by depositing the silicon oxide layer by PECVD and patterning the silicon oxide layer by RIE or wet etching;

[0058] Fig.13 For Fig.12 Schematic diagram of the structure obtained after the piezoelectric layer is patterned by ICP-RIE;

[0059] Fig.14 For Fig.13 Schematic diagram of the structure obtained by thinning the silicon substrate from the back side by the wafer thinning process based on the present invention;

[0060] Fig.15 For Fig.14 Schematic diagram of the structure obtained after releasing the piezoelectric layer film from the back through the xenon difluoride etching process;

[0061] Fig.16 For Fig.15 A schematic diagram of the structure obtained by depositing metal on the back of the piezoelectric layer film through an electron beam evaporation process to form a bottom electrode;

[0062] Fig.17 For Fig.16 Schematic diagram of the structure obtained after removing the front silicon oxide layer through a reactive ion etching process;

[0063] Fig.18It is a schematic diagram of the structure obtained after a metal layer is deposited and patterned on a high-resistance silicon substrate to form a metal bottom electrode in the second manufacturing process (Example 2) of the present invention;

[0064] Fig.19 For Fig.18 Schematic diagram of the structure obtained by depositing the piezoelectric layer by magnetron sputtering on the basis of FIG.

[0065] Fig. 20 For Fig.19 Schematic diagram of the structure obtained by depositing the silicon oxide layer by PECVD and patterning the silicon oxide layer by RIE or wet etching;

[0066] Fig.21 For Fig. 20 Schematic diagram of the structure obtained after the piezoelectric layer is patterned by ICP-RIE;

[0067] Fig. 22 For Fig.21 Schematic diagram of the structure obtained after removing the front silicon oxide layer by RIE;

[0068] Fig.23 For Fig. 22 A schematic diagram of a structure obtained by depositing and patterning a metal layer on the basis of the arc-shaped interdigitated metal upper electrode;

[0069] Fig.24 For Fig.23 Schematic diagram of the structure obtained after releasing the piezoelectric layer film from the front through a xenon difluoride etching process. DETAILED DESCRIPTION

[0070] In order to make the present invention more clearly understood, preferred embodiments are described in detail below with reference to the accompanying drawings.

[0071] The present invention provides a piezoelectric ring-peak Lamb wave resonator with parasitic mode suppression and quality factor improvement based on micro-nano processing technology, such as Figures 1 to 7 As shown, it includes a metal upper electrode layer a, a piezoelectric film layer b, a metal bottom electrode layer c, and a substrate layer d; wherein:

[0072] The metal upper electrode layer a comprises a plurality of arc-shaped electrode fingers 1 evenly spaced and arranged on the piezoelectric film layer b;

[0073] The piezoelectric film layer b includes a circular or annular piezoelectric thin disk 2 and an unreleased piezoelectric layer 3;

[0074] The metal bottom electrode layer c adopts a floating potential bottom electrode that is not connected to the positive and negative electrodes, or an arc-shaped interdigitated bottom electrode 4 that is connected to the upper electrode with opposite polarity;

[0075] The substrate layer d includes a substrate 6 for supporting the piezoelectric film layer b and a release cavity 5;

[0076] The piezoelectric thin disk 2 is disposed on the release cavity 5 of the substrate layer d, and is connected to the unreleased piezoelectric layer 3 by one or more beams obtained by patterning the piezoelectric film layer b and made of the same material as the piezoelectric film layer b.

[0077] Wherein, the substrate 6 is a high-resistance silicon substrate.

[0078] When an arc-shaped interdigitated bottom electrode connected with the upper electrode in opposite polarity is used, the bottom electrode needs to be led out to the device surface through the through hole 7 .

[0079] Among them, there are multiple arc-shaped metal fingers 1 constituting the metal upper electrode, which have uniform width and are evenly arranged at equal intervals on the surface of the piezoelectric film layer; at the same time, the arc-shaped metal fingers have a common center, and the radius of the arc-shaped metal fingers is larger as they are closer to the edge of the piezoelectric thin disk.

[0080] The arc electrode fingers 8 are alternately connected to the positive electrode or the negative electrode from the center to the edge of the piezoelectric thin disk 2. The connection method is to design one or more openings on the arc electrode fingers to be connected to the positive electrode, and design one or more metal electrodes 9 to pass through the openings to connect the arc electrode fingers to be connected to the negative electrode, and then connect the arc electrode fingers to be connected to the positive electrode in the same way.

[0081] The manufacturing process of the present invention is mainly divided into two types. The first manufacturing process includes preparing a piezoelectric layer on a high-resistance silicon substrate by a magnetron sputtering process, epitaxial molecular beam growth (MBE), substrate transfer and other processes; depositing metal by a magnetron sputtering, electron beam evaporation or thermal evaporation process and forming an upper electrode by wet or dry etching patterning, or preparing an upper electrode by a lift-off process; preparing a silicon oxide hard mask by a plasma enhanced chemical vapor deposition (PECVD), magnetron sputtering and other processes; preparing a silicon oxide hard mask by a reactive ion etching (RIE), wet etching, hydrogen fluoride dry vapor The silicon oxide hard mask is patterned by etching and other processes; the piezoelectric layer is patterned by wet etching, inductively coupled reactive ion etching (ICP-RIE), RIE, ion beam etching (IBE) and other processes; the silicon substrate is thinned from the back by wafer thinning process; the silicon substrate on the back of the device area is etched by xenon difluoride dry etching process to complete the device release; metal is deposited on the back of the piezoelectric layer in the device area by magnetron sputtering, electron beam evaporation or thermal evaporation to form a bottom electrode; finally, the front silicon oxide mask is removed by RIE and other processes to complete the device manufacturing. This manufacturing process can be used to manufacture a ring peak resonator with a floating potential bottom electrode that is not connected to the positive and negative poles. The second manufacturing process includes depositing metal by magnetron sputtering, electron beam evaporation or thermal evaporation and forming a bottom electrode by wet or dry etching patterning, or preparing a bottom electrode by a lift-off process; preparing a piezoelectric layer by a magnetron sputtering process; preparing a silicon oxide hard mask by PECVD, magnetron sputtering and other processes; patterning the silicon oxide hard mask by RIE, wet etching, hydrogen fluoride dry vapor etching and other processes; patterning the piezoelectric layer by wet etching ICP-RIE, RIE, IBE and other processes to define release holes and upper and lower electrode through holes; removing the front silicon oxide mask by RIE and other processes; depositing metal by magnetron sputtering, electron beam evaporation or thermal evaporation and preparing an upper electrode and metal connecting the upper and lower electrode through holes by a lift-off process; and finally releasing the device from the front by a xenon difluoride dry etching process. This manufacturing process can be used to make a ring peak resonator using a floating potential bottom electrode that is not connected to the positive and negative poles, or an arc-shaped interdigitated bottom electrode connected to the upper electrode with opposite polarity.

[0082] Example 1

[0083] This embodiment provides a piezoelectric ring-peak Lamb wave resonator with parasitic mode suppression and quality factor improvement based on micro-nano processing and a manufacturing method thereof. The structure of the ring-peak Lamb wave resonator is as follows: Figure 1 , 4 , 5, the production method includes the following steps (process flow as shown in Figure 8 shown):

[0084] 1. Fabrication of piezoelectric film layer b: A 710 μm thick high-resistance silicon wafer is used as the substrate, and a 1.1 μm thick Al2O3 layer is deposited on the surface of the silicon wafer using a reactive magnetron sputtering process. 0.8 Sc 0.2 N piezoelectric layer, complete the production of piezoelectric film layer b, such as Fig.10 shown.

[0085] 2. Fabrication of the metal upper electrode layer a: Spin-coat the lift-off photoresist (LOR) and the ordinary photoresist in sequence and pre-bake them respectively, use the first mask to prepare the sacrificial layer of the lift-off process according to the standard photolithography process, then deposit 10 nanometers thick titanium and 200 nanometers thick platinum by electron beam evaporation, and finally remove the photoresist by PG Remover organic solution to complete the fabrication of the metal upper electrode layer a, such as Fig.11 shown.

[0086] 3. Make a silicon oxide hard mask: Use PECVD to deposit a 4-micron thick silicon oxide layer on the device surface. Spin-coat photoresist, use the second mask to expose, and develop, and use reactive ion etching to completely etch the 4-micron thick PECVD silicon oxide layer to complete the production of the silicon oxide hard mask. Fig.12 shown.

[0087] 4. Patterning piezoelectric film layer b: Using ICP-RIE process, completely etch the 1.1 μm thick Al0.8Sc0.2N piezoelectric layer to complete the patterning of piezoelectric film layer b, such as Fig.13 shown.

[0088] 5. Thinning the substrate layer d: Use the wafer thinning process to thin the silicon wafer from the back to 350 microns to complete the thinning of the substrate layer d, such as Fig.14 shown.

[0089] 6. Etching substrate layer d: Spin-coat photoresist on the back of the silicon wafer, use the third mask to expose and develop, and then completely etch the substrate silicon through the xenon difluoride etching process to complete the etching of substrate layer d and release the device, such as Fig.15 shown.

[0090] 7. Fabrication of metal bottom electrode layer c: Using electron beam evaporation process, 10 nanometers thick titanium and 200 nanometers thick platinum are deposited on the back of the released piezoelectric layer to form a bottom electrode, completing the fabrication of metal bottom electrode layer c, such as Fig.16 shown.

[0091] 8. Remove the silicon oxide hard mask: Use RIE to completely remove the 4-micron thick silicon oxide layer on the front side, complete the silicon oxide hard mask removal, and expose the front electrode, such as Fig.17 shown.

[0092] Example 2

[0093] This embodiment provides a piezoelectric ring-peak Lamb wave resonator with parasitic mode suppression and quality factor improvement based on micro-nano processing and a manufacturing method thereof. The structure of the ring-peak Lamb wave resonator is as follows: Figure 2 , 6 , 7, the production method includes the following steps (process flow as shown in Fig. 9 shown):

[0094] 1. Fabrication of metal bottom electrode layer c: A 710 μm thick high-resistance silicon wafer is used as the substrate, and the first mask is used to prepare the sacrificial layer of the lift-off process according to the standard photolithography process. Then, 10 nm thick titanium and 200 nm thick platinum are deposited by electron beam evaporation. Finally, the photoresist is removed by PG Remover organic solution to complete the fabrication of the metal bottom electrode layer c. Fig.18 shown.

[0095] 2. Fabrication of piezoelectric film layer b: Using reactive magnetron sputtering technology to deposit a 1.1 μm thick Al0.8Sc0.2N piezoelectric layer on the surface of the silicon wafer, the piezoelectric film layer b is fabricated. Fig.19 shown.

[0096] 3. Make a silicon oxide hard mask: Use PECVD to deposit a 4-micron thick silicon oxide layer on the device surface. Spin-coat photoresist, use the second mask to expose, and develop, and use reactive ion etching to completely etch the 4-micron thick PECVD silicon oxide layer to complete the production of the silicon oxide hard mask. Fig. 20 shown.

[0097] 4. Patterning piezoelectric film layer b: Using ICP-RIE process, completely etch the 1.1 μm thick Al0.8Sc0.2N piezoelectric layer to complete the patterning of piezoelectric film layer b, such as Fig.21 shown.

[0098] 5. Remove the silicon oxide hard mask: Use RIE to completely remove the 4-micron thick silicon oxide layer on the front side, complete the removal of the silicon oxide hard mask, and expose the front piezoelectric layer, such as Fig. 22 shown.

[0099] 6. Fabrication of the metal upper electrode layer a: Use the third mask plate to prepare the sacrificial layer of the lift-off process according to the standard photolithography process, then deposit 10 nanometers thick titanium and 200 nanometers thick platinum by electron beam evaporation, and finally remove the photoresist by PGRemover organic solution to complete the fabrication of the metal upper electrode layer a, such as Fig.23 shown.

[0100] 7. Etching substrate layer d: Etching the substrate silicon through the xenon difluoride etching process to complete the etching of the substrate layer d and release the device, such as Fig.24 shown.

[0101] The above description is only a preferred embodiment of the present invention and is not any formal or substantial limitation of the present invention. It should be pointed out that a person skilled in the art can make several improvements and supplements without departing from the present invention, and these improvements and supplements should also be regarded as the protection scope of the present invention.

Claims

1. A piezoelectric ring-peak Lamb wave resonator with parasitic mode suppression and quality factor improvement based on micro-nano processing technology, characterized in that: The invention comprises a metal upper electrode layer (a), a piezoelectric film layer (b), a metal bottom electrode layer (c), and a substrate layer (d); wherein: The metal upper electrode layer (a) comprises a plurality of arc-shaped electrode fingers (1) uniformly spaced and arranged on the piezoelectric film layer (b); The piezoelectric film layer (b) comprises a circular or annular piezoelectric thin disk (2) and an unreleased piezoelectric layer (3); The metal bottom electrode layer (c) adopts a floating potential bottom electrode that is not connected to the positive and negative electrodes, or an arc-shaped interdigitated bottom electrode (4) that is connected to the upper electrode with opposite polarity; The substrate layer (d) comprises a substrate (6) for supporting the piezoelectric film layer (b) and a release cavity (5); The piezoelectric thin disk (2) is arranged on the release cavity (5) of the substrate layer (d), and is connected to the unreleased piezoelectric layer (3) by one or more beams obtained by patterning the piezoelectric film layer (b) and made of the same material as the piezoelectric film layer (b).

2. The piezoelectric ring-peak Lamb wave resonator according to claim 1, characterized in that: The substrate (6) is a high-resistance silicon substrate.

3. The piezoelectric ring-peak Lamb wave resonator according to claim 1, characterized in that: When using an arc-shaped interdigitated bottom electrode connected with the upper electrode in opposite polarity, it is necessary to lead the bottom electrode to the surface of the device through a through hole (7).

4. The piezoelectric ring-peak Lamb wave resonator according to claim 1, characterized in that: The number of the arc-shaped electrode fingers (1) is multiple, the width is uniform and they are evenly arranged at equal intervals on the surface of the piezoelectric thin film layer (b); at the same time, the arc-shaped electrode fingers share a common center, and the radius of the arc-shaped electrode fingers is larger as they are closer to the edge of the piezoelectric thin disk.

5. The piezoelectric ring-peak Lamb wave resonator according to claim 1, characterized in that: The arc-shaped electrode fingers (8) are alternately connected to the positive electrode or the negative electrode from the center to the edge of the piezoelectric thin disk (2). The connection method is to design one or more openings on the arc-shaped electrode fingers to be connected to the positive electrode, design one or more metal electrodes (9) to pass through the openings, connect the arc-shaped electrode fingers to be connected to the negative electrode, and then connect the arc-shaped electrode fingers to be connected to the positive electrode in the same way.

6. The method for manufacturing a piezoelectric ring-peak Lamb wave resonator according to any one of claims 1 to 5, characterized in that: The production method is selected from any one of method 1 and method 2, wherein: The method 1 comprises the following steps: Step 1: growing a piezoelectric layer on a high-resistance silicon substrate; Step 2: Making a metal upper electrode on the piezoelectric layer; Step 3: Deposit a layer of silicon oxide, and pattern the silicon oxide layer by applying a resin, photolithography, developing, and then etching; Step 4: After removing the remaining photoresist in step 3, the piezoelectric layer is etched; Step 5: Thinning the high-resistance silicon substrate from the back side through a wafer thinning process; Step 6: Apply glue, photolithography, and development on the back of the thinned high-resistance silicon substrate, and then use the xenon difluoride dry etching process to etch the back silicon substrate of the device area; the purpose is to release the piezoelectric layer in the device area so that the device can work normally after completion; Step 7: depositing a bottom electrode metal on the back of the piezoelectric layer in the device area to form a bottom electrode; Step 8: Remove the front silicon oxide layer to complete the device fabrication. The second method comprises the following steps: Step S1: preparing a metal bottom electrode on a high-resistance silicon substrate; Step S2: growing a piezoelectric layer; Step S3: depositing a layer of silicon oxide, and patterning the silicon oxide layer by coating, photolithography, development, and etching; Step S4: After removing the remaining photoresist in step S3, the piezoelectric layer is etched to define release holes and upper and lower electrode holes. The etching process can adopt various methods such as ICP-RIE, RIE, wet etching, IBE, etc. Step S5: removing the front silicon oxide layer; Step S6: depositing the upper electrode metal through a lift-off process and patterning it. The thickness of the photoresist used in the spin coating should be greater than the thickness of the electrode metal; Step S7: Use xenon difluoride dry etching process to etch the substrate silicon to release the device, completing the device manufacturing.

7. The method according to claim 6, characterized in that The piezoelectric layer is grown in step 1 and step S2 by magnetron sputtering, epitaxial molecular beam growth (MBE) or substrate transfer technology; the material of the piezoelectric layer is selected from one or more of aluminum nitride, scandium-doped aluminum nitride and zinc oxide.

8. The method according to claim 6, characterized in that The metal upper electrode in step 2 is prepared in the same manner as the metal bottom electrode in step S1. The metal upper electrode or the metal bottom electrode is prepared by depositing electrode metal and coating, photolithography, development, and then etching, or depositing electrode metal and patterning by a lift-off process. The thickness of the photoresist spin coating used at this time should be greater than the thickness of the electrode metal. Before depositing the electrode metal, titanium metal is first deposited as an adhesion layer; the deposition is performed by thermal evaporation, electron beam evaporation or magnetron sputtering; The electrode metal is selected from one or more of aluminum, platinum, gold and molybdenum.

9. The method according to claim 6, characterized in that The etching processes involved in the method 1 and the method 2 adopt inductively coupled reactive ion etching (ICP-RIE), ion beam etching (IBE), hydrogen fluoride dry steam etching or wet etching.

10. The method according to claim 6, characterized in that In the step 7, titanium metal is first deposited as an adhesion layer before depositing the bottom electrode metal; the bottom electrode metal is selected from one or more of aluminum, platinum, gold and molybdenum, and the deposition is performed by thermal evaporation, electron beam evaporation or magnetron sputtering; Before depositing the upper electrode metal in step S6, titanium metal is first deposited as an adhesion layer; the upper electrode metal is selected from one or more of aluminum, platinum, gold and molybdenum, and the deposition is performed by thermal evaporation, electron beam evaporation or magnetron sputtering.

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