Non-inductive numerical control attenuator based on active resistor

Abstract

The invention discloses a non-inductive numerical control attenuator based on an active resistor. The device is formed by connecting a plurality of attenuation modules with different attenuation functions in series. The attenuation module is an improved attenuation module and comprises an attenuation unit, an input end, an output end, a control end and a level end. The input end and the output end are respectively used as two ports of the attenuation unit, so that a circuit can be conveniently accessed; the control end is used for connecting a digital control signal to the attenuation unit; and the level end is used for connecting a high level to the attenuation unit. The three-well structure NMOS field effect transistor with the alternating current floating body technology and the alternating current floating gate technology is continuously in a conducting state, an active resistor is achieved and serves as an attenuation resistor, the high-frequency stray capacitance effect is effectively reduced, and therefore the stability of the resistor and the stability of the stray capacitance of the resistor in a frequency band are guaranteed.

Description

Technical Field

[0001] The invention belongs to the technical field of basic electronic circuits, and in particular relates to an inductor-free digitally controlled attenuator based on an active resistor. Background Art

[0002] As an amplitude control unit, the attenuator plays a key role in communication, radar and measurement systems, and its performance directly affects the system effect. The main performance indicators of the attenuator include working bandwidth, attenuation dynamic range, attenuation step, attenuation accuracy, additional phase shift and insertion loss. Common attenuator structures include switch path type, distributed and switch embedded type. The switch path type structure causes large insertion loss and large chip footprint due to the large number of SPDT switches used; the distributed structure also cannot avoid the problem of excessive chip area due to the use of a large number of transmission lines.

[0003] The switch embedded structure is widely used in attenuator design to achieve a large attenuation range and low insertion loss in a small area. This structure includes T-type, bridge T-type and π-type. When designing, the number of attenuation units, attenuation amount and structure type are usually determined according to the attenuation range and attenuation step.

[0004] When designing a switch-embedded attenuation unit, a switch transistor control circuit is usually used to absorb and convert electromagnetic energy through a passive attenuation resistor to achieve signal attenuation. However, since the switch transistor is built into the structure of the switch-embedded attenuation unit and is equivalent to a resistor and a capacitor in the on and off states, respectively, its on and off states will cause changes in the input and output impedances in the reference state and the attenuation state. Through this impedance change, the insertion loss difference between the reference state and the attenuation state can be adjusted to achieve the required attenuation. This is the basic principle of the switch-embedded attenuation unit to achieve signal attenuation, but this impedance change will also cause phase errors while achieving signal attenuation. In addition, in high-frequency design, the parasitic capacitance effect of the passive attenuation resistor may cause significant changes in the input and output impedances, thereby affecting the frequency response and overall performance of the attenuator. Furthermore, due to the limitations of different attenuation amounts and attenuation structures, there may be different degrees of inter-stage mismatch between the attenuation units, and inter-stage inductors are usually required for matching, which may increase the chip area of ​​the attenuator.

[0005] Since the performance of the attenuator is difficult to optimize at the same time, the existing structure usually focuses on optimizing one or two key indicators, the most common of which are attenuation accuracy and additional phase shift. In order to achieve a better additional phase shift, capacitive compensation technology is usually used to reduce the phase difference between the reference state and the attenuation state. However, although capacitive compensation technology has been widely used in phase compensation, the existing solutions have not been able to completely solve the phase error problem caused by parasitic capacitance. While achieving a smaller chip area, further optimizing the comprehensive performance such as attenuation accuracy and additional phase shift still faces great challenges. Therefore, it is urgent to explore new solutions to achieve better comprehensive performance in a compact area. Summary of the invention

[0006] The object of the present invention is to overcome the above-mentioned deficiencies of the prior art and provide an inductor-free digitally controlled attenuator based on an active resistor.

[0007] The technical solutions adopted by the present invention to achieve the above-mentioned purpose are as follows: An inductorless digitally controlled attenuator based on an active resistor, the digitally controlled attenuator being composed of a plurality of attenuation modules with different attenuation functions connected in series; wherein the input end of the first attenuation module serves as the radio frequency input end of the digitally controlled attenuator, and the output end of the last attenuation module serves as the radio frequency output end of the digitally controlled attenuator; The attenuation module adopts an improved attenuation module, including an attenuation unit, an input end, an output end, a control end and a level end; the input end and the output end are respectively used as two ports of the attenuation unit, which are convenient for connecting to the circuit; the control end is used to connect the digital control signal to the attenuation unit; the level end is used to connect the high level to the attenuation unit.

[0008] Preferably, the attenuation unit includes an improved switch embedded attenuation structure and a compensation capacitor; the improved switch embedded attenuation structure specifically replaces the passive attenuation resistor in the switch embedded attenuation structure with an active resistor, and introduces a compensation capacitor into the improved switch embedded attenuation structure for phase compensation.

[0009] Preferably, the improved switch embedded attenuation structure includes a switching transistor and an active resistor; the switching transistor is used to control the state switching of the improved switch embedded attenuation structure, and the active resistor is used as the attenuation resistor to achieve the required signal amplitude attenuation; at the same time, the capacitive compensation technology is used to adjust the phase difference between the reference state and the attenuation state, thereby achieving phase compensation.

[0010] Preferably, in the improved switch embedded attenuation structure, the switch transistor and the active resistor are both field effect transistors, preferably triple-well NMOS field effect transistors, and more preferably triple-well NMOS field effect transistors with AC floating body technology and AC floating gate technology.

[0011] Preferably, the triple-well structure NMOS field effect transistor with AC floating body technology and AC floating gate technology includes a DC control end, an input end, an output end, a triple-well structure NMOS field effect transistor M2, a first passive resistor R1, and a second passive resistor R2; the gate of the triple-well structure NMOS field effect transistor M2 is connected to one end of the first passive resistor R1; the other end of the first passive resistor R1 serves as a DC control end to access a digital control signal or a high level; the substrate of the triple-well structure NMOS field effect transistor M2 is connected to one end of the second passive resistor R2, and the other end of the second passive resistor R2 is connected to the power ground; the drain and source of the triple-well structure NMOS field effect transistor M2 serve as the input end and the output end, respectively, to facilitate access to the circuit.

[0012] Preferably, when the triple-well structure NMOS field effect transistor with AC floating body technology and AC floating gate technology is used as a switching transistor, the DC control terminal is connected to a digital control signal, and the triple-well structure NMOS field effect transistor M2 is in an on or off state, which is used to control the state switching of the improved switch embedded attenuation structure; when the control signal is at a high level, the triple-well structure NMOS field effect transistor M2 is turned on and the signal path is opened; when the control signal is at a low level, the triple-well structure NMOS field effect transistor M2 is turned off and the signal path is closed.

[0013] Preferably, when the triple-well structure NMOS field effect transistor with AC floating body technology and AC floating gate technology is used as an active resistor, the DC control terminal is connected to a high level as a level input terminal, and the triple-well structure NMOS field effect transistor M2 is continuously turned on to reduce the high-frequency parasitic capacitance effect.

[0014] Preferably, in the improved switch embedded attenuation structure, the active resistor is connected to the circuit in series or in parallel.

[0015] Preferably, each attenuation module in the digitally controlled attenuator adopts one of an improved switch-embedded simple T-shaped structure with a compensation capacitor, an improved switch-embedded asymmetric T-shaped structure, and an improved switch-embedded π-shaped structure.

[0016] Preferably, by controlling the high and low level states of the digital control signal of each attenuation module, signal amplitude attenuation in various states is achieved within the operating frequency range and within the attenuation range with a fixed step length.

[0017] Compared with the prior art, the present invention has the following beneficial effects: (1) The present invention aims at the problem of significant parasitic capacitance effect generated by passive attenuation resistors in traditional switch embedded attenuators in high-frequency circuit design, and the serious deterioration of circuit performance caused by this. By making the Triple-well NMOS (triple-well structure N-type metal-oxide-semiconductor) field effect transistor with AC floating body technology and AC floating gate technology continuously in the on state, a Triple-well NMOS active resistor is realized. The Triple-well NMOS active resistor is used instead of the traditional passive attenuation resistor as the attenuation resistor, which effectively reduces the high-frequency parasitic capacitance effect, thereby ensuring the stability of the resistor and its parasitic capacitance within the frequency band.

[0018] (2) The present invention adopts triple-well NMOS field effect transistors as switch transistors and active resistors, improves the switch embedded attenuation structure, and combines capacitive compensation technology for phase compensation, forming an improved switch embedded attenuation structure with compensation capacitors, which further effectively reduces the amplitude and phase errors.

[0019] (3) Based on the optimization of the performance of each attenuation unit by using an improved switch embedded attenuation structure with compensation capacitors, the present invention analyzes the S parameters and input and output impedances of each attenuation unit and carefully designs the arrangement order of each attenuation unit. Finally, without the need for an inter-stage inductor, the minimum core area of ​​the switch embedded attenuator is achieved, which has the advantage of being easy to achieve miniaturization.

[0020] (4) The present invention overcomes the difficulties of the prior art by adopting a triple-well NMOS active resistor and an inductor-free design, achieving excellent comprehensive performance in a compact core area and having excellent temperature robustness. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 This is the structural block diagram of the digital controlled attenuator.

[0023] Figure 2 (a) is the structural block diagram of the traditional attenuation module.

[0024] Figure 2 (b) is a structural block diagram of the improved attenuation module of the present invention.

[0025] Figure 3It is a structural block diagram of the digital controlled attenuator of the present invention.

[0026] Figure 4 This is a microscopic photograph of the chip of the digitally controlled attenuator of the present invention.

[0027] Figure 5 (a) is the circuit topology diagram of NMOS field effect transistor.

[0028] Figure 5 (b) is a circuit topology diagram of the Triple-well NMOS field effect transistor with AC floating body technology and AC floating gate technology of the present invention.

[0029] Figure 6 (a) is the circuit topology diagram of a traditional passive attenuation resistor in series.

[0030] Figure 6 (b) is a circuit topology diagram of the triple-well NMOS active resistor series connection of the present invention.

[0031] Figure 6 (c) is the circuit topology diagram of the traditional passive attenuation resistor in parallel form.

[0032] Figure 6 (d) is a circuit topology diagram of the triple-well NMOS active resistor in parallel according to the present invention.

[0033] Figure 7 The circuit topology diagram of the improved switch embedded simple T-shaped structure with compensation capacitor of the present invention.

[0034] Figure 8 The circuit topology diagram of the improved switch embedded asymmetric T-type structure with compensation capacitor of the present invention.

[0035] Fig. 9 The circuit topology diagram of the improved switch embedded π-type structure with compensation capacitor of the present invention.

[0036] Fig.10 (a) is a 16Ω resistance simulation comparison result of the Triple-well NMOS active resistor and the passive attenuation resistor of the present invention.

[0037] Fig.10 (b) is a simulation comparison result of the parasitic capacitance of the Triple-well NMOS active resistor and the passive attenuation resistor under a resistance of 16Ω of the present invention.

[0038] Fig.10 (c) is a 31Ω resistance simulation comparison result of the Triple-well NMOS active resistor and the passive attenuation resistor of the present invention.

[0039] Fig.10 (d) is a simulation comparison result of the parasitic capacitance of the Triple-well NMOS active resistor and the passive attenuation resistor under a resistance of 31Ω of the present invention.

[0040] Fig.10 (e) is a 122Ω resistance simulation comparison result of the Triple-well NMOS active resistor and the passive attenuation resistor of the present invention.

[0041] Fig.10 (f) is a simulation comparison result of the parasitic capacitance of the Triple-well NMOS active resistor and the passive attenuation resistor under a resistance of 122Ω of the present invention.

[0042] Fig.10 (g) is a 157Ω resistance simulation comparison result of the Triple-well NMOS active resistor and the passive attenuation resistor of the present invention.

[0043] Fig.10 (h) is a simulation comparison result of the parasitic capacitance of the Triple-well NMOS active resistor and the passive attenuation resistor under a resistance of 157Ω of the present invention.

[0044] Fig.11 (a) is the simulation comparison result of the RMS amplitude error of the digital controlled attenuator of the present invention under high and low temperature conditions.

[0045] Fig.11 (b) is the simulation comparison result of the root mean square phase error of the digital controlled attenuator of the present invention under high and low temperature conditions.

[0046] Fig.11 (c) is the S11 simulation comparison result of the digital controlled attenuator of the present invention under high and low temperature conditions.

[0047] Fig.11 (d) is the S22 simulation comparison result of the digital controlled attenuator of the present invention under high and low temperature conditions.

[0048] Fig.11 (e) is the insertion loss simulation comparison result of the digital controlled attenuator of the present invention under high and low temperature conditions. DETAILED DESCRIPTION

[0049] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0050] See also Figure 1As shown, an embodiment of the present invention provides an inductor-free digitally controlled attenuator based on an active resistor, wherein the digitally controlled attenuator is composed of K attenuation modules with different attenuation functions connected in series; wherein the input end of the first attenuation module serves as the RF input end of the digitally controlled attenuator, and the output end of the last attenuation module serves as the RF output end of the digitally controlled attenuator; by controlling the high and low level states of the digital control signals of each attenuation module, within the operating frequency range, within the attenuation range with a fixed step length, signal amplitude attenuation in multiple states is achieved.

[0051] See also Figure 2 As shown in (b), the attenuation module adopts an improved attenuation module. Figure 2 The traditional attenuation module shown in (a) has an additional level terminal; specifically, it includes an attenuation unit, an input terminal, an output terminal, a control terminal and a level terminal; the input terminal and the output terminal are respectively used as two ports of the attenuation unit, which are convenient for connecting to the circuit; the control terminal is used to connect the digital control signal to the attenuation unit; the level terminal is used to connect the high level to the attenuation unit.

[0052] By way of example, the attenuation unit includes an improved switch embedded attenuation structure and a compensation capacitor; the improved switch embedded attenuation structure specifically replaces the passive attenuation resistor in the switch embedded attenuation structure with an active resistor, and introduces a compensation capacitor into the improved switch embedded attenuation structure for phase compensation.

[0053] Specifically, the improved switch embedded attenuation structure includes a switching transistor and an active resistor; the state switching of the improved switch embedded attenuation structure is controlled by the switching transistor, and the active resistor is used as the attenuation resistor to achieve the required signal amplitude attenuation; at the same time, the capacitive compensation technology is used to adjust the phase difference between the reference state and the attenuation state, thereby achieving phase compensation.

[0054] In one implementation manner, in the improved switch embedded attenuation structure, the switch transistor and the active resistor are both field effect transistors, preferably triple-well structure NMOS field effect transistors, and more preferably triple-well structure NMOS field effect transistors with AC floating body technology and AC floating gate technology.

[0055] NMOS field effect transistors can be found in Figure 5 The circuit topology diagram is shown in (a).

[0056] Triple-well NMOS field-effect transistors with AC floating body technology and AC floating gate technology can be found in Figure 5The circuit topology shown in (b) specifically includes a DC control terminal, an input terminal, an output terminal, a triple-well structure NMOS field effect transistor M2, a first passive resistor R1, and a second passive resistor R2; the gate of the triple-well structure NMOS field effect transistor M2 is connected to one end of the first passive resistor R1; the other end of the first passive resistor R1 serves as a DC control terminal to access a digital control signal or a high level; the substrate of the triple-well structure NMOS field effect transistor M2 is connected to one end of the second passive resistor R2, and the other end of the second passive resistor R2 is connected to a power ground; the drain and source of the triple-well structure NMOS field effect transistor M2 serve as an input terminal and an output terminal, respectively, so as to facilitate access to the circuit; When the DC control terminal is connected to a high level, the triple-well structure NMOS field effect transistor M2 with AC floating body technology and AC floating gate technology is turned on, which can be approximately equivalent to a resistor, allowing the signal to pass; when the DC control terminal is connected to a low level, the triple-well structure NMOS field effect transistor M2 with AC floating body technology and AC floating gate technology is cut off, which can be approximately equivalent to a capacitor, blocking the signal from passing.

[0057] When the DC control terminal is connected to a digital control signal, as a control terminal, the triple-well structure NMOS field effect transistor M2 with AC floating body technology and AC floating gate technology is in an on or off state, and as a switching transistor, it is used to control the state switching of the improved switch embedded attenuation structure; when the DC control terminal is connected to a high level, as a level input terminal, the triple-well structure NMOS field effect transistor M2 with AC floating body technology and AC floating gate technology is continuously turned on, and acts as an active resistor to reduce the high-frequency parasitic capacitance effect.

[0058] Compared with traditional passive attenuation resistors, the triple-well structure NMOS active resistor and its parasitic capacitance have better stability within the frequency band, and specifically includes an input end, an output end, a level input end and a triple-well structure NMOS field effect transistor with AC floating body technology and AC floating gate technology; the level input end is the port when the DC control end is connected to a high level.

[0059] The triple-well structure NMOS active resistor can be connected to the circuit in two forms: series connection and parallel connection. When the triple-well structure NMOS active resistor is connected to the circuit in series, a triple-well structure NMOS field effect transistor M3 with AC floating body technology and AC floating gate technology is used to replace the traditional passive attenuation resistor R3. The gate of the triple-well structure NMOS field effect transistor M3 is connected to one end of the passive resistor R4; the other end of the passive resistor R4 is used as the level input end; the substrate of the triple-well structure NMOS field effect transistor M3 is connected to one end of the passive resistor R5, and the other end of the passive resistor R5 is connected to the power ground; the drain and source of the triple-well structure NMOS field effect transistor M3 are used as the input end and the output end, respectively, to facilitate the connection to the circuit. See Figure 6 Middle (a) - Figure 6 The circuit topology diagram shown in (b) is shown in the figure. When the triple-well structure NMOS active resistor is connected to the circuit in parallel, the triple-well structure NMOS field effect transistor M4 with AC floating body technology and AC floating gate technology is used to replace the traditional passive attenuation resistor R6. The gate of the triple-well structure NMOS field effect transistor M4 is connected to one end of the passive resistor R7; the other end of the passive resistor R7 is used as the level input end; the substrate of the triple-well structure NMOS field effect transistor M4 is connected to one end of the passive resistor R8, and the other end of the passive resistor R8 is connected to the power ground; the drain and source of the triple-well structure NMOS field effect transistor M4 are used as the input end and the output end respectively, so as to facilitate the connection to the circuit. Please refer to Figure 6 Medium (c) - Figure 6 The circuit topology diagram is shown in (d).

[0060] See also Figure 3 As shown, this embodiment provides an inductorless digitally controlled attenuator, which is composed of a 4dB attenuation module, a 0.5dB attenuation module, an 8dB attenuation module, a 2dB attenuation module, and a 1dB attenuation module connected in series from the RF input end to the RF output end. Figure 4The corresponding microscopic photo of the digital controlled attenuator chip. In order to solve the problem that the compact core area and excellent comprehensive performance of the attenuator are difficult to achieve at the same time, the attenuator uses Triple-well NMOS active resistors instead of traditional passive attenuation resistors as attenuation resistors, which reduces the high-frequency parasitic capacitance effect and ensures the stability of the resistor and its parasitic capacitance within the frequency band. Furthermore, combined with the switch Triple-well NMOS field effect transistor, the switch embedded attenuation structure is improved, and the capacitive compensation technology is used for phase compensation. The improved switch embedded attenuation structure with compensation capacitor effectively reduces the amplitude and phase errors of the traditional switch embedded attenuation structure. The digital controlled attenuator realizes five attenuation units of 0.5dB, 1dB, 2dB, 4dB and 8dB respectively through the simple T-type, asymmetric T-type and π-type improved switch embedded structures with compensation capacitors; under the inductor-free design, each attenuation unit is directly cascaded after careful arrangement to effectively reduce the core area of ​​the chip. Thanks to the Triple-well NMOS active resistor and inductor-free design, the present invention achieves high attenuation accuracy, low additional phase shift and low insertion loss in a compact core area, and has excellent comprehensive performance and temperature robustness.

[0061] The 0.5dB attenuation module and the 1dB attenuation module both adopt an improved switch embedded simple T-type structure with compensation capacitors; the 2dB attenuation module adopts an improved switch embedded asymmetric T-type structure with compensation capacitors; the 4dB attenuation module and the 8dB attenuation module both adopt an improved switch embedded π-type structure with compensation capacitors.

[0062] See also Figure 7As shown, the improved switch embedded simple T-type structure with compensation capacitor includes ultra-wideband RF input and output ports In1 / Out1, two DC control ports, a triple-well structure NMOS field effect transistor M5 with AC floating body technology and AC floating gate technology (as a switching transistor), a triple-well structure NMOS field effect transistor M6 with AC floating body technology and AC floating gate technology (as an active resistor), a compensation capacitor C1, and passive resistors R9-R12; wherein the two DC control ports include a first forward control terminal and a first level input terminal. Among them, the ultra-wideband RF input and output port In1 / Out1 shares the same port as the input and output ends, and is connected to the input end (drain) of the triple-well structure NMOS field effect transistor M5; the gate of the triple-well structure NMOS field effect transistor M5 is connected to one end of the passive resistor R9; the other end of the passive resistor R9 serves as a DC control end; the substrate of the triple-well structure NMOS field effect transistor M5 is connected to one end of the passive resistor R10, and the other end of the passive resistor R10 is connected to the power ground; the first forward control end 1 is the port when the DC control end of the triple-well structure NMOS field effect transistor M5 with AC floating body technology and AC floating gate technology is connected to the forward digital control signal; the triple-well structure NMOS field effect transistor M The output end (source) of 5 is connected to the input end (drain) of the triple-well structure NMOS field effect transistor M6 and one end of the compensation capacitor C1 respectively; the output end (source) of the triple-well structure NMOS field effect transistor M6 and the other end of the compensation capacitor C1 are both connected to the power ground; the gate of the triple-well structure NMOS field effect transistor M6 is connected to one end of the passive resistor R11; the other end of the passive resistor R11 serves as a DC control end; the substrate of the triple-well structure NMOS field effect transistor M6 is connected to one end of the passive resistor R12, and the other end of the passive resistor R12 is connected to the power ground; the first level input end is the port when the DC control end of the triple-well structure NMOS field effect transistor M6 with AC floating body technology and AC floating gate technology is connected to a high level.

[0063] The first forward control terminal is controlled by a digital control signal. When the digital control signal connected to the first forward control terminal is at a low level, the triple-well structure NMOS field effect transistor M5 with AC floating body technology and AC floating gate technology is turned off, and the simple T-type structure is in a reference state. When the digital control signal connected to the first forward control terminal is at a high level, the triple-well structure NMOS field effect transistor M5 with AC floating body technology and AC floating gate technology is turned on, and the simple T-type structure is in an attenuation state. The first level input terminal is connected to a high level, and the triple-well structure NMOS field effect transistor M6 with AC floating body technology and AC floating gate technology is continuously turned on as an active resistor. The 0.5dB attenuation module and the 1dB attenuation module achieve 0.5dB and 1dB signal amplitude attenuation respectively by adjusting the insertion loss difference between the reference state and the attenuation state of the improved switch embedded simple T-type attenuation structure with compensation capacitor.

[0064] See also Figure 8As shown, the improved switch embedded asymmetric T-type structure with compensation capacitor includes an ultra-wideband RF input port In2, an ultra-wideband RF output port Out2, four DC control ports, a triple-well structure NMOS field effect transistor M8 with AC floating body technology and AC floating gate technology (as a switching transistor), a triple-well structure NMOS field effect transistor M9 with AC floating body technology and AC floating gate technology (as a switching transistor), a triple-well structure NMOS field effect transistor M7 with AC floating body technology and AC floating gate technology (as an active resistor), a triple-well structure NMOS field effect transistor M10 with AC floating body technology and AC floating gate technology (as an active resistor), a compensation capacitor C2, and passive resistors R13-R20; wherein the four DC control ports include a second level input terminal, a first reverse control terminal, a second forward control terminal, and a third level input terminal. The ultra-wideband RF input port In2 is respectively connected to the input end (drain) of the triple-well structure NMOS field effect transistor M7, the input end (drain) of the triple-well structure NMOS field effect transistor M8, and the input end (drain) of the triple-well structure NMOS field effect transistor M9; the ultra-wideband RF output port Out2 is respectively connected to the output end (source) of the triple-well structure NMOS field effect transistor M7, the output end (source) of the triple-well structure NMOS field effect transistor M8; the output end (source) of the triple-well structure NMOS field effect transistor M9 is The gate of the triple-well structure NMOS field effect transistor M7 is connected to one end of the passive resistor R13; the other end of the passive resistor R13 is used as a DC control terminal; the substrate of the triple-well structure NMOS field effect transistor M7 is connected to one end of the passive resistor R14, and the other end of the passive resistor R14 is connected to the power ground. The gate of the triple-well structure NMOS field effect transistor M8 is connected to one end of the passive resistor R15; the other end of the passive resistor R15 is used as a DC control terminal; the substrate of the triple-well structure NMOS field effect transistor M8 is connected to one end of the passive resistor R16, and the other end of the passive resistor R16 is connected to the power ground. The gate of the triple-well structure NMOS field effect transistor M9 is connected to one end of the passive resistor R17; the other end of the passive resistor R17 serves as a DC control end; the substrate of the triple-well structure NMOS field effect transistor M9 is connected to one end of the passive resistor R18, and the other end of the passive resistor R18 is connected to the power ground.The gate of the triple-well structure NMOS field effect transistor M10 is connected to one end of the passive resistor R19; the other end of the passive resistor R19 is used as a DC control end; the substrate of the triple-well structure NMOS field effect transistor M10 is connected to one end of the passive resistor R20, and the other end of the passive resistor R20 is connected to the power ground. The second level input end, the first reverse control end, the second forward control end, and the third level input end are respectively the port when the DC control end of the triple-well structure NMOS field effect transistor M7 with AC floating body technology and AC floating gate technology is connected to a high level, the port when the DC control end of the triple-well structure NMOS field effect transistor M8 with AC floating body technology and AC floating gate technology is connected to a reverse digital control signal, the port when the DC control end of the triple-well structure NMOS field effect transistor M9 with AC floating body technology and AC floating gate technology is connected to a forward digital control signal, and the port when the DC control end of the triple-well structure NMOS field effect transistor M10 with AC floating body technology and AC floating gate technology is connected to a high level.

[0065] The second forward control terminal and the first reverse control terminal are controlled by a set of complementary digital control signals. When the digital control signal connected to the second forward control terminal is at a low level and the digital control signal connected to the first reverse control terminal is at a high level, the triple-well structure NMOS field effect transistor M8 with AC floating body technology and AC floating gate technology is turned on, the triple-well structure NMOS field effect transistor M9 with AC floating body technology and AC floating gate technology is turned off, and the asymmetric T-type attenuation structure is in a reference state. When the digital control signal connected to the second forward control terminal is at a high level and the digital control signal connected to the first reverse control terminal is at a low level, the triple-well structure NMOS field effect transistor M8 with AC floating body technology and AC floating gate technology is turned off, the triple-well structure NMOS field effect transistor M9 with AC floating body technology and AC floating gate technology is turned on, and the asymmetric T-type attenuation structure is in an attenuation state. The second level input terminal and the third level input terminal are connected to a high level, and the triple-well structure NMOS field effect transistors M7 and M10 with AC floating body technology and AC floating gate technology are continuously turned on as active resistors. The 2dB attenuation unit achieves 2dB signal amplitude attenuation by adjusting the insertion loss difference between the reference state and the attenuation state of the improved switch embedded asymmetric T-type attenuation structure with compensation capacitor.

[0066] See also Fig. 9As shown, the improved switch embedded π-type structure with compensation capacitor includes an ultra-wideband RF input port In3, an ultra-wideband RF output port Out3, six DC control ports, a triple-well structure NMOS field effect transistor M12 with AC floating body technology and AC floating gate technology (as a switch transistor), a triple-well structure NMOS field effect transistor M13 with AC floating body technology and AC floating gate technology (as a switch transistor), a triple-well structure NMOS field effect transistor M15 with AC floating body technology and AC floating gate technology (as a switch transistor), and a triple-well structure NMOS field effect transistor M16 with AC floating body technology and AC floating gate technology. A triple-well structure NMOS field effect transistor M11 with AC gate technology (as an active resistor), a triple-well structure NMOS field effect transistor M14 with AC floating body technology and AC floating gate technology (as an active resistor), a triple-well structure NMOS field effect transistor M16 with AC floating body technology and AC floating gate technology (as an active resistor), a compensation capacitor C3, a compensation capacitor C4, and passive resistors R21-R32; wherein the six DC control ports include a fourth level input terminal, a second reverse control terminal, a third forward control terminal, a fifth level input terminal, a fourth forward control terminal, and a sixth level input terminal. The ultra-wideband RF input port In3 is respectively connected to the input end (drain) of the triple-well structure NMOS field effect transistor M11, the input end (drain) of the triple-well structure NMOS field effect transistor M12, and the input end (drain) of the triple-well structure NMOS field effect transistor M13; the ultra-wideband RF output port Out3 is respectively connected to the output end (source) of the triple-well structure NMOS field effect transistor M11, the output end (source) of the triple-well structure NMOS field effect transistor M12, and the input end (drain) of the triple-well structure NMOS field effect transistor M15; the triple-well structure NMOS field effect transistor M11 is connected to the output end (source) of the triple-well structure NMOS field effect transistor M12, and the input end (drain) of the triple-well structure NMOS field effect transistor M15; the triple-well structure NMOS field The output end (source) of the NMOS field effect transistor M13 is respectively connected to the input end (drain) of the triple-well structure NMOS field effect transistor M14 and one end of the compensation capacitor C3; the output end (source) of the triple-well structure NMOS field effect transistor M14 and the other end of the compensation capacitor C3 are both connected to the power ground; the output end (source) of the triple-well structure NMOS field effect transistor M15 is respectively connected to the input end (drain) of the triple-well structure NMOS field effect transistor M16 and one end of the compensation capacitor C4, and the output end (source) of the triple-well structure NMOS field effect transistor M16 and the other end of the compensation capacitor C4 are both connected to the power ground. The gate of the triple-well structure NMOS field effect transistor M11 is connected to one end of the passive resistor R21; the other end of the passive resistor R21 serves as a DC control end; the substrate of the triple-well structure NMOS field effect transistor M11 is connected to one end of the passive resistor R22, and the other end of the passive resistor R22 is connected to the power ground.The gate of the triple-well structure NMOS field effect transistor M12 is connected to one end of the passive resistor R23; the other end of the passive resistor R23 serves as a DC control terminal; the substrate of the triple-well structure NMOS field effect transistor M12 is connected to one end of the passive resistor R24, and the other end of the passive resistor R24 ​​is connected to the power ground. The gate of the triple-well structure NMOS field effect transistor M13 is connected to one end of the passive resistor R25; the other end of the passive resistor R25 serves as a DC control terminal; the substrate of the triple-well structure NMOS field effect transistor M13 is connected to one end of the passive resistor R26, and the other end of the passive resistor R26 is connected to the power ground. The gate of the triple-well structure NMOS field effect transistor M14 is connected to one end of the passive resistor R27; the other end of the passive resistor R27 serves as a DC control terminal; the substrate of the triple-well structure NMOS field effect transistor M14 is connected to one end of the passive resistor R28, and the other end of the passive resistor R28 is connected to the power ground. The gate of the triple-well structure NMOS field effect transistor M15 is connected to one end of the passive resistor R29; the other end of the passive resistor R29 serves as a DC control terminal; the substrate of the triple-well structure NMOS field effect transistor M15 is connected to one end of the passive resistor R30, and the other end of the passive resistor R30 is connected to the power ground. The gate of the triple-well structure NMOS field effect transistor M16 is connected to one end of the passive resistor R31; the other end of the passive resistor R31 serves as a DC control terminal; the substrate of the triple-well structure NMOS field effect transistor M16 is connected to one end of the passive resistor R32, and the other end of the passive resistor R32 is connected to the power ground. The fourth level input terminal, the second reverse control terminal, the third forward control terminal, the fifth level input terminal, the fourth forward control terminal and the sixth level input terminal are respectively the port when the DC control terminal of the triple-well structure NMOS field effect transistor M11 with AC floating body technology and AC floating gate technology is connected to a high level, the port when the DC control terminal of the triple-well structure NMOS field effect transistor M12 with AC floating body technology and AC floating gate technology is connected to a reverse digital control signal, the port when the DC control terminal of the triple-well structure NMOS field effect transistor M13 with AC floating body technology and AC floating gate technology is connected to a forward digital control signal, the port when the DC control terminal of the triple-well structure NMOS field effect transistor M14 with AC floating body technology and AC floating gate technology is connected to a high level, the port when the DC control terminal of the triple-well structure NMOS field effect transistor M15 with AC floating body technology and AC floating gate technology is connected to a forward digital control signal, and the port when the DC control terminal of the triple-well structure NMOS field effect transistor M16 with AC floating body technology and AC floating gate technology is connected to a high level.

[0067] The signal connected to the third forward control terminal and the fourth forward control terminal and the signal connected to the second reverse control terminal are a set of logically complementary digital control signals, wherein the third forward control terminal and the fourth forward control terminal are connected to the same digital control signal. When the digital control signal connected to the third forward control terminal and the fourth forward control terminal is at a low level, and the digital control signal connected to the second reverse control terminal is at a high level, the triple-well structure NMOS field effect transistor M12 with AC floating body technology and AC floating gate technology is turned on, and the triple-well structure NMOS field effect transistors M13 and M15 with AC floating body technology and AC floating gate technology are turned off, and the π-type structure is in a reference state. When the digital control signal connected to the third forward control terminal and the fourth forward control terminal is at a high level, and the digital control signal connected to the second reverse control terminal is at a low level, the triple-well structure NMOS field effect transistor M12 with AC floating body technology and AC floating gate technology is turned off, and the triple-well structure NMOS field effect transistors M13 and M15 with AC floating body technology and AC floating gate technology are turned on, and the π-type structure is in an attenuation state. The fourth level input terminal, the fifth level input terminal, and the sixth level input terminal are connected to a high level, and the triple-well structure NMOS field effect transistors M11, M14, and M16 with AC floating body technology and AC floating gate technology are continuously turned on as active resistors. The 4dB attenuation unit and the 8dB attenuation unit achieve 4dB and 8dB signal amplitude attenuation respectively by adjusting the insertion loss difference between the reference state and the attenuation state of the improved switch embedded π-type attenuation structure with compensation capacitor.

[0068] The above-mentioned attenuators are controlled by five-bit digital signals respectively. The different level states of the digital control signals of each attenuation module and the corresponding signal attenuation are shown in Table 1 below.

[0069] Table 1 Comparison table of five-bit digital control signal attenuation

[0070] In the above Table 1, 0 represents a low level, and 1 represents a high level. It can be seen that the present invention realizes an attenuation range of 0 to 15.5 dB with a step length of 0.5 dB within the operating frequency range of DC to 35 GHz by controlling the change of the high and low level states of the digital control signals of the 0.5 dB attenuation module, the 1 dB attenuation module, the 2 dB attenuation module, the 4 dB attenuation module, and the 8 dB attenuation module, and a total of 32 states of signal amplitude attenuation.

[0071] The simulation comparison results of the active resistor (using Triple-well NMOS field effect transistor) and the passive attenuation resistor of the present invention are shown in FIG. Fig.10 As shown. In the comparison, four resistors with different resistance values, 16Ω, 31Ω, 122Ω and 157Ω, were selected for analysis. Within the working frequency band, Fig.10 Medium (a) to Fig.10 The active resistor in (h) (using a Triple-well NMOS field-effect transistor) shows small changes in both resistance and parasitic capacitance, thus ensuring the stability of the resistance and its parasitic capacitance within this frequency band.

[0072] The simulation comparison results of the digital controlled attenuator of the present invention under high and low temperature conditions are as follows: Fig.11 Medium (a) to Fig.11 As shown in (e), the figure shows that the changes of the RMS amplitude error, RMS phase error, S11, S22 and insertion loss of the digitally controlled attenuator under different temperature conditions are all within the acceptable range, showing excellent temperature robustness.

[0073] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. An inductorless digitally controlled attenuator based on an active resistor, characterized in that: The digital controlled attenuator is composed of a plurality of attenuation modules with different attenuation functions connected in series; wherein the input end of the first attenuation module serves as the RF input end of the digital controlled attenuator, and the output end of the last attenuation module serves as the RF output end of the digital controlled attenuator; The attenuation module adopts an improved attenuation module, including an attenuation unit, an input end, an output end, a control end and a level end; the input end and the output end are respectively used as two ports of the attenuation unit, which are convenient for connecting to the circuit; the control end is used to connect the digital control signal to the attenuation unit; the level end is used to connect the high level to the attenuation unit.

2. The digital controlled attenuator according to claim 1, characterized in that: The attenuation unit includes an improved switch embedded attenuation structure and a compensation capacitor; the improved switch embedded attenuation structure specifically replaces the passive attenuation resistor in the switch embedded attenuation structure with an active resistor, and introduces a compensation capacitor into the improved switch embedded attenuation structure for phase compensation.

3. The digital controlled attenuator according to claim 2, characterized in that: The improved switch embedded attenuation structure comprises a switch transistor and an active resistor; the switch transistor is used to control the state switching of the improved switch embedded attenuation structure, and the active resistor is used as the attenuation resistor to achieve the required signal amplitude attenuation.

4. The digital controlled attenuator according to claim 3, characterized in that: In the improved switch embedded attenuation structure, the switch transistor and the active resistor both adopt triple-well structure NMOS field effect transistors with AC floating body technology and AC floating gate technology.

5. The digital controlled attenuator according to claim 3, characterized in that: The triple-well structure NMOS field effect transistor with AC floating body technology and AC floating gate technology includes a DC control terminal, an input terminal, an output terminal, a triple-well structure NMOS field effect transistor M2, a first passive resistor R1, and a second passive resistor R2; the gate of the triple-well structure NMOS field effect transistor M2 is connected to one end of the first passive resistor R1; the other end of the first passive resistor R1 is used as a DC control terminal to access a digital control signal or a high level; the substrate of the triple-well structure NMOS field effect transistor M2 is connected to one end of the second passive resistor R2, and the other end of the second passive resistor R2 is connected to the power ground; the drain and source of the triple-well structure NMOS field effect transistor M2 are used as the input terminal and the output terminal respectively, so as to facilitate access to the circuit.

6. The digitally controlled attenuator according to claim 5, characterized in that: When the triple-well structure NMOS field effect transistor with AC floating body technology and AC floating gate technology is used as a switching transistor, the DC control terminal is connected to the digital control signal, and the triple-well structure NMOS field effect transistor M2 is in an on or off state, which is used to control the state switching of the improved switch embedded attenuation structure; when the digital control signal is at a high level, the triple-well structure NMOS field effect transistor M2 is turned on to open the signal path; when the digital control signal is at a low level, the triple-well structure NMOS field effect transistor M2 is turned off to close the signal path.

7. The digitally controlled attenuator according to claim 5, characterized in that: When the triple-well structure NMOS field effect transistor with AC floating body technology and AC floating gate technology is used as an active resistor, the DC control terminal is connected to a high level as a level input terminal, and the triple-well structure NMOS field effect transistor M2 is continuously turned on to reduce the high-frequency parasitic capacitance effect.

8. The digital controlled attenuator according to claim 3, characterized in that: In the improved switch embedded attenuation structure, the active resistor is connected to the circuit in series or in parallel.

9. The digitally controlled attenuator according to claim 4, characterized in that: Each attenuation module in the digital controlled attenuator adopts one of an improved switch embedded simple T-type structure with a compensation capacitor, an improved switch embedded asymmetric T-type structure, and an improved switch embedded π-type structure.

10. The digitally controlled attenuator according to claim 1, characterized in that: By controlling the high and low level states of the digital control signals of each attenuation module, signal amplitude attenuation in various states can be achieved within the operating frequency range and with a fixed step length within the attenuation range.

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