PWM control device

Abstract

The PWM control device is provided with a normalization counter (56). A normalization counter (56) counts up or down with an average per 2N / Cmax for each input of the clock signal between 0 and 2N. Here, N is a natural number, and Cmax is a value that varies according to a carrier period. The PWM control device is further provided with comparators (54a, 54b, 54c) that compare the normalized count value of the normalization counter (56) with a comparison value for determining the duty ratio of the PWM signal, and that output the comparison result as the PWM signal.

Description

Cross-reference to related applications This application claims the benefit of Japanese Patent Application No. 2023-171797 filed on October 3, 2023, the entire contents of which, including specification, claims, drawings, and abstract, are incorporated herein by reference. Technical Field

[0001] The present disclosure relates to a pulse width modulation (PWM) control device that generates a PWM signal for performing inverter control on a motor, etc. Background Art

[0002] In a motor control device that uses a three-phase motor to control the speed and rotation angle (position) of a load, a PWM converter that uses a PWM signal to drive a three-phase voltage-type converter is usually used as a power converter, and a microcontroller with a built-in PWM circuit as a peripheral device is used as a control processor.

[0003] Fig. 9 This is a block diagram showing the configuration of a conventional PWM circuit 5 a in the case of outputting a so-called triangular wave PWM signal.

[0004] The PWM circuit 5a includes a PWM counter 51, a counter upper limit value storage unit 52, comparison value storage units 53a, 53b, 53c, comparators 54a, 54b, 54c, and complementary dead time generation units 55a, 55b, 55c. The PWM counter 51 counts up and down a clock signal (not shown). The counter upper limit value storage unit 52 stores a count upper limit value for determining a carrier cycle of PWM. The comparison value storage units 53a, 53b, 53c store comparison values ​​for determining the duty ratios of the PWM signals of the U phase, the V phase, and the W phase. The comparators 54a, 54b, 54c compare the value of the PWM counter 51 with the values ​​of the comparison value storage units 53a, 53b, 53c, respectively, and generate an active PWM signal when the value of the PWM counter 51 is lower than the value of the comparison value storage units 53a, 53b, 53c. The complementary dead time generating units 55a, 55b, 55c output positive phase PWM signals and negative phase PWM signals in a complementary relationship in consideration of the dead time based on the PWM signals generated by the comparators 54a, 54b, 54c. Various implementation means such as the configuration disclosed in Patent Document 1 are known as the complementary dead time generating units 55a, 55b, 55c.

[0005] Fig.12 It is shown Fig. 9 The timing diagram of the PWM output of the U phase of the PWM circuit 5a shown in FIG. Fig.12 In FIG. 1 , for simplicity, an example of a case where the dead time is 0 is shown.

[0006] The PWM counter 51 counts a clock signal (not shown). The counter upper limit value is input to the PWM counter 51 from the counter upper limit value storage unit 52. The PWM counter 51 outputs a PWM count value that counts up and down between 0 and the counter upper limit value, and an up and down identification signal indicating the current counting direction. The PWM count value is input to the inverting input terminal of the comparator 54a. The comparison value is input from the comparison value storage unit 53a to the non-inverting input terminal of the comparator 54a. The comparator 54a compares the PWM count value with the comparison value, and outputs ON when the PWM count value is less than the comparison value, outputs OFF when the PWM count value exceeds the comparison value, and outputs ON when the PWM count value is less than the comparison value. The PWM signal output by the comparator 54a is input to the complementary dead time generation unit 55a. The complementary dead time generation unit 55a outputs the PWM signal output by the comparator 54a as a positive phase PWM signal, and outputs the inverted signal as a negative phase PWM signal. In fact, in order to prevent the switching time of the converter section from being turned on at the same time, a dead time is inserted between the positive phase ON and the negative phase ON, in which both are turned off. Fig.12 It is omitted in the above. The counter upper limit value storage unit 52 stores the counter upper limit update value input from the outside of the PWM circuit as the counter upper limit value at the time when the count changes from down counting to up counting based on the up / down identification signal input from the PWM counter 51, and outputs it to the counter upper limit value storage unit 52. The comparison value storage unit 53a stores the U-phase comparison value update value input from the outside of the PWM circuit as the U-phase comparison value at the time when the count direction changes based on the up / down identification signal input from the PWM counter 51, and outputs it to the comparison value storage unit 53a. As for the V phase and the W phase, similarly to the U phase, the comparison value storage units 53b, 53c, comparators 54b, 54c, and complementary / dead time generation units 55b, 55c of the V and W phases have the same functions as the comparison value storage unit 53a, the comparator 54a, and the complementary / dead time generation unit 55a of the U phase.

[0007] The carrier cycle of the PWM signal can be expressed by the following equation (1) using the cycle of the clock signal input to the PWM circuit and the counter upper limit value stored in the counter upper limit value storage unit 52 .

[0008] Carrier cycle = clock cycle × counter upper limit × 2 (1)

[0009] In addition, the comparison value for making the duty ratio 50% is 1 / 2 of the counter upper limit value. Therefore, even if the duty ratio is the same, the comparison value will be different depending on the counter upper limit value determined by the carrier cycle and the clock cycle. Fig.122 shows a case where the second carrier cycle (T2) is made larger than the first carrier cycle (T1). In this case, the counter upper limit value of T2 is larger than the counter upper limit value of T1. Fig.12 2 shows the difference in the comparison value of the 50% duty cycle in the second half (down count interval) of the first carrier cycle (T1) and the first half (up count interval) of the second carrier cycle (T2).

[0010] Fig.10 It shows the use of built-in Fig. 9 and Fig.12 The microcontroller 1 of the conventional PWM circuit 5a described above is a block diagram of the motor system. The microcontroller 1 functions as a motor control device. Fig.10 The motor system is described below. The command value X is output to the microcontroller 1 through the upper control device (not shown). The command value X is the speed and rotation angle of the load. The motor system includes a detector 9 for detecting the rotation angle of the motor 7. The rotation angle of the motor 7 is a position detection value of the load 8 connected to the motor 7 and driven, and is output as a position detection value θm via the detector interface 13. In addition, the motor system includes a three-phase voltage type converter 6 driven by a PWM signal output by the microcontroller 1. The three-phase voltage type converter 6 supplies power to the motor 7. The currents of at least two phases (for example, Iu and Iv) of the three-phase current (Iu, Iv, Iw) flowing in the motor 7 are detected by current detectors 10 and 11, and are output as current detection values ​​Iud and Ivd via the A / D converter 12.

[0011] The microcontroller 1 uses the built-in CPU to sequentially perform the operations of the position / speed control processing 2, the current control processing 3a, and the PWM output rate conversion processing 4a according to the stored program. The position / speed control processing 2 takes the command value X and the position detection value θm as input, performs feedback processing based on the position control loop and the speed control loop, and various feedforward processing, and outputs the torque command value Tc. The current control processing 3a takes the torque command value Tc and the current detection values ​​Iud and Ivd as input, performs feedback processing based on the current control loop and feedforward processing based on, for example, the dq axis control theory, and outputs the voltage command values ​​Vuc, Vvc, and Vwc of the three phases (U phase, V phase, and W phase). The PWM output rate conversion processing 4a converts the voltage command values ​​Vuc, Vvc, and Vwc into comparison values ​​for the PWM circuit 5a, and sets the PWM circuit 5a. The PWM circuit 5a is used Fig. 9 and Fig.12 The conventional PWM circuit described above is a logic circuit built into the microcontroller 1 as a peripheral device.

[0012] Usually, the voltage command values ​​Vuc, Vvc, and Vwc are normalized by a power of 2 and then output. That is, in a three-phase voltage-type converter of a DC voltage Vdc, if Vdc / 2 is defined as an output voltage of 0V, the output voltage range is -Vdc / 2 to +Vdc / 2. In the voltage command values ​​Vuc, Vvc, and Vwc, the lower limit of the output voltage range -Vdc / 2 is set to a PWM output rate of -100% (reverse phase 100% ON), and the upper limit of the output voltage range +Vdc / 2 is set to a PWM output rate of +100% (positive phase 100% ON), and the PWM output rate 100% is normalized by 2 to the power of N (hereinafter expressed as 2^N). Here, N is a natural number.

[0013] When the voltage command values ​​Vuc, Vvc, and Vwc are normalized by 2^N', the counter upper limit value is set to Cmax, and the PWM output rate conversion process 4a becomes the calculation process of the following equations (2) to (4). Here, the division based on 2^(N'+1) can be realized by bit shift calculation, so the calculation load can be reduced.

[0014] U phase comparison value update value = Vuc × Cmax / 2^(N'+1)+Cmax / 2··(2) V phase comparison value update value = Vvc × Cmax / 2^(N'+1)+Cmax / 2··(3) W phase comparison value update value = Vwc × Cmax / 2^(N'+1)+Cmax / 2··(4)

[0015] In addition, regarding the counter upper limit value Cmax, there are cases where the counter upper limit value Cmax is set to a fixed value without achieving synchronization between the PWM signal carrier and the position / speed control process 2 and the current control process 3a, and there are cases where the counter upper limit value Cmax is made variable in order to achieve synchronization between the PWM signal carrier and the position / speed control process 2 and the current control process 3a. When the counter upper limit value Cmax is made variable, a carrier frequency change unit (not shown) measures the timing of the PWM signal carrier and the position / speed control process 2 and the current control process 3a, and based on the measured timing, the counter upper limit value Cmax is changed and output within a certain range (for example, within a positive / negative number %) for the reference value of the counter upper limit value. Prior art literature Patent Literature

[0016] Patent Document 1: Japanese Patent Application Publication No. 2016-19276 Summary of the invention

[0017] In a PWM converter, power semiconductors such as IGBTs are switched at the carrier frequency of the PWM signal, so ripple currents that depend on the carrier frequency are generated. From the perspective of reducing ripple currents, a higher carrier frequency is desirable, but if the carrier frequency is increased, the switching losses of the power semiconductors that are proportional to the carrier frequency will increase, which will become a problem. In addition, the performance of the microcontroller will also become a problem due to the need to complete the current control operation in a shorter time.

[0018] In recent years, the use of power semiconductors using wide-bandgap semiconductors such as SiC, which can switch at a higher speed than conventional power semiconductors using Si, has expanded, and the restrictions on carrier frequency caused by switching losses have been improved. In addition, the performance and cost reduction of devices such as FPGAs that can program logic circuits are also developing. By using FPGAs to circuitize current control processing logic, it is possible to improve the restrictions on carrier frequency caused by the performance of microprocessors without developing ASICs.

[0019] Fig.11 This is a block diagram showing the structure of a motor system including a motor control device using a microcontroller and an FPGA. Fig.10 The parts that are different from the motor control device that has been described above will be described.

[0020] The FPGA 14 uses a programmed logic circuit to make the current control circuit 3b, the PWM output rate conversion circuit A (reference numeral 4b), and the PWM circuit 5a operate in parallel. The current control circuit 3b is implemented by a logic circuit and is Fig.10 The circuit has the same function as the current control processing 3a implemented by the operation processing of the microcontroller in the previous example, which takes the torque command value Tc and the current detection values ​​Iud and Ivd as inputs, performs feedback processing based on the current control loop and feedforward processing based on, for example, the dq axis control theory, and outputs the voltage command values ​​Vuc, Vvc, and Vwc of the three phases (U phase, V phase, and W phase). Similarly, the PWM output rate conversion circuit A (reference numeral 4b) is implemented by a logic circuit and is the same as in Fig.10 A circuit having the same function as the PWM output rate conversion processing 4a implemented by the calculation processing of a microcontroller in the previous example, which converts the voltage command values ​​Vuc, Vvc, and Vwc into comparison value update values ​​(U phase, V phase, and W phase) for the PWM circuit 5a and outputs them.

[0021] Here, the PWM output rate conversion circuit A (reference numeral 4b) needs to perform the calculations of the above-mentioned equations (2) to (4) using a logic circuit, and thus requires three multiplication circuits.

[0022] In FPGA, hardware multipliers that can perform multiplication at high speed are limited resources, and it is desirable to limit the number of them used. In addition, although it is also possible to use programmable logic elements (hereinafter referred to as LE) to implement multiplication circuits, if LEs are used to form a circuit that performs multiplication with one clock, the amount of LEs used and the speed of operation will become a problem. Although the amount of LEs used and the speed of operation can be improved by forming a circuit that performs multiplication with multiple clocks, it will lead to a decrease in throughput, which is disadvantageous for the purpose of using FPGAs, which is to make the current control processing logic circuit and increase the speed.

[0023] Furthermore, the current control processing is accelerated by using the logic circuit of the FPGA. Fig.11 In the example of , it is also envisioned that the current detection is oversampled with respect to the carrier frequency, and filtering is performed based on the relationship between the AD conversion timing and the switching timing based on the PWM counter, thereby reducing the ripple component superimposed on the current to improve the accuracy of current detection. However, since the upper limit value of the PWM counter of the PWM circuit 5a is not normalized, it is not easy to determine the phase relationship between the PWM counter and the current detection timing, and there is also a problem that it is difficult to use for filtering processing for current detection.

[0024] The PWM control device involved in the present disclosure is characterized in that it has a normalized counter, which counts up or down for each input of the clock signal between 0 and 2^N at an average of 2^N / Cmax each time, wherein N is a natural number and Cmax is a value that changes according to the carrier period. The PWM control device also has a comparator, which compares the normalized count value of the normalized counter with a comparison value used to determine the duty cycle of the PWM signal, and outputs the comparison result as a PWM signal.

[0025] The PWM control device according to the present disclosure may further include: a PWM counter that counts up or down by 1 for each input of the clock signal between 0 and Cmax; a counter comparison unit that compares the count conversion value that is the product of the normalized count value and Cmax with the PWM count value of the PWM counter and outputs it as a counter comparison result; and a counter increment calculation unit, wherein 2^N / Cmax is defined as a counter increment reference value ΔC, and the counter increment calculation unit performs the following processing: as a provisional counter increment value, the count conversion value that is the product of the normalized count value and Cmax is calculated by the PWM counter. When the PWM counter is counting, ΔC is obtained, and when the PWM counter is counting down, -ΔC is obtained as the counter correction reference value ΔCc, and the value after ΔC is shifted to the right by m bits is obtained as the counter correction value. When the PWM counter value is greater than the count change value in the counter comparison result, ΔCc is obtained, when it is less than the count change value, -ΔCc is obtained, and when they are equal, 0 is obtained as the counter increment value, and the value obtained by adding the counter correction value to the provisional counter increment value is obtained. The normalized counter adds the count increment value to the current normalized count value at the time when the clock signal is input to update the normalized count value.

[0026] In the PWM control device involved in the present disclosure, it may also be that the counter comparison unit uses the nth decimal place in the fixed-point N places of the count transformation value as the effective number of bits, and compares them with the PWM count value of the PWM counter, and the delay clock number Cd from the time when n is reflected in the update of the normalized count value via the counter comparison unit and the counter increment operation unit relative to the normalized count value satisfies the relationship 2^n≥Cd.

[0027] In the PWM control device involved in the present disclosure, it may also be that the m serving as the shift amount of the counter correction reference value ΔCc satisfies the relationship m0-1≤m≤m0+1 relative to m0, and m0 is the smallest integer that satisfies 2^m0≥Cd×2^n relative to the n in the alignment of the counter comparison unit and the number of delayed clocks Cd.

[0028] In the PWM control device according to the present disclosure, regarding ΔC and m, fixed-point bits less than the m bits are added to the internal count value of the normalization counter and the counter increment reference value of the counter increment calculation unit so that ΔC / 2^m does not become zero. Effects of the Invention

[0029] According to the present disclosure, the upper limit value of the normalized count value (carrier) to be compared with the comparison value for determining the duty cycle of the PWM signal can be made constant regardless of the carrier cycle. Therefore, even when the carrier cycle is changed, the comparison value at the same duty cycle is constant, and the conventional multiplier for the comparison value (the multiplier in the PWM output rate conversion circuit) can be removed. Furthermore, by extracting the upper bits of the normalized count value, the phase relationship of 1 unit of the power of 2 can be easily obtained for the carrier cycle of PWM, and correction calculations such as filtering processing for current detection become easy. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 : is a block diagram showing a normalized PWM circuit according to the embodiment. Figure 2 This is a block diagram showing a motor system including a motor control device using a microcontroller and an FPGA according to an embodiment. Figure 3 : is a block diagram showing a counter comparator according to the embodiment. Figure 4 : is a block diagram showing a counter increment calculator according to the embodiment. Figure 5A : is a timing chart showing an example of changes in internal signals in the embodiment. Figure 5B : is a timing chart showing an example of changes in internal signals in the embodiment. Fig. 6A It is an explanatory diagram of the relationship between the PWM count value and the count conversion value in the embodiment (Cd=1). Figure 6B It is an explanatory diagram of the relationship between the PWM count value and the count conversion value in the embodiment (Cd=1). Fig. 7A It is an explanatory diagram of the relationship between the PWM count value and the count conversion value in the embodiment (Cd=2). Figure 7B It is an explanatory diagram of the relationship between the PWM count value and the count conversion value in the embodiment (Cd=2). Figure 8 It is a timing chart of the normalized PWM circuit involved in the embodiment. Fig. 9 This is a block diagram showing a PWM circuit in the prior art. Fig.10 : is a block diagram showing a motor system in the related art. Fig.11 1 is a block diagram showing another motor system in the prior art. Fig.12 This is a timing chart showing a PWM circuit in the prior art. DETAILED DESCRIPTION

[0031] Hereinafter, embodiments of the present disclosure will be described based on the drawings. Hereinafter, a case where a so-called triangular wave PWM signal is output will be described. Figure 1 It is a block diagram showing a normalization PWM circuit 5 b according to the embodiment. Figure 2 This is a block diagram showing a motor system including a motor control device using a microcontroller and an FPGA according to an embodiment. Figure 2 The motor control device is relative to Fig.11 In the motor control device (conventional technology), a PWM output rate conversion circuit B (reference numeral 4c) that does not require multiplication is used instead of a PWM output rate conversion circuit A (reference numeral 4b) that requires multiplication, and a normalized PWM circuit 5b is used instead of a PWM circuit 5a. Hereinafter, only the parts that are different from the conventional technology described so far will be described. In addition, the output of the PWM counter 51 will be referred to as a PWM count value or a PWM counter value. In addition, the counter comparator 58 (reference numeral 4c) is referred to as a PWM counter value. Figure 1 ) is called the count comparison signal, counter comparison signal, or counter comparison result.

[0032] The PWM control device is configured to include a normalized PWM circuit 5b. Figure 1 The normalized PWM circuit 5b includes a normalized counter 56 that counts up and down from 0 to 2^N in synchronization with the up and down counting of the PWM counter 51 from 0 to the counter upper limit value Cmax. In the normalized PWM circuit 5b, the normalized count value of the normalized counter 56 is output to the non-inverting input terminal of the comparator 54a, 54b, and 54c instead of the PWM count value of the PWM counter 51, so that the PWM signal is output using the normalized count value as a carrier. The normalized count value is multiplied by the counter upper limit value Cmax stored in the counter upper limit value storage unit 52 through the multiplier 57, and is output to the counter comparator 58 as a count conversion value. That is, the count conversion value can be expressed by the following formula (5). In addition, the count conversion value includes N bits of fixed point bits. In addition, the count conversion value includes N fixed-point bits because if the normalized count value is normalized by 2^N with respect to the counter upper limit value Cmax, that is, considered based on Cmax, the normalized count value includes N fixed-point bits.

[0033] Count conversion value = normalized count value × Cmax (5)

[0034] The counter comparator 58 compares the PWM count value and the count conversion value, and outputs a count comparison signal to the counter increment operator 59. The count comparison signal is output as 1 when the PWM count value is greater than the count conversion value, as -1 when it is less than the count conversion value, and as 0 when they are equal. In addition, the above output value example is set for the convenience of explaining the functions of this embodiment, and does not limit the actual method. The counter increment operator 59 takes the counter increment reference value stored in the counter increment reference value storage unit 60, the counter comparison signal, and the upper and lower identification signal output by the PWM counter 51 as input, calculates the count increment value and outputs it. The normalization counter 56 adds the count increment value to the normalization count value by inputting a clock signal not shown.

[0035] The counter increment base value is determined by Figure 2 The microcontroller 1 calculates the reference value Cmax0 of the counter upper limit value Cmax and the counter upper limit value 2^N of the normalized counter by the following formula (6) and sets it in advance in the counter increment reference value storage unit 60 by an initial setting method not shown. In addition, the counter increment reference value is a natural number.

[0036] Counter increment reference value = 2^N / Cmax0···(6)

[0037] Figure 3 1 is a block diagram showing an example of the configuration of the counter comparator 58. The counter comparator 58 includes pipeline registers 61a, 61b, and 61c, and the pipeline registers 61a, 61b, and 61c latch and output the input values ​​with a clock signal (not shown) for the PWM counter value and the count conversion value as inputs and the counter comparison result as outputs. The PWM counter value latched by the pipeline register 61a and the count conversion value latched by the pipeline register 61b are aligned by shift operators 581a and 581b, and are input to the comparator 582. The comparator 582 outputs 1 when the latched value of the PWM counter value is greater than the latched value of the count conversion value, outputs -1 when it is less than, and outputs 0 when they are equal. The output of the comparator 582 is latched with a clock signal (not shown) via the pipeline register 61c and output as the counter comparison result. Furthermore, if a sufficient operating frequency can be ensured even without providing pipeline registers, the pipeline registers 61a, 61b, and 61c may not be provided. However, the pipeline registers 61a and 61b need to be made the same in terms of validity and invalidity.

[0038] Here, the alignment by the shift operator 581a and the shift operator 581b is described. As described above, the count conversion value includes N bits of fixed-point bits relative to the PWM counter value. In order for the comparator 582 to perform a comparison including an n-bit fixed-point, the shift operator 581a shifts the latch value of the PWM counter to the left by n bits, that is, adds n bits of 0 to the lower bit of the LSB of the latch value of the PWM counter, and the shift operator 581b shifts the latch value of the count conversion value to the right by (Nn) bits, that is, takes out the nth bit as the LSB. The method of determining n will be described later.

[0039] Figure 4 : is a block diagram showing a configuration example of the counter increment operator 59. The count direction selector 591 switches the output between the counter increment reference value (hereinafter referred to as ΔC) and -ΔC after the sign is inverted by the sign inverter 592 according to the up and down identification signal. That is, ΔC is output when the up and down identification signal is an up count, and -ΔC is output when the up and down identification signal is a down count. The shift operator 593 shifts ΔC to the right by m bits, that is, takes out the mth bit as the LSB, and outputs the counter correction reference value ΔCc. The counter correction value selector 594 switches the output between ΔCc, -ΔCc after the sign is inverted by the sign inverter 595, and 0 according to the counter comparison signal. That is, ΔCc is output when the counter comparison signal is 1, -ΔCc is output when it is -1, and 0 is output when it is 0. The adder 596 adds the output of the count direction selector 591 and the output of the counter correction value selector 594 and outputs them. The output of the adder 596 is latched by the pipeline register 61d with a clock signal (not shown) and output as a counter increment value. In addition, if a sufficient operating frequency can be ensured even without the pipeline register, the pipeline register 61d may not be provided. The method for determining the shift number m of the shift operator 593 will be described later.

[0040] In addition, the following Figure 1 The number of delayed clocks in the feedback path from when the normalized count value of the normalized counter 56 is reflected in the update of the normalized count via the multiplier 57, the counter comparator 58, and the counter increment operator 59 is defined as Cd. Regarding the number of delayed clocks Cd, if the number of stages of pipeline registers inserted in the feedback path is set to L, then Cd=L+1.

[0041] Figure 5A , Figure 5B It is a timing chart showing an example of changes in internal signals. Figure 5A This is a timing chart when Cmax=2000, N=14, Cd=1, m=1, and n=1. Figure 5B This is a timing diagram for the case where Cmax = 2000, N = 14, Cd = 2, m = 2, and n = 1. Figure 5A , Figure 5B In the example, the PWM count value (after alignment) is expressed as Figure 3 The output of the shift operator 581a. In addition, the count conversion value (after alignment) represents Figure 3 The output of the shift operator 581b is the value after discarding the part that is less than the number of significant digits.

[0042] Here, the counter comparator 58 will be further described. Fig. 6A , Figure 6B 1 and 2 are examples of timing charts for comparing PWM count values ​​and count conversion values ​​when the fixed-point bit width n = 0 and Cd = 1. In these figures, the count conversion value is represented by a value (plotted position) including a fixed decimal part. Fig. 6A , the case where the rounded value of the portion of the count conversion value smaller than the number of significant digits (here n=0, so the decimal portion) is compared with the PWM count value is shown. Figure 6B , the case where the value after discarding the number of bits less than the effective digit of the count conversion value (here n=0, so it is the decimal part) is compared with the PWM count value is shown.

[0043] The counter comparison result as the output of the counter comparator 58 is usually 0. When the difference between the count conversion value and the PWM count value exceeds a certain range, the counter comparison result becomes +1 or -1. The range in which the counter comparison result becomes +1 or -1 is determined by Figure 3 The comparison of fixed-point width n and Figure 3 Here, the comparison method refers to the comparison method in the comparator 582. Figure 3 After the bit alignment processing in the shift operator 581b, the part of the count transformation value that is less than the effective number of digits is rounded off or discarded.

[0044] When the counter comparison result is 0 continuously, the difference between the PWM count value and the count conversion value becomes monotonically decreasing or monotonically increasing. Fig. 6A , Figure 6B The figure shows a monotonically decreasing situation. When the count change value is lower than the specified range relative to the PWM count value (the range between the dotted line and the single-point dashed line in the figure), the counter comparison result becomes 1, and the counter increment value is corrected in the positive direction. As a result, in the next cycle, the count change value returns to the specified range relative to the PWM count value (the counter comparison result becomes 0). In addition, when the comparison fixed point width n increases by 1, Fig. 6A , Figure 6B The range in which the counter comparison result is 0 is narrowed to 1 / 2.

[0045] like Fig. 6A , Figure 6BAs shown, when the delay clock number Cd=1, at the next clock when the counter comparison result changes to 1 or -1, the count increment value is corrected and the count comparison result returns to 0.

[0046] Fig. 7A , Figure 7B This is an example of a timing chart of the PWM count value and the count conversion value when the number of delay clocks Cd=2. Fig. 7A , the case where the comparison fixed-point width n=0 is shown. Figure 7B In FIG. 1 , the comparison fixed point bit width n=1 is shown. When the number of delayed clocks Cd=2, as shown in FIG. Fig. 7A , Figure 7B As shown, at the next clock when the counter comparison result changes to 1 or -1, the counter increment value is not corrected, so the difference between the PWM count value and the counter conversion value increases relative to the case of Cd=1.

[0047] Therefore, it can be Figure 7B As shown in FIG. 1 , by making the comparison fixed point width n=1, the range of the counter comparison result=0 is narrowed to 1 / 2. As a result, the counter comparison result changes to 1 or -1 more quickly, and the correction of the counter increment value also becomes faster accordingly. As a result, the increase in the difference between the PWM count value and the count conversion value caused by making Cd=2 can be suppressed.

[0048] In addition, hope Figure 3 The comparison fixed point bit width n used in the comparison of the comparator 582 is determined according to the number of delayed clocks Cd. The comparison fixed point bit width n can be set so that 2^n≥Cd is satisfied with respect to the number of delayed clocks Cd. Thus, the response of the comparator 582 becomes faster corresponding to the delay based on the number of delayed clocks Cd. Figure 1 The feedback of the normalized counter 56 becomes faster.

[0049] Here, Figure 4 The setting of the counter correction shift number m of the shift operator 593 is examined. When the counter comparison signal changes from 0 to 1, or from 0 to -1, the state of 1 or -1 lasts at least Cd delay clock times. Therefore, the counter correction value needs to be set to less than 1 / Cd of the counter increment reference value. In addition, it is necessary to go down with the comparison fixed point number n. Figure 1 The feedback of the normalized counter 56 becomes faster, and the counter correction value is reduced accordingly. That is, the optimal value of the counter correction shift number m becomes the smallest integer satisfying 2^m≥Cd×2^n according to the delay clock number Cd and the comparison fixed point bit width n. In addition, the counter correction shift number m can also be changed by plus or minus 1 relative to the optimal value.

[0050] The above-mentioned "smallest integer satisfying 2^m≥Cd×2^n" as the optimal value of the counter correction shift number m is further described. This point is assumed to be m=m1+m2, and the relationship between m1 and n and the relationship between Cd and m2 are considered separately.

[0051] The relationship between m1 and n is considered in the case of Cd = 1. n is the number of effective bits of the fixed point part when the PWM counter value is compared with the count conversion value in the counter comparator 58. Therefore, Fig. 6A , Figure 6B , Fig. 7A , Figure 7B The width of the range where the counter comparison result=0 is shown to be 1 / 2^n.

[0052] In the case of Cd = 1, at the next clock when the counter comparison result changes to +1 or -1, the counter comparison result of the PWM count value and the count change value is returned to 0 by correcting the counter increment value of the normalization counter 56. Therefore, in terms of the unit system of the PWM count value, the correction value of the counter increment value is equivalent to the range that can be corrected to the counter comparison result = 0, that is, 1 / 2^n. This is the above-mentioned "need to be compared with the number of comparison fixed points n downward Figure 1 The meaning is that the feedback of the normalized counter 56 becomes faster and the counter correction value decreases accordingly.

[0053] If the correction amount 1 / 2^n of the counter increment value in the unit system of the PWM count value is changed to the counter correction reference value ΔCc' in the unit system of the normalized count value, the following equation (7) is obtained. In this equation, the above equation (6) is used.

[0054] ΔCc'=1 / 2^n×2^N / Cmax ≒1 / 2^n×2^N / Cmax0 ≒ΔC / 2^n···(7)

[0055] According to the above formula (7) and the above shift operator 593 (refer to Figure 4 ) states that “shift ΔC to the right by m bits, i.e., take out the mth bit as the LSB and output the counter correction reference value ΔCc”, and when m1=n and Cd=1, the counter correction reference value ΔCc′ becomes the following equation (8).

[0056] ΔCc'=ΔC / 2^m1=ΔC / 2^n···(8)

[0057] The relationship between Cd and m2 is based on the above "When the counter comparison signal changes from 0 to 1, or from 0 to -1, the state of 1 or -1 continues for at least Cd delay clock times. Therefore, the counter correction value needs to be set to less than 1 / Cd of the counter increment reference value". The above is based on the premise of n = 0, so if the above "counter increment reference value" is replaced by the counter correction reference value Cc' when Cd = 1, it becomes the following formula (9).

[0058] ΔCc' / 2^m2≤ΔCc' / Cd ΔC / 2^(m1+m2)≤ΔC / 2^n / Cd ΔC / 2^m≤ΔC / 2^n / Cd 2^m≥Cd×2^n···(9)

[0059] According to the above formula (9), the "smallest integer satisfying 2^m≥Cd×2^n" can be obtained as the optimal value of the counter correction shift number m. Figure 4 In the case where the counter increment reference value ΔC and the counter correction shift number m satisfy the relationship ΔC<2^m, the counter correction reference value ΔCc becomes 0, so Figure 1 That is, if m is too large, the feedback to the normalization counter 56 will no longer work. In order to prevent this, under the above conditions (conditions for the optimal value of the counter correction shift number m), it is set to "the smallest integer".

[0060] As mentioned above, in Figure 4 In the case where the counter increment reference value ΔC and the counter correction shift number m satisfy the relationship ΔC<2^m, the counter correction reference value ΔCc becomes 0, so Figure 1 The feedback of the normalized counter 56 no longer works. Figure 1 A fixed point bit with a bit width of m or less is added to the internal count value of the normalized counter 56 and the count increment reference value set in the counter increment reference value storage unit 60 so as to satisfy ΔCc ≥ 1. Even when a fixed point bit is added, the normalized counter 56 outputs only the integer part as the normalized count value.

[0061] Figure 8 is a timing diagram of the normalized PWM circuit of this embodiment, showing the output and Fig.12An example of the case of an equivalent PWM signal. The PWM counter 51 counts up and down between 0 and the counter upper limit value Cmax(n), and the normalized counter 56 counts up and down between 0 and 2^N in synchronization with the PWM counter 51. That is, when the PWM counter 51 counts up from 0 to the counter upper limit value Cmax(n) at a slope of 1, the normalized PWM counter counts up from 0 to 2^N at an average slope of 2^N / Cmax(n), and when the PWM counter 51 counts down from the counter upper limit value Cmax(n) to 0 at -1 each time, the normalized PWM counter counts down from 2^N to 0 at an average slope of 2^N / Cmax(n). The positive phase PWM signal and the negative phase PWM signal are not the values ​​of the PWM counter 51, but are generated by comparing the value of the normalized counter 56 with the comparison value, so they are the same as Fig.12 Unlike conventional technologies, the comparison value remains constant even when the carrier period is changed.

[0062] By setting the PWM circuit to the structure of the normalized PWM circuit 5b, Figure 2 The PWM output rate conversion circuit B (reference numeral 4c) is relative to Fig.11 That is, by substituting Cmax=2^N, N=N'+1 into the above equations (2) to (4), the following equations (10) to (12) are obtained, and the PWM output rate conversion circuit B (illustration mark 4c) can be formed by removing the multiplication circuit and only by the addition process.

[0063] U phase comparison value update value = Vuc + 2^N' (10) V phase comparison value update value = Vvc + 2^N' (11) W phase comparison value update value = Vwc + 2^N' (12)

[0064] So far, as a configuration example of the present embodiment, a configuration example of a so-called triangular wave PWM using a counter that performs up and down counting as a PWM signal carrier has been described, but the scope of the present disclosure is not limited to the triangular wave PWM. For example, the present disclosure can also be easily applied to a so-called sawtooth wave PWM that is reset to zero after reaching the upper limit value of the counter and continues to count up as a PWM signal carrier.

[0065] exist Figure 1In the configuration example, the PWM signals outputted from the comparators 54a, 54b, 54c are configured to generate a positive phase PWM signal and a negative phase PWM signal provided with a dead time by using the complementary dead time generating units 55a, 55b, 55c, but this does not limit the scope of application of the present disclosure. For example, the count value of the normalization counter 56 is compared with the positive phase comparison value and the negative phase comparison value by using a comparator to output a positive phase PWM signal and a negative phase PWM signal, and various known methods of outputting complementary PWM signals may be combined.

Claims

1. A PWM control device, characterized in that: A normalized counter is provided, which counts up or down by 2^N / Cmax for each input of a clock signal between 0 and 2^N. The N is a natural number, The Cmax is a value that varies according to the carrier period. The PWM control device further includes a comparator that compares the normalized count value of the normalization counter with a comparison value for determining a duty ratio of the PWM signal and outputs the comparison result as a PWM signal.

2. The PWM control device according to claim 1, characterized in that: Also available: a PWM counter that counts up or down by 1 at a time for each input of the clock signal between 0 and the Cmax; a counter comparison unit that compares the count change value, which is the product of the normalized count value and the Cmax, with the PWM count value of the PWM counter and outputs the result as a counter comparison result; as well as Counter increment unit, The 2^N / Cmax is defined as the counter increment reference value ΔC. The counter increment operation unit performs the following processing: As the provisional counter increment value, ΔC is obtained when the PWM counter is counting up, and -ΔC is obtained when the PWM counter is counting down. As the counter correction reference value ΔCc, the value obtained by shifting ΔC to the right by m bits is obtained. As the counter correction value, ΔCc is obtained when the PWM counter value is larger than the count change value in the counter comparison result, -ΔCc is obtained when it is smaller, and 0 is obtained when they are equal. As the counter increment value, a value obtained by adding the counter correction value to the provisional counter increment value is obtained, The normalized counter adds the count increment value to the current normalized count value at the time when the clock signal is input, so as to update the normalized count value.

3. The PWM control device according to claim 2, characterized in that: The counter comparison unit compares the number of decimal places n among the fixed-point N places of the count conversion value as the number of effective digits and compares them with the PWM count value of the PWM counter. The delay clock number Cd from n to the normalized count value until the normalized count value is reflected in the update of the normalized count value via the counter comparison unit and the counter increment operation unit satisfies the relationship of 2^n≥Cd.

4. The PWM control device according to claim 3, characterized in that: The m as the shift amount of the counter correction reference value ΔCc satisfies the relationship m0-1≤m≤m0+1 relative to m0, and m0 is the smallest integer satisfying 2^m0≥Cd×2^n relative to the n in the alignment of the counter comparison unit and the number of delay clocks Cd.

5. The PWM control device according to claim 4, characterized in that: Regarding ΔC and m, fixed-point bits equal to or less than the m bits are added to the internal count value of the normalization counter and the counter increment reference value of the counter increment calculation unit so that ΔC / 2^m does not become zero.

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