Method for improving multi-level ADC linearity, multi-level ADC inter-electrode amplifier and multi-level ADC
By using controlled switches in the interstage amplifier of multi-stage ADCs, the output and clearance of differential signals are solved, and the linearity and performance of the ADC are improved.
Patent Information
- Application Number
- CN202411848388.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-16
- Publication Date
- 2025-04-04
AI Technical Summary
When the input signal is switched greatly, the output signal is established incorrectly, resulting in the linearity and performance of the ADC.
By introducing a controlled switch into the interstage amplifier, the interstage amplifier controls the interstage amplifier to clear the differential signal before the previous ADC completes the data conversion, and outputs the differential signal after the data conversion is completed, thereby avoiding the adverse effect of the sudden change in the input signal on the output signal.
It effectively overcomes the problem of errors in the output signal establishment when the input signal is switched greatly, and improves the linearity and performance of multi-stage ADCs.
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Figure CN119766242A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and in particular to an ADC (Analog to Digital Converter). Specifically, it relates to a method for improving the linearity of a multi-stage ADC, a multi-stage ADC inter-electrode amplifier, and a multi-stage ADC. Background Art
[0002] ADC is a commonly used important electronic device, its main function is to convert analog signals into digital signals. With the development of integrated circuit technology, analog-to-digital converters are also developing towards high speed, high precision and low power consumption.
[0003] In order to improve the performance of analog-to-digital converters, various types of analog-to-digital converters have emerged, including but not limited to pipeline analog-to-digital converters (Pipeline ADC), pipeline successive comparison analog-to-digital converters (Pipeline SAR ADC), time interleaved analog-to-digital converters (Time interleaved ADC), etc. They all belong to the category of multi-stage ADC.
[0004] A multi-stage ADC consists of at least two sub-ADCs connected and working together through an inter-stage amplifier (or residual amplifier). Currently, for high-speed and high-precision analog-to-digital converters, residual amplifiers are gradually adopting open-loop structures due to the trade-off between speed and power consumption. The voltage and current amplifiers are widely used due to their high linearity.
[0005] High-speed, high-linearity interstage amplifiers are one of the core and most critical modules of high-speed, high-precision analog-to-digital converters, and are also the most challenging and difficult modules to design. Currently, only ADI (analog devices, inc.) and TI (Texas Instruments) in the United States have mastered the design technology of a series of high-speed, high-linearity interstage amplifiers, and they have been applied in many mass-produced high-speed, high-precision analog-to-digital converters of ADI and TI.
[0006] A typical interstage amplifier is Figure 1 As shown, it is a differential amplifier structure. The input stage of the differential amplifier adopts the architecture of super source follower, the output voltage is strictly equal to its input voltage, and it has a small output resistance. The output voltage is linearized through resistors Rs1 and Rs2, and the input voltage is converted into output current through linearized transconductance, and amplified by the current mirror composed of M21 and M201 and the current mirror composed of M22 / M202. The output current is integrated on the capacitive load C101 or C102, respectively, to generate an output voltage signal. Since the output current is only proportional to 1 / Rs1 or 1 / Rs2, it is strictly linear. The specific working principle of the amplifier will not be repeated here.
[0007] The inter-electrode amplifier works between the two stages of the multi-stage ADC. Its main function is to amplify the differential signal output by the front-stage ADC and input it into the back-stage ADC. The circuit working timing and signal waveform are shown in Figure 2 As shown, the input signal waveform and output signal waveform are as follows Figure 3 The inter-electrode amplifier amplifies the differential signal of the front-stage ADC (ADC1) and drives the sampling circuit of the rear-stage ADC (ADC2). The input of the inter-electrode amplifier is directly connected to the output of the front-stage ADC. When the front-stage ADC converts, its output keeps changing (see Figure 3 Amplifier input signal ( Figure 3 In the bad situation, the input signal difference switches from a large positive value to a small negative value. Since the amplifier output signal needs a certain time to establish, the inter-stage amplifier cannot establish the correct output signal within the time τ due to the sudden change of the input signal difference. In this case, when the post-stage sampling is finished, the amplifier output establishment accuracy will decrease, and even an erroneous differential signal will appear (see Figure 3 The Vop-onV in the circuit seriously affects the linearity and performance of the ADC. Summary of the invention
[0008] The main purpose of the present application is to provide a method for improving the linearity of a multi-stage ADC, a multi-stage ADC inter-electrode amplifier and a multi-stage ADC, so as to solve the problem of the linearity of the multi-stage ADC in the prior art.
[0009] In order to achieve the above object, according to one aspect of the specific implementation of the present application, a method for improving the linearity of a multi-stage ADC is provided, characterized in that it includes the following steps:
[0010] a. Detect multi-level ADC working timing pulses;
[0011] b. Determine whether the previous ADC has completed data conversion, if yes, proceed to step c, otherwise proceed to step d;
[0012] c. The inter-stage amplifier outputs a differential signal, and the process returns to step a;
[0013] d. The interstage amplifier clears the differential signal and returns to step a.
[0014] In some embodiments, in step c, the inter-stage amplifier is controlled to output a differential signal through a controlled switch.
[0015] In some embodiments, in step d, the differential signal is cleared by controlling the inter-stage amplifier via the controlled switch.
[0016] In some embodiments, the multi-stage ADC is a Pipeline ADC or a Pipeline SAR ADC or a Timeinterleaved ADC.
[0017] In order to achieve the above-mentioned purpose, according to another aspect of the specific implementation of the present application, a multi-stage ADC interstage amplifier is provided, wherein the input end of the interstage amplifier is connected to the output end of the previous stage ADC, and the output end of the interstage amplifier is connected to the input end of the next stage ADC, and the interstage amplifier includes a controlled switch, and the controlled switch controls the interstage amplifier to clear the differential signal before the previous stage ADC completes data conversion; the controlled switch controls the interstage amplifier to output the differential signal after the previous stage ADC completes data conversion.
[0018] In some embodiments, the controlled switch is a PMOS transistor or an NMOS transistor or a CMOS transistor.
[0019] In some embodiments, the multi-stage ADC is a Pipeline ADC or a Pipeline SAR ADC or a Timeinterleaved ADC.
[0020] In order to achieve the above-mentioned purpose, according to another aspect of the specific implementation of the present application, a multi-stage ADC is provided, comprising at least two-stage ADCs, an inter-stage amplifier is connected between each stage ADC, the input end of the inter-stage amplifier is connected to the output end of the previous stage ADC, and the output end of the inter-stage amplifier is connected to the input end of the next stage ADC, characterized in that the inter-stage amplifier comprises a controlled switch, the controlled switch controls the inter-stage amplifier to clear the differential signal before the previous stage ADC completes data conversion; the controlled switch controls the inter-stage amplifier to output the differential signal after the previous stage ADC completes data conversion.
[0021] In some embodiments, the controlled switch is a PMOS transistor or an NMOS transistor or a CMOS transistor.
[0022] In some embodiments, the multi-stage ADC is a Pipeline ADC or a Pipeline SAR ADC or a Timeinterleaved ADC.
[0023] According to the technical solution of the present application and the further improved technical solution in certain exemplary embodiments thereof, the present application has the following beneficial effects:
[0024] The technical solution of the present application improves the linearity and performance of a multi-stage ADC, and in particular overcomes the problem of output signal establishment errors when the input signal switches significantly.
[0025] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. Additional aspects and advantages of the present application will be partially given in the following description, partially become apparent from the following description, or be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The drawings constituting a part of this application are used to provide a further understanding of this application. The specific implementation modes, illustrative embodiments and their descriptions of this application are used to explain this application and do not constitute an improper limitation on this application. In the drawings:
[0027] Figure 1 It is a schematic diagram of the structure of the inter-stage amplifier circuit in the prior art;
[0028] Figure 2 It is a schematic diagram of the timing pulse waveform of the two-stage ADC operation;
[0029] Figure 3 for Figure 1 Schematic diagram of input signal and output signal waveform of the inter-stage amplifier shown;
[0030] Figure 4 A flowchart of a specific implementation method of this application;
[0031] Figure 5 This is a schematic diagram of the structure of an inter-stage amplifier circuit according to a specific implementation of the present application;
[0032] Figure 6 A schematic diagram of input signal and output signal waveforms of an inter-stage amplifier according to a specific embodiment of the present application;
[0033] Figure 7 Schematic diagrams of several controlled switch structures of specific implementation methods of this application;
[0034] Figure 8 This is a schematic diagram of the multi-stage ADC structure of a specific implementation of the present application. DETAILED DESCRIPTION
[0035] It should be noted that, in the absence of conflict, the specific implementation modes, exemplary embodiments and features thereof in this application can be combined with each other. The present application will now be described in detail with reference to the accompanying drawings and in combination with the following content.
[0036] In order to enable those skilled in the art to better understand the solution of this application, the following will be combined with the drawings in the specific implementation methods and exemplary embodiments of this application to clearly and completely describe the technical solutions in the specific implementation methods and exemplary embodiments of this application. Obviously, the described exemplary embodiments are only part of the embodiments of this application, not all of them. Based on the specific implementation methods and exemplary embodiments in this application, all other implementation methods and embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of this application.
[0037] The method flow of this application to improve the linearity of multi-level ADC is as follows Figure 4 As shown, the following steps are included:
[0038] S401 detects the multi-stage ADC working timing pulse.
[0039] The working timing pulse of the multi-level ADC is as follows Figure 2 As shown (the figure shows the working timing pulse waveforms of two stages of the multi-stage ADC). It can be seen that after the current stage ADC (ADC1) completes data conversion, after a period of time τ, the subsequent stage ADC (ADC2) will enter the sampling process.
[0040] S402 determines whether the previous ADC has completed data conversion, if yes, proceeds to step S403, otherwise proceeds to step S404.
[0041] In this step, the working state of each stage ADC can be judged according to the working timing pulses of the multi-stage ADC.
[0042] S403: the inter-stage amplifier outputs a differential signal, and the process returns to step S401 to enter the next working cycle.
[0043] In this step, the inter-stage amplifier is controlled by the controlled switch to output a differential signal.
[0044] S404: the inter-stage amplifier clears the differential signal, and the process returns to step S401 to enter the next working cycle.
[0045] In this step, the inter-stage amplifier is controlled by the controlled switch to clear the differential signal.
[0046] The method for improving the linearity of a multi-stage ADC in the present application can be applied to a Pipeline ADC (pipeline ADC) or a Pipeline SAR ADC (successive approximation pipeline ADC) or a Time interleaved ADC (time interleaved ADC).
[0047] Example
[0048] The structure of the inter-stage amplifier of the multi-stage ADC in this example is as follows Figure 5 As shown, the inter-stage amplifier input terminals VIN and VIP are connected to the output terminals of the preceding ADC (not shown in the figure), and the inter-stage amplifier output terminals VOP and VON are connected to the input terminals of the succeeding ADC (not shown in the figure).
[0049] The interstage amplifier in this example includes a controlled switch K5, such as Figure 5 As shown. The controlled switch K5 is controlled by the control signal CK_RST. Before the front-stage ADC completes data conversion, the controlled switch K5 is in a closed state, controlling the inter-stage amplifier to clear the differential signal, and the inter-stage amplifier output terminals VOP and VON have no differential signal output. After the front-stage ADC completes data conversion, the controlled switch K5 is disconnected, controlling the inter-stage amplifier output terminals VOP and VON to output the differential signal Vop-Von.
[0050] according to Figure 6 As shown in the input and output waveforms, the controlled switch K5 of the interstage amplifier in this example is always in a closed state before the pre-stage ADC completes the data conversion, and the differential signal output by the interstage amplifier in the AB time period is 0. After the pre-stage ADC completes the data conversion, the controlled switch K5 is disconnected from time B, and the differential signal at the output end of the interstage amplifier is established from 0. After time τ (time period BC), the differential signal is established and the correct differential signal Vop-Von is output.
[0051] In the interstage amplifier of this example, when the input signal changes suddenly (such as the input signal difference switches from a large positive value to a small negative value), the controlled switch K5 is in a closed state, and no differential signal is output at the output end of the interstage amplifier, thereby avoiding the influence of this unstable state on the output signal, improving the linearity of the multi-stage ADC, and improving the performance of the multi-stage ADC.
[0052] In the interstage amplifier of this example, the controlled switch K5 can adopt switch devices of various structures. In order to be compatible with integrated circuits and facilitate processing and manufacturing, it is recommended to adopt PMOS transistors, NMOS transistors or CMOS transistors, such as Figure 7 As shown in Figures a, b and c in Figure 1. For PMOS transistors or NMOS transistors, only single-end control is required. When the control signal k is valid, the P terminal and N terminal are turned on, otherwise they are turned off. For CMOS transistors, two control signals k1 and k2 with opposite phases are required for control.
[0053] The interstage amplifier in this example can be applied to Pipeline ADC, Pipeline SAR ADC or Timeinterleaved ADC.
[0054] The multi-stage ADC structure in this example is as follows Figure 8As shown, it includes n (n≥2) stages of ADC, and an inter-stage amplifier is connected between each stage of ADC, the input end of the inter-stage amplifier is connected to the output end of the previous stage ADC, and the output end of the inter-stage amplifier is connected to the input end of the subsequent stage ADC.
[0055] The structure of the interstage amplifier in this example is as follows Figure 5 As shown, it includes a controlled switch K5. The controlled switch K5 is controlled by the control signal CK_RST. Before the front-stage ADC completes data conversion, the controlled switch K5 is in a closed state, controlling the inter-stage amplifier to clear the differential signal, and the inter-stage amplifier output terminals VOP and VON have no differential signal output. After the front-stage ADC completes data conversion, the controlled switch K5 is disconnected, and the inter-stage amplifier output terminals VOP and VON are controlled to output the differential signal Vop-Von.
[0056] In the interstage amplifier of this example, the controlled switch K5 can be a switch device of various structures, such as a PMOS transistor, an NMOS transistor, or a CMOS transistor. Figure 7 As shown in Figures a, b and c.
[0057] The interstage amplifier in this example can be applied to a Pipeline ADC (pipeline ADC) or a PipelineSAR ADC (successive approximation pipeline ADC) or a Time interleaved ADC (time interleaved ADC).
Claims
1. A method for improving the linearity of a multi-stage ADC, characterized in that: The following steps are involved: a. Detect multi-level ADC working timing pulses; b. Determine whether the previous ADC has completed data conversion, if yes, proceed to step c, otherwise proceed to step d; c. The inter-stage amplifier outputs a differential signal, and the process returns to step a; d. The interstage amplifier clears the differential signal and returns to step a.
2. The method for improving the linearity of a multi-stage ADC according to claim 1, characterized in that: Step c: controlling the inter-stage amplifier to output a differential signal through a controlled switch.
3. The method for improving the linearity of a multi-stage ADC according to claim 1, wherein: Step d, controlling the inter-stage amplifier through the controlled switch to clear the differential signal.
4. The method for improving the linearity of a multi-stage ADC according to claim 1, wherein: The multi-stage ADC is a Pipeline ADC, a Pipeline SAR ADC, or a Time interleaved ADC.
5. A multi-stage ADC inter-stage amplifier, wherein the input end of the inter-stage amplifier is connected to the output end of the previous stage ADC, and the output end of the inter-stage amplifier is connected to the input end of the next stage ADC, characterized in that: The interstage amplifier includes a controlled switch, which controls the interstage amplifier to clear the differential signal before the previous ADC completes data conversion; the controlled switch controls the interstage amplifier to output the differential signal after the previous ADC completes data conversion.
6. The multi-stage ADC inter-stage amplifier according to claim 5, characterized in that: The controlled switch is a PMOS transistor, an NMOS transistor, or a CMOS transistor.
7. The multi-stage ADC inter-stage amplifier according to claim 5, characterized in that: The multi-stage ADC is PipelineADC or PipelineSAR ADC or Time interleaved ADC.
8. A multi-stage ADC, comprising at least two stages of ADC, wherein an inter-stage amplifier is connected between each stage of ADC, wherein the input end of the inter-stage amplifier is connected to the output end of the preceding stage ADC, and the output end of the inter-stage amplifier is connected to the input end of the succeeding stage ADC, wherein: The interstage amplifier includes a controlled switch, which controls the interstage amplifier to clear the differential signal before the previous ADC completes data conversion; the controlled switch controls the interstage amplifier to output the differential signal after the previous ADC completes data conversion.
9. The multi-stage ADC according to claim 8, characterized in that: The controlled switch is a PMOS transistor, an NMOS transistor, or a CMOS transistor.
10. The multi-stage ADC according to claim 8, characterized in that: The multi-stage ADC is a Pipeline ADC or a PipelineSAR ADC or a Time interleaved ADC.