Incremental Delta-Sigma Analog-to-Digital Converter Circuit

Abstract

This disclosure provides an incremental Delta-Sigma analog-to-digital converter (ADC) circuit, including a modulator and an integrator cascaded filter. The incremental Delta-Sigma ADC circuit has an order of L, where L is a constant greater than 1. The modulator includes a chopper control signal generation module, which has L frequency-divided signal inputs for the sampling clock. The chopper control signal generation module generates a chopper control signal based on the L frequency-divided signals of the sampling clock through combinational logic. The modulator outputs a modulated signal based on the chopper control signal. The integrator cascaded filter receives the modulated signal and outputs a corresponding converted signal based on the average error of the ADC circuit within the conversion period. Under chopper timing control, the modulator bitstream, after being processed by the integrator cascaded filter, can achieve complete cancellation of DC offset within one chopper cycle, eliminating the residual offset of the ADC circuit and reducing the influence of flicker noise.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of data conversion circuit, in particular to an incremental Delta-Sigma analog-digital conversion circuit. BACKGROUND

[0002] The existing single-loop discrete-time incremental Delta-Sigma analog-digital conversion circuit, in a conversion period, the difference between the input signal and the feedback signal is continuously accumulated, the quantization error is averaged, and after the end of a conversion period, the integrator and the filter are reset, and then the next conversion period is entered. The quantization accuracy of the ADC depends on the degree of averaging of the quantization error, and the degree of averaging of the quantization error is related to the order L of the loop filter and the number of clock periods contained in a conversion period.

[0003] Due to the existence of periodic reset, when the order of the loop filter of the incremental Delta-Sigma analog-digital conversion circuit is greater than 1, the weight of the signal processed by the decimation filter is uneven. Taking the CoI filter as an example, the distribution of the signal weight of the CoI filter is related to the order, and the higher the order, the greater the degree of unevenness of the signal weight. Even if the chopper frequency is , there is still offset residual for high-order incremental Delta-Sigma analog-digital conversion circuits, and the residual value of the offset increases with the increase of the order and decreases with the increase of the decimation rate M. SUMMARY

[0004] The technical problem to be solved by the present disclosure is to overcome the defect that the DC offset of the existing incremental Delta-Sigma analog-digital conversion circuit cannot be eliminated, and to provide an incremental Delta-Sigma analog-digital conversion circuit.

[0005] The present disclosure solves the above technical problems by the following technical solutions:

[0006] The present disclosure provides an incremental Delta-Sigma analog-digital conversion circuit, comprising a modulator and a CoI filter;

[0007] The order of the incremental Delta-Sigma analog-digital conversion circuit is L, and L is a constant greater than 1;

[0008] The modulator comprises a chopper control signal generation module;

[0009] The chopping control signal generation module comprises L frequency division signal input terminals of a sampling clock, and the chopping control signal generation module modulates the chopping control signal based on the L frequency division signals of the sampling clock;

[0010] The modulator outputs a modulation signal based on the chopping control signal;

[0011] The modulation signal comprises a DC offset, the DC offset matches the chopping timing of the chopping control signal, and the DC offsets of all the modulation signals in the same chopping period of the chopping timing are mutually offset after being averaged with weights;

[0012] The integrator filter receives the modulation signal and outputs a corresponding conversion signal based on the average error of the incremental Delta-Sigma analog-to-digital conversion circuit in a conversion period.

[0013] Preferably, the modulator comprises a loop filter, and the chopping control signal generation module comprises a clock signal modulation unit and a chopping signal output unit;

[0014] The clock signal modulation unit comprises L frequency division clock signal input terminals corresponding to the sampling clock signal and L-1 XNOR logic gates;

[0015] The clock signal modulation unit modulates the L frequency division clock signals received based on the L-1 XNOR logic gates to obtain the chopping control signal;

[0016] The chopping signal output unit is connected to the input terminal and the output terminal of the loop filter, respectively;

[0017] The chopping signal output unit modulates the input signal of the loop filter based on the chopping control signal, demodulates the output signal of the loop filter based on the chopping control signal, and modulates the DC offset output by the loop filter;

[0018] The loop filter integrates the input signal of the loop filter and outputs a corresponding modulation analog signal.

[0019] Preferably, the frequency of the frequency division clock signal input by the frequency division clock signal input terminal is , n = 1, 2, 3, …, L, is the frequency of the sampling clock signal.

[0020] Preferably, when L = 3, the clock signal modulation unit comprises a first frequency division clock signal input terminal with a frequency of , a second frequency division clock signal input terminal with a frequency of , and a third frequency division clock signal input terminal with a frequency of a third divided clock signal input end, and a first EXCLUSIVE-OR logic gate and a second EXCLUSIVE-OR logic gate;

[0021] the first divided clock signal input end and the second divided clock signal input end input a first EXCLUSIVE-OR logic gate, and output a first modulated clock signal;

[0022] the output end of the first EXCLUSIVE-OR gate and the third divided clock signal input end input a second EXCLUSIVE-OR logic gate, and output a second modulated clock signal;

[0023] the second modulated clock signal is used as the chopping control signal, and the chopping signal output unit outputs.

[0024] Preferably, when L=4, the clock signal modulation unit further comprises a fourth divided clock signal input end with a frequency of and a third EXCLUSIVE-OR logic gate;

[0025] the output end of the second EXCLUSIVE-OR logic gate and the fourth divided clock signal input end input the third EXCLUSIVE-OR logic gate, and output a third modulated clock signal;

[0026] the third modulated clock signal is used as the chopping control signal, and the chopping signal output unit outputs.

[0027] Preferably, the chopping signal output unit comprises, respectively, a first logic switch and a second logic switch connected to the input end and the output end of the loop filter.

[0028] the chopping signal output unit is connected to the input end of the loop filter through the first logic switch to control the polarity of the input signal of the loop filter;

[0029] the chopping signal output unit is connected to the output end of the loop filter through the second logic switch to control the polarity of the output signal of the loop filter.

[0030] Preferably, the modulator further comprises a quantizer connected to the output end of the loop filter.

[0031] the quantizer is configured to receive the modulated analog signal demodulated by the chopping control signal, and convert the demodulated modulated analog signal into a corresponding digital signal.

[0032] Preferably, the modulator further comprises a feedback loop, and an input end of the feedback loop is connected to an output end of the quantizer.

[0033] the feedback loop is configured to feed back the quantized digital signal, perform difference processing on the input signal of the modulator and the quantized digital signal to obtain a difference input signal, and send the difference input signal to the input end of the loop filter.

[0034] Preferably, the feedback loop comprises a digital-to-analog converter and an adder.

[0035] The input end of the digital-to-analog converter is connected with the output end of the quantizer, and the output end of the digital-to-analog converter is connected with the adder.

[0036] The input end of the adder receives an input analog signal, and the output end of the adder is connected with the input end of the loop filter.

[0037] The digital-to-analog converter is configured to convert the quantized digital signal into an analog signal as a feedback signal and feed back to the adder.

[0038] The adder is configured to add the input analog signal and the feedback signal to obtain a difference signal, and the difference signal is taken as the input signal of the loop filter. Preferably, a downsampling module is further included, and the downsampling module is connected with the integrator cascade filter.

[0039] The downsampling module is configured to decimate the converted signal output by the integrator cascade filter at a downsampling rate M to obtain an output digital signal.

[0040] The output digital signal is taken as the output of the incremental Delta-Sigma analog-to-digital conversion circuit.

[0041] The positive progress effect of the present disclosure is that, for the characteristic that the processing weight of the integrator cascade filter on the modulated signal output by the modulator in the high-order incremental Delta-Sigma analog-to-digital conversion circuit is non-uniform, under the timing control of the chopping control signal generation module, the modulator code stream is processed by the integrator cascade filter, and in one chopping period, the complete cancellation of the direct current offset can be realized, and the direct current offset of the single conversion result obtained is zero, which realizes the elimination of the residual offset caused by the non-uniform signal weight of the high-order incremental Delta-Sigma analog-to-digital conversion circuit, and also reduces the influence of flicker noise. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 A module schematic diagram of the incremental Delta-Sigma analog-to-digital conversion circuit provided by an exemplary embodiment of the present disclosure is provided.

[0043] Figure 2 A signal weight distribution schematic diagram of the integrator cascade filter in the incremental Delta-Sigma analog-to-digital conversion circuit provided by an exemplary embodiment of the present disclosure is provided.

[0044] Figure 3A circuit structure schematic diagram of the incremental Delta-Sigma analog-digital conversion circuit provided by an exemplary embodiment of the present disclosure is shown in the following figure;

[0045] Figure 4 A chopping signal timing schematic diagram of the incremental Delta-Sigma analog-digital conversion circuit provided by an exemplary embodiment of the present disclosure is shown in the following figure when the order of the loop filter is three;

[0046] Figure 5 A chopping signal timing schematic diagram of the incremental Delta-Sigma analog-digital conversion circuit provided by an exemplary embodiment of the present disclosure is shown in the following figure when the order of the loop filter is four. DETAILED DESCRIPTION

[0047] The present disclosure is further illustrated by the following examples, but the present disclosure is not limited in the scope of the examples.

[0048] In the embodiments of the present disclosure, the prefix words such as "first", "second" are merely used to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of ordinal words such as "first", "second" in the embodiments of the present disclosure does not constitute a limitation on the described objects, and the description of the described objects should be referred to the description in the context of the claims or embodiments, and should not constitute an additional limitation because of the use of such prefix words. In addition, in the description of the embodiments, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0049] In the incremental Delta-Sigma analog-digital conversion circuit, for the first-order to fourth-order CoI filter, the transfer functions are respectively:

[0050]

[0051]

[0052]

[0053]

[0054] wherein M is the down-sampling rate, is the unit delay, is the delay of the input signal for k sampling periods, and k is a constant.

[0055] When the order of the loop filter is greater than 1, the sampling clock frequency is , the chopper frequency of the integrator is , and the 2 division of the chopper frequency, then after one conversion period, the suppression ratio r of the system to the offset voltage equivalent to the input end of the loop filter is calculated as follows:

[0056] ​​​​ ;

[0057] ;

[0058] ;

[0059] Example 1

[0060] This embodiment provides an incremental Delta-Sigma analog-to-digital converter circuit, such as... Figure 1 As shown, it includes a modulator 100 and an integrator cascaded filter 200;

[0061] The order of the incremental Delta-Sigma analog-to-digital converter circuit is L, where L is a constant greater than 1;

[0062] The modulator 100 includes a chopper control signal generation module 110;

[0063] The chopper control signal generation module 110 includes L frequency division signal input terminals of the sampling clock, and the chopper control signal generation module 110 modulates the chopper control signal based on the L frequency division signals of the sampling clock.

[0064] The modulator 100 outputs a modulated signal based on the chopper control signal;

[0065] The modulation signal includes a DC offset, which is matched with the chopping timing of the chopping control signal. The DC offsets of all the modulation signals within the same chopping period of the chopping timing are weighted and then cancel each other out.

[0066] The integrator cascade filter 200 receives the modulation signal and outputs the corresponding conversion signal based on the average error of the incremental Delta-Sigma analog-to-digital converter circuit during the conversion period.

[0067] In this scheme, the distribution of signal weights for first to fourth order CoI filters varies with the data sequence number as follows: Figure 2 As shown in the figure, the vertical axis represents the signal weight, and the horizontal axis represents the corresponding data position. In the second to fourth orders, the modulation signal weight is non-uniform. Since the non-uniformity of the modulation signal weight increases with the order, for the k-th data, its modulation signal weight is closest to the modulation signal weights corresponding to the (k-1)-th and (k+1)-th data, and the change of the modulation signal weight is a monotonic function. Therefore, for systems of different orders, by using the chopper control signal generation module 110 to output a modulation signal that matches the modulation signal weight, the offset can be canceled out to the greatest extent.

[0068] In one embodiment, taking the order of the incremental Delta-Sigma analog-digital conversion circuit as an example, the change of the modulation signal weight is uniformly decreasing, and the modulation signal weight of the kth data based on the second-order transfer function of the CoI filter is (2(M-k+1)) / (M(M+1)), and generally the first data corresponds to the largest modulation signal weight. The chopping control signal generation module 110 outputs a second-order matching chopping control signal, and the chopping control signal corresponds to a chopping timing In the same chopping period of the chopping timing, the first offset corresponding to the first data and the second offset corresponding to the second data offset each other to generate a positive ; similarly, the third offset corresponding to the third data and the fourth offset corresponding to the fourth data offset each other to generate a negative ; and and offsetting each other again can completely eliminate the offset.

[0069] As an implementable way, as shown in Figure 3 , the modulator 100 includes a loop filter 120, and the chopping control signal generation module 110 includes a clock signal modulation unit 111 and a chopping signal output unit 112.

[0070] The clock signal modulation unit 111 includes L frequency division clock signal input ends corresponding to L sampling clock signals and L-1 XNOR logic gates.

[0071] The clock signal modulation unit 111 is configured to modulate the L frequency division clock signals received based on the L-1 XNOR logic gates 1112 to obtain the chopping control signal.

[0072] The chopping signal output unit 112 is connected with the input end and the output end of the loop filter 120, respectively.

[0073] The chopping signal output unit 112 is configured to modulate the input signal of the loop filter 120 based on the chopping control signal, demodulate the output signal of the loop filter 120 based on the chopping control signal, and modulate the direct current offset output by the loop filter.

[0074] The loop filter 120 is configured to perform an integration operation on the input signal of the loop filter to output a corresponding modulation analog signal.

[0075] In this scheme, the clock signal modulation unit 111 sets up corresponding cascaded OR logic gates and L frequency-divided clock signal input terminals 1111 based on the order L. The frequency-divided clock signal input terminals 1111 input the sampling clock divided by two signals such as ck_div2, the sampling clock divided by four signals such as ck_div4, and so on, as well as ck_div2. L Sampling clock 2 L A frequency division signal is used to provide stable timing control, generating a chopper control signal matched to the order L. The chopper signal output unit 112 modulates the input signal of the loop filter 120 with the chopper control signal ck_chop. The chopper control signal ck_chop also demodulates the effective output signal of the loop filter 120. Simultaneously, the DC offset is modulated at the output of the loop filter, so that the DC offset of all the modulated signals output by the modulator 100 within the same chopper cycle of the chopper timing can be canceled out after being averaged with non-uniform weights. The input signal of the loop filter 120 includes the DC offset.

[0076] As one possible approach, the frequency of the divided clock signal input to the divided clock signal input terminal is... n=1,2,3…… L The sampling clock signal frequency.

[0077] In this solution, unlike existing technologies that use a single frequency... The chopper control signal is adjusted by L frequency-divided clock signals that match the order L to obtain a chopper control signal that matches the weight of the modulation signal in the corresponding order, thereby achieving complete cancellation of the DC offset of all the modulation signals in the same chopper cycle of the chopper timing.

[0078] As one possible implementation, when L=3, the clock signal modulation unit 111 includes a frequency of The first frequency divider clock signal input terminal, frequency is The second frequency divider clock signal input terminal and the frequency are The third frequency divider clock signal input terminal, and the first and second XNOR logic gates;

[0079] The first frequency divider clock signal input terminal and the second frequency divider clock signal input terminal are input to a first XOR logic gate, which outputs a first modulation clock signal;

[0080] The output of the first XOR gate is input to the second XOR logic gate, which is connected to the input of the third frequency divider clock signal, and outputs the second modulation clock signal.

[0081] The second modulation clock signal is used as the chopping control signal and is output by the chopping signal output unit 112.

[0082] In this scheme, for a third-order system, the signal weights decrease non-uniformly. For the k-th data point, the modulated signal weights based on the third-order transfer function of the CoI filter are: The modulation weights of the k-th and (k+1)-th data points differ by . The chopper control signal generation module 110 outputs a third-order matched chopper control signal, such as... Figure 4 As shown, ck represents the timing of the sampling clock signal, and ck_chop_2nd is the frequency of... The timing sequence of the first modulation clock signal, the first modulation clock signal is composed of a frequency of The frequency of the divided clock signal is The frequency division signal is obtained by XOR calculation, and ck_chop_3rd is the frequency of The timing sequence of the second modulation clock signal, the second modulation clock signal is composed of the first modulation clock signal and a frequency of... The frequency division signal is XORed and then calculated to obtain the second modulation clock signal timing, which is the chopping timing corresponding to the chopping control signal. The sequence of one chopping cycle in the chopping timing corresponding to the chopping control signal is as follows: After the first four data points are offset, the remaining positive value is... Its weight value is The remaining negative value after canceling out the last four data points is... Its weight value is It can be seen that the weight of the modulated signal of the residual offset after the summation of the 8 data points is independent of k. and The chopper control signal generation module 110 obtains a chopper control signal that matches the weight of the modulation signal in the corresponding order based on the input frequency division clock signal, thereby achieving complete cancellation of the DC offset of all the modulation signals within the same chopper cycle of the chopper timing sequence.

[0083] As one possible implementation, when L=4, the clock signal modulation unit 111 further includes a frequency of The fourth frequency divider clock signal input terminal and the third XOR logic gate;

[0084] The output of the second XOR logic gate and the input of the fourth frequency divider clock signal are input to the third XOR logic gate to output the third modulation clock signal;

[0085] The third modulation clock signal is used as the chopping control signal and is output by the chopping signal output unit 112.

[0086] In this scheme, based on the third-order system, for the fourth-order system, for the k-th data point, the modulation signal weights based on the fourth-order transfer function of the CoI filter are: The difference in the modulated signal weights of the k-th and (k+1)-th data points is... .like Figure 5 As shown, ck represents the timing of the sampling clock signal, and ck_chop_2nd is the frequency of... The timing sequence of the first modulation clock signal, the first modulation clock signal is composed of a frequency of The frequency of the divided clock signal is After XORing the frequency-divided signal, ck_chop_3rd is obtained, where the frequency is... The timing sequence of the second modulation clock signal, the second modulation clock signal is composed of the first modulation clock signal and a frequency of... After XORing the frequency-divided signal, ck_chop_4th is obtained, where the frequency is... The timing sequence of the third modulation clock signal, which is composed of the second modulation clock signal and a frequency of... The frequency division signal is XORed and then calculated to obtain the third modulation clock signal timing, which is the chopping timing corresponding to the chopping control signal. One chopping cycle in the chopping timing corresponding to the chopping control signal uses the sequence... After the first four data points are offset, the remaining positive value is... Its weight value is The remaining negative value after canceling out the last four data points is... Its weight value is , and After offsetting again, the remaining positive value is... Its weight value is Similar to the third-order system, the weight of the residual offset after summing the first 8 data points is independent of k; similarly, the weight of the residual offset after summing the last 8 data points can be calculated as follows: Therefore, for a fourth-order system using the first, second, third, and fourth frequency division clock signals, the chopper control signal obtained by modulation based on the XOR logic gate can match the weights of the modulation signals in the corresponding order, thereby achieving complete cancellation of the DC offset of all the modulation signals within the same chopper cycle of the chopper timing sequence.

[0087] In one possible implementation, the chopper signal output unit 112 is connected to the input and output terminals of the loop filter 120, respectively, and includes:

[0088] The chopper signal output unit 112 is connected to the input terminal of the loop filter 130 through the first logic switch 130 to control the polarity of the input signal of the loop filter 130.

[0089] The chopper signal output unit 112 is connected to the output terminal of the loop filter 130 through the second logic switch 120 to control the polarity of the output signal of the loop filter 130.

[0090] In this scheme, the first logic switch 130 is used to multiply the input signal of the loop filter 120 with the chopper control signal to achieve signal modulation. The first logic switch 130 performs the function of a multiplier. The second logic switch 140 is used to multiply the output signal of the loop filter 120 with the chopper control signal to achieve signal demodulation. The second logic switch 140 also performs the function of a multiplier. By reducing the offset voltage and low-frequency noise through the modulation and demodulation process, it helps to convert DC offset and low-frequency noise to high frequency, so that they can be filtered out by subsequent digital filters.

[0091] As one possible implementation, the modulator 100 further includes a quantizer 160 connected to the output of the loop filter 120;

[0092] The quantizer 160 is used to receive the modulated analog signal after being demodulated by the chopper control signal, and convert the demodulated modulated analog signal into a corresponding digital signal.

[0093] As a possible method for feedback and low-precision bitstream, the modulator 100 also includes a feedback loop, the input of which is connected to the output of the quantizer 160.

[0094] The feedback loop is used to feed back the quantized digital signal, perform differential processing on the input signal of the modulator 100 and the quantized digital signal to obtain a differential input signal, and send the differential input signal to the input terminal of the loop filter 120.

[0095] In this scheme, the quantization error is fed back through the feedback circuit. In the incremental Delta-Sigma analog-to-digital converter circuit, the quantization process of the modulator 100 will generate quantization error. The feedback loop feeds the quantization error from the output to the input, so that the quantization error can be fed back and processed together with the new input signal in the subsequent sampling period.

[0096] In one possible implementation, the feedback loop includes a digital-to-analog converter 170 and an adder 150;

[0097] The input terminal of the digital-to-analog converter 170 is connected to the output terminal of the quantizer 160, and the output terminal of the digital-to-analog converter 170 is connected to the adder 150.

[0098] The input terminal of the adder 150 receives an input analog signal, and the output terminal of the adder 150 is connected to the input terminal of the loop filter 120.

[0099] The digital-to-analog converter 170 is used to convert the quantized digital signal into an analog signal as a feedback signal and feed it back to the adder 150.

[0100] The adder 150 is used to add the input analog signal and the feedback signal to obtain a differential signal, and the differential signal is used as the input signal of the loop filter 130.

[0101] In this scheme, in the incremental Delta-Sigma analog-to-digital converter circuit, adder 150 adds the input signal and the feedback signal to obtain a differential signal. The subtraction is achieved by adding a negative feedback signal within adder 150. The resulting differential signal reflects the difference between the input signal and the feedback signal, i.e., the quantization error. This quantization error is then fed into the subsequent modulator 100 for processing, which alters the spectral distribution of the quantization noise, thus achieving noise shaping.

[0102] As one possible approach, a downsampling module is also included, which is connected to the integrator cascade filter 200;

[0103] The downsampling module is used to extract the converted signal output by the integrator cascade filter 200 at a downsampling rate M to obtain the output digital signal.

[0104] The output digital signal is used as the output of the incremental Delta-Sigma analog-to-digital converter circuit.

[0105] In this scheme, the output rate of the signal is reduced by the downsampling module, which significantly reduces the amount of data. After downsampling, high-frequency noise and the offset of the modulated high frequency in the signal are filtered out, so that subsequent digital processing can be carried out on a cleaner signal basis, thereby improving the accuracy and reliability of the final output signal.

[0106] The incremental Delta-Sigma analog-to-digital converter circuit provided in this embodiment addresses the non-uniform weighting of the modulated signal output from the modulator by the integrator cascade filter in high-order incremental Delta-Sigma analog-to-digital converter circuits. Under the timing control of the chopper control signal generation module, the modulator bitstream is processed by the integrator cascade filter, and the DC offset can be completely canceled within one chopper cycle. The final single conversion result has zero DC offset, thus eliminating the residual offset caused by the non-uniform signal weighting of high-order incremental Delta-Sigma analog-to-digital converter circuits, while also reducing the impact of flicker noise.

[0107] While specific embodiments of this disclosure have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of this disclosure is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of this disclosure, but all such changes and modifications fall within the scope of protection of this disclosure.

Claims

1. An incrementing delta-sigma analog-to-digital conversion circuit, characterized by, The modulator and the integrator cascade filter are included; The order of the delta-sigma analog-to-digital conversion circuit is L, L is a constant greater than 1; The modulator includes a chopping control signal generation module; The chopping control signal generation module includes L frequency division signal input terminals of a sampling clock, and the chopping control signal generation module obtains a chopping control signal based on the L frequency division signals of the sampling clock through combination logic; The modulator outputs a modulation signal based on the chopping control signal; The modulation signal includes a direct current offset, the direct current offset matches the chopping timing of the chopping control signal, and the direct current offsets of all the modulation signals in the same chopping period of the chopping timing are mutually offset after being averaged with weights; The integrator cascade filter receives the modulation signal, and outputs a corresponding conversion signal based on the average error of the delta-sigma analog-to-digital conversion circuit in a conversion period.

2. The incrementally operating delta-sigma analog-to-digital conversion circuit of claim 1, wherein, The modulator includes a loop filter, and the chopping control signal generation module includes a clock signal modulation unit and a chopping signal output unit; The clock signal modulation unit includes L frequency division clock signal input terminals corresponding to a sampling clock signal and L-1 XNOR logic gates; The clock signal modulation unit is configured to obtain the chopping control signal by modulating the received L frequency division clock signals based on the L-1 XNOR logic gates; The chopping signal output unit is connected with the input terminal and the output terminal of the loop filter, respectively; The chopping signal output unit is configured to modulate the input signal of the loop filter based on the chopping control signal, demodulate the output signal of the loop filter based on the chopping control signal, and modulate the direct current offset output by the loop filter; The loop filter is configured to perform an integration operation on the input signal of the loop filter to output a corresponding modulation analog signal.

3. The incrementally operating delta-sigma analog-to-digital conversion circuit of claim 2, wherein, The frequency of the divided clock signal inputted by the divided clock signal input end is n = 1, 2, 3…L, is the sampling clock signal frequency.

4. The incrementally operating delta-sigma analog-to-digital conversion circuit of claim 3, wherein, When L=3, the clock signal modulation unit comprises a first divided clock signal input end with a frequency of , a second divided clock signal input end with a frequency of , and a third divided clock signal input end with a frequency of , and a first XNOR logic gate and a second XNOR logic gate. The first XNOR logic gate inputs a first XNOR logic gate with the first frequency division clock signal input terminal and the second frequency division clock signal input terminal, and outputs a first modulation clock signal; The output terminal of the first XNOR gate inputs a second XNOR logic gate with the third frequency division clock signal input terminal, and outputs a second modulation clock signal; The second modulation clock signal is taken as the chopping control signal and output by the chopping signal output unit.

5. The incrementally operating delta-sigma analog-to-digital conversion circuit of claim 4, wherein, When L=4, the clock signal modulation unit further comprises a fourth frequency division clock signal input end with a frequency of and a third same or logic gate. The output terminal of the second XNOR logic gate inputs the third XNOR logic gate with the fourth frequency division clock signal input terminal, and outputs a third modulation clock signal; The third modulation clock signal is taken as the chopping control signal and output by the chopping signal output unit.

6. The incrementally operating delta-sigma analog-to-digital conversion circuit of claim 2, wherein, The chopping signal output unit is connected with the input terminal and the output terminal of the loop filter, respectively; The chopping signal output unit is connected with the input terminal of the loop filter through a first logic switch to control the polarity of the input signal of the loop filter; The chopping signal output unit is connected with the output terminal of the loop filter through a second logic switch to control the polarity of the output signal of the loop filter.

7. The incrementally operating delta-sigma analog-to-digital conversion circuit of claim 6, wherein, The modulator further includes a quantizer connected with the output terminal of the loop filter; The quantizer is configured to receive the demodulated analog signal and convert the demodulated analog signal into a corresponding digital signal.

8. The incrementally operating delta-sigma analog-to-digital conversion circuit of claim 7, wherein, The modulator further comprises a feedback loop, an input end of the feedback loop being connected with an output end of the quantizer; The feedback loop is configured to feed back the quantized digital signal, perform difference processing on the input signal of the modulator and the quantized digital signal to obtain a difference input signal, and send the difference input signal to an input end of the loop filter.

9. The incrementally operating delta-sigma analog-to-digital conversion circuit of claim 8, wherein, The feedback loop comprises a digital-to-analog converter and an adder; An input end of the digital-to-analog converter is connected with an output end of the quantizer, and an output end of the digital-to-analog converter is connected with the adder; An input end of the adder receives an input analog signal, and an output end of the adder is connected with the input end of the loop filter; The digital-to-analog converter is configured to convert the quantized digital signal into an analog signal as a feedback signal and feed back the feedback signal to the adder; The adder is configured to add the input analog signal and the feedback signal to obtain a difference signal, and send the difference signal as the input signal of the loop filter.

10. The incrementally operating delta-sigma analog-to-digital conversion circuit of claim 2, wherein, The application further comprises a downsampling module connected with the integrator cascade filter; The downsampling module is configured to decimate the converted signal output by the integrator cascade filter at a downsampling rate M to obtain an output digital signal; The output digital signal is taken as an output of the incremental Delta-Sigma analog-to-digital conversion circuit.

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