A state switching method, apparatus and electronic device

Abstract

This disclosure provides a state switching method, apparatus, and electronic device. The state switching method includes: generating and maintaining a state switching signal when a preset state switching condition is met; switching the state of a target object using the state switching signal; calculating the time interval between the current time and the end time of a synchronization alignment signal; the synchronization alignment signal is a signal applied to the target object earlier than the state switching signal; and ending the state switching signal when the time interval meets a preset condition, thus completing the state switching of the target object; the preset condition includes the time interval being an even multiple of a first clock cycle. This embodiment ensures that the output signal of the target object after state switching is synchronized with the synchronization alignment signal, solving the problem of timing disorder and improving circuit performance.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a state switching method, apparatus and electronic device. Background Technology

[0002] In recent years, 5G (5th generation mobile networks) communication has developed rapidly, and the requirements for system power consumption are becoming increasingly stringent. As an important component of the radio frequency transceiver system, the power consumption of the high-speed and high-precision DAC (Digital to Analog Converter) is very important to the power consumption of the entire system. When the communication system operates in TDD (Time Division Duplexing) mode, the transceiver shares a single radio frequency, and the uplink and downlink use different time slots for communication. Therefore, in the time slot when the DAC is not transmitting data (called Sleep Mode), some circuits can be turned off to reduce power consumption. Summary of the Invention

[0003] This disclosure provides a state switching method, apparatus, and electronic device.

[0004] In a first aspect, embodiments of this disclosure provide a state switching method, the method comprising:

[0005] When the preset state switching conditions are met, a state switching signal is generated and maintained.

[0006] The state switching signal is used to switch the state of the target object;

[0007] The time interval between the current moment and the end moment of the synchronization alignment signal is calculated; the synchronization alignment signal is a signal applied to the target object earlier than the state switching signal.

[0008] When the time interval meets a preset condition, the state switching signal ends, and the state switching of the target object is completed; the preset condition includes: the time interval is an even multiple of the first clock cycle.

[0009] Secondly, embodiments of this disclosure provide a state switching device, including: a state switching unit; the state switching unit is configured to implement the state switching method described above.

[0010] Thirdly, embodiments of this disclosure provide an electronic device including the aforementioned state switching device.

[0011] The state switching method of this disclosure applies a state switching signal to the target object by making the time interval between the end time of the state switching signal and the end time of the synchronization alignment signal an even multiple of the first clock cycle of the target object's output signal. This ensures that after the target object performs a state switch, the target object's output signal is synchronized with the synchronization alignment signal, thereby solving the problem of timing disorder caused by the phase change of the output signal after directly performing a state switch on the target object in the current solution, and thus improving circuit performance. Attached Figure Description

[0012] In the accompanying drawings of the embodiments disclosed herein:

[0013] Figure 1 This is a block diagram of the components of a digital-to-analog converter in related technologies;

[0014] Figure 2 This is a block diagram of the clock path in the relevant technology;

[0015] Figure 3 A flowchart of a state switching method provided in an embodiment of this disclosure;

[0016] Figure 4 This is a schematic diagram of a four-phase two-division frequency divider structure provided in an embodiment of the present disclosure;

[0017] Figure 5 Provided for the embodiments of this disclosure Figure 4 The timing diagram of the frequency divider is shown below;

[0018] Figure 6 This is a block diagram of the state switching device provided in the embodiments of this disclosure;

[0019] Figure 7 The target object provided in this embodiment of the disclosure is a frequency divider, and a state switching device is a connection diagram of a state switching device under the condition of synchronizing multiple frequency division signals;

[0020] Figure 8 The target object provided in this embodiment is a frequency divider, and a state switching device is a connection diagram of a state switching device under the condition of synchronizing a frequency division signal;

[0021] Figure 9 A timing diagram of the automatic reset of the frequency divider based on the state switching device in time-division duplex mode provided in the embodiments of this disclosure;

[0022] Figure 10 A schematic diagram of the state switching device after adding a synchronization alignment signal generation circuit, provided in an embodiment of this disclosure;

[0023] Figure 11 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0024] To enable those skilled in the art to better understand the technical solutions of this disclosure, the communication-sensing data processing method and computer-readable storage medium provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0025] The present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of the disclosure.

[0026] The accompanying drawings of the embodiments disclosed herein are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the detailed embodiments to explain this disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the description of the detailed embodiments with reference to the accompanying drawings.

[0027] This disclosure may be described with reference to plan and / or cross-sectional views using the ideal schematic diagrams of this disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances.

[0028] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0029] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0030] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0031] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas of an element, but are not intended to be limiting.

[0032] Appendix Figure 1 This is a system block diagram of a DAC (Digital to Analog Converter), including the Data Path, Clock Path, and the DAC Core. The Data Path includes the Interface circuit, Digital Data Path, Decoder, Serializer, and Switch Driver. The Clock Path includes the Clock & Sync Receiver, Divider, and several clock drivers. The DAC Core comprises multiple DAC Core Slices. In the Clock Path, the CLK (clock signal) from the PLL (Phase Locked Loop) is driven and transmitted to the Divider, which then transmits the divided clock signal to the Decoder (X1 division), Serializer (X2 division), and Switch Driver (X3 division). In TDD mode, disabling the Clock Path significantly reduces the power consumption of the Clock Path itself and its application circuitry.

[0033] Appendix Figure 2This is a traditional clock path block diagram. The PLL (Phase Locked Loop) sends a reference synchronization signal and a clock signal. After passing through the Clock & Sync Receiver, the Initial Sync Pulse Generator generates a reset pulse signal to reset the Divider, ensuring that the clock phases of different frequency domains are deterministic. Therefore, the data and sampling clock phase relationships of the Decoder, Serializer, and Switch Driver are fixed. The problem with this traditional clock path is that when the system operates in TDD mode, when the transmitter switches from a sleep time slot to a normal operating time slot, the Divider's clock also switches from off to resume. However, the start time of the transmitter switching to the normal operating time slot is uncertain, causing a change in the phase of the divided clock. This results in an uncertain data and clock phase relationship for the Decoder, Serializer, and Switch Driver circuits, causing timing problems and degrading DAC performance.

[0034] The state switching method of this disclosure applies a state switching signal (e.g., a first reset signal for waking up the divider) to a target object (e.g., a divider divider). By making the time interval between the end time of the state switching signal and the end time of the synchronization alignment signal (e.g., a reset pulse signal) an even multiple of the first clock cycle of the target object's output signal (e.g., a divide-by-two clock cycle, a divide-by-four clock cycle, a divide-by-six clock cycle, etc.), the phase of the target object's output signal is aligned with the phase of the synchronization alignment signal after the target object undergoes a state switch. This solves the problem of output signal phase change and timing disorder caused by the current solution of directly switching the target object's state, thereby improving circuit performance (e.g., effectively reducing DAC power consumption in TDD mode while ensuring no phase shift).

[0035] The state switching method of this disclosure can be executed by any electronic device, such as a terminal device or a server, that needs to achieve signal synchronization (i.e., phase alignment) after a state switch. The terminal device may include, but is not limited to, in-vehicle devices, user equipment (UE), mobile devices, computing devices, wearable devices, etc., such as, but not limited to, cellular phones, cordless phones, personal digital assistants (PDAs), and portable computers. The state switching method can be implemented by a processor calling computer-readable program instructions stored in memory, or it can be implemented by a server.

[0036] The embodiments disclosed herein can be applied to, but are not limited to, multi-clock-domain low-power circuit systems.

[0037] The embodiments of this disclosure will be described in detail below.

[0038] This invention overcomes the problem in related technologies where the phase uncertainty of the divided clock in time-division duplex (TDD) mode prevents the divided clock from being turned off to further reduce power consumption. It provides a method that automatically sends a reset signal to the clock divider circuit in TDD mode to ensure that there is no phase shift in the divided clocks for different working time slots in TDD mode. The main inventive points are as follows: To resolve the contradiction between the uncertainty of the start time of the normal working time slot and the certainty of the divided clock phase required after clock recovery in TDD mode, it is necessary to save the phase information of the reset signal during DAC initialization. This invention resets the divided circuit using the reset signal during initialization, storing the reset signal on the phase of the divided clock output. Then, a divided clock with a specific phase is used to sample the transmitter's working time slot start signal to obtain a time slot start signal with a determined phase. Finally, this signal is used to generate a reset signal, which is reused to reset the divided circuit, resulting in a divided clock with the same phase as during DAC initialization. By using the above method, when the system is operating in TDD mode, the frequency divider clock can be turned off during the receiver's operating time slot. After switching to the transmitter's operating time slot, a reset signal is automatically sent to the frequency divider, ensuring that the clock and data phase relationship of the switch driver, serializer, and decoder does not change. This effectively reduces DAC power consumption in TDD mode while ensuring that no phase shift problem occurs.

[0039] This disclosure provides a state switching method, such as... Figure 3 As shown, the method may include steps S11-S14:

[0040] S11. When the preset state switching conditions are met, generate and maintain a state switching signal;

[0041] S12. Use a state switching signal to switch the state of the target object;

[0042] S13. Calculate the time interval between the current time and the end time of the synchronization alignment signal; the synchronization alignment signal is a signal applied to the target object earlier than the state switching signal;

[0043] S14. When the time interval meets the preset conditions, the state switching signal ends and the state switching of the target object is completed; the preset conditions include: the time interval is an even multiple of the first clock cycle, and the first clock cycle is the clock cycle of the target object's output signal.

[0044] In this embodiment of the disclosure, the output signal of the target object can be a frequency-divided signal of the reference clock synchronization signal.

[0045] In the embodiments of this disclosure, the aforementioned state switching may include, but is not limited to, resetting the circuit and / or device, changing the circuit and / or device from sleep mode to working mode (i.e., waking up the circuit and / or device in sleep mode), etc. In different application scenarios, the state switching operation may be different, and the detailed operation of state switching is not limited here.

[0046] In this embodiment of the disclosure, the state switching conditions may include, but are not limited to: receiving state switching indication information of the target object, and / or reaching a preset state switching period.

[0047] In this embodiment of the disclosure, the state switching condition may be a received indication, such as receiving a state switching indication sent by the control system to switch the state of the target object; or it may be a set clock information for automatic state switching, such as a set state switching period, which automatically generates and maintains a state switching signal when the state switching period is reached.

[0048] In this embodiment of the disclosure, the state switching conditions, the state switching indication information, and the state switching period may vary in different application scenarios, and no specific limitations are imposed on the detailed conditions. For example, in a scenario where the frequency divider is automatically woken up from sleep mode in TDD mode of a DAC, the state switching indication information may include: wake-up indication information of the target object (such as the frequency divider); the state switching period may include: the sleep mode wake-up period.

[0049] In this embodiment of the disclosure, the synchronization alignment signal can be a synchronization signal implemented on the target object at any time for phase alignment of the target object. For example, it can include, but is not limited to, the synchronization signal when the target object is first powered on (i.e., during initialization), or the synchronization signal implemented on the target object according to any preset synchronization period.

[0050] In this disclosure, the target object can be any electronic device that requires signal synchronization (i.e., phase alignment), including, but not limited to, a divider.

[0051] In this embodiment of the disclosure, the first clock cycle is the clock cycle of the target object output signal. When the target object is a frequency divider, the target object output signal is a frequency-divided signal of the reference clock synchronization signal. The first clock cycle may include, but is not limited to, a frequency-divided clock cycle, a frequency-divided clock cycle, a frequency-divided clock cycle, a frequency-divided clock cycle, ... and the first clock cycle can be the clock cycle of any frequency-divided signal.

[0052] In this embodiment, the target object, state switching signal, synchronization alignment signal, etc., can all be different signals depending on the application scenario, and no specific signal is limited here. For example, in a scenario where the frequency divider is automatically woken up from sleep mode in TDD mode of a DAC, the target object includes the frequency divider, and the state switching signal may include: a first reset signal for waking up the frequency divider; the synchronization alignment signal may include: a second reset signal for phase alignment of the frequency divider output frequency signal.

[0053] In this embodiment of the disclosure, the following describes the scheme of this embodiment, taking the target object as a frequency divider and the first clock period of the output signal of the frequency divider as a divided clock period.

[0054] In the embodiments disclosed herein, such as Figure 4 The diagram shows a schematic of a four-phase divider; the divider includes four high-level triggered latches (e.g., latch1, latch2, latch3, and latch4) and two inverters (e.g., F1 and F2), as shown. Figure 5 As shown, Figure 4 The timing diagram of the frequency divider is shown below. The following is based on... Figure 4 and Figure 5 The problems raised by the embodiments of this disclosure are analyzed.

[0055] In this embodiment of the disclosure, it is assumed that the divider is in a state where it is woken up from sleep mode by a reset signal. At this time, a reset signal reset_0 (high level) is applied to the divider, which can be labeled as reset1, reset2, reset3, and reset4 on latch1, latch2, latch3, and latch4, respectively. The reset signal reset1 of latch1 and the reset signal reset2 of latch2 are both high level. When latch1 and latch2 are reset by the reset signals reset1 and reset2 (for example, when they are woken up from sleep mode), the output signals of latch1 and latch2 are also reset to high level, that is, the output signal clk_div1_0 of latch1 and the output signal clk_div2_0 of latch2 are both high level. When both the reset signals reset3 and reset4 of latch3 and latch4 are low, the output signals of latch3 and latch4 will also be reset to low level when latch3 and latch4 are reset by reset signals reset3 and reset4, respectively. That is, the output signals clk_div3_0 of latch3 and clk_div4_0 of latch4 are both low level.

[0056] In the embodiments disclosed herein, such as Figure 5As shown, during the existence of the reset signal reset_0, the outputs of each latch (latch1, latch2, latch3, and latch4) are reset to the aforementioned level values ​​(clk_div1_0 and clk_div2_0 are high, clk_div3_0 and clk_div4_0 are low). At the end of the reset signal reset_0, latch1 and latch3 are exactly in the high-level period of the clock signal clk (as shown in period t1). Based on the principle of latches, when latch1 and latch3 input a high-level clock signal clk, the input ports D1 and D2 of latch1 and latch3 will sample the output ports Q4 and Q2 of the connected latches latch4 and latch2, respectively, and the output ports Q1 and Q3 of latch1 and latch3 will output the sampling results. At this point, since the reset signal reset4 is low, the output signal clk_div4_0 of latch4 is low, i.e., clk_div4_0 = 0. Therefore, the sampled value D1 obtained by latch1 from Q4 is 0, which makes the output signal clk_div1_0 of Q1 = 0. Similarly, since the reset signal reset2 is high, the output signal clk_div2_0 of latch2 is high, i.e., clk_div2_0 = 1. Therefore, the sampled value D3 obtained by latch3 from Q2 is 1, which makes the output signal clk_div3_0 of Q3 = 1. Since the clock signals clk of latch2 and latch4 are out of phase with those of latch1 and latch3, based on the latch principle, when the clock signals clk of latch2 and latch4 are low, latch2 and latch4 are in a latched state. Therefore, latch2 and latch4 latch the previous output signals (i.e., the levels of reset signals reset2 and reset4), i.e., clk_div2_0 = 1, clk_div4_0 = 0. The output level remains the same as the levels of reset signals reset2 and reset4. Therefore, after the reset signal reset_0 (high level) ends, the output signal levels of clk_div1_0 and clk_div3_0 flip to low level (clk_div1_0 = 0) and high level (clk_div3_0 = 1), respectively, as shown below. Figure 5 The timing sequence corresponding to clk_div1_0 and clk_div3_0 in segment t1 is shown.

[0057] In this embodiment of the disclosure, the clock signal clk then enters a low level (as shown in time period t2). Due to the presence of inverters F1 and F2, latch2 and latch4 are now input with a high-level clock signal clk. Based on the principle of latches, the input ports D2 and D4 of latch2 and latch4 will sample the output ports Q1 and Q3 of the connected latches latch1 and latch3, respectively, and the output ports Q2 and Q4 of latch2 and latch4 will output the sampling results. Given that latches are based on the principle of latches, latches 1 and 3 are currently in a latched state with a low-level clock signal clk input. Therefore, latches 1 and 3 latch the previous output signal, i.e., Q1 = clk_div1_0 = 0 and Q3 = clk_div3_0 = 1. Thus, the input port D2 of latch 2 samples D2 = Q1 = clk_div1_0 = 0, and the input port D4 of latch 4 samples D4 = Q3 = clk_div3_0 = 1. Therefore, the output ports Q2 and Q4 of latches 2 and 4 respectively output the sampling results: Q2 = D2 = Q1 = clk_div1_0 = 0 and Q4 = D4 = Q3 = clk_div3_0 = 1. Therefore, the output levels of latches 2 and 4 have also flipped. At this point, the output levels of all latches (latch 1, latch 2, latch 3, and latch 4) have flipped, and... Figure 5 It can be seen that the first clock cycle of the output signal of each latch is twice the clock signal clk, and the output signal of each latch is out of phase with the output signal of the previous latch, thus realizing the function of four-phase frequency division.

[0058] In this embodiment of the disclosure, based on the above analysis, it can be assumed that the following two reset signals are input to the divider (both are assumed to be high level, but with different phases): the falling edge of the clock signal clk input to the divider is used as the boundary (e.g. Figure 5 As shown at the falling edge of the dashed line b in the clock signal clk, the reset signal can be divided into two phases. The period to the left of the dashed line b, not exceeding the next falling edge, can be considered as reset signal phase zero (Reset phase 0), and the period to the right of the dashed line, not exceeding the next falling edge, can be considered as reset signal phase one (Reset phase 1). During the high-level period of the clock signal clk, the reset signal phase zero (Reset phase 0) has ended, and the output signal levels of latches latch1 (clk_div1_0) and latch3 (clk_div3_0) have both flipped (corresponding to the attached diagram). Figure 5As shown in curve ① (as in time period t1), latch1 (clk_div1_0) flips from the high level given by the initial reset signal to a low level, i.e., clk_div1_0 = 0; latch3 (clk_div3_0) flips from the low level given by the initial reset signal to a high level, i.e., clk_div3_0 = 1; latch2 and latch4 both output the reset level value. Here, we only take the output signal of latch1 as an example for comparison, recording the output clk_div1_0 = 0 when the reset signal phase 0 is applied to the divider.

[0059] In this embodiment of the disclosure, when a reset signal phase 1 is applied to the divider, the reset signal phase 1 starts from the low level of the clock signal clk and continues until the high level ends (i.e., at position c). Similarly, latch 1 and latch 3 will also toggle at the high level of the clock signal clk (corresponding to the attached diagram). Figure 5 As shown in curve ②, during the first phase of the reset signal (Reset phase 1), the clock signal clk reaches a high level. Latch 1 also samples the output of latch 4, and the output of latch 4 is the level of the reset signal reset 4 (low level). Therefore, the output of latch 1 is also clk_div1_1 = 0 (corresponding to the attached curve ②). Figure 5 (As shown in curve ②).

[0060] In this embodiment, since a reset signal phase zero (Reset phase 0) has been applied during time period A, it can be seen from region d that, based on the applied reset signal phase zero (Reset phase 0), the output signal of latch 1 should be high, i.e., clk_div1_0 = 1. However, after a reset signal phase one (Reset phase 1) is applied again during time period B, the output signal of latch 1 becomes low, i.e., clk_div1_1 = 0. Therefore, for latch 1, the output clk_div1_0 when the reset signal phase zero (Reset phase 0) is applied is exactly opposite to the output clk_div1_1 when the reset signal phase one (Reset phase 1) is applied. This will inevitably cause timing disorder in the circuit. If there is one falling edge between the two reset end positions (phase 1), for example, falling edge b, i.e., an odd number of falling edges, then we can summarize that if there is an odd number of falling edges between the end positions of two adjacent reset signals, the output signals of the same latch will be out of phase. Since for a divide-by-two frequency divider, a falling edge of the clock signal clk represents one divide-by-two clock cycle, if the time interval between the end times of two adjacent reset signals is an odd number of divide-by-two clock cycles, the output signals of the divide-by-two frequency divider will be out of phase. Conversely, if the time interval between the end times of two adjacent reset signals is an even number of divide-by-two clock cycles, the output signals of the divide-by-two frequency divider will be in phase.

[0061] In this embodiment, as summarized above, to ensure that the clock period phase of the output signal of the frequency divider is the same when it is reset multiple times, it is necessary to ensure that the time interval between the end times of any two adjacent reset signals is 2*k*T, where k is a positive integer and T is the clock period of the frequency divider signal. This scheme can be applied to any scenario where multiple reset signals are applied to any frequency divider with a frequency divider of 2, and can be extended to scenarios where multiple reset signals are applied to frequency dividers with any frequency divider such as 4, 6, or 8. The difference is that T in the time interval 2*k*T between the end times of any two adjacent reset signals is different for different frequency divider signals. If it is a 4-frequency divider, then T is the clock period of the 4-frequency divider signal; if it is a 6-frequency divider, then T is the clock period of the 6-frequency divider signal; and so on. It can be seen that T is the clock period of the frequency divider output signal, that is, the aforementioned first clock period, that is, the time interval between the end times of any two adjacent reset signals is an even multiple of the first clock period.

[0062] In this embodiment of the disclosure, when there is only one target object and the target object generates one output signal, the even multiple is any even multiple of the first clock cycle;

[0063] When there are one or more target objects, m output signals generated by the target objects, and n types of first clock cycles, the even multiple is any even multiple of the second clock cycle; the second clock cycle is the clock cycle corresponding to the least common multiple of the frequency division numbers corresponding to the n first clock cycles; m and n are positive integers greater than 1, and m is greater than or equal to n.

[0064] In this embodiment of the disclosure, the target object is still a frequency divider as an example. If there is only one frequency divider to be reset, and the frequency divider only generates one type of frequency division signal, such as a frequency division signal of four, then when two adjacent reset signals reset the frequency divider, in order to ensure that the phase of the frequency division signal output by the frequency divider remains unchanged, the time interval between the end times of the two reset signals needs to be any even multiple of the clock period of the frequency division signal of four, such as 2 times, 4 times, 6 times, etc.

[0065] In this embodiment of the disclosure, if there is only one frequency divider to be reset, and the frequency divider generates multiple frequency division signals, such as frequency division signals of 4 and 6, then when the frequency divider is reset by two adjacent reset signals, in order to ensure that the phase of each frequency division signal output by the frequency divider remains unchanged, the time interval between the end times of the two reset signals must be an even multiple of the clock period of the frequency division signal of 4 and an even multiple of the clock period of the frequency division signal of 6. In order to satisfy this condition, the time interval is set to any even multiple of the clock period of the frequency division signal (i.e., the frequency division signal of 12), which is the least common multiple of the frequency division signal of 4 and 6.

[0066] In this embodiment of the disclosure, if there are multiple frequency dividers to be reset, and each frequency divider generates a different frequency division signal, when using a single reset signal to reset multiple frequency dividers, the time interval between the end times of two adjacent reset signals needs to be set to any even multiple of the clock period corresponding to the least common multiple of the various frequency division signals. For example, if two frequency dividers generate frequency division signals of 4 and 8 respectively, then the time interval is set to any even multiple of the clock period of the frequency division signal (i.e., the 8-frequency division signal), which is the least common multiple of the frequency division signal of 4 and 8.

[0067] In the embodiments of this disclosure, the above-described solutions enable the solutions to be applied to various scenarios, thus expanding the scope of application of the solutions.

[0068] In this embodiment of the disclosure, before calculating the time interval between the current time and the end time of the synchronization alignment signal applied to the target object, the method may further include:

[0069] Receive synchronization alignment signal;

[0070] Starting from the end of the synchronization alignment signal, a synchronization phase signal is continuously generated;

[0071] The clock period of the synchronization phase signal is used to calculate the time interval; the clock period of the synchronization phase signal is either the first clock period or the second clock period; the time interval is an even multiple of the clock period of the synchronization phase signal.

[0072] In this embodiment of the disclosure, the state switching signal can be regarded as reset signal 1, and the synchronization alignment signal can be regarded as reset signal 2. Since the synchronization alignment signal is a standard synchronization signal used to phase align the output signal of the target object, in order to ensure that the output signal of the target object is still phase aligned when the target object is switched in any subsequent state (e.g., waking up the target object), the synchronization alignment signal (i.e., reset signal 2) can be saved, especially the end time of reset signal 2. For example, timing can be started at the end time of reset signal 2. The clock period used for timing can be the same as the clock period of the target object's output signal, that is, the same as the first clock period. For example, if the target object outputs a frequency divider signal, the clock period for timing is also the clock period of the frequency divider signal. If the target object outputs a frequency divider signal, the clock period for timing is also the clock period of the frequency divider signal. Similarly, if the signal output by the target object is a multi-frequency divided signal, such as a 2-division signal, a 6-division signal, and an 8-division signal, then the clock period for timing is the clock period of the 24-division signal, which is the least common multiple of the division numbers of the 2-division, 6-division, and 8-division signals (the least common multiple of 2, 6, and 8 is 24).

[0073] In this embodiment of the disclosure, the timing can be implemented by a frequency divider. That is, after receiving the synchronization alignment signal, the frequency divider starts working from the end time of the synchronization alignment signal and continuously generates a frequency division signal (such as the 24-division frequency division signal mentioned above) as a synchronization phase signal.

[0074] In this embodiment of the disclosure, when determining the time interval based on the synchronization phase signal, since the clock period of the synchronization phase signal is either the first clock period or the second clock period, the time interval can be determined directly by an even multiple of the clock period of the synchronization phase signal. That is, it is determined by counting whether the time interval between the current time and the end time of the synchronization alignment signal is an even multiple of the clock period of the synchronization phase signal.

[0075] In this embodiment of the disclosure, based on the above embodiment scheme, by generating a synchronous phase signal and determining the time interval according to the clock period of the synchronous phase signal, the accuracy of the end time of the reset signal 1 is ensured.

[0076] This disclosure also provides a state switching device 100, such as... Figure 6 As shown, it may include: a state switching unit 101; the state switching unit 101 is configured to implement the state switching method described above.

[0077] In this embodiment of the disclosure, the state switching unit 101 may include: a synchronization phase storage circuit 1011 and a state switching signal generation circuit 1012;

[0078] The state switching signal generation circuit 1012 is configured to generate and maintain a state switching signal when a preset state switching condition is met.

[0079] The state switching signal generation circuit 1012 is also configured to use the state switching signal to switch the state of the target object 200.

[0080] The synchronization phase storage circuit 1011 counts the time interval between the current time and the end time of the synchronization alignment signal; the synchronization alignment signal is a signal applied to the target object earlier than the state switching signal.

[0081] The state switching signal generation circuit 1012 is further configured to end the state switching signal and complete the state switching of the target object 200 when the time interval meets a preset condition; the preset condition may include, but is not limited to: the time interval is an even multiple of the first clock cycle, and the first clock cycle is the clock cycle of the output signal of the target object 200.

[0082] In this embodiment of the present disclosure, the signal output terminal of the synchronization phase preservation circuit 1011 is connected to the first signal input terminal of the state switching signal generation circuit 1012;

[0083] The signal output terminal of the state switching signal generation circuit 1012 is connected to the signal input terminal of the target object 200.

[0084] In the embodiments disclosed herein, such as Figure 7As shown, the target object 200 may include, but is not limited to, a divider. For example, the divider may generate an X1 divider for the decoder, an X2 divider for the serializer, and an X3 divider for the switch driver. The divider may include a first divider corresponding to the decoder (for generating the X1 divider), a second divider corresponding to the serializer (for generating the X2 divider), and a third divider corresponding to the switch driver (for generating the X3 divider); or, the divider may generate multiple dividers: X1 divider, X2 divider, X3 divider, etc. The divider is connected to a state switching unit 101, which enables synchronization of multiple divided signals (X1 divider, X2 divider, X3 divider).

[0085] In the embodiments disclosed herein, such as Figure 8 As shown, the frequency divider Divider, which is the target object 200, can also be a frequency divider that only generates one type of frequency division signal. For example, it can be only the first frequency divider Divider-1 mentioned above, which is connected to a first state switching unit 101-1, and the frequency division signal (X1 frequency division) of the first frequency divider Divider-1 is synchronized through the first state switching unit 101-1; or it can be only the second frequency divider Divider-2 mentioned above, which generates only one type of frequency division signal. Divider-2 is connected to a second state switching unit 101-2, which synchronizes the frequency division signal (X2 division) of the second frequency divider Divider-2. Alternatively, it can be only the aforementioned third frequency divider Divider-3, which is connected to a third state switching unit 101-3, which synchronizes the frequency division signal (X3 division) of the third frequency divider Divider-3. The state switching unit 101 includes the aforementioned first state switching unit 101-1, second state switching unit 101-2, and third state switching unit 101-3. Each of the first, second, and third state switching units 101-1 and 101-2 includes a synchronization phase storage circuit 1011 and a state switching signal generation circuit 1012.

[0086] In this embodiment, the synchronization phase preservation circuit 1011 is in a continuous working state. When the target object 200 needs to switch states, the state switching signal generation circuit 1012 can generate a state switching signal (which can be regarded as a first reset signal, such as the aforementioned reset signal 1), apply the state switching signal to the target object 200, and obtain the time interval calculated by the synchronization phase preservation circuit 1011 based on its own clock cycle. This time interval can refer to the duration between the end time of the synchronization alignment signal applied to the target object 200 when the target object 200 was last aligned with the signal phase and the end time of the state switching signal. This time interval needs to satisfy: it is an even multiple of the first clock cycle of the target object 200 output signal to ensure that the phase of the output signal of the target object 200 remains unchanged after the state switch, that is, to maintain synchronization. In order to ensure that the target object 200 can achieve signal synchronization after a state switch (e.g., waking up the target object 200, switching the target object 200 from sleep mode to working mode, for example, waking it up through a sleepstop signal), the time interval is counted, and the state switch signal ends when the time interval is an even multiple of the first clock cycle, thus completing the state switch of the target object 200.

[0087] In this embodiment of the disclosure, when the state switching condition includes state switching indication information of the target object, the state switching signal generation circuit 1012 further includes: a second signal input terminal;

[0088] The second signal input terminal is configured as an input terminal for state switching indication information.

[0089] In this embodiment of the disclosure, the target object 200 can switch states through external state switching indication information (wake-up signal Sleepstop signal). The state switching signal generation circuit 1012 receives the state switching indication information through the second signal input terminal and generates a state switching signal according to the state switching indication information.

[0090] In this embodiment of the disclosure, the target object 200 can also switch states according to a preset state switching cycle. The state switching signal generation circuit 1012 receives the output signal of the synchronization phase preservation circuit 1011 through the first signal input terminal, calculates the duration according to the clock cycle of the output signal, and generates a state switching signal when the calculated duration reaches the state switching cycle.

[0091] In this embodiment of the disclosure, after generating a state switching signal and applying it to the target object 200, the time interval can be counted, and if the time interval is an even multiple of the first clock cycle, the state switching signal is terminated, and the state switching of the target object 200 is completed.

[0092] In this embodiment of the disclosure, after the state transition of the target object 200 is completed, as follows: Figure 7 and Figure 8 The output signals of the decoder, serializer, switch driver, and synchronization phase preservation circuit 1011 (equivalent to a frequency divider) shown are all synchronized.

[0093] In the embodiments disclosed herein, such as Figure 9 As shown, the embodiment of this disclosure is illustrated using the example of a frequency divider that automatically resets in time-division duplex mode (changing from sleep mode to operating mode). In this case, the synchronization phase preservation circuit 1011 also uses frequency division. Figure 9 Curve ③ in the middle represents the synchronization alignment signal (also known as the reset signal, which is used for synchronization alignment, for example, the reset signal DAC Sync Pulse, which can be simply represented as reset-1) synchronizing with the target object 200 (the frequency divider circuit). After this synchronization alignment, the output clock of the target object 200 begins to synchronize. At this time, the synchronization phase preservation circuit 1011 receives the synchronization alignment signal and begins to work, continuously generating state switching signals (such as...). Figure 9 The signal syncphase saved in the image is also a divide-by-two signal. It can store the inverted div2 clock output corresponding to this state switching signal, such as... Figure 9 Curve ④ in the middle indicates that the falling edge of the synchronization alignment signal is stored at the rising edge of the inverted div2 clk output clock after synchronization alignment (that is, the state switching signal generated by the synchronization phase storage circuit 1011 can be aligned with the synchronization alignment signal according to the rising edge of the inverted div2 clk output clock, thus officially starting the clock cycle of the divide-by-two signal and continuously generating the divide-by-two signal). Figure 9 As shown in curve ⑤, the rising edge of the inverted div2 clk output clock and the falling edge of the state switching signal (which can be regarded as another reset signal, as shown by the auto reset signal) are 2*k*T apart, where k is a positive integer and T is the 2-division clock period of the divider.

[0094] In this embodiment of the disclosure, in the state switching signal generation circuit 1012 (also known as the Sync Pulse Auto Gen circuit), a divided-2 inverted output clock (inverted div2 clk) is used to sample the rising edge of the sleep stop signal (end of transmitter sleep mode) and obtain a state switching signal (also known as a reset signal, such as reset-2 in the auto reset signal) with a falling edge interval of 2*k*T from the synchronization alignment signal (reset-1), as shown in the attached figure. Figure 9 As shown in curve ⑥, a state transition signal (reset-2) is automatically generated whenever a state transition indication signal (e.g., the sleepstop signal) rises. The end time of this state transition signal (reset-2), or its falling edge, is 2*k*T apart from the synchronization alignment signal (reset-1). This ensures that the divide-2 clock (div2 clk with sleep mode), which automatically resets after sleep mode, achieves signal synchronization after the state transition signal (reset-2) is used for state transition (e.g., reset). The dashed line d in the sleepstop signal indicates that after detecting the sleepstop signal (e.g., detecting its rising edge), the state transition signal (reset-2) does not need to be generated immediately; it can be generated within a preset time period after the rising edge of the sleepstop signal is detected.

[0095] In this embodiment of the disclosure, by means of appendix Figure 9 It is known that the divide-by-two clock (div2 clk with sleep mode) that automatically resets after sleep mode has the same phase as the divide-by-two clock (div2 clk without sleep mode) that does not enter sleep mode. Therefore, by saving the phase of the synchronization alignment signal (e.g., saving the falling edge of the end of the synchronization alignment signal) and automatically resetting the divider according to the time interval that meets the preset conditions after the sleep mode ends, the goal of turning off the clock divider circuit in TDD mode to reduce power consumption and keeping the clock phase relationship of each clock domain unchanged is achieved.

[0096] In the embodiments disclosed herein, such as Figure 10 As shown, the state switching device 100 may further include: a synchronization alignment signal generation circuit 102;

[0097] The signal input terminal of the synchronization alignment signal generation circuit 102 is the reference clock synchronization signal input terminal; the first clock period can be obtained by dividing the clock period of the reference clock synchronization signal.

[0098] The signal output terminal of the synchronization alignment signal generation circuit 102 is connected to the signal input terminal of the target object 200 and / or to the signal input terminal of the synchronization phase storage circuit 1011.

[0099] The synchronization alignment signal generation circuit 102 is configured to generate a synchronization alignment signal.

[0100] In this embodiment of the disclosure, the synchronization alignment signal generation circuit 102 can act as a clock and synchronization signal receiver to receive clock and synchronization signals from the PLL (phase-locked loop), such as... Figure 9 The clock signal clk to dac and the synchronization signal sync to dac are shown. These two signals can be transmitted to the synchronization alignment signal generation circuit 102 (e.g., the synchronization alignment signal generation circuit 102 can be an initialization synchronization pulse generation module Initial Sync Pulse Generator, used to generate an initial reset signal during initialization, which can serve as the synchronization alignment signal), generating a reset pulse, such as... Figure 9 The reset signal dac sync pulse shown is the same as the reset-1 signal mentioned above, where curve ⑦ represents the clock edge that generates the reset pulse.

[0101] In this embodiment of the disclosure, when the signal output terminal of the synchronization alignment signal generation circuit 102 is connected to the signal input terminal of the target object and the signal input terminal of the synchronization phase preservation circuit 1011:

[0102] The synchronization alignment signal generation circuit 102 is further configured to apply a synchronization alignment signal to the target object 200 to perform phase synchronization of the first clock cycle of the target object 200;

[0103] The synchronization phase storage circuit 1011 is also configured to receive a synchronization alignment signal and continuously generate a synchronization phase signal synchronized with the synchronization alignment signal starting from the end time of the synchronization alignment signal; the clock period of the synchronization phase signal is either a first clock period or a second clock period; the second clock period is the clock period corresponding to the least common multiple of the n frequency division numbers corresponding to the first clock period; n is a positive integer greater than 1.

[0104] In this embodiment of the disclosure, the synchronization alignment signal generation circuit 102 can be connected to the target object 200 only during power-on initialization to perform signal alignment on the target object 200, and is also connected to the synchronization phase storage circuit 1011. When the target object 200 subsequently needs to perform signal synchronization due to state switching, signal synchronization can be performed solely through the state switching unit 101.

[0105] In this embodiment, the synchronization alignment signal generation circuit 102 may be connected only to the synchronization phase storage circuit 1011. After the synchronization alignment signal is generated at any time to trigger the synchronization phase storage circuit 1011 to start working, when the target object 200 needs to synchronize signals during a state switch, the output signal of the target object 200 can be synchronized through the state switching unit 101. The synchronization alignment signal has the same signal phase as the output signal of the target object 200.

[0106] In the embodiments disclosed herein, such as Figure 8 As shown, in the case where a state switching unit 101 is connected to a target object 200, and the target object 200 generates an output signal:

[0107] The state switching signal generation circuit 1012 is also configured to terminate the state switching signal and complete the state switching of the target object when the time interval is any even multiple of the first clock cycle.

[0108] In this embodiment of the disclosure, if there is only one target object 200, for example, only one frequency divider, and only one type of frequency division signal is generated, such as a frequency divider of two or a frequency divider of four, a state switching unit 101 can be set for the target object 200. The clock period of the synchronous phase preservation circuit 1011 in the state switching unit 101 is also the clock period of the output signal of the target object 200 (i.e., the first clock period).

[0109] In the embodiments disclosed herein, such as Figure 7 As shown, in the case where a state switching unit 101 is connected to one or more target objects 200, and the target objects 200 generate m output signals, and the first clock cycle has n possible values:

[0110] The state switching signal generation circuit 1012 is further configured to end the state switching signal and complete the state switching of the target object when the time interval is any even multiple of the second clock cycle; the second clock cycle is the clock cycle corresponding to the least common multiple of the n frequency division numbers corresponding to the first clock cycle; m is a positive integer greater than 1, and m is greater than or equal to n.

[0111] In this embodiment, if there is only one target object 200 but it generates multiple frequency division signals, or if there are multiple target objects 200 (e.g., m objects) and these multiple target objects 200 generate multiple different frequency division signals (e.g., n types), then if signal synchronization is performed using only one state switching unit 101, the clock period of the synchronization phase storage circuit 1011 in the state switching unit 101 needs to be the clock period corresponding to the least common multiple of the n frequency divisions of the target object 200's output signal (i.e., the second clock period). For example, if the target object 200 outputs four frequency division signals, such as a 2-division signal, a 4-division signal, a 6-division signal, and an 8-division signal, then the clock period of the synchronization phase storage circuit 1011 is the 24-division signal (where 24 is the least common multiple of 2, 4, 6, and 8).

[0112] In this embodiment of the present disclosure, a synchronization alignment signal can be generated after the system is powered on. When synchronizing the devices in the system (including the target object 200) for the first time, the reset pulse in the synchronization alignment signal resets the frequency divider (target object 200), so that the clocks of different frequencies have clear synchronization phase information, and the synchronization phase information is stored at the edge of the frequency divider clock (i.e., when the edge of the reset pulse is detected, for example, the falling edge, the synchronization phase storage circuit 1011 is started to generate a frequency divider signal with the same clock period as the output signal of the frequency divider). During the receiver's working time slot, the transmitter enters a sleep state and shuts down the internal frequency divider of the DAC and its application circuits. During the transmitter's normal working time slot, the DAC sleep state ends, and the state switching signal generation circuit 1012 samples the frequency divider signal generated by the synchronization phase storage circuit 1011 and regenerates a synchronization pulse (i.e., the state switching signal) to reset the frequency divider circuit. The phase of the frequency divider after reset is the same as the phase at initialization, so it remains unchanged from the clock phase of other clock domains. Through the above process, the time-division duplex mode can turn off the frequency divider to reduce power consumption, while ensuring that the clock phase relationship of each clock domain does not change.

[0113] This disclosure also provides an electronic device 300, such as... Figure 11 As shown, it includes the aforementioned state switching device 100.

[0114] In embodiments of this disclosure, the electronic device may include, but is not limited to, a digital-to-analog converter (DAC).

[0115] In this embodiment of the disclosure, the solution can be used in, but is not limited to, TDD mode, and can also be used in other scenarios where circuit state switching requires synchronization.

[0116] The solutions disclosed herein can be used in, but are not limited to, DAC circuits, and can also be used in other circuits that require synchronization.

[0117] The solutions disclosed herein can be used in, but are not limited to, frequency division circuits (e.g., including but not limited to, frequency divider circuits, frequency divider circuits, frequency divider circuits, frequency divider circuits, etc.), and can also be used in other circuits that require signal synchronization or reset.

[0118] The synchronization alignment signal in the embodiments of this disclosure may include, but is not limited to, an initialization reset signal, and may be a signal used for phase alignment at any time.

[0119] The method for saving the phase information of the synchronization alignment signal in the embodiments of this disclosure can have various variations. It can use a four-phase frequency divider circuit or other signals that retain synchronization phase information. All circuits that require synchronization phase can save the synchronization phase information.

[0120] The automatic transmission method for synchronization alignment signals in the embodiments of this disclosure can have various variations. It can be implemented in conjunction with the synchronization alignment signal generation circuit 102, or in conjunction with other circuits that transmit determined phase or fixed phase data information, or in conjunction with other external input signals or signals generated internally by the circuit.

[0121] The arbitrary frequency division signal generation circuit of the present disclosure embodiment can have various variations. It can use, but is not limited to, frequency dividers and shift registers. The frequency divider generates a frequency-divided clock, and then the undivided clock is used to serially sample the frequency-divided clock to obtain a multi-phase multi-frequency-divided clock. If there is no need for multiple phases, a single flip-flop can be used directly for output. The present disclosure embodiment can be extended to the generation circuit of arbitrary phase arbitrary frequency-divided clock.

[0122] The embodiment of this disclosure uses a synchronization alignment signal and synchronous timing logic to generate a reset pulse (synchronization alignment pulse) to reset the clocks of different clock domains. The phase information of the synchronization alignment signal is stored through a frequency division circuit (e.g., synchronization phase storage circuit 1011). In TDD mode, a reset pulse (i.e., state switching signal) is automatically generated to reset the frequency division clock with uncertain phase, so that the clock phase relationship of each clock domain is determined. This ensures that the phase relationship between the serializer data and the switch driver clock is determined, avoiding the problem of mis-beats or metastability caused by clock phase changes. Through the above scheme, the shutdown and automatic reset of the switch driver circuit are realized.

[0123] Those skilled in the art will understand that all or some of the functional modules / units disclosed above can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0124] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be executed by several physical components working together.

[0125] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technique for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; read-only optical disc (CD-ROM), digital versatile disc (DVD) or other optical disc storage; magnetic cartridges, magnetic tapes, disk storage or other magnetic storage; and any other media that can be used to store desired information and can be accessed by a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0126] This disclosure has disclosed exemplary embodiments, and although specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A state switching method characterized by comprising: The method includes: When the preset state switching conditions are met, a state switching signal is generated and maintained. The state switching signal is used to switch the state of the target object; The time interval between the current moment and the end moment of the synchronization alignment signal is calculated; the synchronization alignment signal is a signal applied to the target object earlier than the state switching signal. When the time interval meets a preset condition, the state switching signal ends, and the state switching of the target object is completed; the preset condition includes: the time interval is an even multiple of the first clock cycle, and the first clock cycle is the clock cycle of the output signal of the target object.

2. The state switching method according to claim 1, characterized in that, When there is only one target object and the target object generates one output signal, the even multiple is any even multiple of the first clock cycle; When there are one or more target objects, the target objects generate m output signals, and there are n types of first clock cycles, the even multiple is any even multiple of the second clock cycle; the second clock cycle is the clock cycle corresponding to the least common multiple of the n types of frequency division numbers corresponding to the first clock cycle; m and n are positive integers greater than 1, and m is greater than or equal to n.

3. The state transition method according to claim 2, characterized by, Before calculating the time interval between the current moment and the end moment of the synchronization alignment signal applied to the target object, the method further includes: Receive the synchronization alignment signal; Starting from the end time of the synchronization alignment signal, a synchronization phase signal is continuously generated; Wherein, the clock period of the synchronization phase signal is used to calculate the time interval; the clock period of the synchronization phase signal is either the first clock period or the second clock period; the time interval is an even multiple of the clock period of the synchronization phase signal.

4. The state transition method according to any one of claims 1 to 3, characterized by, The state switching conditions include: receiving state switching indication information of the target object, and / or reaching a preset state switching cycle.

5. The state switching method according to claim 4, characterized in that, The state switching indication information includes: the wake-up indication information of the target object; The state switching cycle includes: a sleep mode wake-up cycle; The state switching signal includes: a first reset signal for waking up the target object; The synchronization alignment signal includes a second reset signal for aligning the phase of the frequency division signal output by the target object.

6. A state switching device characterized by comprising: include: A state switching unit; the state switching unit is configured to implement the state switching method according to any one of claims 1-5.

7. The state switching apparatus according to claim 6, wherein The state switching unit includes: a synchronous phase storage circuit and a state switching signal generation circuit; The state switching signal generation circuit is configured to generate and maintain a state switching signal when a preset state switching condition is met. The state switching signal generation circuit is further configured to use the state switching signal to switch the state of the target object; The synchronization phase preservation circuit counts the time interval between the current time and the end time of the synchronization alignment signal; the synchronization alignment signal is a signal applied to the target object earlier than the state switching signal. The state switching signal generation circuit is further configured to terminate the state switching signal and complete the state switching of the target object when the time interval meets a preset condition; the preset condition includes: the time interval is an even multiple of a first clock cycle, and the first clock cycle is the clock cycle of the output signal of the target object.

8. The state switching device according to claim 7, characterized in that, The signal output terminal of the synchronous phase preservation circuit is connected to the first signal input terminal of the state switching signal generation circuit. The signal output terminal of the state switching signal generation circuit is connected to the signal input terminal of the target object.

9. The state switching apparatus according to claim 8, wherein When the state switching condition includes the state switching indication information of the target object, the state switching signal generation circuit further includes: a second signal input terminal; The second signal input terminal is configured as an input terminal for the state switching indication information.

10. The state switching device according to any one of claims 7-9, characterized in that, It also includes: a synchronization alignment signal generation circuit; The signal input terminal of the synchronization alignment signal generation circuit is the reference clock synchronization signal input terminal; the first clock period is obtained by dividing the clock period of the reference clock synchronization signal. The signal output terminal of the synchronization alignment signal generation circuit is connected to the signal input terminal of the target object and / or to the signal input terminal of the synchronization phase preservation circuit. The synchronization alignment signal generation circuit is configured to generate the synchronization alignment signal.

11. The state switching device according to claim 10, characterized in that, When the signal output terminal of the synchronization alignment signal generation circuit is connected to the signal input terminal of the target object and the signal input terminal of the synchronization phase preservation circuit: The synchronization alignment signal generation circuit is further configured to apply the synchronization alignment signal to the target object to perform phase synchronization of the first clock cycle of the target object; The synchronization phase preservation circuit is further configured to receive the synchronization alignment signal and continuously generate a synchronization phase signal synchronized with the synchronization alignment signal starting from the end time of the synchronization alignment signal; the clock period of the synchronization phase signal is either the first clock period or the second clock period; the second clock period is the clock period corresponding to the least common multiple of n frequency divisions corresponding to the first clock period; n is a positive integer greater than 1.

12. The state switching device according to claim 7, characterized in that, In the case where a state switching unit is connected to a target object, and the target object generates an output signal: The state switching signal generation circuit is further configured to terminate the state switching signal and complete the state switching of the target object when the time interval is any even multiple of the first clock cycle.

13. The state switching device according to claim 7, characterized in that, In the case where one or more target objects are connected to a state switching unit, and the target objects generate m output signals, and the first clock cycle has n possible values: The state switching signal generation circuit is further configured to terminate the state switching signal and complete the state switching of the target object when the time interval is any even multiple of the second clock cycle; the second clock cycle is the clock cycle corresponding to the least common multiple of the n frequency division numbers corresponding to the first clock cycle; m is a positive integer greater than 1, and m is greater than or equal to n.

14. An electronic device, characterized in that, Includes the state switching device as described in any one of claims 6-13.

15. The electronic device according to claim 14, characterized in that, The electronic device includes a digital-to-analog converter.

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