Loopback test method, device and system, electronic equipment, medium and program product

Abstract

The invention discloses a loopback test method, device and system, electronic equipment, a medium and a program product, and relates to the technical field of communication. The loopback test device is deployed on a processor which does not support loopback read-write of a register control transmitting end and a register control receiving end, and is used for testing the network quality of the processor. The loopback test device comprises a data cache module and a read-write control logic module. And the data caching module is connected with the segmented interface of the processor and the network communication module, and caches data packets transmitted and received through the network communication module and the segmented interface. And the read-write control logic module is connected with the data caching module, and can ensure that the last data packet is read and written from the data caching module according to the packet ending position of the data packet when the data caching module reaches a critical storage threshold condition. According to the method and the device, the problem that the control logic is complicated when the MAC test is carried out on the processor in the prior art can be solved, the MAC loopback test on the processor can be efficiently and simply realized, the control logic is simple, and the occupied resources are less.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a loopback test method, device, system, electronic equipment, computer-readable storage medium and computer program product. Background Art

[0002] In order to meet the high demand for electronic data transmission and processing rates, processors will integrate Ethernet protocol stacks and Segmented interfaces to support 200G to 400G rates. However, the IP (Intellectual Property) of the Ethernet protocol stack of such processors does not support loopback testing between the receiving and transmitting ends.

[0003] At present, in order to implement the MAC (Medium Access Control) test of the processor, the related technology deploys an asynchronous FIFO (First Input First Output) at the receiving end and a Packet FIFO at the sending end. The control logic of this method is relatively complex and the resource utilization rate is relatively high. Summary of the invention

[0004] The present invention provides a loopback test method, device, system, electronic device, computer-readable storage medium and computer program product, which can efficiently and simply implement MAC loopback testing of a processor, have simple control logic and occupy less resources.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions: On one hand, the present invention provides a loopback test device, comprising a data cache module and a read-write control logic module; the loopback test device is deployed on a target processor to test the network quality of the target processor; the target processor comprises a network communication module, a segmented interface and a register, and the network communication module does not support the register to control the data loopback reading and writing between a receiving end and a sending end; wherein the data cache module is connected to the network communication module via the segmented interface, and is configured to cache data packets received and sent via the network communication module and the segmented interface; the read-write control logic module is connected to the data cache module, and is configured to read and write the last data packet from the data cache module according to the packet end position of the data packet when the data cache module reaches a critical storage threshold condition.

[0006] On the other hand, the present invention provides a loopback test method, deploying a loopback test device on a target processor, comprising: when the network communication module of the target processor is successfully connected to the network card, starting a data packet sending and receiving test; caching the data packets sent and received through the network communication module and the segmented interface into a data cache module of the loopback test device; sending the acquired packet end position to the read-write control logic module, so that the read-write control logic module reads and writes the last data packet from the data cache module based on the packet end position when the data cache module reaches a critical storage threshold condition.

[0007] On the other hand, the present invention provides a loopback test system, comprising a network card and a target processor; wherein the network card and the target processor are respectively deployed to different servers, or the network card and the target processor are deployed in different card slots of the same server; the network card and the target processor communicate data via Ethernet; the target processor is deployed with the loopback test device as described above to test the communication quality between the network card and the target processor.

[0008] The present invention also provides an electronic device, comprising a memory and a processor, wherein the processor is used to implement the steps of the above loopback test method when executing a computer program stored in the memory.

[0009] The present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned loopback test method are implemented.

[0010] Finally, the present invention also provides a computer program product, including a computer program / instruction, which implements the steps of the above loopback test method when executed by a processor.

[0011] The advantage of the technical solution provided by the present invention is that, compared with the related art that needs to use two FIFOs, ordinary FIFO and whole packet cache FIFO, only one data cache module is needed to cache the data stream sent and received by the Segmented interface, thereby simplifying the control logic of the target processor for MAC loopback testing, and realizing simple and efficient data cache control. At the same time, according to the packet end position, the data read and write status can be fed back to the read and write control logic module in real time, which not only further simplifies the data read and write control logic of the data cache module, but also can ensure that the last packet of data is read and written, and effectively control the data read integrity. In addition, the entire loopback test device can be designed using RTL (Register Transfer Level), which is conducive to later engineering maintenance and resource expansion, with less resource occupation, flexible and efficient design. In addition, the loopback test method, loopback test system, electronic device, computer-readable storage medium and computer program product of the present invention have corresponding advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the present invention or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0013] Figure 1 A schematic diagram of an exemplary application scenario provided by the present invention; Figure 2 A schematic diagram of another exemplary application scenario provided by the present invention; Figure 3 A schematic diagram of a loopback test device provided by the present invention in an exemplary application scenario; Figure 4 A waveform diagram of a Segmented interface provided by the present invention in an exemplary application scenario; Figure 5 A schematic diagram of a critical storage threshold condition provided by the present invention in an exemplary application scenario; Figure 6 A schematic diagram of a read control logic circuit provided by the present invention in an exemplary application scenario; Figure 7 A schematic diagram of a write control logic circuit provided by the present invention in an exemplary application scenario; Figure 8 A schematic diagram of a loopback test method provided by the present invention; Fig. 9 A schematic diagram of a framework of an electronic device provided by the present invention in an exemplary application scenario; Fig.10 A schematic diagram of a loopback test system provided by the present invention in an exemplary application scenario; Fig.11 A schematic diagram of the framework of the loopback test system provided by the present invention in another exemplary application scenario. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. The methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the main purpose of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the protection scope of the present invention.

[0015] It should be noted that, in the description of the present invention, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0016] MAC loopback test is used to test the Ethernet connectivity and network quality of the target processor. At present, the relevant technology performs MAC loopback test in the following two ways. The first method is: the internal packet is looped back through the external self-loop head and then returned to the internal verification. This method not only requires the design of various types of packet sending modules and verification modules inside the target processor, but also requires the development of an adaptive MAC interface for transceiver control, which is difficult to implement and has a long debugging cycle. The second method is: use an external test board or instrument to send a data packet, and the external packet is looped back through the MAC internal loop and then returned to the external board or instrument for verification.

[0017] At present, for processors that integrate fractal, configurable, and enhanced Ethernet protocol stacks and support rates from 10G to 400G, such as Altera Agilex7 (product name) series FPGA (Field-Programmable GateArray) and Xilinx (product name) series FPGA, the IP modules of these processors provide Avalon ST (Avalon Streaming Interface, high-speed data stream transmission) interfaces to support 10G to 100G, and support 200G to 400G through Segmented interfaces. Segmented interfaces are a "compressed" data stream format, and data streams exist in the form of "segments", each segment is 8 bytes, that is, 64 bits. The interface width of 400G IP is 1024 bits, divided into 16 segments, and the interface width of 200G IP is 512 bits, divided into 8 segments. Since this type of processor does not currently support loopback testing of receiving and sending, the receiving end of the Segmented interface does not support back pressure, and the sending end supports back pressure but does not support packet disconnection. The related technology uses external logic to design the receiving and sending control logic based on the second method mentioned above. Based on this receiving and sending control logic, an asynchronous FIFO is used at the receiving end, and a Packet FIFO is used at the sending end. The Packet FIFO needs to cache a complete packet of data. However, the control logic of this method is relatively complex, the resource utilization rate is relatively high, and the problem location is relatively cumbersome.

[0018] In order to solve the problems existing in the related technology, the present invention uses a data cache module to cache the data stream received and sent by the Segmented interface, and at the same time, based on the flag of the packet end position that can reflect the data reading and writing status, the read and write control logic module reads and writes the data packet according to the real-time feedback status.

[0019] Based on the technical solution of the present invention, one of the application scenarios of the embodiment of the present invention is as follows: Figure 1As shown, the MAC loopback test of the target processor can be implemented through the first server 101 and the second server 102. In this application scenario, the target processor can be an accelerator card, and the 200G / 400G network card is deployed on the first server 101, and the accelerator card is deployed on the second server 102. The 200G / 400G network card on the first server is connected to the accelerator card on the second server 102 through an optical fiber. The first server 101 can be configured with a data packet processing module, for example, the self-test environment for sending and receiving packets in the DPDK (Data Plane Development Kit) can be installed, such as DPDK-pktgen (the application name of DPDK). The data packet processing module is used to implement complex packet sending and verification work, and configure the relevant parameters of DPDK, including but not limited to the source IP (Internet Protocol Address), destination IP address, source MAC address, destination MAC address, length, rate, etc. The data cache module and read-write control logic module of the present invention are deployed in the acceleration card of the second server 102. The data cache module can use an asynchronous FIFO, for example, and configure the registers of the acceleration card, including but not limited to clearing count statistics, state statistics, and critical storage threshold conditions, to achieve loopback control of sending and receiving. When the 200G / 400G network card is successfully connected to the network communication module of the acceleration card through optical fiber, DPDK-pktgen is started to perform a packet sending and receiving test. After the network communication module of the acceleration card receives the data packet, it determines the starting position and the end position of the data packet, and then caches it to the asynchronous FIFO. Under the control of the read-write control logic module, the read-write control of the asynchronous FIFO is completed to achieve loopback reading and writing of the data packet.

[0020] Based on the technical solution of the present invention, the second application scenario of the embodiment of the present invention is as follows: Figure 2As shown, a MAC loopback test of the target processor can be implemented through a server 103. In this application scenario, the target processor can be an accelerator card, and the data cache module adopts an asynchronous FIFO. The 200G / 400G network card and the accelerator card are respectively deployed in the first PCIE (peripheral component interconnect express, high-speed serial computer expansion bus) card slot and the second PCIE card slot of the server 103. The server 103 is configured with DPDK, and the DPDK related parameters are configured, such as source IP (Internet Protocol Address, network protocol address), destination IP address, source MAC address, destination MAC address, length, rate, etc. The asynchronous FIFO and read-write control logic module are deployed in the accelerator card, and the relevant parameters of the registers of the accelerator card are configured, such as clear count statistics, status statistics, and the empty threshold and full threshold of the asynchronous FIFO. When the 200G / 400G network card is successfully connected to the network communication module of the accelerator card, DPDK-pktgen is started to perform packet sending and receiving test. After the network communication module of the accelerator card receives the data packet, it determines the starting position and the end position of the data packet, and then caches it into the asynchronous FIFO. Under the control of the read-write control logic module, the read and write control of the asynchronous FIFO is completed to realize the loopback reading and writing of the data packet.

[0021] It should be noted that the above application scenarios are only shown to facilitate understanding of the ideas and principles of the present invention, and the embodiments of the present invention are not limited in this respect. On the contrary, the embodiments of the present invention can be applied to any applicable scenario. After introducing the technical solution of the present invention, various non-limiting embodiments of the present invention are described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0022] First see Figure 3 , Figure 3 A schematic diagram of the structural framework of the loopback test device provided in this embodiment under an exemplary implementation manner, this embodiment may include the following contents: The loopback test device is deployed on the target processor to test the connectivity and signal quality of the Ethernet hardware environment of the target processor, that is, the network quality. That is, when the target processor needs to perform a MAC loopback test, the loopback test device of the present invention can be deployed. The target processor referred to in this embodiment refers to a processor that includes at least a network communication module, a segmented interface and a register, and its network communication module does not support register control of data loopback reading and writing between the receiving end and the transmitting end. For the sake of description, the processor that meets this condition is defined as the target processor. For example, the target processor can be an Altera Agilex7 series FPGA, a Xilinx series FPGA, and a processor with a large bandwidth and high-speed interface. The network communication module is used to process high-speed serial interfaces and protocols in the target processor. For example, for the target processor is an Altera Agilex 7 series FPGA, the network communication module is F-Tile, and F-Tile is used to implement Ethernet and other high-speed communication protocols. The network communication module of this embodiment supports rates from 10G to 400G, and for 200G and 400G, its IP interface provides a Segmented interface. That is to say, the data packets sent to the network communication module of the target processor will be divided into the corresponding number of segments according to the interface bit width and the bytes of each segment of the Segmented interface, and then cached through the Segmented interface. Among them, the bit width refers to the number of data bits that can be processed or transmitted at one time. For example, the interface bit width of 400G IP is 1024bit, divided into 16 segments, and the interface bit width of 200G IP is 512bit, divided into 8 segments. When the rate is 400G, the data packet will be divided into 16 segments. When the rate is 200G, the data packet will be divided into 8 segments. The register is used to store the configuration information of the target processor, including but not limited to clear count statistics, state statistics, and critical storage threshold conditions. Among them, the critical storage threshold condition is used to indicate the threshold value at which the data cache module is about to be full and the threshold value to be cleared. Taking the data cache module as FIFO as an example, the critical storage threshold condition may include the empty threshold value and the full threshold value of the asynchronous FIFO.

[0023] In this embodiment, since the network communication module of the target processor does not support the data loopback reading and writing between the receiving end and the transmitting end controlled by the register, in order to realize the MAC loopback test of the target processor, a loopback test device is deployed in the target processor. The loopback test device can be completely designed by RTL, such as verilog (hardware description language) or VHDL (circuit design language) language. As for which hardware programming language to use, it can be flexibly selected according to actual conditions, which does not affect the implementation of the present invention. The device may include a data cache module 301 and a read-write control logic module 302. The data cache module 301 is connected to the network communication module through a segmented interface, and the read-write control logic module 302 is connected to the data cache module 301. That is, the read-write control logic module is used to control the data reading and writing of the data cache module 301. The data cache module 301 will cache the data received by the network communication module through the segmented interface, and the data packets sent out by the network communication module can also be cached to the data cache module 301 first, and then sent to the network communication module through the segmented interface. The data cache module 301 can coordinate the data transmission between modules running at different rates of the target processor during the MAC loopback test to prevent data loss or confusion, and can transfer data between different clock domains to ensure data synchronization and consistency.

[0024] Among them, when the loopback test device is deployed on the target processor, the network hardware environment configuration of the target processor is completed, and the packet sending and receiving test environment for realizing complex packet sending and verification work is configured, such as installing DPDK, and configuring DPDK related parameters such as source IP, destination IP address, source MAC address, destination MAC address, length, rate, etc. Start DPDK to perform packet sending and receiving test, and after the internal loopback of the network communication module of the target processor, return to DPDK for verification.

[0025] Among them, the internal loop control logic of the target processor is: the network communication module receives the data packets sent by DPDK to the target processor, and caches these data packets to the data cache module 301 through the segmented interface, that is, the data cache module 301 is configured to cache the data packets sent and received through the network communication module and the segmented interface. In order to facilitate the management and transmission of data packets, the data packets will add custom identifiers, such as the packet start position and the packet end position. When writing a data packet to the data cache module 301, it is necessary to obtain the packet end position of the data packet, which can be identified by the packet end mark, and then send it to the read-write control logic module 302. When the read-write control logic module 302 writes a data packet to the data cache module 301, it will pay attention to the critical storage threshold condition of the data cache module 301 in real time. When writing data, it will determine whether the data cache module 301 has reached the full threshold, and combine the packet end mark of the next data packet to be written to perform data writing control, and it should be ensured that the last packet of data is written. When a data packet is read from the data cache module 301 and sent to the DPDK through the segmented interface and the network communication module, it is also necessary to pre-fetch the packet end flag of the data packet and then send it to the read-write control logic module 302. When the read-write control logic module 302 reads the data packet from the data cache module 301, it will pay attention to the critical storage threshold condition of the data cache module 301 in real time. When reading data, it will determine whether the data cache module 301 has reached the empty threshold, and combine the packet end flag of the next data packet to be output by the data cache module 301 to perform data reading control, and it should ensure that the last packet of data is read. In other words, the read-write control logic module 302 is configured to realize real-time feedback control of the state according to the packet end flag of the data packet, and when the data cache module 301 reaches the critical storage threshold condition, the last data packet is read and written from the data cache module 301.

[0026] In order to make those skilled in the art more clearly understand the technical solution of the present invention, the present invention is based on the above technical solution, taking the data being cut into 4 Segmented segments as an example, Figure 4 The waveform diagram of the corresponding Segmented interface is shown in Figure 2. Figure 4The first row from top to bottom represents the clock signal, that is, the clock signal, and the diagram includes 17 clock signals; the second row represents the ready signal to receive data, for example, it can be represented as tx_MAC_ready, tx represents the Segmented interface of the transmitter, the third row represents the valid signal to indicate whether the data is valid, for example, it can be represented as tx_MAC_valid, the fourth row represents the first Segmented segment data, for example, it can be represented as tx_MAC_data[63:0], [63:0] indicates that the data bit width of this Segmented segment data is 0~63 bits, x represents invalid data or random numbers, sop is the starting position of the data packet, and eop represents the end position of the data packet; the fifth row represents The second Segmented segment data can be expressed as tx_MAC_data[127:64], for example, [127:64] indicates that the data bit width of this Segmented segment data is 64th to 127th bits; the sixth row represents the third Segmented segment data, for example, it can be expressed as tx_MAC_data[191:128], [191:128] indicates that the data bit width of this Segmented segment data is 128th to 191st bits; the seventh row represents the fourth Segmented segment data, for example, it can be expressed as tx_MAC_data[255:192], [255:192] indicates that the data bit width of this Segmented segment data is 192th to 255th bits. Since data packets are sent and received through the Segmented interface, large data packets need to be split into blocks supported by the Segmented interface, such as 64 bytes per segment. In order to facilitate the management of data packets, each Segmented segment has a representation. The valid identification information corresponding to the Segmented segment into which the data packet is divided once will generate segmented data identification information, such as inframe. Each bit of inframe corresponds to the valid identification information of a Segmented segment. Taking 400G MAC as an example, sending and receiving only supports the Segmented interface. The interface bit width is 1024 bits, which is divided into 16 Segmented segments in total. Each Segmented segment is 8 bytes, a total of 64 bits, and inframe is 16 bits. Each bit of inframe corresponds to the valid flag of each Segmented segment.Therefore, the segmented data identification information represented by the 8th to 11th lines is as follows: the 8th line represents the first bit of the segmented data identification information, which can be represented as tx_MAC_inframe[0]; the 9th line represents the second bit of the segmented data identification information, which can be represented as tx_MAC_inframe[1]; the 10th line represents the third bit of the segmented data identification information, which can be represented as tx_MAC_inframe[2]; and the 11th line represents the fourth bit of the segmented data identification information, which can be represented as tx_MAC_inframe[3]. The 12th to 15th lines represent how many bytes of each Segmented segment are invalid at the eop time, which can be represented by tx_eop_empty. The 12th line represents how many bytes of the first Segmented segment are invalid at the eop time, for example, it can be represented as tx_eop_empty[2:0], where [2:0] indicates that the 0th to 2nd bits of the Segmented segment are invalid at the eop time. The thirteenth line indicates how many bytes of the second Segmented segment are invalid at the eop time, for example, it can be expressed as tx_eop_empty[5:3], [5:3] indicates that the 3rd to 5th bits of the Segmented segment are invalid at the eop time. The fourteenth line indicates how many bytes of the third Segmented segment are invalid at the eop time, for example, it can be expressed as tx_eop_empty[8:6], [8:6] indicates that the 6th to 8th bits of the Segmented segment are invalid at the eop time. The fifteenth line indicates how many bytes of the fourth Segmented segment are invalid at the eop time, for example, it can be expressed as tx_eop_empty[11:9], [11:9] indicates that the 9th to 11th bits of the Segmented segment are invalid at the eop time. Taking 400G MAC as an example, sending and receiving only supports Segmented interface, and the sending interface supports back pressure control. After ready is pulled low, 1-8 clk (clock) data can continue to be sent. When the adjacent bits of inframe jump from 0 to 1, the sop indicating the start position of the packet appears in the Segmented; when the adjacent bits of inframe jump from 1 to 0, it may not be in the same clk, indicating that the eop indicating the end position of the packet appears in the Segmented. Eop_empty is only valid in the corresponding Segmented segment indicated at the end position of the packet, and the remaining Segmented segments are invalid. During the data packet transmission process, if the valid signal is interrupted, the corresponding data and inframe should be maintained, otherwise the integrity of the data packet will be destroyed.

[0027] In the technical solution provided in this embodiment, compared with the related technology that needs to use two FIFOs, ordinary FIFO and whole packet cache FIFO, only one data cache module 301 is needed to cache the data stream sent and received by the Segmented interface, thereby simplifying the control logic of the target processor for MAC loopback testing, and realizing simple and efficient data cache control. At the same time, based on the packet end position, the data read and write status can be fed back to the read and write control logic module 302 in real time, which not only further simplifies the data read and write control logic of the data cache module 301, but also can ensure that the last packet of data is read and written, and effectively control the data read integrity. In addition, the entire loopback test device can be designed using RTL, which is conducive to later engineering maintenance and resource expansion, with less resource occupation, flexible and efficient design.

[0028] It is understandable that an inappropriate setting of the storage critical threshold may cause the last data packet to overflow or the data cache module to be read empty, resulting in a packet disconnection phenomenon. In order to avoid the occurrence of write overflow and packet disconnection, based on the above embodiment, the present invention also provides an implementation method that allows adjustment at any time during the MAC loopback test according to the critical storage threshold condition, which may include the following contents: The read / write control logic module 302 may be connected to a register of a target processor, the register storing a critical storage threshold condition, and the register may be connected to a target peripheral interface of the target processor via a bus; during the MAC test of the target processor, the critical storage threshold condition is adjusted via the target peripheral interface. The bus may be, for example, an Advanced Peripheral Bus (APB), and the target peripheral interface is a predefined external interface, such as a Joint Test Action Group (JTAG) or a Universal Asynchronous Receiver / Transmitter (UART).

[0029] As can be seen from the above, this embodiment, through the first-level data cache module and the variable threshold control method, not only makes up for the problem that the current target processor cannot pass the internal self-loop verification of the IP module, but also ensures the continuous reading and writing of the data packet cache, avoiding write overflow and packet disconnection.

[0030] The above embodiment does not impose any limitation on the data cache module 301. Based on the above embodiment, the present invention also provides an implementation method of using the data cache module 301 to adopt a first-in-first-out storage structure, which can be implemented by a register or a RAM (Random Access Memory), that is, the data cache module 301 can adopt FIFO. When the downstream module of the target processor cannot process the data output by the upstream module in time, the data cache module 301 can temporarily store the data to prevent data loss. For the problem of data transmission between different clock domains handled by the target processor, such as the sending clock and receiving clock of the Segmented interface may have a certain phase difference or frequency difference, in order to avoid the complexity of design and constraints brought by cross-clock domain transmission, or the scenario where the target processor has data written too fast and the interval time is long, or there is a conversion scenario of data interfaces of different widths, such as converting from 8-bit input to 16-bit output, the data cache module 301 can adopt an asynchronous FIFO. In addition, since the present invention needs to obtain the packet end position, as a more convenient and effective implementation method, the data cache module 301 adopts a FWFT (First Word Fall Through, missing one character) type FIFO, which stops once when reading or writing when it is empty, and stops once when writing or reading when it is full. Therefore, before the read enable is effective, the data to be output can be displayed on the output port.

[0031] When the above embodiment provides that the data cache module adopts a FIFO storage structure, the critical storage threshold conditions include a first-in-first-out full threshold and an empty threshold, and the FIFO full threshold is set too large or the empty threshold is set too small, which may cause the last data packet to overflow or the FIFO to read empty, thereby causing a packet disconnection phenomenon. Based on the above embodiment, the present invention also provides a variable FIFO threshold implementation method, which may include the following content: When the length of the data packet read or written from the data cache module 301 changes, the almost full threshold and the almost empty threshold of the register are adjusted through the target peripheral interface; wherein the values ​​of the almost full threshold and the almost empty threshold both increase as the length of the data packet increases.

[0032] In this embodiment, the critical storage threshold condition includes a FIFO full threshold and an empty threshold. The full threshold can be expressed as almost_full, and the empty threshold can be expressed as almost_empty. Figure 5As shown in the figure, when the data data_cnt contained in the FIFO is greater than or equal to almost_full, the almost full signal is valid, that is, almost_full is 1, and almost_full is transmitted to the upstream module A, notifying the upstream module to stop sending data to prevent FIFO from overflowing. In order to avoid data loss and ensure that data will not overflow, there are still N beats of data to be sent to the FIFO one after another, so the value of almost_full should at least be FIFO depth-MN. In order to avoid data overflow, the FIFO depth can be determined according to the transmission rate, the maximum packet interval time and the data bit width. As an efficient implementation method, when initially determining the almost full threshold, it can be calculated by calling the relationship transmission rate × maximum packet interval time / data bit width-MN. After determining the almost full threshold, for different data packet lengths, in order to avoid discontinuous data writing and write overflow, the empty threshold and the almost full threshold can be arbitrarily set and modified through the internal apb interface, effectively improving the loop bandwidth for data packets of different lengths.

[0033] As can be seen from the above, this embodiment ensures the continuous reading and writing of the data packet cache through a first-level FIFO and a variable threshold control method, which makes up for the problem that the internal self-loop verification of the IP cannot be passed at present. The setting of the FIFO full threshold and the empty threshold is matched with the length of the test data packet. For data packets of different lengths, it can not only effectively improve the loopback test bandwidth, but also prevent frequent modification of parameter compilation and debugging, thereby improving the overall efficiency. It has the advantages of flexible design, simplicity, high efficiency, and low resource occupancy.

[0034] Based on the above embodiment, in order to avoid the phenomenon that the FIFO is full or empty when half of a data packet is written or read, based on the above embodiment, the values ​​of the almost full threshold and the almost empty threshold are adjusted to be at least one packet length value through the target peripheral interface. In other words, the values ​​of the almost empty threshold and the almost full threshold of the FIFO should be set to be at least greater than the cache FIFO depth required by the current test packet length.

[0035] Furthermore, the FIFO read and write data packets can be counted through registers, and the status of FIFO empty and full flags can be monitored in real time, which is conducive to rapid positioning and debugging of the system. Once a problem occurs, it can also be used to locate the fault in time.

[0036] As can be seen from the above, this embodiment sets a variable FIFO full threshold and empty threshold, which can effectively improve the read and write bandwidth during the switching process of data packets of different sizes. The full threshold and the empty threshold are reduced by at least the length of a data packet, which can ensure that the FIFO will not be full or empty when a data packet is half written or half read, and the integrity of the packet is maintained.

[0037] The above embodiment does not impose any limitation on the read-write control logic module. In order to realize complete data reading and continuous data reading of the data cache module, and to simplify the control logic and occupy less resources, the present invention also provides a method for realizing read control of the read-write control logic module by using a logic gate circuit, which may include the following contents:

[0038] The read control logic circuit of the read-write control logic module 302 is constructed based on a logic circuit. The read control logic circuit includes a read enable module, a read condition identification module and a read control signal generation module. That is to say, the read enable module, the read condition identification module and the read control signal generation module are constructed using various components of a digital logic circuit, and the functions of the corresponding modules are realized through corresponding logical operations.

[0039] In this embodiment, the input signal of the read enable module is the data receiving ready signal of the segmented interface. The data receiving ready signal means that the receiving end is ready to receive data. Taking the basic handshake signal valid / ready as an example, the sending end sets valid to indicate that the data is valid, and the receiving end sets ready to indicate that the data can be received. When both valid / ready are high, the data is valid. Figure 4The second row of data shown. In order to indicate that the receiving end, such as a FIFO or a data buffer, is ready to receive data from the transmitting end, a read enable signal can be generated. For example, in a FIFO, when rd_en (read enable) is high, the read enable signal is valid, indicating that the FIFO can be read. Usually the enable signal and the data signal are one-to-one, so in order to ensure that the read enable signal is valid, that is, to ensure that the data is read out, the data receiving preparation signal can be processed by timing synchronization and output as a valid read enable signal. When reading data from the data cache module, it is necessary to simultaneously meet the conditions that there is data in the data cache module and that a data can be read out completely, so it is necessary to identify whether this condition is met. This embodiment is identified by a degree condition recognition module. Accordingly, the first input signal of the read condition recognition module is a critical storage threshold condition, and the second input signal is a pre-fetch signal of the packet end mark; when the packet end mark is detected and the empty threshold of the critical storage threshold condition is reached, it indicates that the condition for reading data from the data cache module is not met, and accordingly, a stop read signal is output to indicate the stop read operation. When the conditions of detecting the packet end mark and reaching the empty threshold are not met at the same time, it indicates that the conditions for reading data from the data cache module are met, and accordingly, a read operation valid signal is output. After the read condition is met, it is also necessary to have data to read in the data cache data. Accordingly, when controlling the read data, it is also necessary to obtain a signal whether the data cache module is empty. The data non-empty signal indicates that the data cache module stores data, and the data empty signal indicates that the data cache module does not store data. The read control signal generation module receives the read operation valid signal, splices the valid read enable signal and the data non-empty signal of the data cache module 301 to generate a read control signal; the read control signal controls the reading of the corresponding data packet from the data cache module 301.

[0040] From the above, it can be seen that this embodiment uses a logic circuit to implement read control of the data cache module, which not only ensures complete and continuous reading of the data of the data cache module, but also has simple control logic and occupies less resources. It is also beneficial to later project maintenance and resource expansion, occupies less resources, and has a flexible and efficient design.

[0041] Further, considering the stability of data transmission, based on the above embodiment, the transmitting end interface, namely the Segmented interface, supports back pressure control, so that the Segmented interface can dynamically adjust its transmission rate according to the processing capability of the receiving end to avoid the speed mismatch problem in the data transmission process. Correspondingly, the read enable module also includes multiple triggers, and the total number of triggers is determined according to the number of clock signals allowed to be sent by the target processor when the data is not accepted. For example, according to the IP manual of Altera Agilex7 series FPGA F-Tile, it supports 1-8 clks to be set arbitrarily. Each trigger is interconnected, wherein the input end of the first trigger inputs the data receiving preparation signal, and the signal delay processing is performed in turn through each trigger, and the last trigger outputs the read enable signal. Each trigger includes CLR (clear signal) and SET (set signal). In order to ensure that the read enable signal can coordinate work according to certain time requirements, the trigger can use a synchronous RS trigger. The synchronous RS trigger includes three input ends, input end R, input end S and input control end CP. Whether the input trigger of input end R and input end S is valid is controlled by the CP end. When the CP terminal is 1, the input trigger of input terminal R and input terminal S is valid. At this time, the synchronous RS trigger is a basic RS trigger. When the CP terminal is 0, any trigger of input terminal R and input terminal S cannot change the output state of the trigger.

[0042] As can be seen from the above, the processing speeds of the transmitting and receiving ends of this embodiment are matched, which can ensure the stability and reliability of data transmission and determine the reliability of the MAC loopback test of the target processor.

[0043] The above embodiment does not impose any limitation on the structure of the read control logic circuit. Based on the above embodiment, the present invention further provides an exemplary implementation method, which may include the following contents: For the read enable module, depending on whether the input terminal supports back pressure control, two structures may be included: in an exemplary structure, the read enable module includes a first trigger and a first AND gate; the data receiving ready signal is received to the first input terminal S of the first trigger and the first input terminal of the first AND gate respectively, and the first output terminal of the first trigger The second input terminal of the first AND gate is connected to the first output terminal of the first AND gate; the first output terminal of the first AND gate outputs a valid read enable signal. In another exemplary structure, the read enable module at least includes a first trigger, a second trigger, a third trigger and a first AND gate; the second input terminal S of the second trigger receives a data reception ready signal, and the second output terminal Q of the second trigger is connected to the third input terminal S of the third trigger, and is used to output a delayed signal corresponding to the data reception ready signal; the third output terminal Q of the third trigger is respectively connected to the first input terminal S of the first trigger and the first input terminal of the first AND gate to receive the delayed signal corresponding to the data reception ready signal; the first output terminal of the first trigger Connected to the second input terminal of the first AND gate, the output signal of the first output terminal of the first AND gate and the third output terminal Q of the third flip-flop is used as a valid read enable signal.

[0044] The read condition identification module includes a first NAND gate, and the first NAND gate includes a third input terminal, a fourth input terminal, and a second output terminal; the third input terminal receives a signal corresponding to a critical storage threshold condition, and the fourth input terminal receives a pre-fetch signal of a packet end mark; the second output terminal outputs a read operation valid signal or a stop read signal. The read control signal generation module includes a second AND gate, a first OR gate, a first NAND gate, and a third AND gate; the fifth input terminal of the second AND gate receives a delay signal, the sixth input terminal receives a read operation valid signal or a stop read signal, and the third output terminal is connected to the seventh input terminal of the first OR gate; the eighth input terminal of the first OR gate receives a rising edge signal corresponding to a read enable signal, the fourth output terminal of the first OR gate is connected to the tenth input terminal of the third AND gate, the ninth input terminal of the first NAND gate receives a data empty signal of the data cache module 301, the fifth output terminal of the first NAND gate is connected to the eleventh input terminal of the third AND gate, and the sixth output terminal of the third AND gate outputs a read control signal.

[0045] Among them, the NAND gate is used to perform an AND operation on the input signal. Only when all inputs are high, the output is low level; the AND gate is used to perform an AND operation on the input signal. When all inputs are high level, the output is high level; the NOT gate is used to perform a negation operation on the input signal. When the input is high level, the output is low level; when the input is low level, the output is high level. The OR gate is used to perform an OR operation on the input signal. As long as one input is high level, the output is high level. High level indicates a valid signal, and low level indicates an invalid signal.

[0046] In order to make those skilled in the art more clearly understand the read control logic of the present invention, the present invention also provides an exemplary read control logic circuit, such as Figure 6As shown, the transmitting end of this embodiment supports back pressure control, and the read control logic circuit includes a first trigger, a second trigger, a third trigger, a first AND gate, a first NAND gate, a second AND gate, a first OR gate, a first NAND gate and a third AND gate. Among them, each trigger includes a clear signal CLR and a set signal SET, Figure 6 It is not shown in the figure that the second input terminal S of the second trigger receives the data receiving ready signal, and the second output terminal Q of the second trigger is connected to the third input terminal S of the third trigger to output the delayed signal corresponding to the data receiving ready signal; the third output terminal Q of the third trigger is respectively connected to the first input terminal S of the first trigger and the first input terminal of the first AND gate to receive the delayed signal corresponding to the data receiving ready signal; the first output terminal of the first trigger The first output terminal of the first AND gate is connected to the second input terminal of the first AND gate, and the output signal of the third output terminal Q of the third trigger is used as a valid read enable signal. The third input terminal of the first NAND gate receives a signal corresponding to the critical storage threshold condition, and the fourth input terminal receives a pre-fetch signal of the packet end mark; the second output terminal outputs a read operation valid signal or a stop read signal. The fifth input terminal of the second AND gate receives a delay signal, the sixth input terminal receives a read operation valid signal or a stop read signal, and the third output terminal is connected to the seventh input terminal of the first OR gate; the eighth input terminal of the first OR gate receives a rising edge signal corresponding to the read enable signal, the fourth output terminal of the first OR gate is connected to the tenth input terminal of the third AND gate, the ninth input terminal of the first NOT gate receives a data empty signal of the data cache module, the fifth output terminal of the first NOT gate is connected to the eleventh input terminal of the third AND gate, and the sixth output terminal of the third AND gate outputs a read control signal. First, the read enable signal comes from the delayed signal of the data receiving preparation signal of the Segmented interface at the sending end. The pre-fetch signal of the eop signal can be understood as the output data of the FWFT FIFO. Only when the signal corresponding to the empty threshold and the pre-fetch signal of the packet end position are both 1, the position at A will be 0, that is, when the FIFO read operation detects eop and reaches the empty threshold at the same time, the read operation will be stopped. The rest of the states are valid, that is, the rest of the states will generate a valid read operation signal. In order to make up for the first read enable and maintain data integrity, the delayed signal needs to be beat by one or more beats and calculated with itself once. B is the rising edge of the delayed signal. The rising edge signal and the delayed signal together constitute a valid read enable signal. D splices the signals at B and C, that is, OR operation. As long as one of them is valid and the data is not empty, a read control signal that effectively controls the read data can be generated.

[0047] From the above, it can be seen that this embodiment constructs a read control logic circuit through triggers and logic gate units, which simply and efficiently realizes the control of read data. It can not only realize the integrity and continuity of the data read control of the data cache module, but also facilitates later engineering maintenance and resource expansion, and occupies less resources.

[0048] The above embodiment does not impose any limitation on the read-write control logic module. In order to achieve write integrity and continuous writing of data in the data cache module, and to simplify the control logic and occupy less resources, the present invention also provides a method of using a logic gate circuit to implement write control of the read-write control logic module, which may include the following contents: The write control logic circuit of the read-write control logic module 302 is constructed based on a logic circuit. The write control logic circuit includes a write enable signal generation module and a write control signal generation module. That is to say, the write enable signal generation module and the write control signal generation module are constructed using various components of a digital logic circuit, and the functions of the corresponding modules are realized through corresponding logical operations.

[0049] Among them, the input signals of the write enable signal generation module are the critical storage threshold condition, the packet end position and the segmented data identification information. The packet end position can be represented by a packet end identifier such as eop, wherein the segmented data identification information includes the segmented valid identifier of each segment after the data packet sent and received through the segmented interface is segmented. Since data packets are sent and received through the Segmented interface, large data packets need to be split into blocks supported by the Segmented interface, such as 64 bytes per segment. In order to facilitate the management of data packets, each Segmented segment has a representation. The valid identification information corresponding to the Segmented segment into which the data packet is divided once will generate segmented data identification information, such as inframe. Each bit of inframe corresponds to the valid identification information of a Segmented segment. Taking 400G MAC as an example, sending and receiving only supports the Segmented interface. The interface bit width is 1024 bits, which is divided into 16 Segmented segments in total. Each Segmented segment is 8 bytes, a total of 64 bits, and inframe is 16 bits. Each bit of inframe corresponds to the valid flag of each Segmented segment. Before the segmented data identification information is input into the write enable signal generation module, the segmented data identification information will be bitwise ORed, and the OR result will be input into the write enable signal generation module. When the threshold value of reaching the critical storage threshold condition is not met at the same time, and the bus corresponding to the segmented interface is in an idle state and has no valid data, it indicates that the conditions for the write operation are met, and a write enable valid signal is output, and the write operation can continue. When the threshold value of reaching the critical storage threshold condition is met at the same time, and the bus corresponding to the segmented interface is in an idle state and has no valid data, it indicates that integrity writing or valid writing cannot be performed at present, then a write enable failure signal is output, and the write operation is stopped, which ensures the integrity of the data packet under the critical write condition. The write control signal generation module outputs a write control signal upon receiving a write enable valid signal and a data valid signal, so as to write the corresponding data packet in the data cache module 301 through the write control signal; and when a write enable invalid signal or a data invalid signal is received, the write control signal is not output. The data valid signal can be a valid signal, which is used to indicate the validity of the FIFO output data. When the FIFO successfully reads a data item and presents it at the output port, the valid signal will be set high.

[0050] From the above, it can be seen that this embodiment uses a logic circuit to implement write control of the data cache module, which not only ensures complete and continuous writing of the data cache module, but also has simple write control logic and occupies less resources. It is also beneficial to later project maintenance and resource expansion, and occupies less resources.

[0051] The above embodiment does not impose any limitation on the structure of the write control logic circuit. Based on the above embodiment, the present invention further provides an exemplary implementation method, which may include the following contents: The write enable signal generation module includes a second OR gate, a second NOT gate and a second NAND gate; the write control signal generation module includes a fourth AND gate, the second NAND gate is used to perform an AND operation on the input signal, and the output is low only when all inputs are high; the fourth AND gate is used to perform an AND operation on the input signal, and the output is high only when all inputs are high; the second NOT gate is used to perform a NOT operation on the input signal, and the output is low when the input is high; the output is high when the input is low. The second OR gate is used to perform an OR operation on the input signal, and the output is high as long as one input is high. A high level indicates a valid signal, and a low level indicates an invalid signal.

[0052] The twelfth input terminal of the second OR gate receives the segmented data identification information, the thirteenth input terminal receives the pre-fetch signal of the packet end position, the second OR gate performs an OR operation on the segmented data identification information and the pre-fetch signal of the packet end position, and inputs the OR result to the fourteenth input terminal of the second NOT gate through the seventh output terminal; the second NOT gate performs a NOT operation on the OR result, and inputs the NOT operation result to the sixteenth input terminal of the second NAND gate through the eighth output terminal, the fifteenth input terminal of the second NAND gate inputs the full threshold signal of the critical storage threshold condition, performs an AND NOT operation on the full threshold signal and the NOT operation result, and uses the generated AND NOT operation result as a write enable signal, which is output through the ninth output terminal; wherein the write enable signal includes a write enable valid signal and a write enable invalid signal. The seventeenth input terminal of the fourth AND gate receives the data valid signal, the eighteenth input terminal of the fourth AND gate receives the write enable signal, and outputs the AND operation result of the data valid signal and the write enable signal to the data cache module 301 through the tenth output terminal.

[0053] In order to make those skilled in the art more clearly understand the write control logic of the present invention, the present invention also provides an exemplary write control logic circuit, such as Figure 7As shown, the write control logic circuit comprises a second OR gate, a second NOT gate, a second NAND gate, and a fourth AND gate. The twelfth input terminal of the second OR gate receives the segmented data identification information, the thirteenth input terminal receives the pre-fetch signal of the packet end position, the second OR gate performs an OR operation on the segmented data identification information and the pre-fetch signal of the packet end position, and inputs the OR result to the fourteenth input terminal of the second NOT gate through the seventh output terminal; the second NOT gate performs a NOT operation on the OR result, and inputs the NON operation result to the sixteenth input terminal of the second NAND gate through the eighth output terminal; the fifteenth input terminal of the second NAND gate inputs the nearly full threshold signal of the critical storage threshold condition, performs an AND NOT operation on the nearly full threshold signal and the NON operation result, generates a write enable valid signal or a write enable invalid signal, and outputs it through the ninth output terminal; the seventeenth input terminal receives the data valid signal, the eighteenth input terminal receives the write enable signal, and outputs the AND operation result of the data valid signal and the write enable signal to the data cache module through the tenth output terminal. Based on this circuit structure, after the segment identification information is bitwise ORed, it is ORed with the packet end flag or the signal corresponding to the packet end position. Only when both are 0 at the same time, the position at F can be 1, which means that the current Segmented bus is in an idle state and there is no valid data. G is the AND-NOT operation of F and the full signal. Only when both are 1 at the same time, the position of G will be 0, at which time the write enable of the FIFO will be invalid. In other cases, all are 1, that is, a write enable valid signal is generated. The case where both are 0 means that the current write fifo position has reached a write threshold and satisfies the idle state of the Segmented bus. This ensures the integrity of the data packet under critical write conditions.

[0054] As can be seen from the above, this embodiment constructs a write control logic circuit through triggers and logic gate units, which simply and efficiently realizes the control of write data. It can not only realize a complete and continuous write data cache module, but also facilitates later engineering maintenance and resource expansion, and occupies less resources.

[0055] Based on the above embodiments, in order to improve the MAC loopback test efficiency of the target processor, the present invention further provides an implementation method for implementing a synchronous loopback test of different types of packet lengths on multiple channels, which may include the following contents: The multi-channel selection device is determined according to the number of channels, data bit width, control signal and application scenario. The number of channels is the number of channels to be selected, such as 2 to 1, 4 to 1, 8 to 1, etc.; the data bit width is the data width of each channel, such as 8 bits, 16 bits, 32 bits, etc. The control signal is the number and logic of the selection signal, usually binary encoding, and the application scenario is the signal channel switching. Multi-channel selection devices include but are not limited to multiplexers (MUX), counters, and finite state machines. Among them, the multiplexer can select an output from multiple input channels according to the control signal. In FPGA, MUX can be implemented by LUT (lookup table) and internal logic resources. For example, by cascading multiple LUTs and MUXs, a multi-digit multiplexer can be constructed. By designing a counter and using its output as a channel selection signal, the selection function of multiple channels can be realized. For example, in a multi-channel sampling system, a binary counter can be used, and its output is connected to the address input of an analog switch (such as CD4051) to select different channels for sampling. Finite state machines can implement complex channel selection logic through programming. For example, in a multi-channel sampling system, a finite state machine can generate a control signal according to the timing requirements to control the switching of the channel selection module. When the multi-channel selection device to be used is determined, based on the input signal, selection signal, and output signal information, the input signal: 4 data inputs, such as D0, D1, D2, and D3. Selection signal: 2 selection signals, such as A1 and A0, used to select a channel. Output signal: 1 output signal, such as Y. The hardware language is used to perform logic design on the channel selection, and the synthesis tool converts the hardware language code into the logic resources inside the target processor such as FPGA, such as LUT, register, etc. After confirming that the hardware language code logic of the multi-channel selection device is correctly mapped to the logic resources of the target processor, the corresponding hardware results are deployed on the target processor. For example, the multi-channel selection device can be deployed between the read control logic circuit and the write control logic circuit of the read-write control logic circuit, that is, the multi-channel selection device is connected to the read control logic circuit and the write control logic circuit at the same time.

[0056] For example, taking the multi-channel selection device as MUX and the target processor as FPGA, the LUT (lookup table) in FPGA is a programmable combinational logic unit that can be used to implement any combinational logic function. For simple MUX, such as 2 to 1 or 4 to 1, LUT can be used directly to implement it. During synthesis, the FPGA tool will map the above logic to a LUT6. LUT6 can implement combinational logic with up to 6 inputs, so a 4 to 1 MUX can be directly implemented with a LUT6.

[0057] As can be seen from the above, this embodiment deploys a multi-channel selection device to make the loopback buffer FIFO reusable, implement synchronous loopback testing of multi-channels with different types of packet lengths, and effectively improve the efficiency of the MAC loopback test of the target processor.

[0058] Based on the above embodiments, when the loopback test device in the above embodiments is deployed on the target processor and a MAC loopback test is performed on the target processor, the present invention also provides a loopback test method, see Figure 8 , this embodiment may include the following contents: S801: When the network communication module of the target processor is successfully connected to the network card, a data packet sending and receiving test is started.

[0059] S802: Cache the data packets received and sent through the network communication module and the segmented interface into the data cache module of the loopback test device.

[0060] S803: Send the acquired packet end position to the read / write control logic module, so that the read / write control logic module reads and writes the last data packet from the data cache module based on the packet end position when the data cache module reaches a critical storage threshold condition.

[0061] As can be seen from the above, this embodiment aims at the problem that the target processor's Segmented interface has a complex design of self-initiated and self-retracted loopback and IP does not support internal loopback testing. The network card is used as an external data packet transmitter and receiver, and the target processor is controlled by internal self-loopback, thereby realizing the MAC loopback test of the target processor. Only the first-level data cache module is used to realize the data bridging of the transceiver interface. The read and write status can be clearly identified in real time through the packet end position, ensuring the continuity and integrity of data read and write.

[0062] The description of the features in the embodiment corresponding to the loopback test method can refer to the relevant description of the embodiment corresponding to the loopback test device, which will not be repeated here. It should be noted that there is no strict order of execution between the steps in the present invention. As long as they conform to the logical order, these steps can be executed simultaneously or in a preset order. Figure 8 This is just a schematic and does not mean that this is the only execution order.

[0063] Exemplarily, this embodiment also provides an exemplary method for determining the end position of a packet. When the network communication module receives a target data packet, the target data packet is delayed by at least one clock time to obtain a cached data packet; based on the segmented data identification information of the target data packet and the cached data packet, the packet start position and packet end position of the target data packet are determined.

[0064] Among them, the target data packet is the data packet currently received and parsed, that is, the data packet whose starting and ending positions are determined. For the convenience of description, it is defined as the target data packet. The segmented data identification information includes the segmented valid identification of each segment after the data packet sent and received by the segmented interface is segmented. After the network communication module of the target processor receives the data packet, it can be cached once, and the packet starting position and packet ending position can be parsed through the segmented data identification information and then cached into the data cache module. Exemplarily, the packet starting position and packet ending position can be determined by performing logical operations on the segmented data identification information before and after caching.

[0065] Exemplarily, when the loopback test device includes a multi-channel switching device, the present invention also provides an implementation process for implementing a synchronous loopback test of multi-channels with different types of packet lengths, which may include the following contents: When a first type of data packet and a second type of data packet are simultaneously received through the network communication module and the segmented interface; the first type of data packet is cached in the data cache module of the loopback test device through the first channel, and the first packet end position of the first type of data packet is sent to the read-write control logic module through the first channel, so that the read-write control logic module reads and writes the first type of data packet from the data cache module based on the first packet end position when the data cache module reaches a critical storage threshold condition; the second type of data packet is cached in the data cache module of the loopback test device through the second channel, and the second packet end position of the second type of data packet is sent to the read-write control logic module through the second channel, so that the read-write control logic module reads and writes the second type of data packet from the data cache module based on the second packet end position when the data cache module reaches a critical storage threshold condition.

[0066] The packet lengths of the first type of data packets and the second type of data packets are different. To distinguish them, the channel for processing the first type of data packets is called the first channel, and the channel for processing the second type of data packets is called the second channel.

[0067] As can be seen from the above, the data cache module adopted in this embodiment can be reused to implement synchronous loopback testing of multi-channels with different types of packet lengths, thereby effectively improving the efficiency of the MAC loopback test of the target processor.

[0068] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method.

[0069] The loopback test device mentioned above is described from the perspective of functional modules. Furthermore, the present invention also provides an electronic device, which is described from the perspective of hardware. Fig. 9A schematic diagram of the structure of an electronic device provided in an embodiment of the present invention in one implementation manner. The electronic device includes a memory 901 and a processor 902, wherein the memory 901 stores a computer program, and the processor 902 is configured to run the computer program to execute the steps in any of the above loopback test method embodiments.

[0070] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any one of the above loopback test method embodiments when running.

[0071] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0072] An embodiment of the present invention further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above loopback test method embodiments are implemented.

[0073] An embodiment of the present invention further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above loopback test method embodiments are implemented.

[0074] Finally, the present invention also provides a loopback test system, see Fig.10 , may include a network card 11 and a target processor 12. When performing a loopback test on the target processor 12, the network card 11 and the target processor 12 can be deployed to different servers, or the network card 11 and the target processor 12 can be deployed in different card slots of the same server, such as different PCIE card slots, and the network card 11 and the target processor 12 communicate data via Ethernet. After the target processor is deployed with a loopback test device as described in any of the above embodiments, the communication quality between the network card and the target processor can be tested.

[0075] In order to make those skilled in the art more clearly understand the implementation of the present invention, the present invention also provides an exemplary implementation, such as Fig.11 As shown, it may include the following: In this embodiment, the target processor is an Agilex accelerator card, the network card is a 200G / 400G network card, the network communication module is an Agilex network card, the data cache module is an asynchronous FIFO, and the read-write control logic module includes Figure 6 The read control logic circuit shown and Figure 7 In the write control logic circuit shown, the multi-channel selection device can be a MUX. First, the 200G / 400G network card and the Agilex accelerator card are respectively inserted into the two PCIe card slots of the same server. The server where the 200G / 400G network card is located is installed and configured with the DPDK packet self-test environment. The 200G / 400G network card is directly connected to the Agilex network card through optical fiber, and the relevant parameters of the DPDK and the relevant parameters of the relevant registers of the Agilex accelerator card are configured. When the 200G / 400G network card is successfully connected to the Agilex network card, DPDK can be started for packet transmission and reception testing. After the Agilex network card receives the data packet, it is cached for one beat, and the packet start position and packet end position are parsed through inframe and then cached into the asynchronous FIFO, and the read and write control of the asynchronous FIFO is controlled by the read and write control logic circuit, thereby realizing the loopback reading and writing of the data packet. During the MAC loopback test, the register can be connected to the peripheral port JTAG or UART through the APB bus. The empty threshold and full threshold of the asynchronous FIFO stored in the register can be adjusted in real time through the APB bus according to the different lengths of the data packets. The empty threshold and full threshold should meet the cache depth of at least one data packet length. In addition, the register can also monitor the internal state of the target processor during the MAC loopback test in real time. The MUX multiplexed loopback cache FIFO can realize the synchronous loopback test of multi-channel with different types of packet lengths.

[0076] As can be seen from the above, this embodiment is based on the programmable logic device FPGA as hardware implementation, and realizes the MAC loopback test based on the Segmented interface. The entire circuit is implemented using RTL, which is convenient for system maintenance and function expansion. By pre-fetching the end position of the data packet, it is fed back to the read control logic in advance to effectively control the read integrity of the last packet of data. At the same time, the empty threshold and the full threshold of the asynchronous FIFO are adjusted in real time through registers during the switching process of data packets of different sizes to match data packets of different lengths, effectively improving the loopback test bandwidth, and effectively preventing the tediousness of frequent compilation engineering verification, saving engineering debugging time, and improving the efficiency of MAC loopback testing. Compared with the traditional asynchronous + synchronous two-level cache method, the use of a first-level asynchronous FIFO and a variable threshold control method not only saves logic resources, but also simplifies the control logic. The read-write control logic ensures that there will be no packet break when reading and writing FIFO. Through real-time monitoring of the internal state, abnormal problems can be quickly located.

[0077] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0078] The above is a detailed introduction to a loopback test method, device, system, electronic device, computer-readable storage medium and computer program product provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A loopback test device, characterized in that: Including data cache module and read-write control logic module; The loopback test device is deployed on the target processor to test the network quality of the target processor; the target processor includes a network communication module, a segmented interface and a register, and the network communication module does not support the register to control the data loopback reading and writing between the receiving end and the sending end; Among them, the data cache module is connected to the network communication module through the segmented interface, and is configured to cache the data packets sent and received through the network communication module and the segmented interface; the read-write control logic module is connected to the data cache module, and is configured to read and write the last data packet from the data cache module according to the packet end position of the data packet when the data cache module reaches the critical storage threshold condition.

2. The loopback test device according to claim 1, characterized in that: The read-write control logic module is connected to the register, and the register is connected to the target peripheral interface of the target processor through a bus; The register stores the critical storage threshold condition so that the critical storage threshold condition can be adjusted through the target peripheral interface during a loopback test on the target processor.

3. The loopback test device according to claim 2, characterized in that: The data cache module adopts a first-in-first-out storage structure, and the critical storage threshold conditions include a nearly full threshold and a nearly empty threshold of the first-in-first-out; When the length of the data packet read or written from the data cache module changes, adjusting the almost full threshold and the almost empty threshold of the register through the target peripheral interface; The values ​​of the almost full threshold and the almost empty threshold both increase as the length of the data packet increases.

4. The loopback test device according to claim 3, characterized in that: The values ​​of the almost full threshold and the almost empty threshold are both increased by at least a length value of a data packet through the target peripheral interface.

5. The loopback test device according to any one of claims 1 to 4, characterized in that: The packet end position adopts a packet end mark, and the read-write control logic module includes a read control logic circuit; the read control logic circuit includes a read enable module, a read condition identification module and a read control signal generation module; The input signal of the read enable module is the data receiving preparation signal of the segmented interface, the data receiving preparation signal is subjected to timing synchronization processing, and the output is a valid read enable signal; The first input signal of the read condition recognition module is the critical storage threshold condition, and the second input signal is the pre-fetch signal of the packet end mark; when the packet end mark is detected and the empty threshold of the critical storage threshold condition is reached, a stop reading signal is output; when the conditions of detecting the packet end mark and reaching the empty threshold are not met at the same time, a read operation valid signal is output; Upon receiving the read operation valid signal, the read control signal generating module splices the valid read enable signal and the data non-empty signal of the data cache module to generate a read control signal; the read control signal controls reading the corresponding data packet from the data cache module.

6. The loopback test device according to claim 5, characterized in that: The transmitting end supports back pressure control, the read enable module includes a plurality of triggers, each trigger is interconnected, the input end of the first trigger inputs the data receiving ready signal, and the signal delay processing is performed in turn through each trigger, and the last trigger outputs a read enable signal; The total number of the triggers is determined according to the number of clock signals that the target processor is allowed to send when data is not accepted.

7. The loopback test device according to claim 5, characterized in that: The read enable module includes a first trigger and a first AND gate; The data receiving ready signal is respectively received to the first input terminal S of the first trigger and the first input terminal of the first AND gate, and the first output terminal of the first trigger and a second input terminal of the first AND gate; and a first output terminal of the first AND gate outputs the valid read enable signal.

8. The loopback test device according to claim 6, characterized in that: The read enable module at least includes a first trigger, a second trigger, a third trigger and a first AND gate; The second input terminal S of the second trigger inputs a data receiving ready signal, and the second output terminal Q of the second trigger is connected to the third input terminal S of the third trigger, and is used to output a delay signal corresponding to the data receiving ready signal; The third output terminal Q of the third trigger is respectively connected to the first input terminal S of the first trigger and the first input terminal of the first AND gate to receive the delay signal corresponding to the data receiving ready signal; the first output terminal of the first trigger Connected to the second input terminal of the first AND gate, the first output terminal of the first AND gate and the output signal of the third output terminal Q of the third flip-flop are used as a valid read enable signal.

9. The loopback test device according to claim 5, characterized in that: The read condition identification module includes a first NAND gate, and the first NAND gate includes a third input terminal, a fourth input terminal, and a second output terminal; Among them, the third input terminal receives the signal corresponding to the critical storage threshold condition, the fourth input terminal receives the pre-fetch signal of the packet end mark; the second output terminal outputs the read operation valid signal or the stop reading signal.

10. The loopback test device according to claim 5, characterized in that: The read control signal generating module includes a second AND gate, a first OR gate, a first NOT gate and a third AND gate; The fifth input terminal of the second AND gate receives a delay signal, the sixth input terminal receives the read operation valid signal or the stop reading signal, and the third output terminal is connected to the seventh input terminal of the first OR gate; the eighth input terminal of the first OR gate receives a rising edge signal corresponding to the read enable signal, the fourth output terminal of the first OR gate is connected to the tenth input terminal of the third AND gate, the ninth input terminal of the first NOT gate receives a data empty signal of the data cache module, the fifth output terminal of the first NOT gate is connected to the eleventh input terminal of the third AND gate, and the sixth output terminal of the third AND gate outputs the read control signal.

11. The loopback test device according to any one of claims 1 to 4, characterized in that: The read-write control logic module includes a write control logic circuit; the write control logic circuit includes a write enable signal generation module and a write control signal generation module; Wherein, the input signal of the write enable signal generating module is the critical storage threshold condition, the packet end position and the segmented data identification information, and when the threshold value of reaching the critical storage threshold condition is not satisfied at the same time, and the bus corresponding to the segmented interface is in an idle state and has no valid data, a write enable valid signal is output; when the threshold value of reaching the critical storage threshold condition is satisfied at the same time, and the bus corresponding to the segmented interface is in an idle state and has no valid data, a write enable invalid signal is output; The write control signal generating module outputs a write control signal upon receiving the write enable valid signal and the data valid signal, so as to write a corresponding data packet in the data cache module through the write control signal; The segmented data identification information includes segmented valid identification of each segment after the data packet received and sent through the segmented interface is segmented.

12. The loopback test device according to claim 11, characterized in that: The write enable signal generating module comprises a second OR gate, a second NOT gate and a second NAND gate; The twelfth input terminal of the second OR gate receives the segment data identification information, the thirteenth input terminal receives the packet end mark, the second OR gate performs an OR operation on the segment data identification information and the packet end mark, and inputs the OR result to the fourteenth input terminal of the second NOT gate through the seventh output terminal; the second NOT gate performs a NOT operation on the OR result, and inputs the NOT operation result to the sixteenth input terminal of the second NAND gate through the eighth output terminal, the fifteenth input terminal of the second NAND gate inputs the almost full threshold signal of the critical storage threshold condition, performs an AND NOT operation on the almost full threshold signal and the NOT operation result, and uses the generated AND NOT operation result as a write enable signal, and outputs it through the ninth output terminal; The write enable signal includes a write enable valid signal and a write enable invalid signal.

13. The loopback test device according to claim 11, characterized in that: The write control signal generating module includes a fourth AND gate, and the fourth AND gate includes a seventeenth input terminal and an eighteenth input terminal; The seventeenth input terminal receives a data valid signal, the eighteenth input terminal receives a write enable signal, and outputs an AND operation result of the data valid signal and the write enable signal to the data cache module through the tenth output terminal.

14. A loopback test method, characterized in that: Deploying the loopback test device according to any one of claims 1 to 13 on a target processor comprises: When the network communication module of the target processor is successfully connected to the network card, a data packet sending and receiving test is started; Cache the data packets received and sent through the network communication module and the segmented interface in the data cache module of the loopback test device; The obtained packet end position is sent to the read / write control logic module, so that the read / write control logic module reads and writes the last data packet from the data cache module based on the packet end position when the data cache module reaches a critical storage threshold condition.

15. The loopback test method according to claim 14, characterized in that: Before sending the acquired packet end position to the read-write control logic module, the method further includes: When the network communication module receives the target data packet, the target data packet is delayed by at least one clock time to obtain a cached data packet; Determine the packet start position and packet end position of the target data packet according to the segment data identification information of the target data packet and the cached data packet; The segmented data identification information includes segmented valid identification of each segment after the data packet received and sent by the segmented interface is segmented.

16. The loopback test method according to claim 14, characterized in that: After starting the packet sending and receiving test, it also includes: When a first type of data packet and a second type of data packet are simultaneously received through the network communication module and the segmented interface; wherein the packet lengths of the first type of data packet and the second type of data packet are different; Cache the first type of data packet in the data cache module of the loopback test device through the first channel, and send the first packet end position of the first type of data packet to the read-write control logic module through the first channel, so that the read-write control logic module reads and writes the first type of data packet from the data cache module based on the first packet end position when the data cache module reaches a critical storage threshold condition; The second type of data packet is cached in the data cache module of the loopback test device through the second channel, and the second packet end position of the second type of data packet is sent to the read-write control logic module through the second channel, so that the read-write control logic module reads and writes the second type of data packet from the data cache module based on the second packet end position when the data cache module reaches a critical storage threshold condition.

17. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the loopback test method according to any one of claims 14 to 16 when executing the computer program.

18. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the loopback test method according to any one of claims 14 to 16 are implemented.

19. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the loopback test method described in any one of claims 14 to 16 are implemented.

20. A loopback test system, characterized in that: Includes network card and target processor; The network card and the target processor are respectively deployed to different servers, or the network card and the target processor are deployed in different card slots of the same server; the network card and the target processor perform data communication via Ethernet; The target processor deploys the loopback test device as described in any one of claims 1 to 13 to test the communication quality between the network card and the target processor.

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