Packaging substrate, manufacturing method thereof, electric drive system and vehicle

Abstract

The application provides a packaging substrate and a manufacturing method thereof, an electric driving system and a vehicle, a transmission layer group and a power chip embedded in the transmission layer group, and a first circuit layer, a second circuit layer, a top layer and a power negative electrode layer; the transmission layer group has a first surface and a second surface arranged away from each other along a stacking direction of the packaging substrate, the first circuit layer is stacked on the first surface, and the second circuit layer is stacked on the second surface; the first circuit layer is provided with a first potential transmission part and a negative electrode potential part, the second circuit layer is provided with a second potential transmission part and a positive electrode potential part; the power negative electrode layer is stacked on a side of the first circuit layer away from the first surface and connected to the negative electrode potential part, and the top layer is stacked on the power negative electrode layer.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electric drive control, and more particularly to a packaging substrate and a manufacturing method thereof, an electric drive system and a vehicle. BACKGROUND

[0002] Generally, in the drive system of an electric drive vehicle, the main drive circuit board based on an embedded system adopts an even-numbered symmetric board layer structure, for example, 6 layers or 8 layers. The manufacturing process of the even-numbered symmetric board layer structure is simple and the board warping is small. In actual application, the 6-layer board layer structure is difficult to layout various devices and cannot meet the design requirement of low parasitic inductance. The 8-layer board layer structure has a large heat dissipation requirement due to the large number of layers, and the heat dissipation design of the circuit board is high.

[0003] As shown in Figure 1 , taking a 6-layer board layer structure as an example, along the direction from top to bottom, the first layer 10 is used to arrange devices, the second layer 20 is provided with a first control line and a first power line arranged in sequence along the horizontal direction, the third layer 30 and the fourth layer 40 are used to embed a power chip 70, and the fifth layer 50 is provided with a second power line and a second control line arranged in sequence along the horizontal direction. As can be seen from the figure, the second layer 20 and the fifth layer 50 respectively adopt a partitioning mode to contain different lines arranged along the horizontal direction, resulting in a small layer stacking of the first power line and the first control line, the first control line and the second power line, and a large parasitic inductance of the loop, which cannot meet the design requirement of low parasitic inductance. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a packaging substrate and a manufacturing method thereof, an electric drive system and a vehicle, so as to solve the technical problems that the existing even-numbered board layer structure cannot meet the requirements of low parasitic inductance and high heat dissipation.

[0005] To achieve the above-mentioned purpose, the technical scheme adopted by the present application is:

[0006] A packaging substrate is provided, comprising a transmission layer group and a power chip embedded in the transmission layer group, and a first circuit layer, a second circuit layer, a top layer and a power negative electrode layer.

[0007] The transmission layer group has a first surface and a second surface arranged away along the layer stacking direction of the packaging substrate, the first circuit layer is stacked on the first surface, and the second circuit layer is stacked on the second surface; the first circuit layer is provided with a first potential transmission part and a negative electrode potential part spaced from the first potential transmission part, and the second circuit layer is provided with a second potential transmission part and a positive electrode potential part spaced from the second potential transmission part; the first potential transmission part and the positive electrode potential part are oppositely arranged along the layer stacking direction, and the second potential transmission part and the negative electrode potential part are oppositely arranged along the layer stacking direction.

[0008] and the power supply negative electrode layer is laminated on a side of the first circuit layer facing away from the first surface and connected to the negative electrode potential part, and the top layer is laminated on the power supply negative electrode layer.

[0009] In some embodiments, the packaging substrate further comprises a metal weight layer and a weight insulating layer;

[0010] The weight insulating layer is laminated on a side of the second circuit layer facing away from the second surface, and the metal weight layer is laminated on a side of the weight insulating layer facing away from the second surface, and the weight of the metal weight layer is equal to the sum of the weights of the power supply negative electrode layer and the top layer.

[0011] In some embodiments, the thickness dimension of the metal weight layer along the lamination direction is equal to the sum of the thickness dimensions of the power supply negative electrode layer and the top layer along the lamination direction.

[0012] In some embodiments, the packaging substrate further comprises a metal weight layer and a weight insulating layer;

[0013] The weight insulating layer is laminated on a side of the second circuit layer facing away from the second surface, and the metal weight layer is laminated on a side of the weight insulating layer facing away from the second surface, and the sum of the weights of the metal weight layer and the weight insulating layer is equal to the sum of the weights of the power supply negative electrode layer and the top layer.

[0014] In some embodiments, the thickness dimension of the metal weight layer along the lamination direction is less than the sum of the thickness dimensions of the power supply negative electrode layer and the top layer along the lamination direction, and the thickness dimension of the weight insulating layer along the lamination direction is greater than the sum of the thickness dimensions of the power supply negative electrode layer and the top layer along the lamination direction.

[0015] In some embodiments, the metal weight layer, the power supply negative electrode layer, and the top layer are made of the same material.

[0016] In some embodiments, the power chip is embedded in the transmission layer group between the positive electrode potential part and the first potential transmission part along the lamination direction, and the power chip is embedded in the transmission layer group between the second potential transmission part and the negative electrode potential part along the lamination direction.

[0017] The packaging substrate provided by the present application has the following beneficial effects:

[0018] The packaging substrate provided by the present application adds a power supply negative electrode layer, which is laminated on a side of the first circuit layer facing away from the first surface, and realizes the lamination of the positive electrode potential part and the first potential transmission part and the lamination of the first potential transmission part and the power supply negative electrode layer along the lamination direction of the packaging substrate, thereby meeting the design requirement of low parasitic loop inductance.

[0019] For example, compared with the existing 6-layer board layer structure, the power negative electrode layer is additionally provided, and the power negative electrode layer is stacked on the side of the first circuit layer away from the first surface, so that the positive electrode potential part and the first potential transmission part and the first potential transmission part and the power negative electrode layer are stacked, thereby meeting the design requirement of low parasitic loop inductance.

[0020] For example, compared with the existing 8-layer board layer structure, the packaging substrate provided in the present application additionally provides a power negative electrode layer, so that the design of an odd number of layers can be realized, and the design requirement for heat dissipation can be reduced compared with 8 layers, thereby reducing the design cost compared with 8 layers.

[0021] Another object of the present application is to provide an electric drive system comprising the packaging substrate as described above.

[0022] The electric drive system provided in the present application has the same beneficial effects as the packaging substrate provided in the present application compared with the prior art, which will not be described here.

[0023] Another object of the present application is to provide a vehicle comprising the packaging substrate as described above; or, the vehicle comprises the electric drive system as described above.

[0024] The vehicle provided in the present application has the same beneficial effects as the packaging substrate or the electric drive system provided in the present application compared with the prior art, which will not be described here.

[0025] Another object of the present application is to provide a manufacturing method of a packaging substrate, the manufacturing method comprising:

[0026] providing a first pre-prepared layer group, comprising a transmission layer group having a first surface and a second surface, a power chip embedded in the transmission layer group, a first circuit layer stacked on the first surface, and a second circuit layer stacked on the second surface; wherein the first circuit layer is provided with a first potential transmission part and a negative electrode potential part spaced apart from the first potential transmission part, and the second circuit layer is provided with a second potential transmission part and a positive electrode potential part spaced apart from the second potential transmission part; the first potential transmission part and the positive electrode potential part are oppositely arranged along the stacking direction, and the second potential transmission part and the negative electrode potential part are oppositely arranged along the stacking direction;

[0027] providing a second pre-prepared layer group, comprising a power negative electrode layer and a top layer stacked on the power negative electrode layer, stacking the second pre-prepared layer group on the first pre-prepared layer group, and stacking the power negative electrode layer on the side of the first circuit layer away from the first surface.

[0028] In some embodiments, before or after the second pre-prepared layer group is laminated on the first pre-prepared layer group, the manufacturing method further comprises:

[0029] providing a third pre-prepared layer group comprising a metal weight layer and a weight insulating layer laminated on the metal weight layer, laminating the third pre-prepared layer group on the first pre-prepared layer group, and laminating the weight insulating layer on the side of the second circuit layer away from the second surface.

[0030] Another object of the present application is to provide a manufacturing method of a packaging substrate, which comprises:

[0031] providing a pre-prepared layer group comprising a transmission layer group having a first surface and a second surface, a power chip embedded in the transmission layer group, a first circuit layer laminated on the first surface, a second circuit layer laminated on the second surface, and a weight insulating layer laminated on the second circuit layer; wherein the first circuit layer is provided with a first potential transmission part and a negative potential part spaced apart from the first potential transmission part, and the second circuit layer is provided with a second potential transmission part and a positive potential part spaced apart from the second potential transmission part; the first potential transmission part and the positive potential part are oppositely arranged along the lamination direction, and the second potential transmission part and the negative potential part are oppositely arranged along the lamination direction;

[0032] laminating a power supply negative electrode layer on the side of the first circuit layer away from the first surface;

[0033] laminating a metal weight layer on the side of the weight insulating layer away from the second surface;

[0034] laminating a top layer on the side of the power supply negative electrode layer away from the first surface.

[0035] Another object of the present application is to provide a manufacturing method of a packaging substrate, which comprises:

[0036] providing a pre-prepared layer group comprising a transmission layer group having a first surface and a second surface, a power chip embedded in the transmission layer group, a first circuit layer laminated on the first surface, a second circuit layer laminated on the second surface, and a weight insulating layer laminated on the second circuit layer; wherein the first circuit layer is provided with a first potential transmission part and a negative potential part spaced apart from the first potential transmission part, and the second circuit layer is provided with a second potential transmission part and a positive potential part spaced apart from the second potential transmission part; the first potential transmission part and the positive potential part are oppositely arranged along the lamination direction, and the second potential transmission part and the negative potential part are oppositely arranged along the lamination direction;

[0037] stacking a power negative electrode layer on a side of the first circuit layer away from the first surface;

[0038] stacking a metal weight layer on a side of the weight insulating layer away from the second surface along a part of thickness in the stacking direction;

[0039] stacking a top layer on a side of the power negative electrode layer away from the first surface;

[0040] stacking the metal weight layer on a side of the part of thickness away from the second surface along another part of thickness in the stacking direction.

[0041] The packaging substrate provided by the application has the following advantages:

[0042] The packaging substrate provided by the application adds a power negative electrode layer in the manufacturing process, and stacks the power negative electrode layer on a side of the first potential transmission part and the negative potential part away from the first surface along the stacking direction of the packaging substrate, thereby realizing the stacking of the positive potential part and the first potential transmission part and the stacking of the first potential transmission part and the power negative electrode layer, and meeting the design requirement of low parasitic loop inductance.

[0043] For example, by using the manufacturing method of the packaging substrate provided by the application, a power negative electrode layer is added on the basis of the existing 6-layer board layer structure, thereby realizing the manufacturing of an odd number of layers, reducing the manufacturing requirement of the packaging substrate on heat dissipation compared with 8 layers, and thereby reducing the manufacturing cost compared with 8 layers. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0045] Figure 1 The figure is a schematic diagram of the existing 6-layer board layer structure;

[0046] Figure 2 The figure is a packaging substrate provided by an embodiment of the application, which has 7 metal layers;

[0047] Figure 3 The figure is a flowchart of the manufacturing method of the packaging substrate provided by an embodiment of the application;

[0048] Figure 4 The figure is a flowchart of the manufacturing method of the packaging substrate provided by another embodiment of the application;

[0049] Figure 5A flowchart of a method for manufacturing a packaging substrate according to another embodiment of the present application is provided.

[0050] Figure 6 A flowchart of a method for manufacturing a packaging substrate according to another embodiment of the present application is provided.

[0051] In the drawings:

[0052] 100, top layer; 201, negative potential part; 202, power supply negative layer; 300, metal hole; 301, first potential transmission part; 302, second potential transmission part; 400, positive potential part; 500, transmission layer group; 501, first signal transmission layer; 502, second signal transmission layer; 600, power chip; 700, counterweight insulating layer; 800, metal counterweight layer. DETAILED DESCRIPTION

[0053] In order to make the technical problems to be solved, technical solutions and beneficial effects of the present application clearer, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.

[0054] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0055] It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0056] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0057] Now the packaging substrate and the manufacturing method thereof, the electric drive system and the vehicle according to the embodiments of the present application will be described.

[0058] Please refer toFigure 2 The packaging substrate provided by the embodiment of the present application comprises a transmission layer group 500, a power chip 600 embedded in the transmission layer group 500, and a first circuit layer, a second circuit layer, a top layer 100 and a power negative electrode layer 202.

[0059] The transmission layer group 500 has a first surface and a second surface arranged away from each other along the stacking direction of the packaging substrate, the first circuit layer is stacked on the first surface, and the second circuit layer is stacked on the second surface; the first circuit layer is provided with a first potential transmission part 301 and a negative electrode potential part 201 spaced apart from the first potential transmission part 301, and the second circuit layer is provided with a second potential transmission part 302 and a positive electrode potential part 400 spaced apart from the second potential transmission part 302; the first potential transmission part 301 and the positive electrode potential part 400 are oppositely arranged along the stacking direction, and the second potential transmission part 302 and the negative electrode potential part 201 are oppositely arranged along the stacking direction.

[0060] The power negative electrode layer 202 is stacked on the side of the first circuit layer away from the first surface and connected to the negative electrode potential part 201, and the top layer 100 is stacked on the power negative electrode layer 202.

[0061] The packaging substrate refers to a structure in which a plurality of layers are sequentially stacked along the stacking direction and a plurality of different functional devices are integrated on the surface and inside thereof, the layers include but are not limited to metal layers, protective layers, dielectric layers, insulating layers, etc., the plurality of layers constitute the main part of the packaging substrate and play the roles of supporting and conducting electricity, and each functional device is arranged on the surface or inside of the plurality of layers. The plurality of layers of the packaging substrate and the functions of each layer are known to those skilled in the art, and the embodiment of the present application does not make a detailed description thereof. The power chip 600 is embedded in the transmission layer group 500, and the embedding mode of the power chip 600 and the connection relationship between different ends of the power chip 600 and each layer are known to those skilled in the art, and the embodiment of the present application does not make a detailed description thereof. Generally, the packaging substrate can be a PCB (Printed Circuit Board, printed circuit board), also known as a printed wiring board.

[0062] Generally, the power chip is embedded in the transmission layer group 500, and the first circuit layer and the second circuit layer refer to two metal layer structures located on the outside of the transmission layer group 500, the first circuit layer and the second circuit layer have the interconnection function of electricity and / or signals and play the role of connecting the substrate to the external circuit, the thickness size of the first circuit layer and the second circuit layer is customized according to different requirements, and the material thereof can be one of copper, aluminum, copper-aluminum alloy and other metals or metal alloys.

[0063] In the actual packaging substrate, insulating layers can be optionally arranged between the layer structures inside the transmission layer group 500, between the transmission layer group 500 and the first and second circuit layers, and between the first and second circuit layers and the layer structures located outside the first and second circuit layers. The embodiments do not describe the insulating layers and other metal layers in detail.

[0064] Generally, the power negative electrode layer 202, the negative potential part 201, and the positive potential part 400 have the interconnection function of electricity and / or signals, and serve to connect the substrate to an external circuit. The thickness of the power negative electrode layer 202 is customized according to different requirements, and the material of the power negative electrode layer 202 can be one of metals or metal alloys such as copper, aluminum, and copper-aluminum alloy. In some embodiments, the power negative electrode layer 202 can be a copper foil. The positive potential part 400 can be referred to as DC+, and the power negative electrode layer can also be referred to as DC-. The functions of the power negative electrode layer 202, the negative potential part 201, and the positive potential part 400 in the packaging substrate, the layering relationship with other layer structures, and the connection relationship with functional devices are known to those skilled in the art, and the embodiments of the present application do not describe them in detail.

[0065] Generally, the first potential transmission part 301 and the second potential transmission part 302 have the interconnection function of electricity and / or signals, and the power chip 600 can be connected to electricity or input / output signals through the potential transmission part and / or signal transmission layer. The first potential transmission part 301 and the second potential transmission part 302 can be referred to as two electrodes of AC. The functions of the potential transmission part and the layering relationship with other layer structures, and the connection relationship with functional devices are known to those skilled in the art, and the embodiments of the present application do not describe them in detail.

[0066] Generally, the first potential transmission part 301 and the second potential transmission part 302 are connected through the metal hole 300. The metal hole 300 refers to a part between the two first and second circuit layers on the packaging substrate, which is perforated and plated with metal on the hole wall to electrically connect the first potential transmission part 301 and the second potential transmission part 302. The aperture and number of the metal hole 300 are customized according to different requirements. The material, function, and connection relationship with each layer structure of the metal hole 300 are known to those skilled in the art, and the embodiments of the present application do not describe them in detail.

[0067] The packaging substrate provided by the embodiments of the present application adds the power negative electrode layer 202, which is laminated on the side of the first potential transmission part 301 and the negative potential part 201 away from the first surface, and realizes the lamination of the positive potential part 400 and the first potential transmission part 301, and the lamination of the first potential transmission part 301 and the power negative electrode layer 202 along the lamination direction of the packaging substrate, thereby meeting the design requirement of low parasitic loop inductance.

[0068] For example, compared with the existing 6-layer board layer structure as shown in Figure 1 The power supply negative electrode layer 202 is added, and the power supply negative electrode layer 202 is stacked on the side of the first potential transmission part 301 and the negative electrode potential part 201 away from the first surface along the stacking direction of the packaging substrate, so as to realize the stacking of the positive electrode potential part 400 and the first potential transmission part 301 and the stacking of the first potential transmission part 301 and the power supply negative electrode layer 202, thereby meeting the design requirement of low parasitic loop inductance.

[0069] For example, compared with the existing 8-layer board layer structure, the packaging substrate provided by the embodiment of the present application adds the power supply negative electrode layer 202, so as to realize the design of an odd number of layers, and the design requirement for heat dissipation can be reduced compared with 8 layers, thereby reducing the design cost compared with 8 layers.

[0070] It should be noted that the number of layers of the existing 6-layer and 8-layer board layer structure mentioned in the embodiment of the present application refers to the number of metal layers of the board layer structure, and the number of layers of the odd number of layers of the packaging substrate mentioned in the embodiment of the present application refers to the number of metal layers of the packaging substrate. For example, the packaging substrate provided by the embodiment of the present application can be 7 metal layers. The packaging substrate mentioned in the embodiment of the present application does not only include metal layers, but can also include layers of other materials, such as non-metallic insulating layers, such as dielectric layers or protective layers of other materials, and these layers can be arranged between any two adjacent layers of the packaging substrate or any outer surface of the packaging substrate according to actual needs. The arrangement and function of these layers are selected according to needs, which is a common technology in the art, and the present application does not make specific limitations.

[0071] As shown in Figure 2 The transmission layer group 500 can include two signal transmission layers, namely a first signal transmission layer 501 and a second signal transmission layer 502, and an insulating layer can be arranged between the two signal transmission layers. Generally, the signal transmission layer refers to a layer structure inside the first line layer and the second line layer, and has the function of electrical and / or signal interconnection. The number of layers and the thickness of the signal transmission layer are customized according to different needs. The material, function and stacking relationship with other layer structures of the signal transmission layer, and the connection relationship with each functional device are common technologies in the art, and the embodiment of the present application does not make detailed description.

[0072] It should be noted that the metal counterweight layer 800 and the counterweight insulating layer 700 mentioned in the embodiment of the present application can be arranged for the purpose of counterweight, but are not limited to providing the function of counterweight. For example, the metal counterweight layer 800 can be optionally connected with each functional device or layer structure in the packaging substrate according to specific needs to play a role other than counterweight. In the actual packaging substrate, the side of the metal counterweight layer 800 away from the top layer 100 can be provided with a cooling flow channel to provide cooling effect for the packaging substrate.

[0073] In some embodiments, the packaging substrate further comprises a metal weight layer 800 and a weight insulation layer 700, the weight insulation layer 700 is laminated on the side of the second circuit layer away from the second surface, and the metal weight layer 800 is laminated on the side of the weight insulation layer 700 away from the second surface, and the weight of the metal weight layer 800 is equal to the sum of the weights of the power negative electrode layer 202 and the top layer 100.

[0074] As an example, as shown in Figure 2 , along the lamination direction of the packaging substrate, the top layer 100, the power negative electrode layer 202, the first potential transmission part 301, the first signal transmission layer 501, the second signal transmission layer 502, the positive electrode potential part 400, and the metal weight layer 800 constitute an odd number of 7 layers of metal layers. Compared with the 6-layer board layer structure as shown in Figure 1 , along the lamination direction of the packaging substrate, the 7-layer metal layer substrate realizes the lamination of the positive electrode potential part 400 and the first potential transmission part 301 and the first potential transmission part 301 and the power negative electrode layer 202, thereby meeting the design requirement of low parasitic loop inductance. Compared with the 8-layer board layer structure, the design requirement for heat dissipation can be reduced, thereby reducing the design cost compared with the 8-layer.

[0075] As an example, the above-mentioned 7-layer metal layer substrate considers that the manufacturing process of the 7-layer substrate may cause larger warping, and therefore the metal weight layer 800 is added to be separated by the weight insulation layer 700. Since the weight insulation layer 700 can be ignored when its thickness is small, or it can be equal to the weight of the insulation layer between the power negative electrode layer 202 and the first circuit layer, the weight of the metal weight layer 800 is equal to the sum of the weights of the power negative electrode layer 202 and the top layer 100, so as to realize smaller warping and basically not change the heat dissipation effect.

[0076] In some embodiments, the weight of the metal weight layer 800 is equal to the sum of the weights of the power negative electrode layer 202 and the top layer 100 by making the thickness dimension of the metal weight layer 800 along the lamination direction equal to the sum of the thickness dimensions of the power negative electrode layer 202 and the top layer 100 along the lamination direction.

[0077] In some embodiments, the packaging substrate further comprises a metal weight layer 800 and a weight insulation layer 700; the weight insulation layer 700 is laminated on the side of the second circuit layer away from the second surface, and the metal weight layer 800 is laminated on the side of the weight insulation layer 700 away from the second surface, and the sum of the weights of the metal weight layer 800 and the weight insulation layer 700 is equal to the sum of the weights of the power negative electrode layer 202 and the top layer 100.

[0078] Specifically, the thickness dimension of the metal weight layer 800 along the stacking direction is less than the sum of the thickness dimensions of the power negative electrode layer 202 and the top layer 100 along the stacking direction, and the thickness dimension of the weight insulating layer 700 along the stacking direction is greater than the sum of the thickness dimensions of the power negative electrode layer 202 and the top layer 100 along the stacking direction. In this way, by making the thickness dimension of the weight insulating layer 700 along the stacking direction much greater than the sum of the thickness dimensions of the power negative electrode layer 202 and the top layer 100 along the stacking direction, for example, greater than twice the sum of the thickness dimensions of the power negative electrode layer 202 and the top layer 100 along the stacking direction, a smaller warping is achieved without substantially changing the heat dissipation effect. In some embodiments, the metal weight layer 800, the power negative electrode layer 202, and the top layer 100 are made of the same material, for example, all of them can be made of copper.

[0079] In some embodiments, the power chip 600 is embedded in the transmission layer group 500 between the positive electrode potential part 400 and the first potential transmission part 301 along the stacking direction, and the power chip 600 is embedded in the transmission layer group 500 between the second potential transmission part 302 and the negative electrode potential part 201 along the stacking direction.

[0080] Another object of the embodiments of the present application is to provide an electric drive system, which comprises the packaging substrate as above. The electric drive system provided by the embodiments of the present application has the same beneficial effects as the packaging substrate provided by the embodiments of the present application compared with the prior art, which will not be described here again.

[0081] Another object of the embodiments of the present application is to provide a vehicle, which comprises the packaging substrate as above; or, the vehicle comprises the electric drive system as above. The vehicle provided by the embodiments of the present application has the same beneficial effects as the packaging substrate or the electric drive system provided by the embodiments of the present application compared with the prior art, which will not be described here again.

[0082] As shown in Figure 3 and Figure 4 Another object of the embodiments of the present application is to provide a manufacturing method of a packaging substrate, which comprises:

[0083] 1001、providing a first pre-layer group, including a transmission layer group 500 having a first surface and a second surface, a power chip 600 embedded in the transmission layer group 500, and a first circuit layer laminated on the first surface and a second circuit layer laminated on the second surface; wherein the first circuit layer is provided with a first potential transmission part 301 and a negative potential part 201 spaced apart from the first potential transmission part 301, and the second circuit layer is provided with a second potential transmission part 302 and a positive potential part 400 spaced apart from the second potential transmission part 302; the first potential transmission part 301 and the positive potential part 400 are oppositely arranged along a lamination direction, and the second potential transmission part 302 and the negative potential part 201 are oppositely arranged along the lamination direction;

[0084] 1002、providing a second pre-layer group, including a power negative electrode layer 202 and a top layer 100 laminated on the power negative electrode layer 202, laminating the second pre-layer group on the first pre-layer group, and laminating the power negative electrode layer 202 on a side of the first circuit layer away from the first surface.

[0085] In some embodiments, before or after the step of providing the second pre-layer group, including the power negative electrode layer 202 and the top layer 100 laminated on the power negative electrode layer 202, laminating the second pre-layer group on the first pre-layer group, and laminating the power negative electrode layer 202 on a side of the first potential transmission part 301 and the negative potential part 201 away from the first surface, the manufacturing method further includes:

[0086] 1003、providing a third pre-layer group, including a metal counterweight layer 800 and a counterweight insulating layer 700 laminated on the metal counterweight layer 800, laminating the third pre-layer group on the first pre-layer group, and laminating the counterweight insulating layer 700 on a side of the second circuit layer away from the second surface.

[0087] As shown in Figure 3 and Figure 4 , the steps 1012 and 1013 can be operated simultaneously, or one can be operated before the other.

[0088] As shown in Figure 5 , another object of the embodiments of the present application is to provide a manufacturing method of a packaging substrate, which includes:

[0089] 1011、provide a pre-prepared layer group, including a transmission layer group 500 having a first surface and a second surface, a power chip 600 embedded in the transmission layer group 500, and a first circuit layer stacked on the first surface, a second circuit layer stacked on the second surface, and a counterweight insulating layer 700 stacked on the second circuit layer; wherein the first circuit layer is provided with a first potential transmission part 301 and a negative potential part 201 spaced apart from the first potential transmission part 301, and the second circuit layer is provided with a second potential transmission part 302 and a positive potential part 400 spaced apart from the second potential transmission part 302; the first potential transmission part 301 and the positive potential part 400 are oppositely arranged along the stacking direction, and the second potential transmission part 302 and the negative potential part 201 are oppositely arranged along the stacking direction;

[0090] 1012、stack the power negative layer 202 on the side of the first circuit layer away from the first surface;

[0091] 1013、stack the metal counterweight layer 800 on the side of the counterweight insulating layer 700 away from the second surface;

[0092] 1014、stack the top layer 100 on the side of the power negative layer 202 away from the first surface.

[0093] As Figure 6 shown, another purpose of the embodiment of the application is to provide a packaging substrate manufacturing method, which comprises:

[0094] 1111、provide a pre-prepared layer group, including a transmission layer group 500 having a first surface and a second surface, a power chip 600 embedded in the transmission layer group 500, and a first circuit layer stacked on the first surface, a second circuit layer stacked on the second surface, and a counterweight insulating layer 700 stacked on the second circuit layer; wherein the first circuit layer is provided with a first potential transmission part 301 and a negative potential part 201 spaced apart from the first potential transmission part 301, and the second circuit layer is provided with a second potential transmission part 302 and a positive potential part 400 spaced apart from the second potential transmission part 302; the first potential transmission part 301 and the positive potential part 400 are oppositely arranged along the stacking direction, and the second potential transmission part 302 and the negative potential part 201 are oppositely arranged along the stacking direction;

[0095] 1112、stack the power negative layer 202 on the side of the first circuit layer away from the first surface;

[0096] 1113、stack the metal counterweight layer 800 on the side of the counterweight insulating layer 700 away from the second surface along a part of the thickness in the stacking direction;

[0097] 1114、stack the top layer 100 on the side of the power negative layer 202 away from the first surface;

[0098] 1115、stacking the metal weight layer 800 along another part of the thickness of the layer structure away from the second surface on one side of the part of the thickness.

[0099] The packaging substrate provided by the embodiment of the present application provides and adds the power negative electrode layer 202 in the manufacturing process, and stacks the power negative electrode layer 202 away from the first surface on one side of the first potential transmission part 301 and the negative potential part 201, along the stacking direction of the packaging substrate, realizes the stacking of the positive potential part 400 and the first potential transmission part 301 and the first potential transmission part 301 and the power negative electrode layer 202, thereby meeting the design requirement of low parasitic loop inductance.

[0100] For example, by the manufacturing method of the packaging substrate provided by the embodiment of the present application, the power negative electrode layer 202 is added on the basis of the existing 6-layer layer structure, thereby realizing the manufacturing of the odd layer, and compared with the 8-layer, the manufacturing requirement of heat dissipation of the packaging substrate can be reduced, thereby the manufacturing cost can be reduced compared with the 8-layer.

[0101] The above only describes the preferred embodiments of the present application and is not intended to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A packaging substrate, characterized in that: It includes a transmission layer group (500) and a power chip (600) embedded in the transmission layer group (500), as well as a first line layer, a second line layer, a top layer (100) and a power supply negative layer (202); The transmission layer group (500) has a first surface and a second surface disposed opposite to each other along the stacking direction of the packaging substrate. The first circuit layer is stacked on the first surface, and the second circuit layer is stacked on the second surface. The first circuit layer is provided with a first potential transmission portion (301) and a negative potential portion (201) spaced apart from the first potential transmission portion (301). The second circuit layer is provided with a second potential transmission portion (302) and a positive potential portion (400) spaced apart from the second potential transmission portion (302). The first potential transmission portion (301) and the positive potential portion (400) are disposed opposite to each other along the stacking direction, and the second potential transmission portion (302) and the negative potential portion (201) are disposed opposite to each other along the stacking direction. Furthermore, the power supply negative electrode layer (202) is stacked on the side of the first circuit layer away from the first surface and connected to the negative electrode potential portion (201), and the top layer (100) is stacked on the power supply negative electrode layer (202).

2. The packaging substrate as described in claim 1, characterized in that: The packaging substrate also includes a metal counterweight layer (800) and a counterweight insulating layer (700); The counterweight insulation layer (700) is stacked on the side of the second circuit layer away from the second surface, and the metal counterweight layer (800) is stacked on the side of the counterweight insulation layer (700) away from the second surface. The weight of the metal counterweight layer (800) is equal to the sum of the weights of the power supply negative electrode layer (202) and the top layer (100).

3. The packaging substrate as described in claim 2, characterized in that: The thickness of the metal counterweight layer (800) along the stacking direction is equal to the sum of the thicknesses of the power supply negative electrode layer (202) and the top layer (100) along the stacking direction.

4. The packaging substrate as described in claim 1, characterized in that: The packaging substrate also includes a metal counterweight layer (800) and a counterweight insulating layer (700); The counterweight insulation layer (700) is stacked on the side of the second circuit layer away from the second surface, and the metal counterweight layer (800) is stacked on the side of the counterweight insulation layer (700) away from the second surface. The sum of the weights of the metal counterweight layer (800) and the counterweight insulation layer (700) is equal to the sum of the weights of the power supply negative electrode layer (202) and the top layer (100).

5. The packaging substrate as described in claim 4, characterized in that: The thickness of the metal counterweight layer (800) along the stacking direction is less than the sum of the thicknesses of the power supply negative electrode layer (202) and the top layer (100) along the stacking direction, and the thickness of the counterweight insulating layer (700) along the stacking direction is greater than the sum of the thicknesses of the power supply negative electrode layer (202) and the top layer (100) along the stacking direction.

6. The packaging substrate as described in any one of claims 2-5, characterized in that: The metal counterweight layer (800), the power supply negative electrode layer (202), and the top layer (100) are made of the same material.

7. The packaging substrate according to any one of claims 1-5, characterized in that: The power chip (600) is embedded in the transmission layer group (500) located between the positive potential section (400) and the first potential transmission section (301) along the stacking direction, and the power chip (600) is embedded in the transmission layer group (500) located between the second potential transmission section (302) and the negative potential section (201) along the stacking direction.

8. An electric drive system, characterized in that: The electric drive system includes a packaged substrate as described in any one of claims 1-7.

9. A vehicle, characterized in that: The vehicle includes a packaging substrate as described in any one of claims 1-7; Alternatively, the vehicle may include the electric drive system as described in claim 8.

10. A method for manufacturing a packaging substrate, characterized in that: The manufacturing method includes: A first prefabricated layer group is provided, including a transmission layer group (500) having a first surface and a second surface, a power chip (600) embedded in the transmission layer group (500), and a first circuit layer stacked on the first surface and a second circuit layer stacked on the second surface; wherein, the first circuit layer is provided with a first potential transmission part (301) and a negative potential part (201) spaced apart from the first potential transmission part (301), and the second circuit layer is provided with a second potential transmission part (302) and a positive potential part (400) spaced apart from the second potential transmission part (302); the first potential transmission part (301) and the positive potential part (400) are arranged opposite to each other along the stacking direction, and the second potential transmission part (302) and the negative potential part (201) are arranged opposite to each other along the stacking direction; A second prefabricated layer group is provided, including a power negative layer (202) and a top layer (100) stacked on the power negative layer (202), the second prefabricated layer group is stacked on the first prefabricated layer group, and the power negative layer (202) is stacked on the side of the first circuit layer opposite to the first surface.

11. The method for manufacturing a packaging substrate as described in claim 10, characterized in that: Before or after stacking the second prefabricated layer group on the first prefabricated layer group, the manufacturing method further includes: A third prefabricated layer assembly is provided, including a metal counterweight layer (800) and a counterweight insulating layer (700) stacked on the metal counterweight layer (800), the third prefabricated layer assembly is stacked on the first prefabricated layer assembly, and the counterweight insulating layer (700) is stacked on the side of the second circuit layer opposite to the second surface.

12. A method for manufacturing a packaging substrate, characterized in that: The manufacturing method includes: A prefabricated layer assembly is provided, including a transmission layer assembly (500) having a first surface and a second surface, a power chip (600) embedded in the transmission layer assembly (500), a first circuit layer stacked on the first surface, a second circuit layer stacked on the second surface, and a counterweight insulating layer (700) stacked on the second circuit layer; wherein, the first circuit layer is provided with a first potential transmission part (301) and a negative potential part (201) spaced apart from the first potential transmission part (301), and the second circuit layer is provided with a second potential transmission part (302) and a positive potential part (400) spaced apart from the second potential transmission part (302); the first potential transmission part (301) and the positive potential part (400) are arranged opposite to each other along the stacking direction, and the second potential transmission part (302) and the negative potential part (201) are arranged opposite to each other along the stacking direction; The negative power supply layer (202) is stacked on the side of the first circuit layer away from the first surface; The metal counterweight layer (800) is stacked on the side of the counterweight insulation layer (700) away from the second surface; The top layer (100) is stacked on the side of the power supply negative layer (202) away from the first surface.

13. A method for manufacturing a packaging substrate, characterized in that: The manufacturing method includes: A prefabricated layer assembly is provided, including a transmission layer assembly (500) having a first surface and a second surface, a power chip (600) embedded in the transmission layer assembly (500), a first circuit layer stacked on the first surface, a second circuit layer stacked on the second surface, and a counterweight insulating layer (700) stacked on the second circuit layer; wherein, the first circuit layer is provided with a first potential transmission part (301) and a negative potential part (201) spaced apart from the first potential transmission part (301), and the second circuit layer is provided with a second potential transmission part (302) and a positive potential part (400) spaced apart from the second potential transmission part (302); the first potential transmission part (301) and the positive potential part (400) are arranged opposite to each other along the stacking direction, and the second potential transmission part (302) and the negative potential part (201) are arranged opposite to each other along the stacking direction; The negative power supply layer (202) is stacked on the side of the first circuit layer away from the first surface; A portion of the thickness of the metal counterweight layer (800) along the stacking direction is stacked on the side of the counterweight insulation layer (700) away from the second surface; The top layer (100) is stacked on the side of the power supply negative electrode layer (202) away from the first surface; The metal counterweight layer (800) is stacked along the stacking direction with another portion of its thickness on the side of the portion of its thickness away from the second surface.

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