3D memory device and method for manufacturing the same

Abstract

The present application discloses a 3D memory device and a manufacturing method thereof. The manufacturing method comprises: forming a stop layer and a sacrificial layer on a substrate having a plurality of grooves, each groove being filled with the sacrificial layer, and the substrate and the sacrificial layer being separated by the stop layer; forming a stacked structure on the sacrificial layer; forming a channel column passing through the stacked structure, the channel column extending toward the substrate, the sidewall of the channel column contacting the sacrificial layer, and the channel column including a channel layer; forming a plurality of gate line gaps, each of which extends toward the substrate into the sacrificial layer; sequentially removing the sacrificial layer and the stop layer through the plurality of gate line gaps, so as to form a first gap between the stacked structure and the substrate, and part of the sidewall of the channel column being exposed by the first gap; removing part of the sidewall of the channel column through the first gap, so that part of the channel layer is exposed; and forming an epitaxial layer in the first gap, the channel layer being electrically connected to the substrate through the epitaxial layer, and each gate line gap corresponding to the position of the corresponding groove.

Description

[0001] This application is a divisional application of the Chinese invention patent application with an application date of March 25, 2020, application number 202010220516.2, and application name “3D memory device and manufacturing method thereof”. Technical Field

[0002] The present invention relates to memory technology, and more particularly, to a 3D memory device and a method for manufacturing the same. Background Art

[0003] The development direction of semiconductor technology is to reduce the feature size and improve the integration. For memory devices, the improvement of the storage density of memory devices is closely related to the progress of semiconductor manufacturing process. As the feature size of semiconductor manufacturing process becomes smaller and smaller, the storage density of memory devices becomes higher and higher.

[0004] In order to further improve storage density, a three-dimensional memory device (ie, a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, which can multiply the integration density per unit area of ​​a wafer and reduce costs.

[0005] In 3D memory devices, gate stack structures and channel pillars are generally used to provide selection transistors and storage transistors, and conductive channels are used to form the interconnection between the peripheral circuit and the storage string. Among them, the channel pillars are formed in the channel holes, and the bottom of each channel hole forms an epitaxial structure for electrically connecting the channel layer of the channel pillars and the semiconductor substrate. However, in order to make the channel layer contact the epitaxial layer, it is necessary to remove a part of the silicon-oxygen-nitrogen-oxygen (SONO) structure formed on the epitaxial structure through an etching process, thereby exposing the epitaxial structure. The etching process may cause damage to the SONO structure. As the storage capacity of 3D memory devices increases, the number of layers of the gate stack structure will gradually increase, further increasing the difficulty of etching.

[0006] Therefore, it is hoped to further improve the manufacturing process of the 3D memory device, thereby increasing the yield of the 3D memory device. Summary of the invention

[0007] The object of the present invention is to provide an improved 3D memory device and a manufacturing method thereof, which can form an epitaxial layer electrically connecting the channel layer to the substrate without forming an epitaxial structure in the channel hole and etching the SONO structure at the bottom of the channel hole.

[0008] According to one aspect of the present invention, a method for manufacturing a 3D memory device is provided, comprising: forming a stop layer and a sacrificial layer on a substrate, the substrate having a plurality of grooves and each of the grooves being filled with the sacrificial layer, the substrate and the sacrificial layer being separated by the stop layer; forming a stacked structure on the sacrificial layer, comprising alternately stacked interlayer sacrificial layers and interlayer dielectric layers; forming a channel column passing through the stacked structure, the channel column extending toward the substrate, the sidewall of the channel column contacting the sacrificial layer, the channel column comprising a channel layer; forming a plurality of gate line gaps, each of the gate line gaps extending toward the substrate into the sacrificial layer; removing the sacrificial layer and the stop layer in sequence through the plurality of gate line gaps so as to form a first gap between the stacked structure and the substrate, a portion of the sidewall of the channel column being exposed by the first gap; removing a portion of the sidewall of the channel column through the first gap so that a portion of the channel layer is exposed; and forming an epitaxial layer in the first gap, the channel layer being electrically connected to the substrate through the epitaxial layer, wherein each of the gate line gaps corresponds to the position of the corresponding groove.

[0009] Preferably, the surface of the substrate includes a storage area, a step area and a peripheral area, each of the grooves extends through the storage area and the step area to the peripheral area, and the manufacturing method also includes: removing part of the stacked structure to form a plurality of steps located above the step area, and exposing the sacrificial layer above the peripheral area; removing the sacrificial layer and the stop layer above the peripheral area, and retaining the sacrificial layer and the stop layer in the groove; and forming a first insulating layer above the step area and the peripheral area, the first insulating layer covering the plurality of steps and the substrate, wherein the gate line gap passes through the stacked structure and the first insulating layer toward the substrate, respectively.

[0010] Preferably, a lateral dimension of the groove is not smaller than a lateral dimension of the gate line gap.

[0011] Preferably, in the step of forming the epitaxial layer, the epitaxial layer grows from the substrate surface toward the stacked structure, stops growing when it is spaced a preset distance from the stacked structure, and retains part of the first gap. The manufacturing method also includes: forming a second insulating layer on the surface of the epitaxial layer.

[0012] Preferably, part of the first gap is reserved between the second insulating layer and the stacked structure, the layer of the stacked structure close to the substrate is an interlayer insulating layer, and the manufacturing method further comprises: forming a gate conductor layer in the first gap through the gate line gap.

[0013] Preferably, it also includes: forming a channel epitaxial portion on the surface of the channel pillar exposed in the first gap, the channel epitaxial portion is in contact with the channel layer and the epitaxial layer respectively, wherein the second insulating layer extends to the surface of the channel epitaxial portion.

[0014] Preferably, a gate conductor layer is formed in the first gap and is surrounded by at least the second insulating layer and the interlayer insulating layer.

[0015] Preferably, the second insulating layer is in contact with the stacked structure, and a layer of the stacked structure close to the substrate is an interlayer sacrificial layer. The manufacturing method further comprises: replacing the interlayer sacrificial layer with the gate conductor layer through the gate line gap.

[0016] Preferably, the method further comprises: forming a conductive channel in the gate line gap, wherein the conductive channel contacts the epitaxial layer; and forming a third insulating layer in the gate line gap, wherein the third insulating layer separates the conductive channel from the stacked structure.

[0017] Preferably, it also includes: forming a doped region in the substrate and contacting the epitaxial layer, wherein the bottom end of the channel column is located in the doped region, and the doped region and the epitaxial layer together serve as the well region.

[0018] According to another aspect of the present invention, a 3D memory device is provided, comprising: a substrate having a plurality of grooves; an epitaxial layer located on the substrate, and each of the grooves is filled with the epitaxial layer; a stacked structure located on the epitaxial layer, comprising alternately stacked gate conductor layers and interlayer dielectric layers; a channel column passing through the stacked structure, the channel column extending toward the substrate, the channel column comprising a channel layer, a portion of the channel layer being exposed through the sidewall of the channel column so that the channel layer is electrically connected to the substrate through the epitaxial layer; and a plurality of conductive channels, each of the conductive channels extending toward the substrate to the epitaxial layer, wherein each of the conductive channels corresponds to the position of a corresponding groove.

[0019] Preferably, the substrate surface includes a storage area, a step area and a peripheral area, each of the grooves passes through the storage area and the step area and extends to the peripheral area, the stacked structure above the step area presents a plurality of steps, and the 3D storage device further includes: a first insulating layer, covering the steps and the peripheral area of ​​the substrate, wherein the conductive path passes through the stacked structure and the first insulating layer respectively toward the substrate.

[0020] Preferably, it further comprises a channel epitaxial portion, which is located between the substrate and the stacked structure and is in contact with the channel layer and the epitaxial layer respectively.

[0021] Preferably, it further comprises a doped region located in the substrate, wherein the doped region is in contact with the epitaxial layer.

[0022] Preferably, it further comprises a third insulating layer, wherein the third insulating layer is located between the conductive channel and the stacked structure.

[0023] According to the 3D memory device and the manufacturing method thereof of the embodiment of the present invention, a sacrificial layer is formed between the substrate and the stacked structure to reserve a space for forming a first gap, the sacrificial layer is removed through the gate line gap and then a part of the channel pillar sidewall is removed through the first gap to expose the channel layer, and then an epitaxial layer is formed on the substrate, and the epitaxial layer enables the substrate and the channel layer to be electrically connected. Since a groove is formed in the substrate and a part of the sacrificial layer is filled in the groove, the etching process window of the gate line gap is increased, that is, the area of ​​the sacrificial layer exposed by the gate line gap is guaranteed, and at the same time, it is guaranteed that the gate line gap will not damage the stop layer between the substrate and the sacrificial layer.

[0024] Furthermore, since the grooves correspond to the storage area, the step area and the peripheral area respectively, and the inner surface of the grooves is covered by the stop layer, while ensuring that the gate line gap corresponding to the storage area can expose enough sacrificial layer, the gate line gap corresponding to the peripheral area is prevented from passing through the stop layer to reach the substrate and damaging the structure in the substrate.

[0025] Therefore, the 3D memory device and the manufacturing method thereof according to the embodiments of the present invention improve product yield and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0027] Figure 1a and 1b The circuit diagram and structural schematic diagram of a memory cell string of a 3D memory device are shown respectively.

[0028] Figure 2a A perspective view of a 3D memory device is shown.

[0029] Figure 2b A top view of a 3D memory device is shown.

[0030] Figures 2c to 2e Schematic cross-sectional views of a 3D memory device when a gate line gap is formed are shown respectively.

[0031] Figure 3a to Figure 3l-2 The structure diagrams of various stages of the method for manufacturing a 3D memory device according to an embodiment of the present invention are shown. DETAILED DESCRIPTION

[0032] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0033] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0034] If the purpose is to describe the situation of being directly on another layer or another area, this article will use the expression "directly on..." or "on... and adjacent to...".

[0035] In this application, the term "semiconductor structure" refers to the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. Many specific details of the present invention, such as the structure, materials, dimensions, processing techniques and technologies of the device are described below to facilitate a clearer understanding of the present invention. However, as can be appreciated by those skilled in the art, the present invention may be implemented without following these specific details.

[0036] The present invention may be embodied in various forms, some examples of which will be described below.

[0037] Figure 1a and 1b 1 and 2 respectively show a circuit diagram and a schematic diagram of a storage cell string of a 3D storage device. The storage cell string shown in this embodiment includes 4 storage cells. It can be understood that the present invention is not limited to this, and the number of storage cells in the storage cell string can be any number, for example, 32 or 64.

[0038] like Figure 1aAs shown, the first end of the memory cell string 100 is connected to the bit line (Bit-Line, BL), and the second end is connected to the source line (Source Line, SL). The memory cell string 100 includes a plurality of transistors connected in series between the first end and the second end, including: a first selection transistor (drain side selection transistor) Q1, storage transistors M1 to M4, and a second selection transistor (source side selection transistor) Q2. The gate of the first selection transistor Q1 is connected to the drain selection gate line (Selection Gate for Drain, SGD), also known as the top gate selection line. The gate of the second selection transistor Q2 is connected to the source selection gate line (Selection Gate for Source, SGS), also known as the bottom gate selection line. The gates of the storage transistors M1 to M4 are respectively connected to the corresponding word lines of the word lines (Word-Line) WL1 to WL4.

[0039] like Figure 1b As shown, the selection transistors Q1 and Q2 of the memory cell string 100 include a top gate conductor layer 122 and a bottom gate-to-body layer 123, respectively, and the memory transistors M1 to M4 include a gate conductor layer 121, respectively. The gate conductor layers 121, 122, and 123 are consistent with the stacking order of the transistors in the memory cell string 100, and adjacent gate conductor layers are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel column 110. The channel column 110 is adjacent to the gate stack structure or penetrates the gate stack structure. In the middle part of the channel column 110, a tunnel dielectric layer 112, a charge storage layer 113, and a gate dielectric layer 114 are sandwiched between the gate conductor layer 121 and the channel layer 111, thereby forming memory transistors M1 to M4. At both ends of the channel pillar 110 , a gate dielectric layer 114 is sandwiched between the gate conductor layers 122 and 123 and the channel layer 111 , thereby forming selection transistors Q1 and Q2 .

[0040] In this embodiment, the channel layer 111 is composed of, for example, polysilicon, the tunnel dielectric layer 112 and the gate dielectric layer 114 are respectively composed of oxides, such as silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals, such as silicon nitride containing metal or semiconductor particles, and the gate conductor layers 121, 122 and 123 are composed of metals, such as tungsten. The channel layer 111 is used to provide a channel region for controlling the selection transistor and the control transistor, and the doping type of the channel layer 111 is the same as that of the selection transistor and the control transistor. For example, for N-type selection transistors and control transistors, the channel layer 111 can be N-type doped polysilicon.

[0041] In this embodiment, the core of the channel pillar 110 is the channel layer 111, and the tunnel dielectric layer 112, the charge storage layer 113 and the gate dielectric layer 114 form a stacked structure surrounding the sidewalls of the core. In an alternative embodiment, the core of the channel pillar 110 is an additional insulating layer, and the channel layer 111, the tunnel dielectric layer 112, the charge storage layer 113 and the gate dielectric layer 114 form a stacked structure surrounding the semiconductor layer.

[0042] In this embodiment, the selection transistors Q1 and Q2 and the storage transistors M1 to M4 use a common channel layer 111 and a gate dielectric layer 114. In the channel pillar 110, the channel layer 111 provides source and drain regions and channel layers of multiple transistors. In an alternative embodiment, the semiconductor layer and the gate dielectric layer of the selection transistors Q1 and Q2 and the semiconductor layer and the gate dielectric layer of the storage transistors M1 to M4 can be formed separately in independent steps. In the channel pillar 110, the semiconductor layer of the selection transistors Q1 and Q2 and the semiconductor layer of the storage transistors M1 to M4 are electrically connected to each other.

[0043] In some other embodiments, the selection transistor Q1 can also be made into a structure like the storage transistors M1 to M4, specifically, a tunnel dielectric layer 112, a charge storage layer 113 and a gate dielectric layer 114 are sandwiched between the gate conductor layer 121 and the channel layer 111 at the upper part of the channel pillar 110, thereby forming the selection transistor Q1. Since the structure of the selection transistor Q1 is the same as that of the storage transistors M1 to M4, the formation process of the channel pillar can be simplified.

[0044] In the write operation, the memory cell string 100 uses the FN tunneling effect to write data into the selected memory transistors among the memory transistors M1 to M4. Taking the memory transistor M2 as an example, while the source line SL is grounded, the source selection gate line SGS is biased to a voltage of approximately zero volts, so that the selection transistor Q2 corresponding to the source selection gate line SGS is disconnected, and the drain selection gate line SGD is biased to a high voltage VDD, so that the selection transistor Q1 corresponding to the drain selection gate line SGD is turned on. Further, the bit line BL2 is grounded, the word line WL2 is biased to a programming voltage VPG, for example, about 20V, and the remaining word lines are biased to a low voltage VPS1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, the electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting the data into charge and storing it in the charge storage layer 113 of the memory transistor M2.

[0045] In the read operation, the memory cell string 100 determines the amount of charge in the charge storage layer according to the conduction state of the selected memory transistors among the memory transistors M1 to M4, thereby obtaining data represented by the amount of charge. Taking the memory transistor M2 as an example, the word line WL2 is biased at the read voltage VRD, and the remaining word lines are biased at the high voltage VPS2. The conduction state of the memory transistor M2 is related to its threshold voltage, that is, it is related to the amount of charge in the charge storage layer, so the data value can be determined according to the conduction state of the memory transistor M2. The memory transistors M1, M3 and M4 are always in the conduction state, so the conduction state of the memory cell string 100 depends on the conduction state of the memory transistor M2. The control circuit determines the conduction state of the memory transistor M2 according to the electrical signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

[0046] Figure 2a 3D memory device is shown in a perspective view. Wherein, X, Y, and Z represent the length direction, width direction, and height direction of the 3D memory device, respectively. Figure 2a The various insulating layers in the 3D memory device are not shown.

[0047] The 3D memory device shown in this embodiment includes 4*4 memory cell strings 100, totaling 16 memory cells, each memory cell string 100 includes 4 memory cells, thereby forming a 4*4*4 memory array of 64 memory cells. It can be understood that the present invention is not limited thereto, and the 3D memory device can include any number of memory cell strings, for example, 1024, and the number of memory cells in each memory cell string can be any number, for example, 32 or 64.

[0048] In the 3D memory device, the memory cell strings each include their own channel pillars 110, and common gate conductor layers 121, 122, and 123. The gate conductor layers 121, 122, and 123 are in the same stacking order as the transistors in the memory cell string 100, and adjacent gate conductor layers are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure 120. The interlayer insulating layer is not shown in the figure.

[0049] The internal structure of the channel pillar 110 is as follows: Figure 2b As shown, no detailed description is given here. In the middle part of the channel pillar 110, the gate conductor layer 121, together with the channel layer 111, the tunnel dielectric layer 112, the charge storage layer 113 and the gate dielectric layer 114 inside the channel pillar 110, form storage transistors M1 to M4. At both ends of the channel pillar 110, the gate conductor layers 122 and 123, together with the channel layer 111 and the gate dielectric layer 114 inside the channel pillar 110, form selection transistors Q1 and Q2.

[0050] The channel pillars 110 penetrate the gate stack structure 120 and are arranged in an array. The first ends of multiple channel pillars 110 in the same column are commonly connected to the same bit line (i.e., one of the bit lines BL1 to BL4), and the second ends are commonly connected to the substrate 101. The second ends form a common source connection via the substrate 100.

[0051] The gate conductor 122 of the drain side selection transistor Q1 is divided into different gate lines by a gate line slit 109. The gate lines of a plurality of channel pillars 110 in the same row are commonly connected to the same drain selection gate line (ie, one of the drain selection gate lines SGD1 to SGD4).

[0052] The gate conductors 121 of the memory transistors M1 and M4 are connected as one at different levels. If the gate conductors 121 of the memory transistors M1 and M4 are divided into different gate lines by the gate line gap 109, the gate lines at the same level reach the interconnection layer 132 via their respective conductive channels 131, thereby being interconnected with each other, and then connected to the same word line (i.e., one of the word lines WL1 to WL4) via the conductive channel 133.

[0053] The gate conductors of the source side selection transistor Q2 are connected as one. If the bottom gate conductor layer 123 of the source side selection transistor Q2 is divided into different gate lines by the gate line gap 109, the gate lines reach the interconnection layer 132 via their respective conductive channels 131, thereby interconnecting with each other, and then connected to the same source selection line SGS via the conductive channel 133.

[0054] Figure 2b A top view of a 3D memory device is shown, wherein X and Y represent the length direction and the width direction of the 3D memory device, respectively. The 3D memory device includes a storage area, a step area, and a peripheral area, which correspond to the storage area 10, the step area 20, and the peripheral circuit area 30 on the substrate surface below, respectively. Figures 2c to 2e Schematic cross-sectional views of a 3D memory device when a gate line gap is formed are shown respectively. Figure 2c is along Figure 2b The BB line in the Figure 2d and Figure 2e is along Figure 2b The image is taken along the AA line.

[0055] like Figure 2c and Figure 2dAs shown, before forming the gate line gap 207, the semiconductor structure that has been formed includes a substrate 201, a stop layer 203, a sacrificial layer 204, a first insulating layer 205, a channel pillar 210, and a stacked structure 250. The stop layer 203 and the sacrificial layer 204 are sequentially stacked on the surface of the substrate 201 along the height direction of the 3D memory device, wherein the stop layer 203 and the sacrificial layer 204 are only located in the storage area 10 and the step area 20. The stacked structure 250 is located on the sacrificial layer 204, and a plurality of steps are formed in the step area. The first insulating layer 205 covers the substrate 201 corresponding to the peripheral area 30 and the steps corresponding to the step area 20.

[0056] Further, the stacked structure 250 and the first insulating layer 205 are etched respectively to form a gate line gap 207 extending along the X direction of the device, and the gate line gap 207 corresponds to the storage area 10, the step area 20 and the peripheral area 30 respectively. Further, the sacrificial layer 204 is removed through the gate line gap 207, and a part of the side wall of the channel pillar 210 is exposed. Further, part of the side wall of the channel pillar 210 is removed in sequence to expose the channel layer of the channel pillar, and the stop layer 203 is removed to expose the substrate 201. Further, an epitaxial layer is formed on the surface of the substrate 201, and the epitaxial layer is in contact with the channel layer of the channel pillar 210 and the substrate 201 respectively, so as to achieve the purpose of electrically connecting the channel layer and the substrate 201.

[0057] The electrical connection between the channel layer and the substrate 201 is achieved by the above method, which can avoid the formation of an epitaxial structure in the channel hole and avoid the use of an etching process to remove the SONO structure on the epitaxial structure at the bottom of the channel hole.

[0058] However, the above process has strict requirements on the depth of the gate line gap 207. Figure 2c As shown, when the depth of the gate line gap 207 is too shallow (for example, when it is h1), the area of ​​the sacrificial layer 204 exposed by the gate line gap 207 is limited, and the sacrificial layer 204 is often not removed cleanly or even cannot be removed through the gate line gap 207. When the depth of the gate line gap 207 is too deep (for example, when it is h2), the stop layer 203 between the substrate 201 and the sacrificial layer 204 will be damaged. In the step of removing the sacrificial layer 204, the substrate 201 will be damaged, thereby destroying the structure in the substrate 201 (for example, the doped region, the well region, etc. formed in the substrate 201).

[0059] At the same time, when forming the gate line gap 207, the stacked structure 250 and the first insulating layer 205 need to be etched simultaneously. Since the structure and material of the first insulating layer 205 are single, the etching rate of the first insulating layer 205 is greater than that of the stacked structure 250. Figure 2dAs shown, when the depth of the gate line gap 207 corresponding to the storage area 10 is guaranteed to be on the surface of the stop layer 203, due to the high etching rate of the first insulating layer 205 and the absence of a corresponding stop layer in the peripheral area 30, the gate line gap 207 corresponding to the peripheral area 30 will directly reach the substrate 201, and in the subsequent step of removing the sacrificial layer 204, the structure in the substrate 201 (for example, the doped region, well region, etc. formed in the substrate 201) will be destroyed. Figure 2e As shown, when the depth of the gate line gap 207 corresponding to the peripheral area 30 is ensured to be on the surface of the substrate 201, the depth of the gate line gap 207 corresponding to the storage area 10 is relatively shallow, so that the sacrificial layer 204 cannot be effectively removed.

[0060] Figure 3a to Figure 3l-2 The structure diagrams of various stages of the method for manufacturing a 3D memory device according to an embodiment of the present invention are shown.

[0061] like Figure 3a As shown, the method starts with a semiconductor substrate 101 having a plurality of doped regions 101a formed thereon. A plurality of grooves 102 are formed on the substrate 101 through a zero mask. A stop layer 103 and a sacrificial layer 104 are formed on the substrate 101, each groove 102 is filled with the sacrificial layer 104, and the substrate 101 and the sacrificial layer 104 are separated by the stop layer 103. A stacked structure 150 is formed on the sacrificial layer 104, including alternately stacked interlayer sacrificial layers 152 and interlayer dielectric layers 151. Figure 3a is along Figure 2b It is intercepted by the BB line or CC line.

[0062] In the present embodiment, the substrate 101 is, for example, a single crystal silicon substrate, and the surface of the substrate 101 includes adjacent storage areas 10, step areas 20, and peripheral areas 30. Each groove 102 extends through the storage area 10 and the step area 20 to the peripheral area 30. The stop layer 102 and the sacrificial layer 104 have a high etching selectivity, for example, the material of the stop layer 102 includes but is not limited to silicon oxide, the material of the sacrificial layer 104 includes but is not limited to polysilicon, and the structure of the sacrificial layer 104 can also be configured in other ways according to the needs of those skilled in the art. The interlayer sacrificial layer 152 and the interlayer dielectric layer 151 have a high etching selectivity, so that the interlayer sacrificial layer 152 can be replaced with a gate conductor layer in the subsequent process, for example, the material of the interlayer dielectric layer 151 includes but is not limited to silicon oxide, and the material of the interlayer sacrificial layer 152 includes but is not limited to silicon nitride.

[0063] Further, a portion of the stacked structure 150 is removed to form a plurality of steps located above the step region 20, and the sacrificial layer 104 above the peripheral region 30 is exposed; the sacrificial layer 104 and the stop layer 103 above the peripheral region 30 are removed, and the sacrificial layer 104 and the stop layer 103 filled in the groove 102 are retained; a first insulating layer 105 is formed above the step region 20 and the peripheral region 30, and the first insulating layer 105 covers the plurality of steps and the peripheral region 30 on the surface of the substrate 101, such as Figure 3b As shown. Among them, Figure 3b is along Figure 2b In this embodiment, the material of the first insulating layer 105 includes but is not limited to silicon oxide.

[0064] Furthermore, a channel column 110 is formed in the storage region 10 and passes through the stacked structure 150. The channel column 110 extends toward the substrate 101, and the sidewall of the channel column 110 contacts the sacrificial layer 104. Figure 3c As shown. Among them, Figure 3c is along Figure 2b Intercepted by the BB line in .

[0065] In this embodiment, the bottom of the channel pillar 110 extends into the doped region 101a. In some other embodiments, the bottom of the channel pillar 110 may also extend into the sacrificial layer 104 or the stop layer 103. The channel pillar 110 includes a gate dielectric layer 114, a charge storage layer 113, a tunnel dielectric layer 112, and a channel layer 111 that sequentially cover the inner surface of the channel hole 106. In some other embodiments, the channel pillar 110 also includes an insulating core 115, which is surrounded by the channel layer 111.

[0066] Furthermore, a plurality of gate line gaps 107 are formed, and the gate line gaps 107 extend toward the substrate 101 into the sacrificial layer 104, and each gate line gap 107 corresponds to the position of a corresponding groove 102, such as Figure 3d-1 and Figure 3d-2 As shown. Among them, Figure 3d-1 is along Figure 2b The BB line in the Figure 3d-2 is along Figure 2b Intercepted by the CC line in .

[0067] In this step, anisotropic etching is performed on the stacked structure 150, the first insulating layer 105 and the sacrificial layer 104. The anisotropic etching can be performed by dry etching, such as ion milling etching, plasma etching, reactive ion etching, and laser ablation. For example, by controlling the etching time, the etching is stopped in the sacrificial layer 104 or other predetermined positions.

[0068] In this embodiment, since the substrate 101 has a groove 102 corresponding to the gate line gap 107, the window of the gate line gap etching process is increased, that is, the area of ​​the gate line gap 107 exposing the sacrificial layer 104 is ensured, and at the same time, it is ensured that the gate line gap 107 will not damage the stop layer 103 between the substrate 101 and the sacrificial layer 104. At the same time, since the grooves 102 correspond to the storage area 10, the step area 20 and the peripheral area 30 respectively, and the inner surface of the groove 102 corresponding to each area is covered by the stop layer 103, therefore, while ensuring that the gate line gap 107 corresponding to the storage area 10 can expose enough sacrificial layer 104, the gate line gap 107 corresponding to the peripheral area 30 is prevented from reaching the substrate 101 and damaging the structure in the substrate 101. The lateral size of the groove 102 is not less than the lateral size of the gate line gap 107. In some preferred embodiments, the lateral size of the groove 102 is greater than the lateral size of the gate line gap 107, so as to further achieve the purpose of increasing the etching process window.

[0069] Furthermore, the sacrificial layer 104 is removed through the plurality of gate line gaps 107 to form a first gap 1071, and a portion of the sidewall of the channel pillar 110 is exposed by the first gap 1071. Figure 3e-1 and Figure 3e-2 As shown. Among them, Figure 3e-1 is along Figure 2b The BB line in the Figure 3e-2 is along Figure 2b Intercepted by the CC line in .

[0070] In this step, the sacrificial layer 104 is removed by wet etching, for example. Since the sacrificial layer 104 exposed by the gate line gap 107 has a large area, the sacrificial layer 104 can be completely removed. The stop layer 103 protects the substrate 101 and prevents the substrate 101 from being damaged by the corrosive agent.

[0071] Further, a portion of the sidewall of the channel pillar is removed through the first gap 1071 to expose a portion of the channel layer 111, and the stop layer 103 is removed through the first gap 1071. Figure 3f-1 and Figure 3f-2 As shown. Among them, Figure 3f-1 is along Figure 2b The BB line in the Figure 3f-2 is along Figure 2b Intercepted by the CC line in .

[0072] In this step, for example, a wet etching process is used to sequentially remove the gate dielectric layer 114, the charge storage layer 113, and the tunnel dielectric layer 112 exposed in the first gap 1071 to expose the channel layer 111, and the sacrificial layer 104 can be removed simultaneously with the gate dielectric layer 114 and / or the tunnel dielectric layer 112.

[0073] Furthermore, an epitaxial layer 140 and a channel outer edge portion 116 are formed in the first gap 1071, and the channel layer 111 is electrically connected to the substrate 101 via the epitaxial layer 140. Figure 3g-1 and Figure 3g-2 As shown. Among them, Figure 3g-1 is along Figure 2b The BB line in the Figure 3g-2 is along Figure 2b Intercepted by the CC line in .

[0074] In this embodiment, the channel outer edge 116 grows from the surface of the channel layer 111 along the radial direction of the channel pillar, contacts the epitaxial layer 140, and the epitaxial layer 140 grows from the surface of the substrate 101 toward the stacked structure 150, and stops growing when it is spaced a preset distance from the stacked structure 150, and retains part of the first gap 1071. Among them, the material of the channel outer edge 116 includes but is not limited to polysilicon, the material of the epitaxial layer 140 includes but is not limited to silicon, and the groove 102 is filled with the epitaxial layer 140. The epitaxial layer 140 and the doped region 101a together serve as a well region, and the structure of the epitaxial layer 140 can also be set in other ways according to the needs of those skilled in the art.

[0075] In some other embodiments, the growth of the epitaxial layer 140 stops when it contacts the insulating structure 150 , and the layer of the stacked structure 150 close to the substrate 101 is an interlayer insulating layer.

[0076] Furthermore, a second insulating layer 108 is formed on the surface of the epitaxial layer 140, and the second insulating layer 108 extends to the surface of the channel outer edge portion 116, as shown in FIG. Figure 3h shown.

[0077] In this step, for example, a surface oxidation process is used to oxidize the surface of the epitaxial layer 140 and the channel epitaxial portion 116 exposed in the first gap 1071 to form the second insulating layer 108, wherein the material of the second insulating layer 108 includes but is not limited to silicon oxide. However, the embodiment of the present invention is not limited thereto, and those skilled in the art may select other processes to form the second insulating layer 108 as needed.

[0078] In this embodiment, a portion of the first gap 1071 is reserved between the second insulating layer 108 and the stacked structure 150 , and the layer of the stacked structure 150 close to the substrate 101 is an interlayer insulating layer.

[0079] In some other embodiments, the second insulating layer 108 is in contact with the stacked structure 150 , and the layer of the stacked structure 150 close to the substrate 101 is an interlayer sacrificial layer.

[0080] Furthermore, the interlayer sacrificial layer is removed relative to the interlayer insulating layer 151 in the stacked structure 150 through the gate line gap 107 to form a second gap 1072, as shown in FIG. Figure 3iFurther, the gate line gap 107, the first gap 1071 and the second gap 1072 are filled with a conductive material 109, as shown in FIG. Figure 3j As shown, the conductive material 109 includes but is not limited to metal tungsten, and in the gate line gap, the conductive material 109 is not filled, and the gap is retained.

[0081] Furthermore, a back etching process is used to remove part of the conductive material through the remaining gap to re-form the gate line gap 107, such as Figure 3k shown.

[0082] In this step, the interlayer sacrificial layer is replaced by gate conductor layers 121, 122, 123 to form a stacked structure 120. In this embodiment, the space of the first gap 1071 is fully utilized to form the bottom gate conductor layer 123, and the bottom gate conductor layer 123 is at least surrounded by the second insulating layer 1081 and the interlayer insulating layer 151.

[0083] Furthermore, a third insulating layer 1082 is formed on the sidewall of the gate line gap 107, and a conductive channel 160 is formed in the gate line gap 107. The conductive channel 160 contacts the epitaxial layer 140, and the third insulating layer 1082 separates the conductive channel 160 from the stacked structure 150. Figure 3l-1 and Figure 3l-2 As shown. Among them, Figure 3l-1 is along Figure 2b The BB line in the Figure 3l-2 is along Figure 2b Intercepted by the CC line in .

[0084] In this embodiment, the conductive channel 160 passes through the second insulating layer 1081 and contacts the epitaxial layer 140. The conductive channel 160 includes an adhesive layer 161 and a conductive layer 162. The material of the adhesive layer 161 includes but is not limited to titanium nitride, and the material of the conductive layer 162 includes but is not limited to metal tungsten.

[0085] According to the 3D memory device and the manufacturing method thereof of the embodiment of the present invention, a sacrificial layer is formed between the substrate and the stacked structure to reserve a space for forming a first gap, the sacrificial layer is removed through the gate line gap and then a part of the channel pillar sidewall is removed through the first gap to expose the channel layer, and then an epitaxial layer is formed on the substrate, and the epitaxial layer enables the substrate and the channel layer to be electrically connected. Since a groove is formed in the substrate and a part of the sacrificial layer is filled in the groove, the etching process window of the gate line gap is increased, that is, the area of ​​the sacrificial layer exposed by the gate line gap is guaranteed, and at the same time, it is guaranteed that the gate line gap will not damage the stop layer between the substrate and the sacrificial layer.

[0086] Furthermore, since the grooves correspond to the storage area, the step area and the peripheral area respectively, and the inner surface of the grooves is covered by the stop layer, while ensuring that the gate line gap corresponding to the storage area can expose enough sacrificial layer, the gate line gap corresponding to the peripheral area is prevented from passing through the stop layer to reach the substrate and damaging the structure in the substrate.

[0087] Therefore, the 3D memory device and the manufacturing method thereof according to the embodiments of the present invention improve product yield and reliability.

[0088] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, it should be understood by those skilled in the art that various technical means can be used to form layers, regions, etc. of the desired shape. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0089] The embodiments of the present invention are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A 3D memory device, comprising: a substrate having a groove; A stacked structure comprising gate conductor layers and interlayer dielectric layers alternately stacked along a first direction; A first conductive layer is located between the substrate and the stacked structure, and the groove is filled with the first conductive layer; A channel column extending along the first direction and passing through the stacked structure, wherein the channel column comprises a channel layer, and the first conductive layer is connected to the channel layer and the substrate; as well as a gate line gap structure, penetrating the stacked structure along the first direction and extending along the second direction, the gate line gap structure comprising a conductive channel and a first insulating layer located between the conductive channel and the stacked structure, The conductive path extends along the first direction to the first conductive layer, and the conductive path corresponds to the position of the groove. The groove includes a top and a bottom disposed opposite to each other along the first direction, the top is closer to the stacked structure than the bottom, the gate line gap structure includes a first end and a second end disposed opposite to each other along the first direction, the first end is closer to the substrate than the second end, Along the third direction, the top dimension of the groove is larger than the dimension of the first end of the gate line gap structure, and The second direction and the third direction are both perpendicular to the first direction, and the second direction intersects the third direction.

2. The 3D memory device according to claim 1, wherein: The conductive path and the groove overlap in the third direction.

3. The 3D memory device according to claim 1, wherein: The first conductive layer includes silicon.

4. The 3D memory device according to claim 1, wherein: The channel pillar includes a first portion extending into the substrate, the first portion including a functional layer between the channel layer and the substrate.

5. The 3D memory device according to claim 1, wherein: The conductive channel includes a first conductive material layer and a second conductive material layer, wherein the second conductive material layer is located between the first conductive material layer and the first insulating layer.

6. The 3D memory device according to claim 1, wherein: The material of the first conductive material layer includes tungsten, and the material of the second conductive material layer includes titanium nitride.

7. The 3D memory device according to claim 1, further comprising, A second conductive layer is located between the substrate and the stacked structure and is in contact with the channel layer and the first conductive layer respectively.

8. The 3D memory device according to claim 7, wherein: The second conductive layer contacts a portion of the channel layer.

9. The 3D memory device according to claim 1, wherein: The conductive path is connected to the substrate.

10. The 3D memory device according to claim 1, wherein: The substrate includes a storage area, a step area and a peripheral area, the groove extends through the storage area and the step area to the peripheral area along the second direction, the stacked structure of the step area includes a plurality of steps, and the 3D memory device further includes: a second insulating layer, covering the step and the peripheral area of ​​the substrate, The conductive path passes through the stacked structure and the second insulating layer along the first direction.

11. The 3D memory device according to claim 1, wherein: The substrate includes a doped region, and the doped region is in contact with the first conductive layer. 12 . The 3D memory device according to claim 1 , further comprising a third insulating layer, the third insulating layer being located between the conductive channel and the stacked structure.

13. A method for manufacturing a 3D memory device, comprising: forming a substrate having a groove; Forming a stacked structure on a substrate, the stacked structure comprising gate conductor layers and interlayer dielectric layers alternately stacked along a first direction; forming a first conductive layer, wherein the first conductive layer is located between the substrate and the stacked structure, and the groove is filled with the first conductive layer; forming a channel column, wherein the channel column passes through the stacked structure along the first direction, the channel column comprises a channel layer, and the first conductive layer is connected to the channel layer and the substrate; as well as A gate line gap structure is formed, wherein the gate line gap structure includes a conductive channel and a first insulating layer located between the conductive channel and the stacked structure, wherein: The conductive path extends along the first direction to the first conductive layer, and the conductive path corresponds to the position of the groove. The groove includes a top and a bottom disposed opposite to each other along the first direction, the top is closer to the stacked structure than the bottom, the gate line gap structure includes a first end and a second end disposed opposite to each other along the first direction, the first end is closer to the substrate than the second end, Along the third direction, the top dimension of the groove is larger than the dimension of the first end of the gate line gap structure, and The second direction and the third direction are both perpendicular to the first direction, and the second direction intersects the third direction.

14. The manufacturing method according to claim 13, wherein: The forming of the first conductive layer comprises: forming a stop layer and a sacrificial layer on a substrate, wherein the groove is filled with the sacrificial layer, and the substrate and the sacrificial layer are separated by the stop layer; removing the sacrificial layer and the stop layer so as to form a first gap between the stacked structure and the substrate; A first conductive layer is formed in the first gap.

15. The manufacturing method according to claim 14, wherein: The forming of the stacked structure comprises: forming interlayer sacrificial layers and interlayer dielectric layers alternately stacked on the sacrificial layer; Removing the interlayer sacrificial layer to form a second gap; A gate conductive layer is formed in the second gap to form gate conductive layers and interlayer dielectric layers alternately stacked in a first direction.

16. The manufacturing method according to claim 15, wherein: The forming of the gate line gap structure comprises: Forming a gate line gap along a first direction passing through the alternately stacked interlayer sacrificial layers and interlayer dielectric layers and extending to the sacrificial layers; Removing the interlayer sacrificial layer through the gate line gap to form a second gap; forming a gate conductive layer in the second gap to form gate conductive layers and interlayer dielectric layers alternately stacked in a first direction; A first insulating layer is formed on the sidewall of the gate line gap, a conductive channel is formed in the gate line gap, the first insulating layer is located between the conductive channel and the first insulating layer, the conductive channel extends to the first conductive layer along the first direction, and the conductive channel corresponds to the position of the groove.

17. The manufacturing method according to claim 16, wherein: Forming the channel pillar comprises: forming a channel hole along the first direction passing through the alternately stacked interlayer sacrificial layers and interlayer dielectric layers and extending into the substrate; forming a functional layer on the surface of the channel hole, and forming a channel layer on the surface of the functional layer; removing the sacrificial layer and the stop layer through the gate line gap, so as to form a first gap between the stacked structure and the substrate, wherein the first gap exposes a portion of the functional layer; removing a portion of the functional layer exposed by the first gap, so that a portion of the channel layer is exposed; A first conductive layer is formed in the first gap, the first conductive layer being connected to the channel layer and the substrate.

18. The manufacturing method according to claim 17, further comprising: A second conductive layer is formed on the surface of the exposed portion of the channel layer, wherein the second conductive layer is in contact with the exposed portion of the channel layer.

19. The manufacturing method according to claim 13, wherein: The substrate surface includes a storage area, a step area and a peripheral area, the groove extends through the storage area and the step area to the peripheral area along the second direction, and the manufacturing method further includes: removing a portion of the stacked structure located in the step region to form a plurality of steps, forming a second insulating layer above the step region and the peripheral region, wherein the second insulating layer covers the plurality of steps and the substrate, The conductive path passes through the stacked structure and the second insulating layer respectively along the first direction.

20. The manufacturing method according to claim 13, further comprising: forming a doped region in the substrate and contacting the first conductive layer, Wherein, the bottom end of the channel column is located in the doping region.

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