Preparation Method of a Grouped Pair Structure Non-Volatile Memory

Abstract

The present invention provides a method for fabricating a paired-structured non-volatile memory. The fabrication method includes: providing a substrate, on which a gate material layer, a first hard mask layer, and a second hard mask layer are sequentially stacked; forming a first opening in the second hard mask layer; forming a first sidewall within the first opening, the first sidewall being an annular structure that adheres to the sidewalls of the first opening; filling a third hard mask layer within the first opening; removing the second hard mask layer; forming a second sidewall outside the first sidewall; removing the third hard mask layer; using the first sidewall and the second sidewall as masks, etching the first hard mask layer and the gate material layer downward in sequence to form a gate ring; and etching and removing two opposite ends of the gate ring, so that the gate ring is separated into gate electrodes of two memory tubes of the same paired memory cell. In this way, the area of the paired memory cell of the paired-structured non-volatile memory can be reduced, and the size and cost of the memory chip can be decreased.

Description

Technical Field

[0001] The present invention relates to the technical field of memory manufacturing, and particularly relates to a method for preparing a paired structure non-volatile memory. Background Art

[0002] Figure 1 It is a layout diagram of a paired structure non-volatile memory. Figure 2 It is Figure 1 The architecture diagram of a paired storage unit of the shown paired structure non-volatile memory. Figure 3 It is a cross-sectional schematic diagram of a paired structure non-volatile memory, wherein, Figure 3 It is Figure 1 The cross-sectional schematic diagram of the position shown by the BB line in Figure 1 , Figure 2 and Figure 3 As shown in Summary of the Invention

[0003] The present invention provides a method for preparing a paired structure non-volatile memory, which can reduce the area of the paired storage unit of the paired structure non-volatile memory, reduce the size and cost of the storage chip, and improve the cost performance of the storage chip.

[0004] To achieve the above object, the method for manufacturing a paired-structured non-volatile memory provided in this embodiment includes: providing a substrate, on which a gate material layer, a first hard mask layer, and a second hard mask layer are sequentially stacked from bottom to top; forming a first opening in the second hard mask layer; forming a first sidewall in the first opening, the first sidewall being an annular structure attached to the sidewalls of the first opening; filling a third hard mask layer in the first opening; removing the second hard mask layer; forming a second sidewall outside the first sidewall, the second sidewall surrounding and attaching to the first sidewall; removing the third hard mask layer; using the first sidewall and the second sidewall as masks, etching the first hard mask layer and the gate material layer downward in sequence to form a gate ring; etching and removing two opposite ends of the gate ring so that the gate ring separates the gate electrodes of two memory tubes of the same paired memory cell.

[0005] Optionally, in the step of providing the substrate, the substrate has an isolation structure and an active region defined by the isolation structure; in the step of forming the gate ring, the gate ring spans the active region, and two opposite ends of the gate ring are located on the isolation structures on both sides of the active region.

[0006] Optionally, the first sidewall spans the active region, and two opposite ends of the first sidewall extend beyond the active region and are located on the isolation structures on both sides of the active region.

[0007] Optionally, the method for etching and removing two opposite ends of the gate ring includes: forming a second photoresist mask layer on the substrate, the second photoresist mask layer having a plurality of second openings located above the isolation structure, and two opposite ends of the gate ring are exposed from the corresponding second openings; using the second photoresist mask layer as a mask, etching and removing two opposite ends of the gate ring and stopping on the isolation structure.

[0008] Optionally, two memory tubes of the same paired memory cell are electrically connected through the active region between the gate electrodes of the two memory tubes.

[0009] Optionally, the method for filling the third hard mask layer in the first opening includes: forming a third hard mask layer on the substrate, the third hard mask layer covering the second hard mask layer and the first sidewall and filling the first opening; removing the third hard mask layer above the second hard mask layer through a chemical mechanical polishing process or a back etching process.

[0010] Optionally, the first sidewall and the second sidewall are made of the same material; the first sidewall, the first hard mask layer, the second hard mask layer, and the third hard mask layer are made of different materials.

[0011] Optionally, in the step of providing the substrate, the substrate has a storage region and a logic region. A charge trap layer is formed on the storage region, and a gate oxide layer is formed on the logic region. The gate material layer covers the charge trap layer and the gate oxide layer; the subsequently formed gate ring is located on the storage region.

[0012] Optionally, after removing the third hard mask layer and before etching the first hard mask layer and the gate material layer downward in sequence, the manufacturing method further includes: forming a first photoresist mask layer on the first hard mask layer, where the first photoresist mask layer covers part of the logic region and exposes the storage region; the step of etching the first hard mask layer and the gate material layer downward in sequence includes: using the first sidewall, the second sidewall, and the first photoresist mask layer as a common mask to etch the first hard mask layer, the gate material layer, the charge trap layer, and the gate oxide layer downward and stopping on the substrate, and the remaining part of the gate material layer serves as the gate ring and part serves as the select gate on the logic region.

[0013] Optionally, after etching the first hard mask layer and the gate material layer downward in sequence and before etching and removing the two opposite ends of the gate ring, the manufacturing method further includes: removing the first sidewall, the second sidewall, and the first hard mask layer.

[0014] The preparation method of the paired-structure non-volatile memory provided by the present invention has the following advantages: (1) Using the first sidewall and the second sidewall as masks, etching the gate material layer to form a gate ring, and then etching and removing two opposite ends of the gate ring, so that the gate ring divides the gate electrodes of the two memory tubes of the same paired memory cell. In this way, the distance between the gate electrodes of the two memory tubes of the same paired memory cell is not restricted by the resolution of lithography, and the distance between the gate electrodes of the two memory tubes of the same paired memory cell is smaller, thereby reducing the area of the paired memory cell of the paired-structure non-volatile memory, helping to reduce the size and cost of the memory chip, and improving the cost performance of the memory chip; (2) In this application, the first sidewall is formed in the first opening of the second hard mask layer, then the third hard mask layer is filled in the first opening, and then the second hard mask layer is removed. Next, the second sidewall is formed on the outside of the first sidewall and the third hard mask layer is removed. After that, using the first sidewall and the second sidewall as masks, the first hard mask layer and the gate material layer are etched downward in sequence to form a gate ring. In this way, the gate ring can be defined by one-step self-aligned etching, that is, the distance between the gate electrodes of the two memory tubes of the same paired memory cell and the length of the gate electrode of the memory tube are defined by one-step self-aligned etching. The process is relatively simple, and it helps to improve the size consistency of the two gate electrodes of the paired memory cell and the performance consistency of the two memory tubes of the paired memory cell, thereby improving the performance of the paired-structure non-volatile memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a layout diagram of a paired-structure non-volatile memory.

[0016] Figure 2 is Figure 1 an architecture diagram of a paired memory cell of the paired-structure non-volatile memory shown.

[0017] Figure 3 is a cross-sectional schematic diagram of a paired-structure non-volatile memory.

[0018] Figure 4 is a flowchart of the preparation method of the paired-structure non-volatile memory provided by an embodiment of the present invention.

[0019] Figures 5 to 30 is a process structure schematic diagram of the preparation method of the paired-structure non-volatile memory provided by an embodiment of the present invention.

[0020] Description of reference numerals: 100 - active region; 101 - isolation structure; 102 - charge trap layer; 103 - gate oxide layer; 104 - gate material layer; 104a - gate ring; 104b - select transistor gate; 104c - gate electrode; 105 - amorphous carbon layer; 106 - silicon oxynitride layer; 107 - second hard mask layer; 108 - first opening; 109 - first sidewall; 110 - third hard mask layer; 111 - second sidewall; 112 - bottom anti-reflection coating; 113 - first photoresist mask layer; 114 - second photoresist mask layer; 114a - second opening. Detailed implementation manners

[0021] The following further elaborates on the preparation method of the paired structure non-volatile memory proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are in very simplified forms and use non-precise scales, only for facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0022] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for facilitating the description of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation of the present application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more, and at least one means it can be one, two or more, unless otherwise specifically defined.

[0023] Figure 4 It is a flowchart of the preparation method of the paired structure non-volatile memory provided in an embodiment of the present invention. As Figure 4 shown, the preparation method of the paired structure non-volatile memory provided in the present application includes:

[0024] Step S1, providing a substrate, on which a gate material layer, a first hard mask layer, and a second hard mask layer are sequentially stacked from bottom to top;

[0025] Step S2, forming a first opening in the second hard mask layer;

[0026] Step S3: Form a first sidewall within the first opening. The first sidewall is an annular structure that adheres to the sidewall of the first opening.

[0027] Step S4: Fill the third hard mask layer within the first opening.

[0028] Step S5: Remove the second hard mask layer.

[0029] Step S6: Form a second sidewall outside the first sidewall. The second sidewall surrounds and adheres to the first sidewall.

[0030] Step S7: Remove the third hard mask layer.

[0031] Step S8: Using the first sidewall and the second sidewall as masks, etch the first hard mask layer and the gate material layer downward in sequence to form a gate ring.

[0032] Step S9: Etch and remove two opposite ends of the gate ring, such that the gate ring is separated into gate electrodes of two memory transistors of the same group of memory cells.

[0033] It should be understood that although Figure 4 the steps in the flowchart are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 4 at least a part of the steps in

[0034] Figures 5 to 30 can include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments, and the execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turns with at least a part of other steps or steps or stages in other steps. Figure 4 、 Figures 5 to 30 This is a process structure schematic diagram of a preparation method for a paired structure non-volatile memory provided by an embodiment of the present invention. The following will describe the preparation method for the paired structure non-volatile memory provided in this application with reference to Figure 5 、 Figure 7 、 Figure 9 、 Figure 11 、 Figure 13 、 Figure 15 、 Figure 17 、 Figure 19 、 Figure 21 、 Figure 23 、 Figure 25 、 Figure 27 、 Figure 29 and Figure 30 are top views during the preparation process, Figure 6 、Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 , Figure 26 and Figure 28 are cross-sectional views during the manufacturing process, and the cross-sectional views are all cross-sectional views along the direction shown by line CC in the top view (refer to Figure 5 ).

[0035] Refer to Figure 5 and Figure 6 . A gate material layer 104, a first hard mask layer, and a second hard mask layer 107 are sequentially stacked from bottom to top on the substrate provided in step S1.

[0036] In this embodiment, refer to Figure 5 and Figure 6 . The substrate has an isolation structure 101 and an active region 100 defined by the isolation structure 101. The active region 100 and the isolation structure 101 may both be formed on the top of the substrate. The substrate may have multiple active regions 100; the multiple active regions 100 may be arranged in parallel, but are not limited thereto. The isolation structure 101 may be a shallow trench isolation (STI) structure, but is not limited thereto; the isolation structure 101 includes a shallow trench formed in the substrate and an isolation oxide layer filling the shallow trench, and the isolation oxide layer includes, for example, silicon oxide.

[0037] In this embodiment, the substrate may be a silicon substrate. In other embodiments, the substrate may also be a germanium substrate, a silicon germanium substrate, a silicon on insulator (SOI), or a germanium on insulator (GOI), etc., and certain doping particles may also be implanted into the substrate according to design requirements to change electrical parameters.

[0038] In this embodiment, the memory cell of the paired structure non-volatile memory is a charge trap type memory cell, but is not limited thereto. Refer to Figure 6 . The substrate has a storage area and a logic area. A charge trap layer 102 is formed on the storage area, and a gate oxide layer 103 is formed on the logic area. Or, the charge trap layer 102 covers the storage area of the substrate for forming the memory cell, and the gate oxide layer 103 covers the logic area of the substrate, and the logic area is located outside the storage area.

[0039] Exemplarily, the charge trap layer 102 may be an ONO layer, including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer sequentially stacked from bottom to top, but is not limited thereto. Exemplarily, the gate oxide layer 103 may include a silicon oxide layer.

[0040] It should be noted that, for the convenience of showing the relationship between the isolation structure 101 and the active region 100 in the substrate, Figure 5 the first hard mask layer, the gate material layer 104, the charge trap layer 102, and the gate oxide layer 103 between the substrate and the second hard mask layer 107 are not shown.

[0041] Refer to Figure 5 and Figure 6 As shown, the gate material layer 104 covers the charge trap layer 102 and the gate oxide layer 103. Exemplarily, the gate material layer 104 includes, but is not limited to, a polysilicon layer.

[0042] In this embodiment, the first hard mask layer is a double-layer structure, including an amorphous carbon (a-C) layer 105 covering the gate material layer 104 and a silicon oxynitride (SiON) layer 106 covering the amorphous carbon layer 105. The silicon oxynitride layer 106 can be used as a dielectric anti-reflective coating (DARC) between the amorphous carbon layer 105 and the second hard mask layer 107. In some other embodiments, the first hard mask layer can also be a single-layer structure including a single material layer. In some embodiments, the silicon oxynitride layer 106 can be replaced with silicon carbon oxide (SiCO), etc., as long as it is ensured that the materials of the sidewalls (including the first sidewall and the second sidewall), the first hard mask layer, the second hard mask layer, and the third hard mask layer are different.

[0043] The second hard mask layer 107 includes, but is not limited to, a silicon nitride layer.

[0044] In this embodiment, the formation temperatures of both the second hard mask layer 107 and the silicon oxynitride layer 106 can be below 400 °C.

[0045] Exemplarily, the thickness of the gate material layer 104 is 600 Å to 1000 Å, for example, 800 Å. The thickness of the amorphous carbon layer 105 is 400 Å to 800 Å, for example, 600 Å. The thickness of the silicon oxynitride layer 106 is 100 Å to 300 Å, for example, 200 Å. The thickness of the second hard mask layer 107 is 400 Å to 800 Å, for example, 600 Å. It should be noted that the thicknesses of the gate material layer 104, the amorphous carbon layer 105, the silicon oxynitride layer 106, and the second hard mask layer 107 can be adjusted as needed.

[0046] Refer to Figure 7 and Figure 8 As shown, step S2 is performed to form a first opening 108 in the second hard mask layer 107.

[0047] In this embodiment, the first opening 108 can span across the active region 100 and extend at both ends to the isolation structures 101 on both sides of the active region 100. Refer to Figure 7 As shown, the opening shape of the first opening 108 can be rectangular, but is not limited thereto.

[0048] In step S2, a plurality of first openings 108 can be formed in the second hard mask layer 107, and the plurality of first openings 108 can be arranged in an array so as to form storage tubes arranged in an array subsequently.

[0049] Exemplarily, step S2 can include: forming a photoresist layer on the second hard mask layer 107; performing exposure and development on the photoresist layer to form a patterned photoresist layer; using the patterned photoresist layer as a mask to etch the second hard mask layer 107 and stop on the first hard mask layer to form the first opening 108.

[0050] In this embodiment, after etching through the second hard mask layer 107, appropriate over-etching can be performed and stopped in the silicon oxynitride layer 106. During the process of etching to form the first opening 108, when it is detected that the etching reaches the surface of the silicon oxynitride layer 106, slightly over-etching can be performed by fixing the etching time so that the etching stops in the silicon oxynitride layer 106.

[0051] In this embodiment, the width of the first opening 108 (i.e., Figure 8 the dimension in the horizontal direction) can be set according to the gate electrode lengths of the two storage tubes of the paired storage unit and the designed spacing between the two gate electrodes. Exemplarily, the width of the first opening 108 can be 70 nm to 100 nm, for example, 85 nm.

[0052] Refer to Figure 9 and Figure 10 As shown, perform step S3 to form a first sidewall 109 in the first opening 108, and the first sidewall 109 is an annular structure that adheres to the sidewalls of the first opening 108.

[0053] In this embodiment, refer to Figure 9 As shown, the first sidewall 109 spans across the active region 100, and the two opposite ends (i.e., the left and right ends) of the first sidewall 109 extend beyond the active region 100 and are located on the isolation structures 101 on both sides of the active region 100.

[0054] Exemplarily, step S3 may specifically include: forming a first sidewall material layer on the second hard mask layer 107, and the first sidewall material layer conformally covers the top surface of the second hard mask layer 107, the sidewalls and the bottom surface of the first opening 108; using an anisotropic dry etching process to etch away the first sidewall material layer on the top surface of the second hard mask layer 107 and a part of the first sidewall material layer at the bottom of the first opening 108, and retaining the first sidewall material layer on the sidewalls of the first opening 108 as the first sidewall 109.

[0055] The material of the first sidewall 109 is different from that of the second hard mask layer 107 and the first hard mask layer. In this way, during the etching process of forming the first sidewall 109, the etching rate of the first sidewall material layer is much greater than that of the second hard mask layer 107 and the first hard mask layer, that is, the first sidewall material layer can be selectively etched, so that a high-precision first sidewall 109 can be formed and the etching damage to the second hard mask layer 107 and the first hard mask layer is small. Exemplarily, the material of the first sidewall 109 includes but is not limited to amorphous silicon.

[0056] Reference Figure 10 As shown, the width D1 of the first sidewall 109 can be set according to the gate electrode lengths of the two memory transistors of the paired memory cell and the designed spacing between the two gate electrodes. Exemplarily, the width of the first sidewall 109 is 25 nm to 35 nm, for example, 30 nm.

[0057] Reference Figure 11 and Figure 12 As shown, step S4 is executed to fill the third hard mask layer 110 in the first opening 108.

[0058] Exemplarily, step S4 may specifically include: forming a third hard mask layer 110 on the substrate, the third hard mask layer 110 covers the second hard mask layer 107 and the first sidewall 109, and fills the first opening 108; removing a part of the third hard mask layer 110 through a chemical mechanical polishing process or a back etching process, that is, removing the third hard mask layer 110 above the second hard mask layer 107 to expose the top surface of the second hard mask layer 107.

[0059] It should be noted that in this embodiment, when step S4 is executed, the height of the storage area of the substrate is different from the height of other areas on its side. When removing a part of the third hard mask layer 110, if a chemical mechanical polishing process is used, the structure of other areas will be damaged. Therefore, it is preferred to use a back etching process to remove a part of the third hard mask layer 110. In other embodiments, if there is no large height difference in each area of the substrate, a chemical mechanical polishing process can also be selected to remove a part of the third hard mask layer 110.

[0060] In this embodiment, the third hard mask layer 110 may not need to fill the first opening 108 completely. That is, even if there are small seams or pits in the central region of the third hard mask layer 110 (i.e., the region in the first opening 108 that is not filled by the first sidewall 109), it does not affect the third hard mask layer 110's protection of the sidewalls of the first sidewall 109 it covers and the silicon oxynitride layer 106. Exemplarily, the third hard mask layer 110 can be formed by an atomic layer deposition (ALD) process, which can improve the filling quality of the third hard mask layer 110 in filling the first opening 108.

[0061] In this embodiment, the material of the third hard mask layer 110 is different from that of the first sidewall 109, the second hard mask layer 107, and the first hard mask layer, so as to selectively etch and remove the second hard mask layer 107 subsequently and facilitate the control of the formation of the subsequent second sidewall. Exemplarily, the third hard mask layer 110 includes, but is not limited to, silicon oxide.

[0062] Refer to Figure 13 and Figure 14 As shown, perform step S5 to remove the second hard mask layer 107.

[0063] In this embodiment, the second hard mask layer 107 can be removed by a wet etching process. The etching solution used in the wet etching process includes diluted hydrofluoric acid (DHF) and H 3 PO 4 , so that the etching rate of the second hard mask layer 107 is much greater than that of the silicon oxynitride layer 106, the first sidewall 109 made of amorphous silicon, and the third hard mask layer 110 made of silicon oxide. That is, the second hard mask layer 107 can be selectively etched, and then the second hard mask layer 107 can be removed completely and the etching process is easy to control.

[0064] Refer to Figure 15 and Figure 16 As shown, perform step S6 to form a second sidewall 111 on the outer side of the first sidewall 109. The second sidewall 111 surrounds and adheres to the first sidewall 109.

[0065] Exemplarily, step S6 may include: forming a second sidewall material layer on the first hard mask layer. The second sidewall material layer covers the first sidewall 109, the third hard mask layer 110, and the first hard mask layer; using an anisotropic dry etching process to etch and remove part of the second sidewall material layer and stop on the silicon oxynitride layer 106, that is, removing the second sidewall material layer above the first sidewall 109 and above the third hard mask layer 110, and retaining the second sidewall material layer on the sidewall of the first sidewall away from the third hard mask layer 110 as the second sidewall 111.

[0066] As Figure 15As shown, the second sidewall 111 is also a ring structure. The second sidewall 111 spans across the active region 100 and the two opposite ends (i.e., Figure 15 the left and right ends) are located on the isolation structures 101 on both sides of the active region 100.

[0067] It should be noted that, referring to Figure 16 as shown, since over-etching was performed when forming the first opening 108 and it stopped in the silicon oxynitride layer 106 of the first hard mask layer, the bottom surface of the first sidewall 109 is slightly lower than the bottom surface of the second sidewall 111.

[0068] In this embodiment, the materials of the first sidewall 109 and the second sidewall 111 can be the same, that is, the materials of both the first sidewall 109 and the second sidewall 111 are amorphous silicon. This facilitates the subsequent removal of the first sidewall 109 and the second sidewall 111 simultaneously, contributing to the simplification of the process steps.

[0069] In this embodiment, the width D2 of the second sidewall 111 can be set according to the gate electrode length of the memory cell. Exemplarily, the width of the second sidewall 111 is 30 nm to 40 nm, for example, 35 nm. The thickness of the second sidewall material layer can be set according to the width of the second sidewall 111. Exemplarily, the thickness of the second sidewall material layer is 300 Å to 500 Å, for example, 400 Å; the formation temperature of the second sidewall material layer can be below 400 °C.

[0070] Referring to Figure 17 and Figure 18 as shown, perform step S7 to remove the third hard mask layer 110.

[0071] Exemplarily, a wet etching process can be used to remove the third hard mask layer 110. For example, diluted hydrofluoric acid can be used to remove the third hard mask layer 110 which is silicon oxide. Diluted hydrofluoric acid can selectively etch silicon oxide and cause little damage to the silicon oxynitride layer 106, the first sidewall 109 and the second sidewall 111 which are amorphous silicon, thus facilitating the control of the etching of the third hard mask layer 110.

[0072] Referring to Figure 19 and Figure 20 as shown, form a first photoresist mask layer 113 on the first hard mask layer. The first photoresist mask layer 113 covers a part of the logic region (corresponding to the gate oxide layer 103) to protect the part of the gate material layer in the logic region, and the first photoresist mask layer 113 exposes the memory region (corresponding to the charge trap layer 102).

[0073] It should be noted that, in addition to the part of the logic region, the first photoresist mask layer 113 can also cover other regions that need to be protected. Specifically, the pattern of the first photoresist mask layer 113 can be set according to the actual situation.

[0074] The first photoresist mask layer 113 can be formed through exposure and development processes. The first photoresist mask layer 113 can use a KrF photoresist. The KrF photoresist is a photoresist fabricated using a 248 nm KrF light source, suitable for line width processes above 0.13 μm. Using a KrF photoresist helps to form high-precision small-sized patterns.

[0075] Reference Figure 20 As shown, a bottom anti-reflection coating (BARC) 112 can also be formed between the first photoresist mask layer 113 and the first hard mask layer. Setting the bottom anti-reflection coating 112 can reduce the reflection of light on the lower surface of the photoresist during the exposure of the first photoresist mask layer 113, so that most of the exposure energy is absorbed by the photoresist, which helps to improve the pattern accuracy of the first photoresist mask layer 113.

[0076] Next, step S8 is executed. Using the first sidewall 109 and the second sidewall 111 as masks, the first hard mask layer and the gate material layer 104 are etched downward in sequence to form a gate ring 104a.

[0077] Exemplarily, step S8 can include: Reference Figure 19 and Figure 20 As shown, using the first sidewall 109, the second sidewall 111, and the first photoresist mask layer 113 together as masks, the bottom anti-reflection coating 112 and the silicon oxynitride layer 106 of the first hard mask layer are etched downward, and a slight over-etching can be performed and stopped in the amorphous carbon layer 105 of the first hard mask layer; reference Figure 21 and Figure 22 As shown, continue to etch the amorphous carbon layer 105 downward and stop on the gate material layer 104; reference Figure 23 and Figure 24 As shown, continue to etch the gate material layer 104 downward and stop on the charge trap layer 102 and the gate oxide layer 103. The remaining part of the gate material layer 104 serves as the gate ring 104a and part serves as the select gate 104b located on the logic region; reference Figure 25 and Figure 26 As shown, then etch the charge trap layer 102 and the gate oxide layer 103 downward and stop on the substrate.

[0078] Since the surface of the substrate is not flat when coating the bottom anti-reflection coating 112, there may be differences in the thickness of the bottom anti-reflection coating 112 between different regions. Therefore, when etching the bottom anti-reflection coating 112, an appropriate proportion of over-etching can be performed and stopped in the silicon oxynitride layer 106, which can ensure that the bottom anti-reflection coating 112 is etched through.

[0079] After etching the charge trap layer 102 and the gate oxide layer 103, reference Figure 27 and Figure 28As shown, the first sidewall 109, the second sidewall 111, the first photoresist mask layer 113, the bottom anti-reflection coating 112, and the first hard mask layer are removed.

[0080] It should be noted that during the actual etching process, the mask will damage part of the thickness. Exemplarily, referring to Figure 20 and Figure 22 As shown, after the etching of the amorphous carbon layer 105 is completed, the first photoresist mask layer 113 can be etched and consumed; referring to Figure 22 and Figure 24 As shown, after the etching of the gate material layer 104 is completed, the first sidewall 109, the second sidewall 111, and the bottom anti-reflection coating 112 can be etched and consumed; referring to Figure 24 and Figure 26 As shown, after the etching of the charge trap layer 102 and the gate oxide layer 103 is completed, the silicon oxynitride layer 106 can be etched and consumed; after the etching of the charge trap layer 102 and the gate oxide layer 103 is completed, only the remaining amorphous carbon layer 105 needs to be removed to expose the gate electrode 104c of the memory tube and the select gate 104b of the select tube, but not limited thereto.

[0081] Referring to Figure 27 As shown, the formed gate ring 104a straddles the active region 100, and the two opposite ends of the gate ring 104a are located on the isolation structures 101 on both sides of the active region 100. The two ends of the formed select gate 104b can also slightly extend beyond its corresponding active region 100.

[0082] In this embodiment, the formed gate ring 104a is located on the storage area.

[0083] It should be noted that the transistor corresponding to the select gate 104b formed in this embodiment can be the bit line select transistor in the bit line selection circuit for selectively connecting the local bit line and the global bit line, but not limited thereto.

[0084] Referring to Figure 30 As shown, perform step S9 to etch and remove the two opposite ends of the gate ring 104a, so that the gate ring 104a cuts out the gate electrodes 104c of the two memory tubes of the same group of memory cells.

[0085] Exemplarily, step S9 may include: as Figure 29 As shown, a second photoresist mask layer 114 is formed on the substrate. The second photoresist mask layer 114 has a plurality of second openings 114a. The second openings 114a are located above the isolation structure 101, and the two opposite ends of the gate ring 104a are exposed from the corresponding second openings 114a; as Figure 30 As shown, using the second photoresist mask layer 114 as a mask, etch and remove the two opposite ends of the gate ring 104a and stop at the isolation structure 101.

[0086] It should be noted that in this embodiment, the two opposite ends of the gate ring 104a are located on the isolation structure 101 on both sides of the active region 100, and the materials of the gate ring 104a and the isolation structure 101 are different. In this way, when etching and removing the two opposite ends of the gate ring 104a, the etching can stop on the isolation structure 101, and the etching control of the gate ring 104a is relatively convenient.

[0087] In this embodiment, as Figure 30 shown, the gate electrode 104c of the memory tube formed by splitting the gate ring 104a can slightly exceed its corresponding active region 100.

[0088] In this embodiment, the gate ring 104a can span one active region 100. Thus, after etching and removing the two opposite ends of the gate ring 104a, one gate ring 104a corresponds to form the gate electrodes 104c of two memory tubes of a pair of memory cells. In other embodiments, the gate ring 104a can also span multiple active regions 100. In the step of etching and removing the two opposite ends of the gate ring 104a, the second photoresist mask layer 114 can also expose a part of the gate ring 104a on the isolation structure between adjacent active regions 100. In this way, when etching the gate ring 104a, a part of the gate ring 104a on the isolation structure between adjacent active regions 100 can also be removed, so that one gate ring 104a can correspond to be split to form the gate electrodes 104c of multiple pairs of memory cells.

[0089] In this embodiment, referring to Figure 30 and Figure 1 , the two memory tubes of the same pair of memory cells of the paired structure non-volatile memory are electrically connected through the active region between the gate electrodes 104c of the two memory tubes. Referring to Figure 1 and Figure 2 shown, a column of paired memory cells can correspond to a group of bit lines (BL). A group of bit lines includes two bit lines. The first memory tube M1 of the same column of paired memory cells is connected to one of the group of bit lines, and the second memory tube M2 of the same column of paired memory cells is connected to the other of the group of bit lines, but it is not limited thereto. When performing data operations, one memory tube of the same pair of memory cells can be used as the selection tube of the other memory tube.

[0090] It should be noted that precisely because in this application, the two memory tubes of the same pair of memory cells are electrically connected through the active region between the two gate electrodes 104c, on the basis of achieving physical and electrical isolation, the distance between the two gate electrodes 104c of the same pair of memory cells can be minimized as much as possible, so that this distance can be less than the resolution of photolithography.

[0091] Optionally, after the etched split gate ring 104a forms the gate electrode 104c of the memory cell, a doping substance can be injected into the substrate between the two gate electrodes 104c of the same pair of memory cells to form a doped region (not shown in the figure). This doped region can be used to control the current between the two memory cells of the same pair and prevent leakage between the two memory cells of the same pair.

[0092] The method for manufacturing the paired structure non-volatile memory provided by the present invention has the following advantages: (1) Using the first sidewall 109 and the second sidewall 111 as masks, the gate material layer 104 is etched to form the gate ring 104a, and then the two opposite ends of the gate ring 104a are etched away, so that the gate ring 104a is split into the gate electrodes 104c of the two memory cells of the same pair. In this way, the distance between the gate electrodes of the two memory cells of the same pair is not restricted by the resolution of lithography, and the distance between the gate electrodes of the two memory cells of the same pair is smaller, thereby reducing the area of the paired memory cells of the paired structure non-volatile memory, helping to reduce the size and cost of the memory chip, and improving the cost performance of the memory chip; (2) In this application, the first sidewall 109 is formed in the first opening 108 of the second hard mask layer 107, then the third hard mask layer 110 is filled in the first opening 108, and then the second hard mask layer 107 is removed. Then, the second sidewall 111 is formed outside the first sidewall 109 and the third hard mask layer 110 is removed. After that, using the first sidewall 109 and the second sidewall 111 as masks, the first hard mask layer and the gate material layer 104 are etched downward in sequence to form the gate ring 104a. In this way, the gate ring 104a can be defined by one-step self-aligned etching, that is, the distance between the gate electrodes of the two memory cells of the same pair and the length of the gate electrode of the memory cell are defined by one-step self-aligned etching. The process is relatively simple, and it helps to improve the size consistency of the two gate electrodes of the paired memory cells and the performance consistency of the two memory cells of the paired memory cells, thereby improving the performance of the paired structure non-volatile memory.

[0093] The above description is only a description of the preferred embodiments of the present invention, and does not limit any scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for preparing a pair structure non-volatile memory, wherein the pair storage unit of the pair structure non-volatile memory comprises two electrically connected storage tubes, characterized in that: The preparation method comprises: Providing a substrate, on which a gate material layer, a first hard mask layer, and a second hard mask layer are sequentially stacked from bottom to top are formed; forming a first opening in the second hard mask layer; forming a first side wall in the first opening, wherein the first side wall is an annular structure covering a side wall of the first opening; filling a third hard mask layer in the first opening; removing the second hard mask layer; A second side wall is formed on the outer side of the first side wall, and the second side wall surrounds and covers the first side wall; removing the third hard mask layer; Using the first sidewall spacer and the second sidewall spacer as masks, sequentially etching the first hard mask layer and the gate material layer downwards to form a gate ring; Etching and removing two opposite ends of the gate ring, so that the gate ring divides the gate electrodes of two storage tubes of the same pair of storage cells; The materials of the first sidewall spacer and the second sidewall spacer are the same; the materials of the first sidewall spacer, the first hard mask layer, the second hard mask layer and the third hard mask layer are different.

2. The method for preparing the pair structure non-volatile memory according to claim 1, characterized in that: In the step of providing a substrate, the substrate has an isolation structure and an active area defined by the isolation structure; In the step of forming the gate ring, the gate ring spans across the active area, and two opposite ends of the gate ring are located on the isolation structures at two sides of the active area.

3. The method for preparing the pair structure non-volatile memory according to claim 2, characterized in that: The first sidewall spacer spans across the active region, and two opposite ends of the first sidewall spacer exceed the active region and are located on the isolation structures at two sides of the active region.

4. The method for preparing the pair structure non-volatile memory according to claim 2, characterized in that: The method of etching and removing two opposite ends of the gate ring comprises: Forming a second photoresist mask layer on the substrate, wherein the second photoresist mask layer has a plurality of second openings, the second openings are located above the isolation structure, and two opposite ends of the gate ring are exposed from the corresponding second openings; Using the second photoresist mask layer as a mask, etching is performed to remove two opposite ends of the gate ring and stop at the isolation structure.

5. The method for preparing the pair structure non-volatile memory according to claim 2, characterized in that: The two storage tubes of the same pair of storage cells are electrically connected via an active region between gate electrodes of the two storage tubes.

6. The method for preparing the pair structure non-volatile memory according to claim 1, characterized in that: The method of filling the first opening with a third hard mask layer comprises: forming a third hard mask layer on the substrate, wherein the third hard mask layer covers the second hard mask layer and the first sidewall spacer and fills the first opening; The third hard mask layer above the second hard mask layer is removed by a chemical mechanical polishing process or an etch-back process.

7. The method for preparing the pair structure non-volatile memory according to claim 1, characterized in that: In the step of providing a substrate, the substrate has a storage area and a logic area, a charge trap layer is formed on the storage area, a gate oxide layer is formed on the logic area, and the gate material layer covers the charge trap layer and the gate oxide layer; the gate ring formed subsequently is located on the storage area.

8. The method for preparing the pair structure non-volatile memory according to claim 7, characterized in that: After removing the third hard mask layer and before sequentially etching downward the first hard mask layer and the gate material layer, the preparation method further comprises: forming a first photoresist mask layer on the first hard mask layer, wherein the first photoresist mask layer covers a portion of the logic area and exposes the storage area; The step of sequentially etching downward the first hard mask layer and the gate material layer comprises: using the first side wall, the second side wall and the first photoresist mask layer together as a mask, etching downward the first hard mask layer, the gate material layer, the charge trap layer and the gate oxide layer and stopping on the substrate, retaining part of the gate material layer as the gate ring and part as the selection tube gate located on the logic area.

9. The method for preparing the pair structure non-volatile memory according to claim 1, characterized in that: After sequentially etching downward the first hard mask layer and the gate material layer and before etching away two opposite ends of the gate ring, the preparation method further includes: removing the first sidewall spacer, the second sidewall spacer and the first hard mask layer.

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