Resistor and method for manufacturing the same, integrated circuit, electronic device

Abstract

The present disclosure provides a resistor and a preparation method thereof, an integrated circuit and an electronic device, and relates to the technical field of semiconductor chips, and aims to solve the problem that the size of a resistor increases when the resistance of the resistor is increased. The integrated circuit comprises a substrate, a channel layer and a barrier layer which are stacked; the integrated circuit has a first device area and a second device area which are arranged at intervals; the integrated circuit further comprises a resistor located in the first device area and a transistor located in the second device area; the resistor comprises a conductive channel; the integrated circuit further comprises a P-type GaN layer located on the side of the barrier layer away from the substrate; the P-type GaN layer comprises a first part located in the first device area and a second part located in the second device area; the first part and the conductive channel overlap in a first direction, and the first direction is perpendicular to the substrate; wherein the thickness of the first part is less than the thickness of the second part. The above-mentioned resistor is applied to an electronic device to provide resistance.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor chips, and particularly relates to a resistor and a preparation method thereof, an integrated circuit and an electronic device. BACKGROUND

[0002] Gallium nitride (GaN) is a semiconductor material with a high bandgap, which exhibits excellent performance in the field of high-frequency and high-power electronic devices. Compared with traditional silicon (Si) materials, GaN has higher electron mobility and breakdown field strength, which makes it very suitable for high-frequency application occasions. However, the parasitic inductance in the interconnection bonding wire of the GaN packaged device and the PCB (Printed Circuit Board) trace will cause voltage spikes / oscillations at high frequencies, leading to various reliability problems, which becomes a bottleneck for the development of high-frequency application potential of GaN devices.

[0003] In some examples, by monolithically integrating the gate drive circuit with the power switch, the parasitic inductance between the gate driver and the power device can be reduced, thereby obtaining a clearer gate drive signal and more robust switching characteristics. The monolithically integrated component module includes, for example, GaN power switch devices, low-voltage GaN devices, diodes, capacitors, and resistors, and various functional modules are built based on these components, making the system design more compact.

[0004] In order to realize more cost-effective GaN power ICs (Integeral Cirtcuit), promote the development of high integration of GaN power ICs, and reduce the size and process complexity of semiconductor devices, it is of great significance. SUMMARY

[0005] Embodiments of the present disclosure provide a resistor and a preparation method thereof, an integrated circuit and an electronic device, aiming to provide a resistor with high square resistance and adjustable square resistance, and at the same time reduce the size of the resistor and the size of the integrated circuit including the resistor.

[0006] To achieve the above-mentioned purpose, embodiments of the present disclosure adopt the following technical solutions:

[0007] On the one hand, an integrated circuit is provided, which includes: a substrate and a channel layer and a barrier layer stacked on one side of the substrate; the integrated circuit has a first device region and a second device region spaced apart; the integrated circuit also includes: a resistor located in the first device region and a transistor located in the second device region; the resistor includes: a first electrode and a second electrode spaced apart and located on a side of the channel layer away from the substrate, and a conductive channel electrically connecting the first electrode and the second electrode; the integrated circuit also includes: a P-type GaN layer located on a side of the barrier layer away from the substrate; the P-type GaN layer includes: a first portion located in the first device region and a second portion located in the second device region; the first portion and the conductive channel overlap in a first direction, and the first direction is perpendicular to the substrate; wherein the thickness of the first portion is less than the thickness of the second portion.

[0008] The integrated circuit provided by the above-mentioned embodiments of the present disclosure, by setting a P-type GaN layer including a first part and a second part with different thicknesses, the thickness of the first part is smaller than the thickness of the second part, the first part can consume the 2DEG in the conductive channel and the 2DEG in the conductive channel is not depleted to obtain a resistor with a larger square resistance, and the square resistance of the resistor can be adjusted by adjusting the thickness of the first part; compared with the increase in the resistance of the resistor by extending the length of the conductive channel provided in some embodiments, extending the length of the conductive channel will increase the size of the resistor. The above-mentioned embodiments of the present disclosure achieve the purpose of increasing the square resistance of the resistor through the setting of the first part, and the size of the resistor can be relatively small, thereby obtaining a resistor with high square resistance and adjustable square resistance and an integrated circuit including the resistor.

[0009] In some embodiments, a ratio of the thickness of the first portion to the thickness of the second portion ranges from 1% to 40%.

[0010] In some embodiments, the thickness of the first portion ranges from 1 nm to 40 nm.

[0011] In some embodiments, the first portion has a rectangular shape in an orthographic projection onto the substrate.

[0012] In some embodiments, one end of the first portion along the second direction contacts the first pole, and the other end of the first portion along the second direction contacts the second pole; wherein the second direction is parallel to the substrate and parallel to the direction in which the first pole and the second pole are arranged.

[0013] In some embodiments, the first portion includes: a first sub-portion and a second sub-portion, the first sub-portion and the second sub-portion are arranged in a direction parallel to the substrate; wherein the thickness of the first sub-portion is smaller than the thickness of the second sub-portion.

[0014] In some embodiments, one end of the first portion along the second direction contacts one of the first pole and the second pole, and the other end of the first portion along the second direction is spaced apart from the other of the first pole and the second pole.

[0015] In some embodiments, the integrated circuit further includes: the transistor includes: a third electrode and a fourth electrode located on a side of the channel layer away from the substrate and spaced apart, and a control electrode located between the third electrode and the fourth electrode; the control electrode is located on a side of the second part away from the substrate; wherein the thickness of the second part ranges from 80nm to 100nm.

[0016] In some embodiments, the integrated circuit further includes: an isolation region located between the first device region and the second device region; the isolation region is configured to electrically isolate the first device region from the second device region.

[0017] On the other hand, a resistor is provided, comprising: a substrate and a channel layer and a barrier layer stacked on one side of the substrate; the resistor further comprises: a first pole and a second pole spaced apart on a side of the channel layer away from the substrate, and a conductive channel electrically connecting the first pole and the second pole; the resistor further comprises: a first portion located on a side of the barrier layer away from the substrate, the material of the first portion comprising P-type GaN; the first portion and the conductive channel overlap in a first direction; wherein the thickness of the first portion ranges from 1 nm to 40 nm.

[0018] In some embodiments, the first portion has a rectangular shape in an orthographic projection onto the substrate.

[0019] On the other hand, a method for preparing a resistor is provided, comprising forming a channel layer on one side of a substrate; forming a barrier layer on a side of the channel layer away from the substrate; forming a first pole and a second pole spaced apart on a side of the channel layer away from the substrate, the first pole and the second pole being electrically connected via a conductive channel; forming a first portion on a side of the barrier layer away from the substrate, the material of the first portion comprising P-type GaN; the first portion and the conductive channel overlap in a first direction, the first direction being perpendicular to the substrate; and the thickness of the first portion ranging from 1 nm to 40 nm.

[0020] In some embodiments, a first portion is formed on a side of the barrier layer away from the substrate, including: forming an initial first portion having a first thickness on a side of the barrier layer away from the substrate; forming a first mask layer on a side of the initial first portion away from the substrate; removing a portion of the first mask layer located in a first device region; the first device region is a region where a resistor is formed; removing a portion of the initial first portion away from the substrate to form an initial first portion having a second thickness; forming a second mask layer on a side of the initial first portion having the second thickness away from the substrate; removing a portion of the second mask layer located in the first sub-region, and the first device region excluding the region where the first portion is pre-formed is the first sub-region; removing a portion of the initial first portion located in the first sub-region to obtain the first portion.

[0021] In some embodiments, the ratio of the second thickness to the first thickness ranges from 1% to 40%.

[0022] In some embodiments, a first portion is formed on a side of the barrier layer away from the substrate, including: forming an initial first portion having a first thickness on a side of the barrier layer away from the substrate; forming a first mask layer on a side of the initial first portion away from the substrate; removing a portion of the first mask layer located in the first sub-region; removing a portion of the initial first portion located in the first sub-region and away from the substrate; removing a portion having a second thickness; removing the remaining portion of the first mask layer; removing a portion of the initial first portion having a third thickness away from the substrate to obtain the first portion; wherein the sum of the third thickness and the second thickness is equal to the first thickness.

[0023] In some embodiments, the ratio of the third thickness to the first thickness ranges from 60% to 99%.

[0024] In some embodiments, the material of the mask layer includes: at least one of silicon oxide and silicon nitride; the mask layer includes: a first mask layer and a second mask layer.

[0025] On the other hand, an electronic device is provided, comprising the integrated circuit and a circuit board according to any one of the above embodiments, wherein the integrated circuit is disposed on the circuit board.

[0026] It can be understood that the beneficial effects achieved by the resistor, the method for manufacturing the resistor, and the electronic device provided by the above embodiments of the present disclosure can be referred to the beneficial effects of the integrated circuit mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure.

[0028] Figure 1 The structure of the integrated circuit according to some embodiments of the present disclosure is shown in FIG. Figure 1 ;

[0029] Figure 2 Based on Figure 1 A cross-sectional view of the integrated circuit shown along section line AA;

[0030] Figure 3 The structure of the integrated circuit according to some embodiments of the present disclosure is shown in FIG. Figure 2 ;

[0031] Figure 4 Based on Figure 3 A cross-sectional view of the integrated circuit shown along section line BB;

[0032] Figure 5 is a graph showing the relationship between the concentration of the two-dimensional electron gas in the conductive channel and the thickness of the P-type GaN layer according to some embodiments;

[0033] Figure 6The structure of the resistor according to some embodiments of the present disclosure is shown in FIG. Figure 1 ;

[0034] Figure 7 The structure of the resistor according to some embodiments of the present disclosure is shown in FIG. Figure 2 ;

[0035] Figure 8 is a flow chart of a method for preparing a resistor according to some embodiments of the present disclosure;

[0036] Figure 9 The structure corresponding to each step of the method for preparing a resistor according to some embodiments of the present disclosure is Figure 1 ;

[0037] Figure 10 The structure corresponding to each step of the method for preparing a resistor according to some embodiments of the present disclosure is Figure 2 ;

[0038] Figure 11 The structure corresponding to each step of the method for preparing a resistor according to some embodiments of the present disclosure is Figure 3 ;

[0039] Figure 12 The structure corresponding to each step of the method for preparing a resistor according to some embodiments of the present disclosure is Figure 4 ;

[0040] Figure 13 Schematic diagram of the structure of an electronic device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0041] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0042] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0043] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0044] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0045] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0046] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0047] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0048] In the context of this disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers, and “over” or “over” means not only “over” or “above” something, but also includes “over” or “above” something with no intervening features or layers (i.e., directly on something).

[0049] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0050] As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0051] Semiconductor: A semiconductor is a material with electrical conductivity between that of a conductor and an insulator at room temperature. Semiconductors include intrinsic semiconductors and impurity semiconductors. Pure semiconductors, free of impurities and defects, with equal concentrations of electrons and holes, are called intrinsic semiconductors.

[0052] In some examples, such as Figure 1 As shown, an integrated circuit 100 is provided, which has different device regions. For example, the integrated circuit 100 includes a first device region 11 and a second device region 12; the integrated circuit 100 includes a resistor 10 located in the first device region 11, and the integrated circuit 100 also includes a high electron mobility transistor (HEMT), a diode or a capacitor located in the second device region 12, etc., which are not limited here.

[0053] For example, Figure 1 and Figure 2 As shown, the integrated circuit 100 includes a substrate 101 and a channel layer 102 and a barrier layer 103 stacked on one side of the substrate 101 .

[0054] Exemplarily, the material of the substrate 101 includes silicon, silicon carbide, gallium nitride, sapphire or diamond, etc., which is not limited here.

[0055] Exemplarily, the material of the channel layer 102 comprises GaN or unintentionally doped AlN; the material of the barrier layer 103 comprises at least one of AlN and AlGaN. The following is described by taking the material of the channel layer 102 as GaN and the material of the barrier layer 103 as AlGaN as an example.

[0056] The AlGaN / GaN can form a heterojunction, and the AlGaN / GaN heterojunction forms a high-density two-dimensional electron gas (2DEG) at the heterojunction interface through spontaneous polarization and piezoelectric polarization effects, and the two-dimensional electron gas is spatially separated from ionized impurities, forming a resistor 10 with a certain resistance.

[0057] In some examples, as shown in Figure 1 and Figure 2 The first device region 11 and the second device region 12 are spaced apart, for example, an isolation region 13 is arranged between the first device region 11 and the second device region 12, and the isolation region 13 is configured to electrically isolate the first device region 11 and the second device region 12. The two-dimensional electron gas at the part of the interface between the channel layer 102 and the barrier layer 103 located in the isolation region 13 is depleted, so that the 2DEG of the first device region 11 and the second device region 12 is electrically isolated.

[0058] Exemplarily, ion implantation is performed on the part of the barrier layer 103 located in the isolation region 13 to deplete the 2DEG at the interface between the channel layer 102 and the barrier layer 103 located in the isolation region 13, so that the 2DEG of the first device region 11 and the second device region 12 is electrically isolated.

[0059] In some examples, as shown in Figure 1 and Figure 2 The resistor 10 comprises a first electrode 104 and a second electrode 105 spaced apart on the side of the channel layer 102 away from the substrate 101, and the conductive channel 106 electrically connects the first electrode 104 and the second electrode.

[0060] Exemplarily, the material of the first electrode 104 and the second electrode 105 is independently selected from at least one of Ti / Al / Ti / Au, Ti / Al / Ni / Au, Ta / Ti / Ni / Au, Ti / Ag, Ti / Al / Ni / TiN and Ti / Al / Ti / TiN.

[0061] Exemplarily, the conductive channel 106 is formed by a 2DEG at the interface of the channel layer 102 and the barrier layer 103 at the first device region 11, and the conductive channel 106 is electrically connected to the first pole 104 and the second pole 105. The conductive channel 106 has a certain square resistance. For example, the size of the conductive channel 106 is changed to form a resistor 10 with different resistance values. Here, square resistance refers to the voltage drop generated by the current density per unit area (i.e., the amount of current per unit area) in the thickness direction of the material. The unit of square resistance is ohm per square (Ω / □). The square resistance of the conductive channel 106 is positively correlated with the resistance value of the resistor 10, that is, the larger the square resistance of the conductive channel 106, the larger the resistance value of the resistor 10.

[0062] For example, Figure 1 As shown, the conductive channel 106 has a width W1 and a length L1. The length L1 of the conductive channel 106 is the extended length of the conductive channel 106, and the width W1 of the conductive channel 106 is the average value of the dimension of the conductive channel 106 in a direction perpendicular to the extended length. The smaller the width W1 of the conductive channel 106, the greater the resistance of the resistor 10, and the longer the length L1 of the conductive channel 106, the greater the resistance of the resistor 10.

[0063] For example, the conductive channel 106 is curved or serpentine, and the length L1 of the conductive channel 106 can be the length of one of the contour lines L2 of the conductive channel 106, or the average length of the two contour lines L2 of the conductive channel 106, or the length L1 of the conductive channel 106 is the length of a line connecting the midpoint of the width W1 of the conductive channel 106 in the direction in which the conductive channel 106 extends, and this is not limited here. For example, in an embodiment of the present disclosure, the length L1 of the conductive channel 106 is the length of a line connecting the midpoint of the width W1 of the conductive channel 106 in the direction in which the conductive channel 106 extends, and the length L1 of the conductive channel 106 is equal to the length of a line connecting the midpoint N of the width W1 of the conductive channel 106 near the first pole 104 to the midpoint M of the width W1 of the conductive channel 106 near the second pole 105 in the direction in which the conductive channel 106 extends.

[0064] In order to obtain a resistor 10 with a larger resistance value, on the one hand, the width W1 of the conductive channel 106 can be reduced. However, due to the influence of the process accuracy of forming the conductive channel 106, it is difficult to continue to reduce the width W1 of the conductive channel 106 after it is reduced to a certain value; on the other hand, the length L1 of the conductive channel 106 can be increased. For example, the conductive channel 106 can be formed into a curved shape, and the distance between the first pole 104 and the second pole 105 can be increased to obtain a resistor 10 with a longer length L1 of the conductive channel 106, thereby obtaining a resistor 10 with a larger resistance value.

[0065] However, increasing the length L1 of the conductive channel 106 increases the area of the integrated circuit 100, which is not conducive to the preparation of the integrated circuit 100 with small size.

[0066] Based on this, as shown in Figure 3 and Figure 4 The embodiment of the present disclosure provides an integrated circuit 100, which further comprises: a P-type GaN layer 107 located on the side of the barrier layer 103 away from the substrate; the P-type GaN layer 107 comprises: a first part 171 located in the first device area 11 and a second part 172 located in the second device area 12; the first part 171 and the conductive channel 106 have an overlap in the first direction Y, and the first direction Y is perpendicular to the substrate 101, wherein the thickness d1 of the first part 171 is less than the thickness d2 of the second part 172, that is, d1 < d2.

[0067] For example, the P-type GaN layer 107 comprises Mg-doped GaN, wherein the doping concentration of Mg ranges from 1×10 18 cm -3 to 6×10 19 cm -3 The doping concentration refers to the number of impurities contained in a unit volume or unit mass of material, which is usually expressed in the number of atoms or ions.

[0068] The P-type GaN layer 107 can consume 2DEG in the conductive channel 106, where the consumption can be understood as the concentration of 2DEG in the conductive channel 106 is reduced due to the arrangement of the P-type GaN layer 107. That is, by arranging the P-type GaN layer 107 with different thicknesses, the concentration of 2DEG in the conductive channel 106 can be adjusted.

[0069] For example, the integrated circuit 100 comprises a transistor located in the second device area 12, the transistor comprises: a third pole 121 and a fourth pole 122 located on the side of the channel layer 102 away from the substrate 101 and arranged at intervals, and a control pole 123 located between the third pole 121 and the fourth pole 122; the control pole 123 is located on the side of the second part 172 away from the substrate 101.

[0070] For example, the transistor is a HEMT, and the second part 172 can deplete 2DEG in the conductive channel 106, so that the transistor is a normally closed transistor.

[0071] Since the thickness d1 of the first part 171 is less than the thickness d2 of the second part 172, the first part 171 can consume 2DEG in the conductive channel 106, and 2DEG in the conductive channel 106 is not depleted. Therefore, the arrangement of the first part 171 increases the sheet resistance of the first device area 11, and the first device area 11 can be used to arrange a resistor 10 with high resistance, thereby obtaining a resistor 10 with a large resistance value.

[0072] Figure 5 The graph shows the relationship between the concentration of the two-dimensional electron gas in the conductive channel 106 and the thickness of the P-type GaN layer 107, wherein the abscissa represents the thickness of the P-type GaN layer 107 in nm; the ordinate represents the concentration of the 2DEG in the conductive channel 106 in cm -2 .

[0073] For example, Figure 1 and Figure 2 As shown, according to the electrical performance characterization method, it can be tested that the square resistance of the conductive channel 106 after the P-type GaN layer 107 is completely etched is about 300Ω / □. In the case where the P-type GaN layer 107 is not provided, to form a resistor 10 with a resistance of 600kΩ, when the width W1 of the conductive channel 106 is 1μm, the required length L1 of the conductive channel 106 is: 600kΩ÷300Ω / □×1μm=2mm. In the orthographic projection onto the substrate 101, the area of ​​the conductive channel 106 is about 2mm×1μm=2000μm. 2 .

[0074] like Figures 3 to 5 As shown in FIG. 1 , the concentration of 2DEG in the conductive channel 106 without the P-type GaN layer 107 is approximately 8×10 12 cm -2 When the thickness of the P-type GaN layer 107 is 30 nm, the concentration of the 2DEG in the conductive channel 106 is about 0.8 x 10 12 cm -2 According to the square resistance of the conductive channel 106 after completely etching the P-type GaN layer 107, which is approximately 300Ω / □, the square resistance of the conductive channel 106 can be obtained to be approximately 3000Ω / □. To form a resistor 10 with a resistance of 600kΩ, when the width W1 of the conductive channel 106 is 1μm, the required length L1 of the conductive channel 106 is: 600kΩ÷3000Ω / □×1μm=0.2mm. In the orthographic projection onto the substrate 101, the area of ​​the conductive channel 106 is approximately 0.2mm×1μm=200μm. 2 .

[0075] In summary, the size of the resistor 10 including the P-type GaN layer 107 is reduced by approximately 90% compared to the resistor 10 without the P-type GaN layer 107. That is, compared to the conductive channel 106 having a curved shape, the embodiments of the present disclosure utilize the P-type GaN layer 107 having a certain thickness range to consume the 2DEG in the conductive channel 106, resulting in a resistor 10 with a larger square resistance. This reduces the size of the resistor 10, thereby reducing the size of the integrated circuit 100 including the resistor 10.

[0076] Furthermore, the resistor 10 with adjustable square resistance can be obtained by adjusting the thickness d1 of the first portion 171 .

[0077] For example, when forming the integrated circuit 100, a P-type GaN layer 107 with a thickness of d2 is first formed, and the portion of the P-type GaN layer 107 located in the first device region 11 is thinned to a thickness of d1 to obtain a first portion 171 with a thickness of d1. The formation of the portion of the P-type GaN layer 107 with a thickness of d1 located in the first device region 11 is described with reference to the content of the resistor preparation method and is not described in detail here.

[0078] In some embodiments, as Figure 4 As shown, the ratio of the thickness d1 of the first portion 171 to the thickness d2 of the second portion 172 ranges from 1% to 40%.

[0079] Exemplarily, the ratio of the thickness d1 of the first portion 171 to the thickness d2 of the second portion 172 is 1%, 3%, 5%, 10%, 12%, 15%, 18%, 20%, 25%, 30%, 33%, 35%, 38% or 40%, etc., which is not limited here.

[0080] Exemplarily, the thickness d2 of the second portion 172 ranges from 80 nm to 100 nm. For example, the thickness d2 of the second portion 172 is 80 nm, 82 nm, 85 nm, 88 nm, 90 nm, 95 nm, or 100 nm, etc., without limitation. The thickness d2 of the second portion 172 can be the thickness of the P-type GaN layer 107 grown on the side of the barrier layer 103 away from the substrate 101. The portion of the P-type GaN layer 107 located in the first device region 11 is thinned to form the first portion 171 having a thickness d1.

[0081] When the thickness of the portion of the P-type GaN layer 107 located in the first device region 11 is thinned to a thickness d1, that is, when the ratio of the thickness d1 of the first portion 171 to the thickness d2 of the second portion 172 is in the range of 1% to 40%, the setting of the first portion 171 can make the resistor 10 have a higher square resistance, facilitating the preparation of a resistor 10 with a larger resistance value and a smaller size, thereby obtaining an integrated circuit 100 with a smaller size.

[0082] In some examples, such as Figure 4 As shown, the thickness d1 of the first portion 171 ranges from 1 nm to 40 nm.

[0083] For example, the thickness d1 of the first portion 171 is 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, or 40 nm, which is not limited here.

[0084] By setting the thickness d1 of the first portion 171 in the range of 1 nm to 40 nm, the resistor 10 can have a higher square resistance, facilitating the preparation of a resistor 10 with a larger resistance value and smaller storage capacity, thereby obtaining an integrated circuit 100 with a smaller size.

[0085] In some examples, such as Figure 3 As shown, in an orthographic projection onto the substrate 101 , the first portion 171 is rectangular.

[0086] For example, the conductive channel 106 of the resistor 10 is rectangular, that is, the conductive channel 106 of the resistor 10 is not bent. Figure 1 Compared with the curved conductive channel 106 shown in the figure, since the embodiment of the present disclosure provides the first part 171, the rectangular first part 171 can consume the 2DEG at the interface between the channel layer 102 and the barrier layer 103 located therebelow, thereby making the square resistance of the resistor 10 larger, so as to obtain a resistor 10 with a smaller size.

[0087] In some examples, such as Figure 4 As shown, one end of the first portion 171 along the second direction X contacts the first electrode 104, and the other end of the first portion 171 along the second direction X contacts the second electrode 105. The second direction X is parallel to the substrate 101 and parallel to the direction in which the first electrode 104 and the second electrode 105 are arranged.

[0088] Exemplarily, the conductive channel 106 of the resistor 10 is rectangular, and in the orthographic projection onto the substrate 101, the first portion 171 can cover the conductive channel 106 of the resistor 10, so that the first portion 171 can fully adjust the concentration of 2DEG in the conductive channel 106 of the resistor 10 to obtain resistors 10 with different resistance values.

[0089] In some examples, such as Figure 6 As shown, the first portion 171 includes: a first sub-portion 1711 and a second sub-portion 1712 , and the first sub-portion 1711 and the second sub-portion 1712 are arranged in a direction parallel to the substrate 101 ; wherein the thickness d11 of the first sub-portion 1711 is less than the thickness d12 of the second sub-portion 1712 .

[0090] For example, the first sub-portion 1711 and the second sub-portion 1712 may be arranged along the second direction X.

[0091] For example, the first sub-section 1711 and the second sub-section 1712 may be connected. In other examples, the first sub-section 1711 and the second sub-section 1712 may be spaced apart.

[0092] By configuring the first portion 171 to include a first sub-portion 1711 and a second sub-portion 1712 , the concentration of 2DEG in the conductive channel 106 of the resistor 10 can be further adjusted by adjusting the thickness of the first portion 171 to obtain resistors 10 with different resistances.

[0093] In some embodiments, as Figure 7 As shown, one end of the first portion 171 along the second direction X contacts one of the first pole 104 and the second pole 105 , and the other end of the first portion 171 along the second direction X is spaced apart from the other of the first pole 104 and the second pole 105 .

[0094] Illustratively, one end of the first portion 171 along the second direction X contacts the first pole 104 , and the other end of the first portion 171 along the second direction X is spaced apart from the second pole 105 .

[0095] In other examples, one end of the first portion 171 along the second direction X contacts the second pole 105 , and the other end of the first portion 171 along the second direction X is spaced apart from the first pole 104 .

[0096] In some other examples, one end of the first portion 171 along the second direction X is spaced apart from the first pole 104 , and the other end of the first portion 171 along the second direction X is spaced apart from the second pole 105 .

[0097] By arranging the first portion 171 in different positional relationships with the first electrode 104 and the second electrode 105 , the concentration of the 2DEG in the conductive channel 106 of the resistor 10 can be flexibly adjusted to obtain resistors 10 with different resistances.

[0098] In some embodiments, as Figure 4 As shown, the integrated circuit 100 further includes a buffer layer 108 located between the substrate 101 and the channel layer 102. The material of the buffer layer 108 includes: C-doped GaN, unintentionally doped GaN, AlN or AlGaN, etc., which are not limited here. When the material of the buffer layer 108 is C-doped GaN, the concentration range of C is 1×10 19 ~1ⅹ10 20 .

[0099] In some embodiments, a nucleation layer (not shown) is further included between the buffer layer 108 and the substrate 101 . The material of the nucleation layer is, for example, AlN.

[0100] Because the buffer layer 108 and the substrate 101 are made of different materials and typically have different lattice constants and thermal expansion coefficients, directly placing the buffer layer 108 on the substrate 101 may cause cracks in the buffer layer 108 due to lattice mismatch and thermal mismatch, resulting in a decrease in crystal quality. Therefore, a nucleation layer is provided to effectively prevent cracks in the buffer layer 108.

[0101] In some embodiments, an insertion layer (not shown) is further included between the channel layer 102 and the barrier layer 103 .

[0102] Exemplarily, the material of the insertion layer includes AlN, and the potential barrier of the insertion layer can be greater than the potential barrier of the barrier layer 103. The provision of the insertion layer can promote the polarization effect between the channel layer 102 and the barrier layer 103, and increase the 2DEG concentration of the heterojunction of the channel layer 102 and the barrier layer 103.

[0103] like Figure 4 As shown, an embodiment of the present disclosure further provides a resistor 10, which includes: a substrate 101 and a channel layer 102 and a barrier layer 103 stacked on one side of the substrate 101; the resistor 10 also includes: a first pole 104 and a second pole 105 spaced apart on a side of the channel layer 102 away from the substrate 101, and a conductive channel 106 electrically connecting the first pole 104 and the second pole 105; the resistor 10 also includes: a first portion 171, the material of the first portion 171 includes P-type GaN; the first portion 171 and the conductive channel 106 overlap in a first direction Y; wherein, the thickness d1 of the first portion 171 ranges from 1 nm to 40 nm.

[0104] Exemplarily, the P-type GaN includes: Mg-doped GaN, wherein the Mg doping concentration ranges from 1×10 18 cm -3 ~6×10 19 cm -3 .

[0105] For the introduction of the resistor 10 , please refer to the above content and will not be repeated here.

[0106] The resistor 10 provided in the embodiment of the present disclosure can provide a resistor 10 with a relatively large resistance and a relatively small size by disposing the first portion 171 with a thickness d1 ranging from 1 nm to 40 nm.

[0107] like Figure 4 and Figure 8 As shown, an embodiment of the present disclosure provides a method for manufacturing a resistor, which includes steps: R1 to R4.

[0108] R1. Form a channel layer 102 on one side of the substrate 101.

[0109] Exemplarily, the material of the substrate 101 includes silicon, silicon carbide, gallium nitride, sapphire or diamond, etc., which is not limited here.

[0110] Illustratively, the channel layer 102 is formed on one side of the substrate 101 by an epitaxial growth method.

[0111] Illustratively, when a buffer layer 108 is further provided on one side of the substrate 101 , the channel layer 102 is formed on a side of the buffer layer 108 away from the substrate 101 .

[0112] R2. Form a barrier layer 103 on a side of the channel layer 102 away from the substrate 101.

[0113] Exemplarily, the material of the barrier layer 103 includes at least one of AlN and AlGaN.

[0114] Illustratively, the barrier layer 103 is formed on a side of the channel layer 102 away from the substrate 101 by an epitaxial growth method.

[0115] A conductive channel 106 is provided at the interface between the channel layer 102 and the barrier layer 103 .

[0116] R3. A first portion 171 is formed on a side of the barrier layer 103 away from the substrate 101. The material of the first portion 171 includes P-type GaN. The first portion 171 overlaps with the conductive channel 106 in the first direction Y. The thickness d1 of the first portion 171 ranges from 1 nm to 40 nm.

[0117] In some examples, such as Figure 3 、 Figure 9 and Figure 10 As shown, the step of forming the first portion 171 on the side of the barrier layer 103 away from the substrate 101 includes: R31 to R37.

[0118] R31 . Form an initial first portion 17 a having a first thickness d3 on a side of the barrier layer 103 away from the substrate 101 .

[0119] Illustratively, the initial first portion 17a is formed by an epitaxial growth method.

[0120] Exemplarily, the first thickness d3 can be equal to the thickness d2 of the second part 172, that is, P-type GaN is used to form a film layer with a thickness of the first thickness d3, and the portion of the film layer located in the second device region 12 is used to form the second part 172. The thickness d2 of the second part 172 is the thickness of the film layer, and the portion of the film layer located in the first device region 11 serves as the initial first part 17a, and after thinning treatment, the first part 171 is formed.

[0121] R32 . Form a first mask layer 301 on a side of the initial first portion 17 a away from the substrate 101 .

[0122] Exemplarily, the first mask layer 301 is formed by an epitaxial growth method.

[0123] Exemplarily, the material of the first mask layer 301 includes at least one of silicon oxide and silicon nitride.

[0124] R33 , removing the portion of the first mask layer 301 located in the first device region 11 ; the first device region 11 is the region where the resistor 10 is formed.

[0125] Illustratively, the portion of the first mask layer 301 located in the first device region 11 is removed by a dry etching process or a wet etching process.

[0126] R34. Remove the portion of the initial first portion 17a away from the substrate 101 to form the initial first portion 17a having a second thickness d4.

[0127] Exemplarily, a portion of the initial first portion 17 a away from the substrate 101 is removed by a dry etching process to form the initial first portion 17 a having the second thickness d4 .

[0128] Exemplarily, the ratio of the second thickness d4 to the first thickness d3 ranges from 1% to 40%. For example, the ratio of the second thickness d4 to the first thickness d3 is 1%, 6%, 10%, 15%, 20%, 25%, 30%, 35%, or 40%, etc., although this is not limiting. In this case, the second thickness d4 is equal to the thickness d1 of the pre-formed first portion 171.

[0129] Illustratively, after step R34 , the method further includes removing the portion of the first mask layer 301 located in the second device region 12 .

[0130] R35 . Form a second mask layer 302 on a side of the initial first portion 17 a away from the substrate 101 .

[0131] Exemplarily, the second mask layer 302 is formed by an epitaxial growth method.

[0132] Exemplarily, the material of the second mask layer 302 includes at least one of silicon oxide and silicon nitride.

[0133] R36 , removing the portion of the second mask layer 302 located in the first sub-region S1 . The first device region 11 excluding the region where the first portion 171 is pre-formed is the first sub-region S1 .

[0134] Illustratively, the portion of the second mask layer 302 located in the first sub-region S1 is removed by a dry etching process or a wet etching process.

[0135] R37 . Remove the portion of the initial first portion 17a located in the first sub-region S1 to obtain the first portion 171 .

[0136] Illustratively, after step R37 , the method further includes: removing the remaining portion of the second mask layer 302 .

[0137] Through the above steps R31 to R37 , the first portion 171 is formed by using a secondary growth mask layer method, so as to further form a resistor 10 with relatively large square resistance and relatively small size.

[0138] In other examples, such as Figure 3 、 Figure 11 and Figure 12 As shown, the step of forming the first portion 171 on the side of the barrier layer 103 away from the substrate 101 includes: T31 to T36.

[0139] T31 . Form an initial first portion 17 a having a first thickness d3 on a side of the barrier layer 103 away from the substrate 101 .

[0140] For an introduction to this step, please refer to the content of step R31, which will not be repeated here.

[0141] T32 . Form a first mask layer 301 on a side of the initial first portion 17 a away from the substrate 101 .

[0142] For an introduction to this step, please refer to the content of step R33, which will not be repeated here.

[0143] T33 , removing the portion of the first mask layer 301 located in the first sub-region S1 .

[0144] Illustratively, the portion of the first mask layer 301 located in the first sub-region S1 is removed by a dry etching process or a wet etching process.

[0145] T34 , removing a portion of the initial first portion 17 a located in the first sub-region S1 and away from the substrate 101 ; the removed portion has a thickness of the second thickness d4 .

[0146] Exemplarily, a portion of the initial first portion 17 a located in the first sub-region S1 and away from the substrate 101 is removed by a dry etching process.

[0147] T35 , removing the remaining portion of the first mask layer 301 .

[0148] Illustratively, the remaining portion of the first mask layer 301 is removed by a dry etching process or a wet etching process.

[0149] T36. Remove the portion of the initial first portion 17a having the third thickness d5 away from the substrate 101 to obtain the first portion 171; wherein the sum of the third thickness d5 and the second thickness d4 is equal to the first thickness d3.

[0150] Exemplarily, a portion of the initial first portion 17 a having the third thickness d5 away from the substrate 101 is removed by a dry etching process.

[0151] Since the sum of the third thickness d5 and the second thickness d4 is equal to the first thickness d3, that is, d3=d4+d5, when the portion of the initial first portion 17a with the third thickness d5 away from the substrate 101 is removed, the portion of the initial first portion 17a located in the first sub-region S1 is completely removed, and the remaining portion of the initial first portion 17a forms the first portion 171 with the second thickness d4.

[0152] Through the above steps T31 to T36 , the first portion 171 is formed by using a method of growing a mask layer once, so as to further form a resistor 10 with relatively large square resistance and relatively small size.

[0153] R4. A first electrode 104 and a second electrode 105 are formed on a side of the channel layer 102 away from the substrate 101 , and the first electrode 104 and the second electrode 105 are electrically connected via a conductive channel 106 .

[0154] Exemplarily, an ohmic metal is deposited by a deposition process, wherein the ohmic metal includes at least one of Ti / Al / Ti / Au, Ti / Al / Ni / Au, Ta / Ti / Ni / Au, Ti / Ag, Ti / Al / Ni / TiN, and Ti / Al / Ti / TiN, and then an annealing process is performed.

[0155] Further, such as Figure 4 As shown, the method for preparing the resistor further includes: ion implantation, wherein ion implantation is performed in a region where the isolation region 13 is preformed, so as to achieve electrical isolation between the first device region 11 and the second device region 12 .

[0156] Through the above steps R1 to R4, a resistor 10 including a first portion 171 is formed. Since the material of the first portion 171 includes P-type GaN, the first portion 171 consumes the 2DEG in the conductive channel 106, resulting in a resistor 10 with a larger square resistance and a reduced size of the resistor 10.

[0157] The embodiment of the present disclosure further provides an electronic device 1000, such as Figure 13 As shown, the electronic device 1000 includes the integrated circuit 100 provided in any of the above embodiments. The integrated circuit 100 includes the resistor 10 provided in any of the above embodiments.

[0158] The electronic device 1000 further includes a circuit board 200 , on which the integrated circuit 100 is disposed.

[0159] like Figure 13As shown, the electronic device 1000 includes the integrated circuit 100 provided by any of the above embodiments. Therefore, the electronic device 1000 provided by the embodiments of the present disclosure has all the beneficial effects of the integrated circuit 100 provided by any of the above embodiments, which will not be described herein.

[0160] For example, the electronic device 1000 is a computer, a mobile phone, a tablet computer, a wearable device, a vehicle-mounted device, or the like, which is a user device or a terminal device of different types; the electronic device 1000 can also be a network device such as a base station. The embodiments of the present disclosure do not specially limit the specific form of the electronic device 1000.

[0161] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which shall be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. An integrated circuit, characterized in that: include: A substrate and a channel layer and a barrier layer stacked on one side of the substrate; The integrated circuit comprises a first device region and a second device region which are spaced apart from each other; The integrated circuit further includes: a resistor located in the first device region and a transistor located in the second device region; the resistor includes: a first electrode and a second electrode located on a side of the channel layer away from the substrate and spaced apart, and a conductive channel electrically connecting the first electrode and the second electrode; The integrated circuit further comprises: a P-type GaN layer located on a side of the barrier layer away from the substrate; the P-type GaN layer comprises: a first portion located in the first device region and a second portion located in the second device region; the first portion and the conductive channel overlap in a first direction, the first direction being perpendicular to the substrate; wherein the thickness of the first portion is smaller than the thickness of the second portion; One end of the first portion along the second direction contacts the first pole, and the other end of the first portion along the second direction contacts the second pole; Wherein, the second direction is parallel to the substrate and parallel to the direction in which the first pole and the second pole are arranged; The first portion includes a first sub-portion and a second sub-portion, wherein the first sub-portion and the second sub-portion are arranged in a direction parallel to the substrate; wherein the thickness of the first sub-portion is smaller than the thickness of the second sub-portion.

2. The integrated circuit according to claim 1, wherein: The ratio of the thickness of the first portion to the thickness of the second portion is in a range of 1% to 40%.

3. The integrated circuit according to claim 2, wherein: The thickness of the first portion ranges from 1 nm to 40 nm.

4. The integrated circuit according to claim 1, wherein: In an orthographic projection onto the substrate, the first portion is rectangular.

5. The integrated circuit according to claim 1, wherein: The transistor comprises: a third electrode and a fourth electrode located on a side of the channel layer away from the substrate and spaced apart from each other, and a control electrode located between the third electrode and the fourth electrode; the control electrode is located on a side of the second portion away from the substrate; Wherein, the thickness of the second portion ranges from 80 nm to 100 nm.

6. The integrated circuit according to any one of claims 1 to 5, characterized in that: The integrated circuit further includes an isolation region located between the first device region and the second device region; the isolation region is configured to electrically isolate the first device region from the second device region.

7. A resistor, characterized in that: include: A substrate and a channel layer and a barrier layer stacked on one side of the substrate; The resistor further comprises: a first electrode and a second electrode spaced apart and arranged on a side of the channel layer away from the substrate, and a conductive channel electrically connecting the first electrode and the second electrode; The resistor further includes: a first portion located on a side of the barrier layer away from the substrate, wherein the material of the first portion includes P-type GaN; the first portion and the conductive channel overlap in a first direction; Wherein, the thickness of the first portion ranges from 1 nm to 40 nm; One end of the first portion along the second direction contacts the first pole, and the other end of the first portion along the second direction contacts the second pole; Wherein, the second direction is parallel to the substrate and parallel to the direction in which the first pole and the second pole are arranged; The first portion includes a first sub-portion and a second sub-portion, wherein the first sub-portion and the second sub-portion are arranged in a direction parallel to the substrate; wherein the thickness of the first sub-portion is smaller than the thickness of the second sub-portion.

8. The resistor according to claim 7, wherein In an orthographic projection onto the substrate, the first portion is rectangular.

9. A method for preparing a resistor, characterized in that: include: forming a channel layer on one side of the substrate; forming a barrier layer on a side of the channel layer away from the substrate; A conductive channel is provided at the interface between the channel layer and the barrier layer; forming a first portion on a side of the barrier layer away from the substrate, wherein the material of the first portion comprises P-type GaN; the first portion overlaps the conductive channel in a first direction, the first direction being perpendicular to the substrate; and the thickness of the first portion ranges from 1 nm to 40 nm; forming a first electrode and a second electrode spaced apart from each other on a side of the channel layer away from the substrate, wherein the first electrode and the second electrode are electrically connected via the conductive channel; One end of the first portion along the second direction contacts the first pole, and the other end of the first portion along the second direction contacts the second pole; Wherein, the second direction is parallel to the substrate and parallel to the direction in which the first pole and the second pole are arranged; The first portion includes a first sub-portion and a second sub-portion, wherein the first sub-portion and the second sub-portion are arranged in a direction parallel to the substrate; wherein the thickness of the first sub-portion is smaller than the thickness of the second sub-portion.

10. The method for preparing a resistor according to claim 9, wherein: The forming of the first portion on a side of the barrier layer away from the substrate comprises: forming an initial first portion having a first thickness on a side of the barrier layer away from the substrate; forming a first mask layer on a side of the initial first portion away from the substrate; removing a portion of the first mask layer located in a first device region where a resistor is formed; removing a portion of the initial first portion away from the substrate to form an initial first portion having a second thickness; forming a second mask layer on a side of the initial first portion having the second thickness away from the substrate; removing the portion of the second mask layer located in the first sub-region, so that the first device region except the region where the first portion is pre-formed becomes the first sub-region; The portion of the initial first portion located in the first sub-region is removed to obtain the first portion.

11. The method for preparing a resistor according to claim 10, wherein: The ratio of the second thickness to the first thickness ranges from 1% to 40%.

12. The method for preparing a resistor according to claim 9, wherein: The forming of the first portion on a side of the barrier layer away from the substrate comprises: forming an initial first portion having a first thickness on a side of the barrier layer away from the substrate; forming a first mask layer on a side of the initial first portion away from the substrate; removing the portion of the first mask layer located in the first sub-region; removing a portion of the initial first portion located in the first sub-region and away from the substrate, with the removed portion having a thickness of a second thickness; removing the remaining portion of the first mask layer; A portion of the initial first portion having a third thickness away from the substrate is removed to obtain a first portion; wherein the sum of the third thickness and the second thickness is equal to the first thickness.

13. The method for preparing a resistor according to claim 12, wherein: The ratio of the third thickness to the first thickness ranges from 60% to 99%.

14. The method for preparing a resistor according to any one of claims 9 to 13, characterized in that: The material of the mask layer includes: at least one of silicon oxide and silicon nitride; the mask layer includes: a first mask layer and a second mask layer.

15. An electronic device, characterized in that: include: The integrated circuit according to any one of claims 1 to 6; A circuit board, on which the integrated circuit is arranged.

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