Semiconductor device, manufacturing method, power module, conversion circuit and vehicle

Abstract

The present invention discloses a semiconductor device, a preparation method, a power module, a conversion circuit and a vehicle. The semiconductor device comprises: a semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the conductivity type of the semiconductor body is a first conductivity type; the semiconductor body also comprises a second conductivity type contact area, and the second conductivity type contact area is located on the first surface; an insulating layer, located on the first surface of the semiconductor body; the insulating layer is provided with an electrode opening exposing the second conductivity type contact area and a portion of the first surface outside the second conductivity type contact area; a first electrode, located in the electrode opening and in contact with the first surface exposed by the electrode opening; wherein the material of the insulating layer contains a charge capture element, and the charge capture element is used to capture the charge in the semiconductor body to reduce the leakage current of the semiconductor device, thereby improving the reliability of the device.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular, to a semiconductor device, a preparation method, a power module, a conversion circuit and a vehicle. Background Art

[0002] As a representative of the third generation of semiconductor materials, silicon carbide (SiC) has excellent physical and electrical properties. Compared with silicon materials, SiC materials have a large bandgap, high breakdown electric field, high thermal conductivity, high electron saturation rate, and strong radiation resistance. Therefore, diode semiconductor devices made of SiC materials can not only operate stably at higher temperatures, but are also suitable for high voltage and high frequency scenarios.

[0003] In the related art, field oxygen in semiconductor devices is usually deposited by PECVD (Plasma Enhance Chemical Vapour Deposition). This process may accumulate charges inside the device. The charges inside the semiconductor device cannot be activated during normal temperature use. However, when the semiconductor device is in a high temperature environment, the accumulated charges inside will be activated under the action of temperature, causing the leakage current of the device to increase, thereby causing the temperature of the device to rise, and then causing the device to fail. Therefore, how to reduce the leakage current of semiconductor devices and improve the reliability of the devices is a technical problem that needs to be solved urgently by people in this field. Summary of the invention

[0004] Embodiments of the present invention provide a semiconductor device, a manufacturing method, a power module, a conversion circuit and a vehicle to reduce leakage current of the semiconductor device and improve reliability of the device.

[0005] According to one aspect of the present invention, there is provided a semiconductor device, comprising:

[0006] A semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the conductivity type of the semiconductor body is a first conductivity type; the semiconductor body further comprises a second conductivity type contact region, the second conductivity type contact region is located on the first surface;

[0007] an insulating layer, located on the first surface of the semiconductor body; the insulating layer is provided with an electrode opening exposing the second conductive type contact region and a portion of the first surface outside the second conductive type contact region;

[0008] A first electrode is located in the electrode opening and contacts the first surface exposed by the electrode opening;

[0009] The material of the insulating layer contains charge trapping elements, and the charge trapping elements are used to capture charges in the semiconductor body to reduce leakage current of the semiconductor device.

[0010] Optionally, the insulating layer includes:

[0011] A field oxide sublayer, located on the first surface of the semiconductor body;

[0012] A charge trapping sublayer, located on a side of the field oxide sublayer away from the semiconductor body;

[0013] Wherein, the material of the charge trapping sublayer contains the charge trapping element.

[0014] Optionally, the charge trapping element includes B and / or P.

[0015] Optionally, the insulating layer further includes:

[0016] The blocking sublayer is located between the field oxide sublayer and the charge trapping sublayer; the blocking sublayer is used to block the charge trapping elements in the charge trapping sublayer from diffusing into the semiconductor body.

[0017] Optionally, the material of the field oxide sublayer includes silicon dioxide;

[0018] The material of the blocking sublayer includes silicon dioxide;

[0019] The material of the charge trapping sublayer includes borophosphosilicate glass.

[0020] Optionally, the thickness of the blocking sublayer is smaller than the thickness of the field oxide sublayer, and the purity of the material of the blocking sublayer is higher than the purity of the material of the field oxide sublayer.

[0021] Optionally, the first surface includes a plurality of second conductive type contact areas and a plurality of first conductive type contact areas; the second conductive type contact areas and the first conductive type contact areas are alternately arranged in sequence;

[0022] The electrode opening exposes a plurality of the second conductive type contact regions and a plurality of the first conductive type contact regions.

[0023] Optionally, the first electrode is a single-layer structure, or the first electrode is a multi-layer structure.

[0024] Optionally, the semiconductor device further includes:

[0025] A passivation layer, located on a side of the first electrode away from the semiconductor body;

[0026] The second electrode is located on the second surface of the semiconductor body.

[0027] Optionally, the semiconductor device is a junction barrier Schottky power diode, or the semiconductor device is a hybrid PiN Schottky diode.

[0028] According to another aspect of the present invention, there is provided a method for preparing a semiconductor device, which is used to prepare the semiconductor device according to any embodiment of the present invention, comprising:

[0029] forming a semiconductor body; the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the conductivity type of the semiconductor body is a first conductivity type; the semiconductor body further comprises a second conductivity type contact region, and the second conductivity type contact region is located on the first surface;

[0030] An insulating layer is formed on the first surface of the semiconductor body, and an electrode opening is formed in the insulating layer to expose the second conductive type contact area and a portion of the first surface outside the second conductive type contact area; wherein the material of the insulating layer contains a charge trapping element, and the charge trapping element is used to capture charges in the semiconductor body to reduce leakage current of the semiconductor device;

[0031] A first electrode is formed in the electrode opening; the first electrode contacts the first surface exposed by the electrode opening.

[0032] Optionally, forming an insulating layer on the first surface of the semiconductor body, and forming an electrode opening in the insulating layer to expose the second conductive type contact region and a portion of the first surface outside the second conductive type contact region, comprises:

[0033] forming a field oxide sublayer on a first surface of the semiconductor body;

[0034] A charge trapping sublayer is formed on a side of the field oxide sublayer away from the semiconductor body; wherein the charge trapping sublayer is made of a material containing the charge trapping element;

[0035] An electrode opening is formed that passes through the charge trapping sublayer and the field oxide sublayer.

[0036] Optionally, the insulating layer further includes a blocking sublayer located between the field oxide sublayer and the charge trapping sublayer; before the charge trapping sublayer is formed on a side of the field oxide sublayer away from the semiconductor body, the method further includes:

[0037] Forming a blocking sublayer on a side of the field oxide sublayer away from the semiconductor body; the blocking sublayer is used to block the charge trapping elements in the charge trapping sublayer from diffusing into the semiconductor body;

[0038] Forming an electrode opening penetrating the charge trapping sublayer and the field oxide sublayer comprises:

[0039] An electrode opening is formed that passes through the charge trapping sublayer, the blocking sublayer, and the field oxide sublayer.

[0040] Optionally, forming a field oxide sublayer on the first surface of the semiconductor body includes:

[0041] A field oxide sublayer made of a material of dioxide is formed by a plasma enhanced chemical vapor deposition process;

[0042] Forming a blocking sublayer on a side of the field oxide sublayer away from the semiconductor body, comprising:

[0043] Depositing a barrier sublayer made of silicon dioxide by a low pressure chemical vapor deposition process;

[0044] Forming a charge trapping sublayer on a side of the blocking sublayer away from the semiconductor body, comprising:

[0045] The charge trapping sublayer is formed by a deposition process and is made of borophosphosilicate glass.

[0046] According to another aspect of the present invention, a power module is provided, comprising a substrate and at least one semiconductor device according to any one of the embodiments of the present invention, wherein the substrate is used for carrying the semiconductor device.

[0047] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0048] The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of the embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0049] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as described in any embodiment of the present invention, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load.

[0050] The embodiment of the present invention provides a semiconductor device, a preparation method, a power module, a conversion circuit and a vehicle, wherein the semiconductor device comprises: a semiconductor body, the semiconductor body comprises a first surface and a second surface arranged opposite to each other; the conductivity type of the semiconductor body is a first conductivity type; the semiconductor body further comprises a second conductivity type contact area, the second conductivity type contact area is located on the first surface; an insulating layer is located on the first surface of the semiconductor body; the insulating layer is provided with an electrode opening exposing a portion of the first surface outside the second conductivity type contact area and the second conductivity type contact area; a first electrode is located in the electrode opening and in contact with the first surface exposed by the electrode opening; wherein the material of the insulating layer contains a charge capture element, the charge capture element is used to capture the charge in the semiconductor body to reduce the leakage current of the semiconductor device. The technical solution provided by the embodiment of the present invention can reduce the leakage level of the device in a high temperature environment by introducing a charge capture element having the ability to capture diffusible charges into the material of the insulating layer, thereby improving the problem of device failure caused by high temperature and improving the reliability of the semiconductor device.

[0051] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0053] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0054] Figure 2 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0055] Figure 3 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0056] Figure 4-5 It is a structural cross-sectional view corresponding to each step of step S110 in a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0057] Figure 6-7 It is a structural cross-sectional view corresponding to each step of step S120 in a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0058] Figure 8 is a structural cross-sectional view corresponding to step S130 in a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0059] Fig. 9 is a structural cross-sectional view corresponding to step S140 in a method for preparing a semiconductor device provided in an embodiment of the present invention;

[0060] Fig.10 is a structural cross-sectional view corresponding to step S220 in a method for preparing a semiconductor device provided in an embodiment of the present invention;

[0061] Fig.11 is a structural cross-sectional view corresponding to step S230 in a method for preparing a semiconductor device provided in an embodiment of the present invention;

[0062] Fig.12 is a structural cross-sectional view corresponding to step S211 in a method for preparing a semiconductor device provided in an embodiment of the present invention;

[0063] Fig.13 It is another structural cross-sectional view corresponding to step S230 in a method for preparing a semiconductor device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0064] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0065] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0066] An embodiment of the present invention provides a semiconductor device, Figure 1is a schematic diagram of a semiconductor device provided by an embodiment of the present invention, with reference to Figure 1 , semiconductor devices include:

[0067] A semiconductor body 1, wherein the semiconductor body 1 comprises a first surface 11 and a second surface 12 arranged opposite to each other; the conductivity type of the semiconductor body 1 is a first conductivity type; the semiconductor body 1 further comprises a second conductivity type contact region 21, and the second conductivity type contact region 21 is located on the first surface 11;

[0068] The insulating layer 30 is located on the first surface 11 of the semiconductor body 1; the insulating layer 30 is provided with an electrode opening exposing the second conductive type contact region 21 and a portion of the first surface 11 outside the second conductive type contact region 21;

[0069] A first electrode 40 is located in the electrode opening and contacts the first surface 11 exposed by the electrode opening;

[0070] The material of the insulating layer 30 contains charge trapping elements, which are used to capture charges in the semiconductor body 1 to reduce leakage current of the semiconductor device.

[0071] Specifically, the semiconductor body 1 can be formed by one epitaxy or multiple epitaxies. That is, the semiconductor body 1 can be a single semiconductor epitaxial layer 20 or a stacked structure formed by multiple semiconductor epitaxial layers 20. The semiconductor body 1 can also include a substrate 10, that is, the semiconductor body 1 includes a substrate 10 and at least one semiconductor epitaxial layer 20 formed on one side of the substrate 10. The material of the substrate 10 can be the same as the material of the semiconductor epitaxial layer 20, or the material of the substrate 10 can be different from the material of the semiconductor epitaxial layer 20.

[0072] In the case where the semiconductor body 1 only includes the semiconductor epitaxial layer 20, the second surface 12 is the surface of the semiconductor body 1 on the side close to the substrate 10, and the first surface 11 is the surface of the semiconductor body 1 on the side away from the substrate 10. In the case where the semiconductor body 1 includes the substrate 10 and the semiconductor epitaxial layer 20, the second surface 12 is the surface of the substrate 10 on the side away from the semiconductor epitaxial layer 20, and the first surface 11 is the surface of the semiconductor epitaxial layer 20 on the side farthest from the substrate 10 away from the substrate 10. Figure 1 The semiconductor body 1 shown includes a substrate 10 and a semiconductor epitaxial layer 20 located on one side of the substrate, the first surface 11 is the surface of the semiconductor epitaxial layer 20 away from the substrate 10, and the second surface 12 is the surface of the substrate 10 away from the semiconductor epitaxial layer 20; the material of the substrate 10 and the semiconductor epitaxial layer 20 can both be SiC, so that the semiconductor device has the advantages of high breakdown electric field, high thermal conductivity, high electron saturation rate, strong radiation resistance and the like.

[0073] The first surface 11 of the semiconductor body 1 of the first conductivity type includes at least one second conductivity type contact region 21. If the first conductivity type is N-type, the second conductivity type is P-type; if the first conductivity type is P-type, the second conductivity type is N-type. Among them, the N-type doping ions can be P (phosphorus) or N (nitrogen) ions, and the P-type doping ions can be Al (aluminum) ions or B (boron) ions. In the embodiment of the present invention, the first conductivity type is N-type and the second conductivity type is P-type.

[0074] The second conductive type contact area 21 and the first electrode 40 may be in ohmic contact. If the area of ​​the second conductive type contact area 21 is smaller than the first surface 11, the first surface 11 exposed by the electrode opening in the insulating layer 30 includes at least one second conductive type contact area 21, and a portion of the first surface 11 outside the second conductive type contact area 21. The area outside the second conductive type contact area 21 in the first surface 11 is of the first conductive type, so the first electrode 40 located in the electrode opening is in contact with at least one second conductive type contact area 21, and is in contact with a portion of the first surface 11 (first conductive type contact area 22) of the first conductive type outside the second conductive type contact area 21. The semiconductor device provided in the embodiment of the present invention may be a junction barrier Schottky power diode (JBS), or a hybrid PiN Schottky diode (MPS).

[0075] Both the junction barrier Schottky diode and the hybrid PiN Schottky diode are structures that combine the pn junction diode and the Schottky diode, which enables them to have the advantages of both diodes at the same time. The junction barrier Schottky diode has the characteristics of the low conduction voltage of the Schottky diode and the high withstand voltage of the pn diode. When the forward voltage drop applied to the JBS diode is small, since the turn-on voltage of the Schottky junction is lower than that of the pn junction, the Schottky junction is turned on before the pn junction. At this time, the current of the JBS diode mainly flows through the conductive channel under the Schottky barrier, that is, it exhibits the characteristics of the Schottky diode. When a large forward voltage drop is applied to the JBS diode, the pn junction is turned on after the Schottky junction is turned on. At this time, the current not only contains the current passing through the conductive channel under the Schottky barrier, but also the composite current generated by the pn junction barrier region. As the forward voltage increases, the composite current in the barrier region also increases. At this time, the JBS diode will mainly show the characteristics of the pn junction diode.

[0076] When a reverse voltage drop is applied to the JBS diode, the depletion region of the pn junction in the drift region 23 will extend toward the N-type region, and as the reverse bias increases, the depletion regions between adjacent pn junctions will be connected and extend longitudinally toward the N+-type substrate 10, resulting in the pinching off of the Schottky conduction channel, thus preventing the large leakage current of the diode caused by the reduction of the Schottky barrier. At this time, the JBS diode mainly exhibits the characteristics of a pn junction diode. Therefore, the JBS diode combines the advantages of a pn diode and a Schottky diode.

[0077] The structure of the MPS diode is similar to that of the JBS diode, but in fact the working principles of the MPS and JBS diodes are different. The pn junction structure in the active region of the JBS diode is used to reduce the leakage current when reverse biased; but the pin junction structure in the MPS diode is set to obtain a high breakdown voltage. The difference between the MPS and JBS diodes is that the pn junction structure in the Schottky region of the MPS diode is in a forward biased state when in the on state, so there is a large resistance in the drift region 23 of the MPS diode, which can also bear a higher breakdown voltage.

[0078] In the related art, the field oxide layer located on the semiconductor body 1 in the JBS diode and the MPS diode is usually deposited by PECVD (Plasma Enhance Chemical Vapour Deposition). This process will cause the accumulation of charges inside the device. When the semiconductor device is in a high temperature environment, such as in a high temperature reverse bias test (HTRB), the accumulated charges inside the semiconductor device will be activated under the action of temperature, causing the leakage of the device to increase, thereby causing the temperature of the device to rise, and then causing the device to fail. In the embodiment of the present invention, the material of the insulating layer 30 located on the semiconductor body 1 contains a charge capture element, and the charge capture element can capture the charge in the semiconductor body 1, thereby reducing the leakage current of the semiconductor device. Among them, the charge capture element includes B and / or P, and can also be other elements that have the function of capturing charges.

[0079] The semiconductor device provided by the embodiment of the present invention comprises: a semiconductor body 1, the semiconductor body 1 comprises a first surface 11 and a second surface 12 arranged opposite to each other; the conductivity type of the semiconductor body 1 is the first conductivity type; the semiconductor body 1 further comprises a second conductivity type contact area 21, the second conductivity type contact area 21 is located on the first surface 11; an insulating layer 30 is located on the first surface 11 of the semiconductor body 1; the insulating layer 30 is provided with an electrode opening exposing the second conductivity type contact area 21 and a part of the first surface 11 outside the second conductivity type contact area 21; a first electrode 40 is located in the electrode opening and in contact with the first surface 11 exposed by the electrode opening; wherein the material of the insulating layer 30 comprises a charge capture element, the charge capture element is used to capture the charge in the semiconductor body 1 to reduce the leakage current of the semiconductor device. The technical solution provided by the embodiment of the present invention can reduce the leakage level of the device in a high temperature environment by introducing a charge capture element having the ability to capture diffusible charges into the material of the insulating layer 30, thereby improving the problem of device failure caused by high temperature and improving the reliability of the semiconductor device.

[0080] Based on the above embodiments, Figure 1 Optionally, the insulating layer 30 includes:

[0081] The field oxide sublayer 31 is located on the first surface 11 of the semiconductor body 1;

[0082] The charge trapping sublayer 32 is located on a side of the field oxide sublayer 31 away from the semiconductor body 1 ; wherein the material of the charge trapping sublayer 32 contains charge trapping elements.

[0083] Specifically, the insulating layer 30 is a stacked structure including a field oxide sublayer 31 and a charge capture sublayer 32. The field oxide sublayer 31 is located on the first surface 11 of the semiconductor body 1 and contacts the first surface 11 of the semiconductor body 1; the charge capture sublayer 32 is located on the side of the field oxide sublayer 31 away from the semiconductor body 1, and may contact the field oxide sublayer 31 or may not contact the field oxide sublayer 31. In the case where the charge capture sublayer 32 is not in contact with the field oxide sublayer 31, other film layers are further provided between the charge capture sublayer 32 and the field oxide sublayer 31.

[0084] The material of the field oxide sublayer 31 may include silicon dioxide; the material of the charge capture sublayer 32 includes borophosphosilicic glass (BPSG), which is a composite glass material formed by doping phosphorus and boron into silicon dioxide. The boron and phosphorus elements in the charge capture sublayer 32 can reduce the leakage level of the device in a high temperature environment, thereby improving the problem of device failure caused by high temperature and improving the reliability of the semiconductor device. In addition, BPSG has excellent hole filling ability, which helps to improve the flatness of the device surface and provides a larger process range for subsequent manufacturing processes. Moreover, due to its special chemical composition, BPSG has good dielectric properties and can improve the insulation of the insulating layer 30.

[0085] Based on the above embodiments, Figure 2 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention, referring to Figure 2 Optionally, the insulating layer 30 further includes:

[0086] The blocking sublayer 33 is located between the field oxide sublayer 31 and the charge trapping sublayer 32 ; the blocking sublayer 33 is used to block the charge trapping elements in the charge trapping sublayer 32 from diffusing into the semiconductor body 1 .

[0087] Specifically, a blocking sublayer 33 is provided between the charge capture sublayer 32 and the field oxide sublayer 31, and the blocking sublayer 33 can block the boron element and the phosphorus element in the charge capture sublayer 32 from diffusing into the semiconductor body 1, thereby effectively preventing the contamination of the surface of the semiconductor body 1 and improving the stability of the semiconductor device. Among them, the material of the blocking sublayer 33 can be undoped silicon dioxide (Undoped Silicate Glass, USG), which can also be called undoped silicate glass. The thickness of the field oxide sublayer 31 is greater than the thickness of the blocking sublayer 33, and the purity of the blocking sublayer 33 material is higher than the purity of the field oxide sublayer 31 material. USG has excellent chemical stability and is not easily corroded by most chemical substances; it can withstand high temperatures and is not easily deformed; USG is used as an electrical insulating material, which can effectively isolate current and reduce electrical conductivity.

[0088] Based on the above embodiments, Figure 1 and Figure 2 Optionally, the first surface 11 includes a plurality of second conductive type contact regions 21 and a plurality of first conductive type contact regions 22; the second conductive type contact regions 21 and the first conductive type contact regions 22 are alternately arranged in sequence.

[0089] Specifically, the second conductive type contact region 21 is located between two adjacent first conductive type contact regions 22, the first conductive type contact region 22 is located between two adjacent second conductive type contact regions 21, and the electrode opening exposes multiple second conductive type contact regions 21 and multiple first conductive type contact regions 22, so that the first electrode 40 is connected to multiple first conductive type contact regions 22 and multiple second conductive type contact regions 21.

[0090] Based on the above embodiments, optionally, the first electrode 40 is a single-layer structure, or the first electrode 40 is a multi-layer structure. Figure 1 and Figure 2 , exemplarily showing that the first electrode 40 is a multi-layer structure, including a Ti layer 41, a TiN layer 42 and an Al layer 43 which are sequentially away from the semiconductor body 1.

[0091] On the basis of the above embodiments, optionally, the semiconductor device further includes a second electrode, and the second electrode is located on the second surface 12 of the semiconductor body 1 .

[0092] The first electrode 40 can be used as an anode and the second electrode can be used as a cathode. When the first electrode 40 is connected to a positive voltage and the second electrode is grounded or connected to a negative voltage, the semiconductor device is in a forward biased state; when the first electrode 40 is connected to a positive voltage and the second electrode is grounded or connected to a negative voltage, the semiconductor device is in a reverse biased state.

[0093] The first electrode 40 can be used as a cathode and the second electrode can be used as an anode. When the first electrode 40 is connected to a positive voltage and the second electrode is grounded or connected to a negative voltage, the semiconductor device is in a reverse bias state; when the first electrode 40 is connected to a positive voltage and the second electrode is grounded or connected to a negative voltage, the semiconductor device is in a forward bias state.

[0094] Based on the above embodiments, Figure 1 and Figure 2 Optionally, the semiconductor device further includes at least one of a passivation layer and a protective layer 50, the passivation layer is located on a side of the first electrode 40 away from the semiconductor body 1, and the protective layer 50 is located on a side of the first electrode 40 away from the semiconductor body 1. In the case where the semiconductor device includes a passivation layer and a protective layer 50, the passivation layer is located on a side of the first electrode 40 away from the semiconductor body 1, and the protective layer 50 is located on a side of the passivation layer away from the semiconductor body 1. The material of the passivation layer may be silicon dioxide and / or silicon nitride, and the material of the protective layer 50 may include polyimide (PI) and / or polyamide (PA).

[0095] The embodiment of the present invention further provides a method for preparing a semiconductor device, which is used to prepare the semiconductor device described in any embodiment of the present invention. Figure 3is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, with reference to Figure 3 , a method for preparing a semiconductor device comprises:

[0096] S10, forming a semiconductor body, and forming a second conductive type contact region on a first surface of the semiconductor body; the semiconductor body comprises a first surface and a second surface arranged opposite to each other; the conductive type of the semiconductor body is the first conductive type.

[0097] Specifically, the semiconductor body 1 can be formed by one epitaxy or multiple epitaxies. That is, the semiconductor body 1 can be a semiconductor epitaxial layer 20 or a stacked structure formed by multiple semiconductor epitaxial layers 20. The semiconductor body 1 can also include a substrate 10, that is, the semiconductor body 1 includes a substrate 10 and at least one semiconductor epitaxial layer 20 formed on one side of the substrate 10. The material of the substrate 10 can be the same as the material of the semiconductor epitaxial layer 20, or the material of the substrate 10 can be different from the material of the semiconductor epitaxial layer 20. Optionally, the material of the substrate 10 and the semiconductor epitaxial layer 20 can be SiC.

[0098] The first surface 11 of the semiconductor body 1 of the first conductivity type includes at least one second conductivity type contact region 21. If the first conductivity type is N-type, the second conductivity type is P-type; if the first conductivity type is P-type, the second conductivity type is N-type. Among them, the N-type doping ions can be P (phosphorus) or N (nitrogen) ions, and the P-type doping ions can be Al (aluminum) ions or B (boron) ions. In the embodiment of the present invention, the first conductivity type is N-type and the second conductivity type is P-type.

[0099] S20. Form an insulating layer on the first surface of the semiconductor body, and form an electrode opening in the insulating layer to expose the second conductive type contact area and a portion of the first surface outside the second conductive type contact area; wherein the material of the insulating layer contains a charge capture element, and the charge capture element is used to capture charges in the semiconductor body to reduce the leakage current of the semiconductor device.

[0100] Specifically, an insulating layer 30 is formed on the first surface 11 of the semiconductor body 1, and an electrode opening is formed in the insulating layer 30. The area of ​​the second conductive type contact region 21 is smaller than the first surface 11, and the first surface 11 exposed by the electrode opening in the insulating layer 30 includes at least one second conductive type contact region 21, and a portion of the first surface 11 outside the second conductive type contact region 21. In the related art, the field oxide layer located on the semiconductor body 1 is usually deposited by a PECVD process, which causes the accumulation of charges inside the device. When the semiconductor device is in a high temperature environment, for example, in a high temperature reverse bias test (High Temperature Reverse Bias, HTRB), the charges accumulated inside the semiconductor device will be activated under the action of temperature, causing the leakage of the device to increase, thereby causing the temperature of the device to rise, and then causing the device to fail. In the embodiment of the present invention, the material of the insulating layer 30 located on the semiconductor body 1 contains a charge capture element, and the charge in the semiconductor body 1 can be captured by the charge capture element, thereby reducing the leakage current of the semiconductor device. Among them, the charge capture element includes B and / or P, and can also be other elements with the function of capturing charges.

[0101] S30, forming a first electrode in the electrode opening; the first electrode contacts the first surface 11 exposed by the electrode opening.

[0102] Specifically, the area outside the second conductive type contact area 21 in the first surface 11 is of the first conductive type, and therefore, the first electrode 40 located in the electrode opening contacts at least one second conductive type contact area 21, and contacts a portion of the first surface 11 of the first conductive type outside the second conductive type contact area 21. The semiconductor device provided in the embodiment of the present invention may be a junction barrier Schottky power diode (JBS), or may be a hybrid PiN Schottky diode (MPS).

[0103] The method for preparing a semiconductor device provided by an embodiment of the present invention comprises: forming a semiconductor body 1; forming an insulating layer 30 on the first surface 11 of the semiconductor body 1, and forming an electrode opening in the insulating layer 30 to expose the second conductive type contact area 21 and a portion of the first surface 11 outside the second conductive type contact area 21; wherein the material of the insulating layer 30 contains a charge capture element, and the charge capture element is used to capture the charge in the semiconductor body 1 to reduce the leakage current of the semiconductor device; forming a first electrode 40 in the electrode opening; and the first electrode 40 is in contact with the first surface 11 exposed by the electrode opening. The technical solution provided by an embodiment of the present invention can reduce the leakage level of the device in a high temperature environment by introducing a charge capture element having the ability to capture diffusible charges into the material of the insulating layer 30, thereby improving the problem of device failure caused by high temperature and improving the reliability of the semiconductor device.

[0104] On the basis of the above embodiment, step S10, forming a semiconductor body and forming a second conductive type contact region on the first surface of the semiconductor body, includes:

[0105] S110, providing a substrate, and forming a semiconductor epitaxial layer on one side of the substrate.

[0106] Specifically, refer to Figure 4 and Figure 5 A semiconductor epitaxial layer 20 is formed on one side of the substrate 10. The material of the substrate 10 and the semiconductor epitaxial layer 20 are the same, both of which are SiC.

[0107] S120, forming a mask layer on a side of the semiconductor epitaxial layer away from the substrate, and patterning the mask layer to form an opening in the mask layer that exposes a preset position of the second conductive type contact region.

[0108] Specifically, refer to Figure 6 and Figure 7 , SiO2 can be deposited as a mask layer 100 on the surface of the semiconductor epitaxial layer 2020 away from the substrate 10 by a deposition process such as CVD, and a photoresist PR is spin-coated on the surface of the first mask layer 100. The photoresist PR of the desired pattern is formed by exposure and development, and then the first mask layer 100 is etched based on the patterned photoresist PR. The first mask layer 100 is patterned, and the patterned mask layer 100 includes an opening 01 exposing a preset position of the second conductive type contact area 21.

[0109] S130 , based on the patterned mask layer, implanting second conductive type ions into the first surface exposed by the mask layer to form a second conductive type contact region.

[0110] Specifically, refer to Figure 8 Based on the patterned mask layer 100, the second conductive type ions are implanted into the first surface 11 exposed by the mask layer 100 to form the second conductive type contact region 21. The region of the first surface 11 not implanted with the second conductive type ions is used as the first conductive type contact region 22.

[0111] S140, removing the mask layer.

[0112] Specifically, refer to Fig. 9 , remove the mask layer 100, and expose the first conductive type contact area 22 and the second conductive type contact area 21. The number of the second conductive type contact areas 21 formed on the first surface 11 is multiple, and the multiple second conductive type contact areas 21 are arranged at intervals; the semiconductor epitaxial layer 20 located between adjacent second conductive type contact areas 21 is used as the first conductive type contact area 22. The second conductive type contact areas 21 and the first conductive type contact areas 22 are arranged alternately in sequence.

[0113] Based on the above embodiments, optionally, step S20, forming an insulating layer on the first surface of the semiconductor body, and forming an electrode opening in the insulating layer to expose the second conductive type contact area and a portion of the first surface outside the second conductive type contact area, includes:

[0114] S210 , forming a field oxide sublayer on a first surface of the semiconductor body.

[0115] S220 , forming a charge trapping sublayer on a side of the field oxide sublayer away from the semiconductor body 1 ; wherein the material of the charge trapping sublayer contains a charge trapping element.

[0116] Specifically, refer to Fig.10 , a field oxide sublayer 31 is formed on the first surface 11 of the semiconductor body 1, and a charge capture sublayer 32 is formed on the side of the field oxide sublayer 31 away from the semiconductor body 1, and the charge capture sublayer 32 is in contact with the field oxide sublayer 31. The material of the charge capture sublayer 32 contains a charge capture element. Optionally, the field oxide sublayer 31 is formed on the first surface 11 of the semiconductor body 1, including: forming the field oxide sublayer 31 whose material is silicon dioxide through a plasma enhanced chemical vapor deposition process. The charge capture sublayer 32 is formed on the side of the blocking sublayer 33 away from the semiconductor body 1, including: forming the charge capture sublayer 32 whose material is borophosphosilicate glass through a deposition process.

[0117] S230 , forming an electrode opening penetrating the charge trapping sublayer and the field oxide sublayer.

[0118] Specifically, an electrode opening 02 is formed through the charge trapping sublayer 32 and the field oxide sublayer 31 by an etching process. The electrode opening 02 exposes the plurality of second conductive type contact regions 21 and the plurality of first conductive type contact regions 22, so that the first electrode 40 is in contact with the plurality of first conductive type contact regions 22 and the plurality of second conductive type contact regions 21.

[0119] Furthermore, the insulating layer 30 further includes a blocking sublayer 33 located between the field oxide sublayer 31 and the charge trapping sublayer 32; before forming the charge trapping sublayer 32 on the side of the field oxide sublayer 31 away from the semiconductor body 1, step S220 further includes:

[0120] S211, forming a blocking sublayer on a side of the field oxide sublayer away from the semiconductor body; the blocking sublayer is used to block the charge trapping elements in the charge trapping sublayer from diffusing into the semiconductor body.

[0121] Specifically, refer to Fig.12, forming a blocking sublayer 33 on the side of the field oxide sublayer 31 away from the semiconductor body 1 may include: forming a blocking sublayer 33 whose material is silicon dioxide by a low pressure chemical vapor deposition (LPCVD) process. The material of the blocking sublayer 33 is undoped silicon dioxide (USG), which can also be called undoped silicate glass. The thickness of the field oxide sublayer 31 is greater than the thickness of the blocking sublayer 33, and the purity of the material of the blocking sublayer 33 is higher than the purity of the material of the field oxide sublayer 31. USG has excellent chemical stability and is not easily corroded by most chemical substances; it can withstand high temperatures and is not easily deformed; USG is used as an electrical insulating material, which can effectively isolate current and reduce electrical conductivity.

[0122] Step S230 forms an electrode opening penetrating the charge trapping sublayer and the field oxide sublayer, including:

[0123] The electrode opening 02 penetrating the charge trapping sublayer 32, the blocking sublayer 33 and the field oxide sublayer 31 is formed by an etching process. Fig.13 )

[0124] Based on the above embodiments, optionally, refer to Figure 1 and Figure 2 Step S30 of forming the first electrode 40 in the electrode opening includes: forming the first electrode 40 with a single film layer structure, or forming the first electrode 40 with a multi-film layer structure. Figure 1 and Figure 2 The first electrode 40 is exemplarily shown to be a multi-layer structure, including a Ti layer 41 , a TiN layer 42 and an Al layer 43 which are sequentially away from the semiconductor body 1 .

[0125] Based on the above embodiments, Figure 1 and Figure 2 Optionally, after forming the first electrode 40 in the electrode opening 02, the method further includes:

[0126] forming at least one of a passivation layer and a protective layer 50 on a side of the first electrode 40 away from the semiconductor body 1;

[0127] A second electrode is formed on the second surface 12 .

[0128] The embodiment of the present invention further provides a power module, comprising a substrate and at least one semiconductor power device according to any embodiment of the present invention, wherein the substrate is used to carry the semiconductor power device. The same technical effects are achieved and will not be described in detail here.

[0129] The embodiment of the present invention further provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor power device as described in any embodiment of the present invention, and the semiconductor power device is electrically connected to the circuit board. It has the same technical effect and is not described here.

[0130] The embodiment of the present invention further provides a vehicle, comprising a load and a power conversion circuit as described in any embodiment of the present invention, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load. The same technical effects are achieved, which will not be described in detail here.

[0131] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the conductivity type of the semiconductor body is a first conductivity type; the semiconductor body further comprises a second conductivity type contact region, the second conductivity type contact region is located on the first surface; an insulating layer, located on the first surface of the semiconductor body; the insulating layer is provided with an electrode opening exposing the second conductive type contact region and a portion of the first surface outside the second conductive type contact region; A first electrode is located in the electrode opening and contacts the first surface exposed by the electrode opening; The material of the insulating layer contains charge trapping elements, and the charge trapping elements are used to capture charges in the semiconductor body to reduce leakage current of the semiconductor device.

2. The semiconductor device according to claim 1, wherein: The insulating layer comprises: A field oxide sublayer, located on the first surface of the semiconductor body; A charge trapping sublayer, located on a side of the field oxide sublayer away from the semiconductor body; Wherein, the material of the charge trapping sublayer contains the charge trapping element.

3. The semiconductor device according to claim 1 or 2, characterized in that: The charge trapping element includes B and / or P.

4. The semiconductor device according to claim 2, characterized in that The insulating layer also includes: The blocking sublayer is located between the field oxide sublayer and the charge trapping sublayer; the blocking sublayer is used to block the charge trapping elements in the charge trapping sublayer from diffusing into the semiconductor body.

5. The semiconductor device according to claim 4, characterized in that The material of the field oxide sublayer includes silicon dioxide; The material of the blocking sublayer includes silicon dioxide; The material of the charge trapping sublayer includes borophosphosilicate glass.

6. The semiconductor device according to claim 5, characterized in that The thickness of the blocking sublayer is smaller than the thickness of the field oxide sublayer, and the purity of the material of the blocking sublayer is higher than the purity of the material of the field oxide sublayer.

7. The semiconductor device according to claim 1, wherein: The first surface includes a plurality of second conductive type contact areas and a plurality of first conductive type contact areas; the second conductive type contact areas and the first conductive type contact areas are alternately arranged in sequence; The electrode opening exposes a plurality of the second conductive type contact regions and a plurality of the first conductive type contact regions.

8. The semiconductor device according to claim 1, wherein: The first electrode is a single-layer structure, or the first electrode is a multi-layer structure.

9. The semiconductor device according to claim 1, wherein: Also includes: A passivation layer, located on a side of the first electrode away from the semiconductor body; The second electrode is located on the second surface of the semiconductor body.

10. The semiconductor device according to claim 1, wherein: The semiconductor device is a junction barrier Schottky power diode, or the semiconductor device is a hybrid PiN Schottky diode.

11. A method for preparing a semiconductor device, characterized in that: Used to prepare the semiconductor device according to any one of claims 1 to 10, comprising: forming a semiconductor body; the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the conductivity type of the semiconductor body is a first conductivity type; the semiconductor body further comprises a second conductivity type contact region, and the second conductivity type contact region is located on the first surface; An insulating layer is formed on the first surface of the semiconductor body, and an electrode opening is formed in the insulating layer to expose the second conductive type contact area and a portion of the first surface outside the second conductive type contact area; wherein the material of the insulating layer contains a charge trapping element, and the charge trapping element is used to capture charges in the semiconductor body to reduce leakage current of the semiconductor device; A first electrode is formed in the electrode opening; the first electrode contacts the first surface exposed by the electrode opening.

12. The method for preparing a semiconductor device according to claim 11, characterized in that: An insulating layer is formed on the first surface of the semiconductor body, and an electrode opening is formed in the insulating layer to expose the second conductive type contact region and a portion of the first surface outside the second conductive type contact region, comprising: forming a field oxide sublayer on a first surface of the semiconductor body; A charge trapping sublayer is formed on a side of the field oxide sublayer away from the semiconductor body; wherein the charge trapping sublayer is made of a material containing the charge trapping element; An electrode opening is formed that passes through the charge trapping sublayer and the field oxide sublayer.

13. The method for preparing a semiconductor device according to claim 12, characterized in that: The insulating layer further comprises a blocking sublayer located between the field oxide sublayer and the charge trapping sublayer; Before forming a charge trapping sublayer on a side of the field oxide sublayer away from the semiconductor body, the method further comprises: Forming a blocking sublayer on a side of the field oxide sublayer away from the semiconductor body; the blocking sublayer is used to block the charge trapping elements in the charge trapping sublayer from diffusing into the semiconductor body; Forming an electrode opening penetrating the charge trapping sublayer and the field oxide sublayer comprises: An electrode opening is formed that passes through the charge trapping sublayer, the blocking sublayer, and the field oxide sublayer.

14. The method for preparing a semiconductor device according to claim 13, characterized in that: Forming a field oxide sublayer on the first surface of the semiconductor body comprises: forming a field oxygen sublayer made of silicon dioxide by a plasma enhanced chemical vapor deposition process; Forming a blocking sublayer on a side of the field oxide sublayer away from the semiconductor body, comprising: forming a barrier sublayer made of silicon dioxide by a low pressure chemical vapor deposition process; Forming a charge trapping sublayer on a side of the blocking sublayer away from the semiconductor body, comprising: The charge trapping sublayer is formed by a deposition process and is made of borophosphosilicate glass.

15. A power module, characterized in that: The invention comprises a substrate and at least one semiconductor device according to any one of claims 1 to 10, wherein the substrate is used for carrying the semiconductor device.

16. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 10, wherein the semiconductor device is electrically connected to the circuit board.

17. A vehicle, characterized in that: It comprises a load and a power conversion circuit as claimed in claim 16, wherein the power conversion circuit is used to convert alternating current and / or direct current into alternating current and / or direct current and then input it into the load.

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