Method for manufacturing a semiconductor device and semiconductor device

Abstract

The application discloses a semiconductor device preparation method and a semiconductor device. The semiconductor device preparation method comprises the following steps: providing a substrate; forming a channel layer on one side of the substrate; forming a barrier layer on the side of the channel layer away from the substrate; forming a functional layer arranged on the whole surface on the side surface of the barrier layer away from the channel layer, the functional layer comprising a hollow part and a titanium nitride pattern part; forming a source-drain material layer group arranged on the whole surface on the side surface of the functional layer away from the barrier layer, the source-drain material layer group comprising a titanium material layer in contact with the functional layer; and performing a patterning treatment and an annealing treatment on the functional layer and the source-drain material layer group to form a source-drain functional part, the source-drain functional part comprising a source part and a drain part arranged at intervals. The semiconductor device preparation method provided by the application can improve the performance of ohmic contact.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a method for fabricating a semiconductor device and the semiconductor device itself. Background Technology

[0002] Ohmic contacts primarily form the source and drain of high electron mobility transistors (HEMTs), and their performance directly affects the transistor's output source-drain current and knee voltage. The performance of ohmic contacts determines the transistor's yield and performance, and the performance of ohmic contacts in related technologies still needs improvement. Summary of the Invention

[0003] The purpose of this application is to at least solve the problem of poor performance of ohmic contacts. This purpose is achieved through the following technical solution:

[0004] The first aspect of this application discloses a method for fabricating a semiconductor device, comprising:

[0005] Provide substrate;

[0006] A trench layer is formed on one side of the substrate;

[0007] A barrier layer is formed on the side of the channel layer opposite to the substrate;

[0008] A functional layer is formed on the surface of the barrier layer away from the channel layer, and the functional layer includes a hollow portion and a titanium nitride patterned portion.

[0009] A source / drain material layer group is formed on the side surface of the functional layer opposite to the barrier layer, the source / drain material layer group including a titanium material layer in contact with the functional layer;

[0010] The functional layer and the source / drain material layer group are patterned and annealed to form a source / drain functional part, which includes a source part and a drain part arranged at intervals.

[0011] In the preparation method provided in this application, after forming the barrier layer, a functional layer is formed on the side of the barrier layer facing away from the channel layer. The functional layer includes a titanium nitride pattern and a hollowed-out portion. A source / drain material layer group with a titanium material layer is formed on the side of the functional layer facing away from the barrier layer. The titanium material layer is in contact with the titanium nitride pattern. Then, the functional layer and the source / drain material layer group are patterned and annealed to form the source / drain functional portion. By setting the titanium nitride pattern, better ohmic performance can be achieved. Specifically, the annealing treatment is used to further react the barrier layer with the titanium metal in the titanium material layer to achieve the connection between the barrier layer and the titanium material layer and eliminate the interface barrier. The titanium nitride pattern is formed at the interface between the barrier layer and the titanium material layer, which can provide a stable intermetallic compound at the interface. The titanium nitride pattern can promote the reaction between the surrounding titanium metal and the barrier layer, thereby increasing the area of ​​ohmic contact between the titanium nitride layer and the barrier layer within a preset time. The titanium nitride pattern is located between the metal (titanium metal) and the semiconductor (barrier layer) interface, reducing defects and density of states at the interface. These defects and states trap charge carriers, increasing interface resistance. In this application, by setting the titanium nitride pattern, the interface states between the barrier layer and the titanium material layer can be reduced, thereby lowering the contact resistance and improving the yield of the semiconductor device fabricated using the above-described method. Furthermore, the titanium nitride pattern can act as a passivator, passivating dangling bonds on the barrier layer surface, reducing surface recombination velocity, and increasing carrier mobility, thereby further reducing contact resistance. The titanium nitride pattern can also alter the current distribution at the contact interface between the barrier layer and the titanium material layer, making the current more uniformly distributed at the interface, reducing local overheating, improving overall contact performance, and thus reducing heat loss during semiconductor device operation, further mitigating heat loss-related problems and alleviating heat dissipation pressure. The semiconductor device fabrication method provided in this application can reduce contact resistance at the interface and improve the problem of local overheating, thereby effectively improving the overall performance of the semiconductor device.

[0012] The second aspect of this application also provides a semiconductor device, which is formed by the method for fabricating the semiconductor device provided in the first aspect of this application. Attached Figure Description

[0013] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0014] Figure 1 This is a flowchart of a method for fabricating a semiconductor device provided in this application;

[0015] Figure 2 This is a schematic diagram of the film structure in a method for fabricating a semiconductor device provided in this application;

[0016] Figure 3 This is a schematic diagram of the functional layer structure in a method for fabricating a semiconductor device provided in this application;

[0017] Figure 4 This is a schematic diagram of the subsequent film structure in a semiconductor device fabrication method provided in this application;

[0018] Figure 5 This is a schematic diagram of the patterned film structure in a semiconductor device fabrication method provided in this application;

[0019] Figures 6 to 7 This is a schematic diagram of the fabrication process of the functional layer in a semiconductor device fabrication method provided in this application;

[0020] Figure 8 This is a schematic diagram of the film structure in another method for fabricating a semiconductor device provided in this application;

[0021] Figures 9 to 10 This is a schematic diagram of the film structure change in another semiconductor device fabrication method provided in this application;

[0022] Figure 11 This is a schematic diagram of the barrier layer fabrication process in a semiconductor device fabrication method provided in this application;

[0023] Figure 12 This is a schematic diagram of the barrier layer fabrication process in another semiconductor device fabrication method provided in this application;

[0024] Figure 13 This is a schematic diagram of the isolation structure in a method for fabricating a semiconductor device provided in this application;

[0025] Figure 14 This is a schematic diagram illustrating the fabrication process of the isolation structure in a semiconductor device fabrication method provided in this application;

[0026] Figure 15 This is a schematic diagram of the film structure in another method for fabricating a semiconductor device provided in this application;

[0027] Figure 16 This is a schematic diagram of the structure of the first semiconductor device provided in this application;

[0028] Figure 17 This is a schematic diagram of the structure of the second type of semiconductor device provided in this application;

[0029] Figure 18 This is a schematic diagram of the structure of the third type of semiconductor device provided in this application;

[0030] Figure 19 This is a schematic diagram of the structure of the fourth type of semiconductor device provided in this application;

[0031] Figure 20 This is a schematic diagram of the structure of the fifth type of semiconductor device provided in this application.

[0032] The attached figures are labeled as follows:

[0033] 1. Semiconductor device; 10. Functional layer; 101. Hole; 102. Titanium nitride patterned area; 11. Substrate; 12. Channel layer; 13. Barrier layer; 131. Receiving via; 132. Receiving trench; 14. Source / drain functional area; 141. Source; 142. Drain; 143. Titanium metal layer; 144. Aluminum metal layer; 145. Titanium nitride layer; 146. Nickel metal layer; 147. Gold metal layer; 15. Cap layer; 16. Titanium material layer; 17. Aluminum material layer; 18. Titanium nitride material layer; 19. Mask layer; 191. Masking area; 192. Hole area; 20. Isolation mask layer; 21. Isolation structure; 22. Source / drain material layer group; 23. Titanium nitride thin film layer; 24. Nickel material layer; 25. Gold material layer. Detailed Implementation

[0034] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0035] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0036] Although terms such as first, second, third, etc., may be used in this document to describe multiple elements, components, regions, layers, and / or segments, these elements, components, regions, layers, and / or segments should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or segment from another. Unless the context clearly indicates otherwise, terms such as "first," "second," and other numerical terms used herein do not imply order or sequence. Therefore, the first element, component, region, layer, or segment discussed below may be referred to as the second element, component, region, layer, or segment without departing from the teachings of the exemplary embodiments.

[0037] For ease of description, spatial relative terms may be used in the text to describe the relationship of one element or feature relative to another element or feature, as shown in the figure. These relative terms include, for example, "inside," "outside," "middle," "outer," "below," "below," "above," "over," etc. Such spatial relative terms are intended to include different orientations of the device in use or operation, other than those depicted in the figure. For example, if the device in the figure is flipped, an element described as "below other elements or features" or "below other elements or features" would subsequently be oriented as "above other elements or features" or "above other elements or features." Therefore, the example term "below" can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or in other directions), and the spatial relative descriptors used in the text will be interpreted accordingly.

[0038] Research has shown that ohmic contacts primarily form the source and drain of high electron mobility transistors (HEMTs), and their performance directly affects the transistor's output source-drain current and knee voltage. The performance of the ohmic contact determines the transistor's yield and performance. However, existing ohmic contacts suffer from problems such as high contact resistance and localized overheating at the contact cross-section, indicating that their performance still needs improvement. Therefore, this application provides a method for fabricating a semiconductor device to improve the performance of the ohmic contact and thus enhance the overall performance of the semiconductor device.

[0039] like Figure 1 As shown, according to an embodiment of this application, a method for fabricating a semiconductor device is proposed, comprising:

[0040] S200, such as Figure 2 As shown, a substrate 11 is provided.

[0041] Specifically, the substrate 11 is made of one of silicon carbide, silicon, or sapphire.

[0042] S400, such as Figure 2 As shown, a channel layer 12 is formed on one side of the substrate 11.

[0043] Specifically, the channel layer 12 can be made of gallium nitride (GaN).

[0044] Specifically, a buffer layer may be formed before the channel layer 12 is formed on the substrate 11.

[0045] S600, such as Figure 2 As shown, a barrier layer 13 is formed on the side of the channel layer 12 away from the substrate 11.

[0046] Specifically, the barrier layer 13 is made of aluminum gallium nitride (AlGaN).

[0047] S800, such as Figure 2 and Figure 3 As shown, a functional layer 10 is formed on the side of the barrier layer 13 facing away from the channel layer 12. The functional layer 10 includes a hollow portion 101 and a titanium nitride pattern portion 102.

[0048] Specifically, the cutout portion 101 is a through-hole penetrating the thickness direction of the functional layer 10, exposing the barrier layer 13. The titanium nitride pattern portion 102 can be a regular granular structure, an irregular block structure, or a mesh structure, etc. Among them, the orthographic projection of the regular granular structure on the substrate 11 can be circular, elliptical, etc.

[0049] S1000, such as Figure 4 As shown, a source / drain material layer group 22 is formed on the side surface of the functional layer 10 away from the barrier layer 13. The source / drain material layer group 22 includes a titanium material layer 16 that is in contact with the functional layer 10.

[0050] Specifically, the source / drain material layer group 22 includes multiple material layers, each of which is a continuous film layer, meaning that the orthogonal projection of the material layer onto the substrate 11 covers the substrate 11. One of the multiple material layers closest to the barrier layer 13 is a titanium material layer 16. The multiple material layers include elemental metal material layers, or may also include metal compound material layers.

[0051] S1200, such as Figure 5 As shown, the functional layer 10 and the source / drain material layer group 22 are patterned and annealed to form the source / drain functional part 14, which includes a source part 141 and a drain part 142 spaced apart.

[0052] In the above-mentioned preparation method provided in this application, after forming the barrier layer 13, a functional layer 10 is formed on the side surface of the barrier layer 13 away from the channel layer 12. The functional layer 10 includes a titanium nitride patterned portion 102 and a hollow portion 101. A source / drain material layer group 22 with a titanium material layer 16 is formed on the side surface of the functional layer 10 away from the barrier layer 13. The titanium material layer 16 is in contact with the titanium nitride patterned portion 102. Then, the functional layer 10 and the source / drain material layer group 22 are patterned and annealed to form the source / drain functional portion 14. Better ohmic performance can be achieved by setting the titanium nitride patterned portion 102. Specifically, the annealing process is used to further react the barrier layer 13 with the titanium metal in the titanium material layer 16 to achieve a connection between the barrier layer 13 and the titanium material layer 16, eliminating the interface barrier. A titanium nitride pattern 102 is formed at the interface between the barrier layer 13 and the titanium material layer 16, providing a stable intermetallic compound at the interface. The titanium nitride pattern 102 promotes the reaction between the surrounding titanium metal and the barrier layer 13, increasing the area of ​​the ohmic contact formed between the titanium nitride layer 145 and the barrier layer 13 within a preset time period. The titanium nitride pattern 102 is located between the metal (titanium metal) and the semiconductor (barrier layer 13) interface, reducing defects and state density at the interface. These defects and states trap charge carriers, increasing the interface resistance. In this application, by providing the titanium nitride pattern 102, the interface states between the barrier layer 13 and the titanium material layer 16 can be reduced, thereby lowering the contact resistance and improving the yield of the semiconductor device fabricated using the above-described method. Furthermore, the titanium nitride pattern 102 can passivate the dangling bonds on the surface of the barrier layer 13, reduce surface recombination velocity, and improve carrier mobility, thereby further reducing contact resistance. The titanium nitride pattern 102 can also alter the current distribution at the interface between the barrier layer 13 and the titanium material layer 16, making the current more uniformly distributed at the interface, reducing local overheating, improving overall contact performance, and thus reducing heat loss during semiconductor device operation, further mitigating heat loss-related problems and alleviating heat dissipation pressure. The semiconductor device fabrication method provided in this application can reduce contact resistance at the interface and improve the problem of local overheating, thereby effectively improving the overall performance of the semiconductor device.

[0053] Specifically, due to the limitations of the annealing process, such as the limited duration for which the annealing furnace can operate continuously at or above a preset temperature, the proportion of ohmic contact area formed at the interface between the titanium material layer 16 and the barrier layer 13 within the preset time is relatively low, easily leading to uneven ohmic contact distribution. This application addresses this by forming a titanium nitride pattern 102 between the titanium material layer 16 and the barrier layer 13. While the titanium nitride pattern 102 itself does not participate in the alloying reaction during annealing, it optimizes the conditions required for alloying, promoting contact reaction between the titanium material layer 16 and the barrier layer 13 surrounding the titanium nitride pattern 102 through the perforated portion 101. This increases the area of ​​ohmic contact formed between the titanium material layer 16 and the barrier layer 13, improving the performance of the ohmic contact.

[0054] In the above embodiments, the functional layer 10 and the source / drain material layer group 22 can be patterned simultaneously or separately. Simultaneous patterning simplifies the fabrication process, saves fabrication costs, and reduces process errors between different film layers by simultaneously patterning multiple film layers.

[0055] In the above embodiments, at least a portion of the area where the titanium material layer 16 and the barrier layer 13 are in direct contact through the cutout 101 can be alloyed after annealing to form a titanium nitride bonding layer (not shown in the figure).

[0056] In one feasible implementation, step S800 includes:

[0057] S810, such as Figure 3 As shown, titanium nitride particles are formed by sputtering to form a titanium nitride pattern 102, and a hollowed-out portion 101 is formed between adjacent titanium nitride particles.

[0058] In the above embodiments, sputtering can be used to directly form spaced titanium nitride particles, with hollow portions 101 naturally formed between adjacent titanium nitride particles, making the preparation process simple.

[0059] In the above embodiments, the sputtering process includes magnetron sputtering, ion beam sputtering, DC sputtering, and reactive sputtering.

[0060] In another feasible implementation, step S800 includes:

[0061] S821, such as Figure 6 As shown, a titanium nitride thin film layer 23 is formed on the side of the barrier layer 13 facing away from the channel layer 12.

[0062] S822, such as Figure 7 As shown, a portion of the titanium nitride thin film layer 23 is removed to form a plurality of hollow portions 101, and a patterned titanium nitride pattern portion 102 is formed.

[0063] In the above embodiments, the thickness of the titanium nitride thin film layer 23 ranges from 3 nm to 5 nm.

[0064] In the above embodiment, a titanium nitride thin film layer 23 can be grown on the surface of the barrier layer 13 facing away from the channel layer 12. Then, the titanium nitride thin film layer 23 is processed to form a hollow portion 101 that penetrates the titanium nitride thin film along the thickness direction of the titanium nitride thin film layer 23. The portion of the titanium nitride thin film layer 23 that is not removed forms a titanium nitride pattern portion 102. The titanium nitride pattern portion 102 can be a continuously arranged mesh structure, or it can be a spaced block structure.

[0065] Since many metal growth equipment cannot achieve the precision required to directly grow titanium nitride particles, the above-mentioned preparation process can be used to form a functional material layer, thereby saving equipment costs while realizing the preparation of the titanium nitride pattern 102.

[0066] In one feasible implementation, step S822 includes:

[0067] Atom bombardment technology is used to remove part of the titanium nitride thin film layer 23 to form multiple hollow parts 101.

[0068] In the above embodiments, the titanium nitride thin film layer 23 can be dispersed by argon (Ar) atoms to form discretely distributed titanium nitride patterned portions 102. The shapes of the different titanium nitride patterned portions 102 are different, and the shapes of the titanium nitride patterned portions 102 are irregular patterns.

[0069] In one feasible implementation, the ratio of the area of ​​the titanium nitride pattern portion 102 to the total area of ​​the functional layer 10 is in the range of 25%-40%.

[0070] In the above embodiments, since the titanium nitride pattern portion 102 itself does not participate in the alloying reaction between the barrier layer 13 and the titanium material layer 16 during the annealing process, the ratio of the total area of ​​the titanium nitride pattern portion 102 to the total area of ​​the functional layer 10 should not be too large to avoid affecting the contact area between the barrier layer 13 and the titanium material layer 16 and thus affecting the ohmic contact area formed after annealing. Simultaneously, since the titanium nitride pattern portion 102 can optimize the conditions required for alloying and promote the contact reaction between the titanium material layer 16 surrounding the titanium nitride pattern portion 102 and the barrier layer 13 through the perforated portion 101, thereby increasing the area of ​​the ohmic contact formed between the titanium nitride layer 145 and the barrier layer 13, the ratio of the area of ​​the titanium nitride pattern portion 102 to the total area of ​​the functional layer 10 should not be too low to ensure its promoting effect. Therefore, by controlling the ratio of the area of ​​the titanium nitride pattern portion 102 to the total area of ​​the functional layer 10 within the range of 25%-40%, a significant improvement in ohmic contact performance can be achieved.

[0071] Specifically, in the functional layer 10, the ratio of the area of ​​the titanium nitride patterned portion 102 to the total area of ​​the functional layer 10 can be 25%, 26%, 30%, 33%, 35%, 38%, 40%, etc.

[0072] In one feasible implementation, step S1000 includes:

[0073] S1100, such as Figure 4 As shown, a titanium material layer 16, an aluminum material layer 17, and a titanium nitride material layer 18 are sequentially formed on the surface of the functional layer 10 facing away from the barrier layer 13.

[0074] Specifically, the thickness of the titanium material layer 16 ranges from 5 nm to 25 nm; the thickness of the aluminum metal layer 144 ranges from 120 nm to 180 nm; and the thickness of the titanium nitride layer 145 ranges from 80 nm to 120 nm.

[0075] In the above embodiment, the source / drain material layer group 22 includes a titanium material layer 16, an aluminum material layer 17, and a titanium nitride material layer 18 stacked along the direction away from the barrier layer 13. The preparation process of the source / drain material layer group 22 includes sequentially forming a full-surface titanium material layer 16, an aluminum material layer 17, and a titanium nitride material layer 18 on the side of the barrier layer 13 away from the channel layer 12, and performing patterning and annealing processes to form the source / drain functional parts 14. The titanium nitride material layer 18 has relatively stable properties. During the annealing process, it can protect the titanium material layer 16 and the aluminum material layer 17, preventing the titanium material layer 16 and the aluminum material layer 17 from overflowing and causing contact between the source part 141 and the drain part 142, thereby causing leakage or even short circuit, which helps to improve the yield and reliability of semiconductor devices. Since no gold material is used when forming the source / drain functional part 14, a gold-free ohmic contact can be formed with the barrier layer 13. Compared with the gold-containing ohmic contact, the preparation method provided in this application has a low material cost, which can reduce the manufacturing cost of semiconductor devices. It can also avoid the contact degradation problem caused by the easy diffusion of gold at high temperatures. In other words, the semiconductor device preparation method provided in this application can manufacture semiconductor devices with stronger stability, higher temperature resistance, and higher reliability.

[0076] In the above embodiments, the titanium nitride patterned portion 102 is located between the barrier layer 13 and the titanium material layer 16, which can reduce the contact resistance at the interface between the barrier layer 13 and the titanium material layer 16, and change the current distribution at the contact interface between the barrier layer 13 and the titanium material layer 16, so that the current is more evenly distributed at the contact interface between the barrier layer 13 and the titanium material layer 16, reducing local overheating and improving the overall contact performance.

[0077] In the above embodiments, the resistance of the non-gold ohmic contact can be as low as 0.1Ω, which helps to further improve the performance of semiconductor devices.

[0078] In the above embodiments, the portion where the aluminum metal layer 144 contacts the titanium material layer 16 can be alloyed after annealing to form a titanium-aluminum alloy layer (not shown in the figure).

[0079] In the above embodiments, the annealing temperature range is 600℃-680℃. Specifically, the source / drain functional unit 14 is formed by stacking titanium material layer 16, aluminum material layer 17, and titanium nitride material layer 18. During the annealing process to form an alloy and achieve ohmic contact, the annealing temperature is relatively low, thereby avoiding damage to the semiconductor device caused by high temperature, improving the overall performance and yield of the semiconductor device, and helping to reduce the manufacturing difficulty and cost.

[0080] CMOS technology, as an integrated circuit manufacturing process, features high integration, low power consumption, and high reliability, and is widely used in the manufacturing of various electronic products. In the semiconductor device fabrication method provided in this application, a gold-free ohmic contact can be formed between the source / drain functional portion 14 and the barrier layer 13. The material of the source / drain functional portion 14 is compatible with existing CMOS manufacturing processes. This compatibility allows GaN devices to be integrated into CMOS processes to form mixed-signal and high-power integrated circuits, thereby further improving overall performance and adding more functions. This promotes the emergence of new devices and expands their application scenarios. For example, new devices can be applied to high-frequency communication, radar systems, power electronic devices, and other fields. Since CMOS process production lines are very mature and large-scale, using gold-free ohmic contact GaN devices allows for the large-scale production of silicon-based gallium nitride devices using existing CMOS processes. This reduces production costs and facilitates the large-scale production and application of gallium nitride devices.

[0081] In the semiconductor device fabrication method provided in this application, the metal material used in the source / drain functional part 14 can be fabricated using a waterless process throughout the entire fabrication process, which can be well integrated with CMOS technology.

[0082] In one feasible implementation, titanium metal is sputtered in a mixed gas of argon and nitrogen in a ratio of 40:7 to form a titanium nitride material layer 18.

[0083] Specifically, titanium nitride material layer 18 is formed by sputtering metallic titanium in a gas mixture of argon and nitrogen at a ratio of 40:7. The ratio of nitrogen atoms to titanium atoms in the formed titanium nitride material layer 18 ranges from 0.8 to 1.2. Titanium nitride is a controllable material, and its work function can be controlled by adjusting the ratio of nitrogen atoms to titanium atoms within the titanium nitride, thus better matching it with the titanium material layer 16 and the aluminum material layer 17.

[0084] In another feasible implementation, step S1000 includes:

[0085] S1200, such as Figure 8 As shown, a titanium material layer 16, an aluminum material layer 17, a nickel material layer 24, and a gold material layer 25 are sequentially formed on the surface of the functional layer 10 facing away from the barrier layer 13.

[0086] In the above embodiment, the source / drain material layer group 22 includes a titanium material layer 16, an aluminum material layer 17, a nickel material layer 24, and a gold material layer 25 stacked along the direction away from the barrier layer 13. The source / drain material layer group 22 includes the titanium material layer 16, the aluminum material layer 17, the nickel material layer 24, and the gold material layer 25 sequentially formed on the surface of the functional layer 10 away from the barrier layer 13. A gold-containing ohmic contact is formed between the source / drain functional part 14 and the barrier layer 13, which has strong ohmic performance. Furthermore, by forming a titanium nitride pattern part 102 between the barrier layer 13 and the titanium material layer 16, the contact resistance at the interface between the barrier layer 13 and the titanium material layer 16 can be further reduced, and the current distribution at the contact interface between the barrier layer 13 and the titanium material layer 16 can be changed, so that the current is more evenly distributed at the contact interface between the barrier layer 13 and the titanium material layer 16, reducing local overheating and improving the overall contact performance.

[0087] In one feasible implementation, the titanium material layer 16 can be formed using a magnetron sputtering process, with an argon gas atmosphere. The aluminum material layer 17 can also be formed using a magnetron sputtering process, with an argon gas atmosphere. The above-mentioned preparation process technology is mature and highly controllable, which can improve the preparation yield of the titanium material layer 16 and the aluminum material layer 17.

[0088] In one feasible implementation, the step of patterning the functional layer 10 and the source / drain material layer group 22 includes:

[0089] S1210, such as Figure 9 As shown, a mask layer 19 is formed on the side surface of the barrier layer 13 facing away from the channel layer 12. The mask layer 19 includes a shielding region 191 and a hole region 192. The hole region 192 is used to form a source portion 141 and a drain portion 142.

[0090] S1220, such as Figure 10 As shown, a functional layer 10 and a source / drain material layer group 22 are sequentially formed on the side of the mask layer 19 facing away from the substrate 11 and the side of the barrier layer 13 facing away from the substrate 11.

[0091] S1230, such as Figure 5 As shown, the mask layer 19 is removed and the portion of the functional layer 10 and the source / drain material layer group 22 located on the side of the mask layer 19 opposite to the substrate 11 is removed.

[0092] Specifically, the material of the mask layer 19 may include photoresist. The specific steps for forming the mask layer 19 include: spin coating, exposure, and development. The spin coating speed can be 6000 r / min, and the photoresist thickness can be 1.1 μm. In the mask layer 19, the aperture region 192 penetrates the mask layer 19 along its thickness direction.

[0093] Specifically, the mask layer 19 and the functional layer 10 and source / drain material layer group 22 located on the side of the mask layer 19 opposite to the substrate 11 can be peeled off, leaving only the portion of the source / drain material layer group 22 located in the hole region 192, thereby achieving patterning of the functional layer 10 and the source / drain material layer group 22.

[0094] In one feasible embodiment, a mask layer 19 is formed on the surface of the barrier layer 13 facing away from the channel layer 12. The mask layer 19 includes a shielding region 191 and an aperture region 192. After the step of forming the source portion 141 and the drain portion 142 in the aperture region 192, the method further includes:

[0095] S1211, such as Figure 11 and Figure 12 As shown, the exposed areas of the via region 192 in the barrier layer 13 are etched to form a receiving hole 131 or a receiving groove 132.

[0096] Specifically, a dry etching process can be used to etch the exposed portion of the via region 192 in the barrier layer 13.

[0097] In the above embodiments, after the barrier layer 13 is etched using a dry etching process, the morphology of the etched surface is conducive to the formation of ohmic contacts, thereby further improving the stability of ohmic contacts.

[0098] In the above embodiments, when the thickness of the barrier layer 13 is greater than a preset thickness value, a receiving groove 132 or a receiving hole 131 can be formed in the barrier layer 13, such as... Figure 11 As shown, the receiving hole 131 penetrates the barrier layer 13 and exposes the channel layer 12. The source portion 141 is located inside the receiving hole 131, and the source portion 141 corresponds to the receiving hole 131 one by one. The source portion 141 is in contact with the sidewall of the receiving hole 131 and is in contact with the channel layer 12 exposed through the receiving hole 131. The drain portion 142 is located inside the receiving hole 131, and the drain portion 142 corresponds to the receiving hole 131 one by one. The drain portion 142 is in contact with the sidewall of the receiving hole 131 and is in contact with the channel layer 12 exposed through the receiving hole 131.

[0099] In the above embodiments, the preset thickness value can be 6 nm. The thickness range of the barrier layer 13 can be 20 nm to 23 nm.

[0100] In the above embodiments, such as Figure 11As shown, when the barrier layer 13 has a receiving hole 131, the circumferential direction of the source portion 141 contacts the sidewall of one of the receiving holes 131, that is, the circumferential direction of the source portion 141 contacts the barrier layer 13, and the bottom of the source portion 141 contacts the channel layer 12. The circumferential direction of the drain portion 142 contacts the sidewall of one of the receiving holes 131, that is, the circumferential direction of the drain portion 142 contacts the barrier layer 13, and the bottom of the drain portion 142 contacts the channel layer 12.

[0101] An ohmic contact can be formed by annealing the sidewall of the source / drain functional section 14 in contact with the barrier layer 13. An ohmic contact can also be formed by annealing the bottom wall of the source / drain functional section 14 in contact with the barrier layer 13. An ohmic contact is more easily formed between the sidewall of the source / drain functional section 14 and the barrier layer 13 than between the bottom wall and the barrier layer 13. Therefore, in the above embodiment, by forming a receiving hole 131 in the barrier layer 13, the contact area between the barrier layer 13 and the sidewall of the source / drain functional section 14 is increased, which helps to improve the formation of ohmic contacts and improve the stability of the semiconductor device.

[0102] In the above embodiments, such as Figure 12 As shown, when the barrier layer 13 has a receiving groove 132, the circumferential direction of the source portion 141 contacts the side wall of the receiving groove 132, that is, the circumferential direction of the source portion 141 contacts the barrier layer 13, and the bottom of the source portion 141 contacts the barrier layer 13. The circumferential direction of the drain portion 142 contacts the side wall of the receiving groove 132, that is, the circumferential direction of the drain portion 142 contacts the barrier layer 13, and the bottom of the drain portion 142 contacts the barrier layer 13.

[0103] The sidewalls of the source / drain functional section 14 are in contact with the barrier layer 13 and are annealed to form an ohmic contact. The bottom wall of the source / drain functional section 14 is in contact with the barrier layer 13 and is annealed to form an ohmic contact. Therefore, in the above embodiment, by forming a receiving groove 132 in the barrier layer 13, the total contact area between the barrier layer 13 and the source / drain functional section 14 is increased, which helps to improve the formation of the ohmic contact and improve the stability of the semiconductor device.

[0104] Specifically, the thickness of the bottom wall of the receiving trench 132 is less than or equal to 2 nm, that is, the thickness of the portion of the barrier layer 13 located on the side of the receiving trench 132 near the substrate 11 is less than or equal to 2 nm.

[0105] In one feasible implementation, when the thickness of the barrier layer 13 is less than or equal to a preset thickness value, that is, when the barrier layer 13 is thin, the barrier layer 13 does not need to be slotted or perforated. After the barrier layer 13 is formed, the functional layer 10 can be formed directly on the side of the barrier layer 13 facing away from the substrate 11.

[0106] In one feasible implementation, such as Figure 13As shown, the method for fabricating a semiconductor device may further include forming an isolation structure 21 for isolating adjacent device regions. The device regions can be used to form transistors or capacitors, etc., wherein the transistors fabricated in the above embodiments of this application may be located in one of the device regions. After the step of patterning the functional layer 10 and the source / drain material layer group 22, the method further includes forming an isolation structure 21, which is disposed around the source / drain functional portion 14. The isolation structure 21 penetrates the barrier layer 13 along the thickness direction of the substrate 11 and penetrates at least a portion of the channel layer 12.

[0107] In the above embodiments, shallow trench isolation technology or ion implantation can be used to form the isolation structure 21 for device isolation.

[0108] The specific steps for forming the isolation structure 21 include:

[0109] An isolation mask layer 20 is formed on the side of the titanium nitride layer 145 and the barrier layer 13 facing away from the substrate 11. The isolation mask layer 20 forms a mask portion covering the device region where the transistor is located and exposes the area around the device region used to form the isolation structure 21. Then, the isolation structure 21 is formed in the area not covered by the mask portion, i.e., the area used to form the isolation structure 21, by shallow trench isolation technology or ion implantation. Then the isolation mask layer 20 is removed.

[0110] Specifically, the material of the isolation mask layer 20 may include photoresist. The specific steps for forming the isolation mask layer 20 include: spin coating, exposure, and development. The spin coating speed can be 1800 rpm, and the photoresist thickness can be 3 μm.

[0111] In one feasible implementation, S600: after the step of forming the barrier layer 13 on the side of the channel layer 12 facing away from the substrate 11, the method further includes:

[0112] like Figure 15 As shown, a cap layer 15 is formed on the side surface of the barrier layer 13 facing away from the channel layer 12, and the cap layer 15 is patterned to form an opening that penetrates the cap layer 15 along the thickness direction of the cap layer 15. The opening is used to form a source portion 141 or a drain portion 142.

[0113] In the above embodiments, the material of the cap layer 15 includes gallium nitride or silicon nitride.

[0114] In the above embodiments, when the cap layer 15 is made of gallium nitride, the material of the cap layer 15 is the same as that of the channel layer 12, which facilitates its fabrication. Silicon nitride is grown in situ, thus simplifying the process and saving production costs. Furthermore, the silicon nitride layer possesses characteristics such as high dielectric constant, low loss, high thermal stability, excellent corrosion resistance, and mechanical strength, making it an effective protective layer that can protect semiconductor devices and extend their lifespan.

[0115] In the above embodiments, when the barrier layer 13 includes a receiving groove 132 or a receiving hole 131, the cap layer 15 can be patterned simultaneously with the barrier layer 13, which will not be described in detail here. When the barrier layer 13 does not include a receiving groove 132 or a receiving hole 131, the cap layer 15 can be patterned separately to form an opening. The opening exposes the area in the barrier layer 13 used to form the source portion 141 and the drain portion 142, thereby facilitating the formation of ohmic contacts between the source portion 141 and the drain portion 142 and the barrier layer 13, respectively.

[0116] The patterning method of the cap layer 15 is similar to the preparation method of forming the receiving hole 131 in the barrier layer 13, and will not be described in detail here.

[0117] In the above embodiments, when the thickness of the barrier layer 13 is less than or equal to a preset thickness value, it is preferable to form a cap layer 15; when the thickness of the barrier layer 13 is greater than the preset thickness value, it is not necessary to form a cap layer 15; or, when the thickness of the barrier layer 13 is greater than the preset thickness value, it is also possible to form a cap layer 15.

[0118] The preparation method provided in this application further includes forming a gate insulating layer and a gate (not shown in the figure) on the side surface of the cap layer 15 facing away from the substrate 11, with the gate located between the source portion 141 and the drain portion 142.

[0119] This application also provides a semiconductor device 1, which is prepared by any of the semiconductor device preparation methods provided in the above embodiments.

[0120] like Figure 5 As shown, the semiconductor device 1 provided in this application includes a substrate 11, a channel layer 12, a barrier layer 13, a functional layer 10, and source / drain functional portions 14. The channel layer 12 is located on one side of the substrate 11, and the barrier layer 13 is located on the side of the channel layer 12 away from the substrate 11. The functional layer 10 is located on the side of the barrier layer 13 away from the channel layer 12, and the functional layer 10 includes a cutout portion 101 and a titanium nitride patterned portion 102. The source / drain functional portions 14 are located on the side of the functional layer 10 away from the barrier layer 13, and the source / drain functional portions 14 include a source portion 141 and a drain portion 142 disposed at intervals, and the source / drain functional portions 14 include a titanium metal layer 143 in contact with the functional layer 10.

[0121] In the semiconductor device 1 provided in this application, the titanium metal layer 143 is formed by patterning a titanium material layer 16. By providing a functional layer 10 between the barrier layer 13 and the titanium metal layer 143, the ohmic contact performance of the contact interface between the barrier layer 13 and the titanium metal layer 143 can be improved. Specifically, the titanium nitride patterned portion 102 can provide a stable intermetallic compound at the contact interface between the barrier layer 13 and the titanium metal layer 143. The titanium nitride patterned portion 102 can promote the reaction between the titanium metal in the surrounding titanium material layer 16 and the barrier layer 13, thereby increasing the area of ​​the ohmic contact formed between the titanium nitride layer 145 and the barrier layer 13 within a preset time period. The titanium nitride pattern 102 is located between the titanium metal layer 143 and the barrier layer 13. It reduces defects and the density of states at the contact interface between the barrier layer 13 and the titanium metal layer 143. These defects and states trap charge carriers, increasing interface resistance. In this application, by providing the titanium nitride pattern 102, the interface states between the barrier layer 13 and the titanium metal layer 143 can be reduced, thereby lowering the contact resistance and improving the yield of the semiconductor device 1. Furthermore, the titanium nitride pattern 102 can act as a passivator, passivating the dangling bonds on the surface of the barrier layer 13, reducing surface recombination velocity, and increasing the carrier mobility, thereby further reducing the contact resistance. The titanium nitride pattern 102 can also change the current distribution at the contact interface between the barrier layer 13 and the titanium metal layer 143, making the current more uniformly distributed at the contact interface, reducing local overheating, improving overall contact performance, and thus reducing heat loss during the operation of the semiconductor device 1, further reducing heat loss-related problems and alleviating heat dissipation pressure. The semiconductor device 1 provided in this application has a low contact resistance at the interface and improves the problem of local overheating, thereby effectively improving the overall performance of the semiconductor device 1.

[0122] In the above embodiment, the cutout portion 101 is a through hole penetrating the thickness direction of the functional layer 10, exposing the barrier layer 13. The titanium nitride pattern portion 102 can be a regular granular structure, an irregular block structure, or a mesh structure, etc. Among them, the orthographic projection of the regular granular structure on the substrate 11 can be circular, elliptical, etc.

[0123] In the semiconductor device 1 provided in this application, such as Figure 16 As shown, the source / drain functional unit 14 includes a titanium metal layer 143, an aluminum metal layer 144, and a titanium nitride layer 145 sequentially disposed along a direction away from the substrate 11. Or as... Figure 17 As shown, the source / drain functional unit 14 includes a titanium metal layer 143, an aluminum metal layer 144, a nickel metal layer 146, and a gold metal layer 147 arranged sequentially along the direction away from the substrate 11.

[0124] Specifically, when the source / drain functional section 14 includes a titanium metal layer 143, an aluminum metal layer 144, and a titanium nitride layer 145 sequentially disposed along a direction away from the substrate 11, the titanium metal layer 143 is patterned from the titanium material layer 16, the aluminum metal layer 144 is patterned from the aluminum material layer 17, and the titanium nitride layer 145 is patterned from the titanium nitride material layer 18. The titanium nitride material layer 18 has relatively stable properties and can protect the titanium material layer 16 and the aluminum material layer 17 during the annealing process, preventing the titanium material layer 16 and the aluminum material layer 17 from overflowing and causing contact between the source section 141 and the drain section 142, thereby causing leakage or even a short circuit, which helps to improve the yield and reliability of the semiconductor device 1. Since no gold material is used when forming the source / drain functional part 14, a gold-free ohmic contact can be formed with the barrier layer 13. Compared with the gold-containing ohmic contact, the material cost of the preparation method provided in this application is low, thereby reducing the manufacturing cost of the semiconductor device 1. It can also avoid the contact degradation problem caused by the easy diffusion of gold at high temperatures. In other words, the semiconductor device 1 prepared by the method provided in this application can manufacture a semiconductor device 1 with stronger stability, higher temperature resistance, and higher reliability.

[0125] In the above embodiments, the titanium metal layer 143 is formed by patterning the titanium material layer 16, the aluminum metal layer 144 is formed by patterning the aluminum material layer 17, the nickel metal layer 146 is formed by patterning the nickel material layer 24, and the gold metal layer 147 is formed by patterning the gold material layer 25.

[0126] In one feasible implementation, the ratio of nitrogen atoms to titanium atoms in the titanium nitride layer 145 ranges from 0.8 to 1.2.

[0127] In the above embodiments, the ratio of nitrogen atoms to titanium atoms in the titanium nitride layer 145 can be 1:1, and can fluctuate within the above range depending on the precision of the actual preparation process. When the ratio of nitrogen atoms to titanium atoms in the titanium nitride layer 145 is within the above range, its work function can be better matched with other metals in the source / drain functional section 14.

[0128] In the semiconductor device 1 provided in this application, such as Figure 17 and Figure 18 As shown, the barrier layer 13 also includes a receiving groove 132 or a receiving hole 131, with the source or drain located in the receiving groove or receiving hole.

[0129] In the semiconductor device 1 provided in this application, such as Figure 19 As shown, it also includes an isolation structure 21, which is disposed around the source / drain functional portion 14. The isolation structure 21 penetrates the barrier layer 13 along the thickness direction of the substrate 11 and penetrates at least a portion of the channel layer 12.

[0130] In one feasible implementation, such as Figure 20As shown, it also includes a cap layer 15, which is located on the side of the barrier layer 13 away from the channel layer 12, and the cap layer 15 is disposed around at least a portion of the source-drain functional section 14 in the circumferential direction.

[0131] In the above embodiments, by providing a cap layer 15 on the side of the barrier layer 13 away from the channel layer 12, it helps to reduce the current collapse effect, increase the barrier height, improve the electrostatic balance, increase the breakdown voltage, and modulate the surface electric field, thereby helping to improve the overall performance of the semiconductor device 1.

[0132] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A trench layer is formed on one side of the substrate; A barrier layer is formed on the side of the channel layer opposite to the substrate; A functional layer is formed on the surface of the barrier layer away from the channel layer, and the functional layer includes a hollow portion and a titanium nitride patterned portion. A source / drain material layer group is formed on the side surface of the functional layer opposite to the barrier layer, the source / drain material layer group including a titanium material layer in contact with the functional layer; The functional layer and the source / drain material layer group are patterned and annealed to form a source / drain functional part, which includes a source part and a drain part arranged at intervals.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of forming a functional layer on the surface of the barrier layer opposite to the channel layer includes: Titanium nitride particles are formed by sputtering to create the titanium nitride pattern, and the cutouts are formed between adjacent titanium nitride particles.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of forming a functional layer on the surface of the barrier layer opposite to the channel layer includes: A titanium nitride thin film layer is formed on the surface of the barrier layer opposite to the channel layer. A portion of the titanium nitride thin film layer is removed to form multiple cutouts, and a patterned titanium nitride pattern is formed.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The step of removing a portion of the titanium nitride thin film layer to form a plurality of cutouts includes: Atomic bombardment technology is used to remove a portion of the titanium nitride thin film layer to form multiple hollow sections.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, In the functional layer, the ratio of the area of ​​the titanium nitride patterned portion to the total area of ​​the functional layer ranges from 25% to 40%.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of forming a source / drain material layer assembly on the surface of the functional layer opposite to the barrier layer includes: A titanium material layer, an aluminum material layer, and a titanium nitride material layer are sequentially formed on the surface of the functional layer opposite to the barrier layer.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The titanium nitride material layer is formed by sputtering metallic titanium in a gas mixture of argon and nitrogen in a ratio of 40:

7.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of forming a source / drain material layer assembly on the surface of the functional layer opposite to the barrier layer includes: A titanium material layer, an aluminum material layer, a nickel material layer, and a gold material layer are sequentially formed on the surface of the functional layer opposite to the barrier layer.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of patterning the functional layer and the source / drain material layer group includes: A mask layer is formed on the surface of the barrier layer opposite to the channel layer. The mask layer includes a shielding region and an aperture region, the aperture region being used to form the source portion and the drain portion. The functional layer and the source / drain material layer group are sequentially formed on the side of the mask layer facing away from the substrate and the side of the barrier layer facing away from the substrate. Remove the mask layer and remove the portion of the functional layer and the source / drain material layer group located on the side of the mask layer opposite to the substrate.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The step of forming a mask layer on the surface of the barrier layer opposite to the channel layer, the mask layer including a shielding region and an aperture region, the aperture region being used to form the source and the drain, further includes: The areas of the barrier layer exposed through the aperture region are etched to form receiving holes or receiving grooves.

11. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of forming a barrier layer on the side of the channel layer opposite to the substrate further includes: A cap layer is formed on the side of the barrier layer opposite to the channel layer, and the cap layer is patterned to form an opening that penetrates the cap layer along its thickness direction. The opening is used to form the source or the drain.

12. A semiconductor device, characterized in that, It is prepared by the method of any one of claims 1-11.

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