Preparation method of field effect transistor

Abstract

The invention provides a preparation method of a field effect transistor, and relates to the technical field of semiconductor electronic devices. The epitaxial growth SrTiO3 thin film is used as the gate dielectric layer, the SrTiO3 thin film has the advantage of low roughness, PPC is used as the supporting layer to achieve transfer of the SrTiO3 thin film, introduction of residues in the preparation process can be reduced to a great extent, the surface of the SrTiO3 thin film is clean and flat, and after the two-dimensional layered semiconductor material serving as the channel material is deposited, the SrTiO3 thin film can be applied to the field of semiconductor devices. The interface between the SrTiO3 thin film and the two-dimensional material is effectively optimized, and the SrTiO3 thin film and the two-dimensional material form quasi Van der Waals contact, so that a high-quality gate dielectric and channel material interface can be obtained, and the performance of the device is greatly improved. Example results show that the field effect transistor prepared by the invention has a high switch ratio of 108, an ultra-low subthreshold swing of 69.2 mV / decand a field effect transistor mobility of 230cm < 2 > / (V.s).

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor electronic devices, and in particular to a method for preparing a field effect transistor. Background Art

[0002] Field effect transistors (FETs) are the cornerstone of modern electronic technology and have promoted technological progress in various electronic device-related fields. However, with the semiconductor industry's unremitting pursuit of device miniaturization, traditional silicon-based field effect transistors have encountered huge challenges, such as short channel effects, increased power consumption, and heat dissipation problems. Two-dimensional (2D) semiconductors with layered structures and atomic thickness as channel materials for field effect transistors can effectively cope with the challenges faced when miniaturizing devices. However, the overall performance of field effect transistors depends not only on the quality of the two-dimensional material, but also on the characteristics of the gate dielectric layer.

[0003] Since there are no dangling bonds on the surface of two-dimensional materials, it is very difficult to grow a gate dielectric layer (such as SrTiO3) directly on the two-dimensional material. The interface quality between the two-dimensional material and the gate dielectric will have a great impact on the overall performance of the device. In order to optimize the interface quality between the two-dimensional material and the gate dielectric, researchers have made many attempts, such as preparing devices by surface modification of the two-dimensional material, introducing a seed layer, and oxidizing the two-dimensional material layer by layer. However, these methods all have certain defects. For example, when modifying the surface of the two-dimensional material, defects may be introduced or damage may be caused to the surface of the material; only a very small number of two-dimensional materials can be oxidized to form oxides suitable as gate dielectric layers. How to further optimize the interface quality between the two-dimensional material and the gate dielectric, thereby improving the overall performance of the field effect transistor device, is still a technical problem that needs to be solved at present. Summary of the invention

[0004] In view of this, the object of the present invention is to provide a method for preparing a field effect transistor. The present invention realizes effective optimization of the interface between the SrTiO3 gate dielectric layer and the two-dimensional material, and prepares a high-performance field effect transistor.

[0005] In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions:

[0006] The present invention provides a method for preparing a field effect transistor, comprising the following steps:

[0007] Epitaxially growing a Sr4Al2O7 sacrificial layer and a SrTiO3 thin film layer on the surface of a single crystal SrTiO3 substrate in sequence, and spin-coating a polypropylene carbonate support layer on the surface of the SrTiO3 thin film layer to obtain a SrTiO3 substrate / Sr4Al2O7 / SrTiO3 / PPC composite layer structure;

[0008] Immersing the SrTiO3 substrate / Sr4Al2O7 / SrTiO3 / PPC composite layer structure in water to dissolve the Sr4Al2O7 sacrificial layer to obtain a SrTiO3 / PPC composite layer structure;

[0009] Transferring the SrTiO3 / PPC composite layer structure to an insulating substrate with a gate metal electrode so that the SrTiO3 thin film layer in the SrTiO3 / PPC composite layer structure covers the gate metal electrode, and then etching the polypropylene carbonate support layer to obtain an insulating substrate / gate metal electrode / SrTiO3 composite structure;

[0010] A two-dimensional layered semiconductor material layer is deposited on the surface of the SrTiO3 thin film layer of the insulating substrate / gate metal electrode / SrTiO3 composite structure, and a source metal electrode and a drain metal electrode are deposited on the surface of the two-dimensional layered semiconductor material layer to obtain the field effect transistor.

[0011] Preferably, the thickness of the Sr4Al2O7 sacrificial layer is 8-15 nm, and the thickness of the SrTiO3 thin film layer is 20-28 nm.

[0012] Preferably, the gate metal electrode comprises a stacked titanium electrode and a gold electrode, the thickness of the titanium electrode is 5-8 nm, the thickness of the gold electrode is 15-20 nm, and the titanium electrode is in contact with the insulating substrate.

[0013] Preferably, the insulating substrate is a silicon substrate whose surface is covered with silicon dioxide, and the thickness of the silicon dioxide is 285 nm.

[0014] Preferably, the etching agent used in the etching is an organic solvent.

[0015] Preferably, the two-dimensional layered semiconductor material in the two-dimensional layered semiconductor material layer is a transition metal chalcogenide.

[0016] Preferably, the transition metal chalcogenide comprises MoS2.

[0017] Preferably, the thickness of the two-dimensional layered semiconductor material layer is 1.4 to 3.5 nm.

[0018] Preferably, the source metal electrode and the drain metal electrode respectively include a stacked chromium electrode and a gold electrode, the thickness of the chromium electrode is 15-20 nm, the thickness of the gold electrode is 45-55 nm, and the chromium electrode is in contact with the two-dimensional layered semiconductor material layer.

[0019] Preferably, the channel width between the source metal electrode and the drain metal is 4-6 μm.

[0020] The present invention provides a method for preparing a field effect transistor. The present invention uses an epitaxially grown SrTiO3 film as a gate dielectric layer, which has the advantage of low roughness, and uses a polypropylene carbonate (PPC) material as a supporting layer to realize the transfer of the SrTiO3 film, which can greatly reduce the introduction of residues in the preparation process, so that the surface of the self-supporting SrTiO3 film is clean and flat. After depositing a two-dimensional layered semiconductor material as a channel material, the interface between the SrTiO3 film and the two-dimensional material is effectively optimized, and the SrTiO3 film forms a quasi-van der Waals contact with the two-dimensional material, so that a high-quality gate dielectric and channel material interface can be obtained, thereby greatly improving the device performance.

[0021] The results of the embodiment show that the present invention successfully prepared a high-performance field effect transistor, wherein the surface roughness of the self-supporting SrTiO3 film reached 269.27 pm, and the field effect transistor had a 10 8 High on / off ratio, ultra-low subthreshold swing of 69.2mV / dec and up to 230cm 2 / (V·s) field effect transistor mobility. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of the peeling and transfer of the self-supporting SrTiO3 film in the present invention, Figure 1 (a) is a schematic diagram of the film structure before peeling, (b) is a schematic diagram of the film peeling, and (c) is a schematic diagram of the structure after the film is transferred to the target substrate;

[0023] Figure 2 This is a schematic diagram of the field effect transistor structure of the present invention;

[0024] Figures 1-2 In the figure, 1-PPC support layer, 2-SrTiO3 thin film layer, 3-Sr4Al2O7 sacrificial layer, 4-single crystal SrTiO3 substrate, 5-gate metal electrode, 6-target substrate (insulating substrate), 7-source metal electrode, 8-drain metal electrode, 9-two-dimensional layered semiconductor material layer;

[0025] Figure 3 The morphology of the surface of the SrTiO3 thin film in Example 1 and the comparative example characterized by atomic force microscopy is shown in FIG. Figure 3 (a) corresponds to the corresponding example, and (b) corresponds to Example 1;

[0026] Figure 4 : are the transfer characteristic curves of the field effect transistors prepared in Example 1 and the comparative example, Figure 4 (a) corresponds to the comparative example, and (b) corresponds to Example 1. DETAILED DESCRIPTION

[0027] The present invention provides a method for preparing a field effect transistor, comprising the following steps:

[0028] Epitaxially growing a Sr4Al2O7 sacrificial layer and a SrTiO3 thin film layer on the surface of a single crystal SrTiO3 substrate in sequence, and spin-coating a polypropylene carbonate support layer on the surface of the SrTiO3 thin film layer to obtain a SrTiO3 substrate / Sr4Al2O7 / SrTiO3 / PPC composite layer structure;

[0029] Immersing the SrTiO3 substrate / Sr4Al2O7 / SrTiO3 / PPC composite layer structure in water to dissolve the Sr4Al2O7 sacrificial layer to obtain a SrTiO3 / PPC composite layer structure;

[0030] Transferring the SrTiO3 / PPC composite layer structure to an insulating substrate with a gate metal electrode so that the SrTiO3 thin film layer in the SrTiO3 / PPC composite layer structure covers the gate metal electrode, and then etching the polypropylene carbonate support layer to obtain an insulating substrate / gate metal electrode / SrTiO3 composite structure;

[0031] A two-dimensional layered semiconductor material layer is deposited on the surface of the SrTiO3 thin film layer of the insulating substrate / gate metal electrode / SrTiO3 composite structure, and a source metal electrode and a drain metal electrode are deposited on the surface of the two-dimensional layered semiconductor material layer to obtain the field effect transistor.

[0032] In the present invention, unless otherwise specified, all preparation raw materials / components are commercially available products well known to those skilled in the art.

[0033] The present invention sequentially epitaxially grows a Sr4Al2O7 sacrificial layer and a SrTiO3 thin film layer on the surface of a single crystal SrTiO3 substrate, and spin-coats a polypropylene carbonate support layer on the surface of the SrTiO3 thin film layer to obtain a SrTiO3 substrate / Sr4Al2O7 / SrTiO3 / PPC composite layer structure.

[0034] In the present invention, the single crystal SrTiO3 substrate is preferably (001) oriented, and the (001) oriented single crystal SrTiO3 substrate is conducive to the formation of epitaxial growth, ensuring the growth quality of the SrTiO3 film. In the present invention, the thickness of the Sr4Al2O7 sacrificial layer is preferably 8 to 15 nm, which can be 8, 10 or 15 nm; the thickness of the SrTiO3 thin film layer is preferably 20 to 28 nm, which can be 20, 21, 22, 23, 24, 25, 26, 27 or 28 nm. Based on the comprehensive consideration of the film stripping integrity and film performance, the present invention controls the thickness of the SrTiO3 thin film layer within the above range. SrTiO3 has high-k characteristics and can be used as an insulating layer. In the present invention, the Sr4Al2O7 sacrificial layer is an epitaxially grown water-soluble sacrificial layer. The lattice constant of Sr4Al2O7 is adjustable within a certain range and has a certain "flexibility", so that the SrTiO3 material can be better grown, and the stress introduced by lattice mismatch during the growth process can be reduced, so that the epitaxially grown high-quality SrTiO3 film can be completely peeled off from the substrate required for growth, which is compatible with the preparation process of two-dimensional material electronic devices; the epitaxially grown crystalline oxide Sr4Al2O7 has the advantage of low roughness.

[0035] In the present invention, the method for epitaxially growing the Sr4Al2O7 sacrificial layer and the SrTiO3 thin film layer is preferably a pulsed laser deposition method. The present invention has no special requirements on the process parameters of the pulsed laser deposition method. The process parameters well known in the art can be used to obtain the Sr4Al2O7 sacrificial layer and the SrTiO3 thin film layer that meet the thickness requirements.

[0036] The present invention has no special requirements for the thickness of the polypropylene carbonate (PPC) support layer. The present invention specifically dissolves polypropylene carbonate in a solvent, then spin-coats it on the surface of the SrTiO3 film layer, and obtains the polypropylene carbonate support layer after drying. The present invention has no special requirements for the polypropylene carbonate, and commercially available products well known in the art can be used. The present invention uses polypropylene carbonate material as a support layer, which has low adsorption to SrTiO3 material, can greatly reduce the impact caused by the residue of the support layer, and make the surface roughness of the SrTiO3 film less than 1nm. The present invention uses PPC as a support layer material to effectively improve the contact interface between the SrTiO3 film and the two-dimensional material, realize quasi-van der Waals contact, and greatly improve the device performance.

[0037] In the present invention, the SrTiO3 substrate / Sr4Al2O7 / SrTiO3 / PPC composite layer structure is as follows Figure 1 As shown in (a), from top to bottom are PPC support layer, SrTiO3 thin film layer, Sr4Al2O7 sacrificial layer, and single crystal SrTiO3 substrate.

[0038] After obtaining the SrTiO3 substrate / Sr4Al2O7 / SrTiO3 / PPC composite layer structure, the present invention immerses the SrTiO3 substrate / Sr4Al2O7 / SrTiO3 / PPC composite layer structure in water to dissolve the Sr4Al2O7 sacrificial layer to obtain the SrTiO3 / PPC composite layer structure.

[0039] In the present invention, the water is preferably ultrapure water. The Sr4Al2O7 sacrificial layer is completely etched by water dissolution, and the SrTiO3 thin film layer is separated from the SrTiO3 substrate to obtain a SrTiO3 thin film with a PPC support layer, that is, the SrTiO3 / PPC composite layer structure. Figure 1 As shown in (b).

[0040] After obtaining the SrTiO3 / PPC composite layer structure, the present invention transfers the SrTiO3 / PPC composite layer structure to an insulating substrate with a gate metal electrode, so that the SrTiO3 thin film layer in the SrTiO3 / PPC composite layer structure covers the gate metal electrode, and then etches the polypropylene carbonate support layer to obtain an insulating substrate / gate metal electrode / SrTiO3 composite structure.

[0041] In the present invention, the insulating substrate is preferably a silicon substrate with a surface covered with silicon dioxide, and the thickness of the silicon dioxide is preferably 285nm. In the present invention, the gate metal electrode (i.e., the metal bottom electrode) preferably includes a stacked titanium electrode and a gold electrode, the thickness of the titanium electrode is preferably 5-8nm, the thickness of the gold electrode is preferably 15-20nm, and the titanium electrode is in contact with the insulating substrate, specifically, in contact with the silicon dioxide surface of the insulating substrate. In the present invention, the method for preparing the insulating substrate with the gate metal electrode is preferably: using ultraviolet lithography to expose the electrode pattern; using a dual ion beam evaporation process to prepare a titanium electrode and a gold electrode on the silicon dioxide surface of the insulating substrate; stripping off excess metal film to obtain a gate metal electrode. The present invention has no special requirements for the process parameters of the dual ion beam evaporation process, and the process parameters well known in the art can be used to obtain titanium electrodes and gold electrodes that meet the thickness requirements.

[0042] In the present invention, the transfer method is preferably: float the SrTiO3 / PPC composite layer structure on the water surface, pick up the SrTiO3 / PPC composite layer structure with an insulating substrate with a gate metal electrode, the SrTiO3 / PPC composite layer structure is tightly attached to the insulating substrate with the gate metal electrode, and the SrTiO3 thin film layer covers the gate metal electrode. In the present invention, the structure after the transfer is as follows Figure 1 As shown in (c).

[0043] In the present invention, the etching agent used in the etching is preferably an organic solvent, and the organic solvent is preferably acetone. In the present invention, the sample obtained after the transfer is preferably completely dried before the etching. The polypropylene carbonate support layer is removed by the etching.

[0044] After obtaining the insulating substrate / gate metal electrode / SrTiO3 composite structure, the present invention deposits a two-dimensional layered semiconductor material layer on the surface of the SrTiO3 thin film layer of the insulating substrate / gate metal electrode / SrTiO3 composite structure, and deposits a source metal electrode and a drain metal electrode on the surface of the two-dimensional layered semiconductor material layer to obtain the field effect transistor.

[0045] In the present invention, the two-dimensional layered semiconductor material in the two-dimensional layered semiconductor material layer is preferably a transition metal chalcogenide, and the transition metal chalcogenide preferably includes MoS2; the thickness of the two-dimensional layered semiconductor material layer is preferably 1.4 to 3.5 nm, which can be 1.4, 2.1, 2.8 or 3.5 nm. In the present invention, the two-dimensional layered semiconductor material is used as the channel material of the field effect transistor, and the epitaxially grown self-supporting SrTiO3 film is used as the gate dielectric layer.

[0046] The present invention preferably uses mechanical exfoliation and fixed-point transfer to transfer the two-dimensional layered semiconductor material to the surface of the SrTiO3 film. The specific operation is preferably: mechanically exfoliating the two-dimensional layered semiconductor material with an adhesive tape to form a two-dimensional layered semiconductor nanosheet, and then transferring the two-dimensional layered semiconductor nanosheet to the surface of the SrTiO3 film. The present invention has no special requirements for the operation method of the transfer, and a transfer method familiar to those skilled in the art can be used.

[0047] In the present invention, the source metal electrode and the drain metal electrode preferably include a stacked chromium electrode and a gold electrode, respectively. The thickness of the chromium electrode is preferably 15 to 20 nm, and the thickness of the gold electrode is preferably 45 to 55 nm. The chromium electrode is in contact with the two-dimensional layered semiconductor material layer. The source metal electrode and the drain metal electrode may also overlap the SrTiO3 thin film layer, respectively. In the present invention, the channel width between the source metal electrode and the drain metal is preferably 4 to 6 μm, and may be 4, 5 or 6 μm.

[0048] In the present invention, the deposition method of the source metal electrode and the drain metal electrode is preferably: preparing the patterns of the source metal electrode and the drain metal electrode by electron beam exposure; preparing the chromium electrode and the gold electrode by thermal evaporation technology; and stripping off the excess metal film by a stripping method to obtain the source metal electrode and the drain metal electrode respectively.

[0049] In the present invention, the structure of the field effect transistor is as follows Figure 2As shown, the field effect transistor comprises, from bottom to top, an insulating substrate, a gate metal electrode, a self-supporting SrTiO3 film, a two-dimensional layered semiconductor material layer, and a source-drain metal electrode (i.e., a source metal electrode and a drain metal electrode).

[0050] The present invention uses crystalline oxide SrTiO3 as the gate dielectric layer material of the field effect transistor and a two-dimensional layered semiconductor material as the channel material. Crystalline oxide needs to grow on a specific substrate, and a strong covalent bond will be formed between the film and the substrate so that the film cannot be separated from the substrate required for growth. Therefore, it is difficult to integrate large-area crystalline oxides into the existing two-dimensional material device preparation process. The present invention can achieve the transfer of large-area high-quality oxide films by growing a sacrificial layer, so that it is not constrained by the substrate and avoids the formation of cracks in the oxide film during the peeling process. In addition, the self-supporting oxide film obtained in this way also has good flexibility and can be used to prepare flexible devices; the present invention uses PPC material as a supporting layer, which greatly reduces the introduction of residues in the preparation process, so that the surface of the self-supporting SrTiO3 film is clean and smooth, and a high-quality gate dielectric and channel material interface is obtained. The present invention combines the advantages of high-k materials, two-dimensional materials and epitaxial growth, and uses PPC materials as a supporting layer. The obtained epitaxial material, namely crystalline oxide (SrTiO3), has the advantage of low roughness and can form quasi-van der Waals contact with the two-dimensional material, thereby obtaining a high-quality interface, greatly improving device performance, and providing a new design idea for electronic devices using crystalline oxide as a gate dielectric.

[0051] In order to further illustrate the present invention, the method for preparing the field effect transistor provided by the present invention is described in detail below in conjunction with examples, but they should not be construed as limiting the protection scope of the present invention.

[0052] Example 1

[0053] The preparation steps of field effect transistor are as follows:

[0054] (1) Material growth

[0055] A pulsed laser deposition system was used to grow a Sr4Al2O7 sacrificial layer (10 nm thick) and a SrTiO3 thin film layer (23 nm thick) on a single crystal SrTiO3 substrate ((001) orientation).

[0056] (2) Substrate selection

[0057] A silicon substrate with 285 nm silicon dioxide on the surface was selected as the target substrate.

[0058] (3) Preparation of gate metal electrode

[0059] The electrode pattern is exposed by UV lithography; a 5nm titanium electrode and a 15nm gold electrode are prepared on the silicon dioxide surface of the substrate by dual ion beam evaporation; and the excess metal film is stripped off (only the UV lithography pattern is retained) by combining the stripping method to obtain the gate metal electrode.

[0060] (4) Transfer dielectric layer material

[0061] A PPC (polypropylene carbonate) support layer (structured as shown in Figure 2) was spin-coated on the sample on which the Sr4Al2O7 sacrificial layer and the SrTiO3 thin film layer were grown. Figure 1 The sample is immersed in water to completely dissolve the sacrificial layer (as shown in (a)). Figure 1 The SrTiO3 film with the PPC support layer floats on the water surface, and the SrTiO3 film with the PPC support layer is picked up by a target substrate with a gate metal electrode (as shown in FIG. Figure 1 As shown in (c), the SrTiO3 film covers the gate metal electrode; and the PPC supporting layer is removed with acetone.

[0062] (5) Preparation and transfer of transition metal chalcogenide MoS2 nanosheets

[0063] The transition metal sulfide compound MoS2 material is mechanically exfoliated with tape to form MoS2 nanosheets, which are then transferred to the self-supporting SrTiO3 film of step (4). The thickness of the MoS2 nanosheets is 2.8 nm.

[0064] (6) Preparation of source metal electrode and drain metal electrode

[0065] The source metal electrode and the drain metal electrode were patterned by electron beam exposure. The metal electrodes were prepared by thermal evaporation technology, with a chromium electrode thickness of 15 nm and a gold electrode thickness of 45 nm. The excess metal film was stripped off by stripping method to obtain the source metal electrode and the drain metal electrode, with a channel width of 5 μm. Finally, a field effect transistor was obtained, with a structure as shown in FIG. Figure 2 shown.

[0066] Film surface morphology characterization: The structure prepared in step (4) was placed on the atomic force microscope sample stage, and the morphology of the SrTiO3 film on the metal electrode was characterized in tapping mode to obtain the sample surface roughness. The results are as follows: Figure 3 As shown in (b), it can be seen that the surface roughness of the SrTiO3 film is 269.27 pm.

[0067] Electrical performance test:

[0068] Place the prepared field effect transistor device in the probe station, connect the source metal electrode and drain metal electrode of the sample to the two ends of the ammeter respectively, connect the gate of the sample to the source meter, and test the transfer characteristic curve of the device under different bias voltages. The results are as follows: Figure 4 The device has an on / off ratio of 10 8 The subthreshold swing is as low as 69.2mV / dec, and the field effect transistor mobility is 230cm 2 / (V·s), showing excellent electrical properties.

[0069] Comparative Example

[0070] The spin-coated PPC support layer in step (4) of Example 1 was replaced by a spin-coated PMMA (polymethyl methacrylate) support layer, and the rest was the same as Example 1 to obtain a field effect transistor.

[0071] Film surface morphology characterization: The structure prepared in step (4) of the comparative example was placed on the sample stage of an atomic force microscope, and the morphology of the SrTiO3 film on the metal electrode was characterized in the tapping mode to obtain the surface roughness of the sample. Figure 3 As shown in (a), the surface roughness of the SrTiO3 film is 2009 pm. The field effect transistor device prepared in the comparative example was tested for electrical properties in the same manner as in Example 1. The test results are shown in FIG. Figure 4 As shown in (a). The switching ratio of the device in comparative example 1 is 10 6 The subthreshold swing is as low as 202mV / dec, and the field effect transistor mobility is 20cm 2 / (V·s).

[0072] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A method for preparing a field effect transistor, characterized in that: The following steps are involved: Epitaxially growing a Sr4Al2O7 sacrificial layer and a SrTiO3 thin film layer on the surface of a single crystal SrTiO3 substrate in sequence, and spin-coating a polypropylene carbonate support layer on the surface of the SrTiO3 thin film layer to obtain a SrTiO3 substrate / Sr4Al2O7 / SrTiO3 / PPC composite layer structure; Immersing the SrTiO3 substrate / Sr4Al2O7 / SrTiO3 / PPC composite layer structure in water to dissolve the Sr4Al2O7 sacrificial layer to obtain a SrTiO3 / PPC composite layer structure; Transferring the SrTiO3 / PPC composite layer structure to an insulating substrate with a gate metal electrode so that the SrTiO3 thin film layer in the SrTiO3 / PPC composite layer structure covers the gate metal electrode, and then etching the polypropylene carbonate support layer to obtain an insulating substrate / gate metal electrode / SrTiO3 composite structure; A two-dimensional layered semiconductor material layer is deposited on the surface of the SrTiO3 thin film layer of the insulating substrate / gate metal electrode / SrTiO3 composite structure, and a source metal electrode and a drain metal electrode are deposited on the surface of the two-dimensional layered semiconductor material layer to obtain the field effect transistor.

2. The preparation method according to claim 1, characterized in that: The thickness of the Sr4Al2O7 sacrificial layer is 8-15 nm, and the thickness of the SrTiO3 thin film layer is 20-28 nm.

3. The preparation method according to claim 1, characterized in that: The gate metal electrode comprises a stacked titanium electrode and a gold electrode, the thickness of the titanium electrode is 5-8 nm, the thickness of the gold electrode is 15-20 nm, and the titanium electrode is in contact with an insulating substrate.

4. The preparation method according to claim 1 or 3, characterized in that: The insulating substrate is a silicon substrate whose surface is covered with silicon dioxide, and the thickness of the silicon dioxide is 285 nm.

5. The preparation method according to claim 1, characterized in that: The etching agent used in the etching is an organic solvent.

6. The preparation method according to claim 1, characterized in that: The two-dimensional layered semiconductor material in the two-dimensional layered semiconductor material layer is a transition metal chalcogenide.

7. The preparation method according to claim 6, characterized in that: The transition metal chalcogenide comprises MoS2.

8. The preparation method according to claim 1, 6 or 7, characterized in that: The thickness of the two-dimensional layered semiconductor material layer is 1.4 to 3.5 nm.

9. The preparation method according to claim 1, characterized in that: The source metal electrode and the drain metal electrode respectively include a stacked chromium electrode and a gold electrode, the thickness of the chromium electrode is 15-20 nm, the thickness of the gold electrode is 45-55 nm, and the chromium electrode is in contact with the two-dimensional layered semiconductor material layer.

10. The preparation method according to claim 1 or 9, characterized in that: The channel width between the source metal electrode and the drain metal is 4-6 μm.

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