A superjunction semiconductor structure and its fabrication method

Abstract

This invention provides a superjunction semiconductor structure and its fabrication method, relating to the field of semiconductor technology. The fabrication method includes the following steps: providing a substrate structure; forming a voltage-resistant region on one side of the substrate structure, the voltage-resistant region including a first voltage-resistant region and a second voltage-resistant region; forming a third voltage-resistant region on top of each second voltage-resistant region and a fourth voltage-resistant region on top of each first voltage-resistant region; wherein the third voltage-resistant region and the second voltage-resistant region have the same conductivity type, and the first voltage-resistant region and the fourth voltage-resistant region have the same conductivity type; forming a trench gate structure and a second base region on the side of each first voltage-resistant region away from the substrate structure; forming a first base region on the side of each second base region away from the substrate structure; the second base region and the first base region constitute a boss structure; forming a cutoff layer on the side of each second voltage-resistant region away from the substrate structure; a predetermined height difference exists between the cutoff layer and the boss structure. This invention can improve reverse recovery oscillation without affecting the device breakdown voltage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a superjunction semiconductor structure and its fabrication method. Background Technology

[0002] Superjunction MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices are an extremely important type of power switching device, with advantages such as low on-resistance and low switching losses, and are suitable for various full-bridge and / or half-bridge circuits.

[0003] Superjunction MOSFETs employ a superjunction structure in the breakdown region, consisting of alternating n-pillar and p-pillar regions arranged laterally within the breakdown region. When subjected to reverse bias, this superjunction structure generates a lateral electric field at the PN junction between the n-pillar and p-pillar regions. Before breakdown, the entire n-pillar and p-pillar regions are nearly completely depleted laterally, and the breakdown voltage of the device no longer depends on the doping concentration of the drift region. This reduces the contribution of bulk ionized impurities to the longitudinal electric field, thereby increasing the breakdown voltage of the device without affecting its specific on-resistance.

[0004] However, the superjunction structure significantly increases the PN junction area of ​​the body diode, resulting in more charge carriers being stored inside the device during forward injection, thus increasing the reverse recovery charge (Q). rr The voltage drop is significantly increased. In addition, because the n-pillar and p-pillar regions are rapidly depleted during the reverse recovery process, the reverse recovery of the body diode becomes hard, and the softness factor (S) becomes too small, which further leads to voltage overshoot and oscillation during the reverse recovery process, thereby causing device failure.

[0005] Therefore, there is an urgent need for a superjunction MOSFET device that can improve the number of non-equilibrium carriers in the body diode without affecting the device's breakdown voltage, while also improving the body diode's softness. Summary of the Invention

[0006] In view of this, the purpose of the present invention is to provide a superjunction semiconductor structure and its fabrication method, which can reduce the number of non-equilibrium carriers in the body diode without affecting the breakdown voltage of the device, while increasing the softness of the body diode, thereby improving reverse recovery oscillation.

[0007] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0008] In a first aspect, the present invention provides a method for preparing a superjunction semiconductor, comprising the following steps:

[0009] Provide a substrate structure;

[0010] A voltage withstand region is provided on one side of the substrate structure; the voltage withstand region includes alternating first voltage withstand region and second voltage withstand region; wherein, the first voltage withstand region and the second voltage withstand region have different conductivity types;

[0011] A third withstand voltage region is provided on top of each of the second withstand voltage regions; wherein, the third withstand voltage region has the same conductivity type as the second withstand voltage region;

[0012] A fourth withstand voltage region is provided on top of each of the first withstand voltage regions; wherein, the first withstand voltage region and the fourth withstand voltage region have the same conductivity type;

[0013] A trench gate structure and a second base region are provided on the side of each first withstand voltage region away from the substrate structure; wherein, the second base region is provided on both sides of the trench gate structure;

[0014] A first base region is provided on the side of each second base region away from the substrate structure; wherein, the second base region and the first base region form a boss structure, and the upper surface of the boss structure is flush with the upper surface of the groove gate structure.

[0015] A cutoff layer is provided on the side of each second withstand voltage region away from the substrate structure; wherein, there is a preset height difference between the cutoff layer and the boss structure;

[0016] The doping concentration in the third breakdown voltage region is lower than that in the second breakdown voltage region;

[0017] The doping concentration in the fourth breakdown voltage region is lower than that in the first breakdown voltage region.

[0018] Optionally, the doping concentration of the first breakdown voltage region is equal to the doping concentration of the second breakdown voltage region;

[0019] The doping concentration of the fourth breakdown voltage region is equal to that of the third breakdown voltage region.

[0020] Optionally, the thickness of the first pressure-resistant region is equal to the thickness of the second pressure-resistant region;

[0021] The thickness of the fourth pressure-resistant zone is equal to the thickness of the third pressure-resistant zone.

[0022] Optionally, an active Schottky contact conductor is provided on the side of the stop layer away from the substrate structure.

[0023] Optionally, the lateral and longitudinal surfaces of the first and second base regions are covered by source ohmic contact conductors.

[0024] Optionally, the doping concentration of the stop layer is lower than that of the second base region.

[0025] Optionally, the doping concentration of the stop layer is higher than that of the second breakdown voltage region.

[0026] Optionally, the ratio of the doping concentration of the second breakdown voltage region to that of the third breakdown voltage region is greater than or equal to 3.

[0027] Optionally, the ratio of the doping concentration of the first breakdown voltage region to that of the fourth breakdown voltage region is greater than or equal to 3.

[0028] In a second aspect, the present invention provides a superjunction semiconductor structure, comprising:

[0029] Substrate structure;

[0030] A breakdown voltage region located on one side of the substrate structure; the breakdown voltage region includes alternating first breakdown voltage regions and second breakdown voltage regions; wherein the first breakdown voltage region and the second breakdown voltage region have different conductivity types;

[0031] The third withstand voltage region is located at the top of each of the second withstand voltage regions; wherein, the third withstand voltage region has the same conductivity type as the second withstand voltage region;

[0032] The fourth withstand voltage region is located at the top of each of the first withstand voltage regions; wherein, the first withstand voltage regions and the fourth withstand voltage regions have the same conductivity type;

[0033] A trench gate structure and a second base region are located on the side of each first withstand voltage region away from the substrate structure; wherein, the second base region is disposed on both sides of the trench gate structure;

[0034] The first base region is located on the side of each second base region away from the substrate structure; wherein the second base region and the first base region form a boss structure, and the upper surface of the boss structure is flush with the upper surface of the trench gate structure.

[0035] A stop layer is located on the side of each second withstand voltage region away from the substrate structure; wherein, there is a preset height difference between the stop layer and the boss structure;

[0036] The doping concentration of the third withstand voltage region is lower than that of the second withstand voltage region; the doping concentration of the fourth withstand voltage region is lower than that of the first withstand voltage region.

[0037] The superjunction semiconductor structure and its preparation method provided in this invention have the following beneficial effects:

[0038] The superjunction semiconductor fabrication method of this invention includes the following steps: providing a substrate structure; setting a voltage-resistant region on one side of the substrate structure, the voltage-resistant region including a first voltage-resistant region and a second voltage-resistant region. Then, setting a third voltage-resistant region on top of each second voltage-resistant region, and simultaneously setting a fourth voltage-resistant region on top of each first voltage-resistant region; wherein the third voltage-resistant region and the second voltage-resistant region have the same conductivity type, and the first voltage-resistant region and the fourth voltage-resistant region have the same conductivity type. A trench gate structure and a second base region are set on the side of each first voltage-resistant region away from the substrate structure; the second base region is disposed on both sides of the trench gate structure. A first base region is set on the side of each second base region away from the substrate structure; wherein the second base region and the first base region constitute a boss structure, and the upper surface of the boss structure is flush with the upper surface of the trench gate structure. A cutoff layer is set on the side of each second voltage-resistant region away from the substrate structure; wherein there is a predetermined height difference between the cutoff layer and the boss structure. This method can reduce the number of non-equilibrium carriers in the body diode without affecting the device breakdown voltage, while increasing the softness of the body diode, thereby improving reverse recovery oscillation.

[0039] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0040] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A schematic flowchart of the superjunction semiconductor fabrication method provided by the present invention is shown;

[0042] Figure 2 A schematic diagram of the superjunction semiconductor structure provided by the present invention is shown;

[0043] Figure 3 A schematic diagram of the supersubstrate structure in this invention is shown;

[0044] Figure 4 A schematic diagram of the region where the first epitaxial layer is disposed and the corresponding ion implantation position is shown in this invention;

[0045] Figure 5 A schematic diagram of the region where the second epitaxial layer is disposed and the corresponding ion implantation position is shown in this invention;

[0046] Figure 6 A schematic diagram of the region where the third epitaxial layer is disposed and the corresponding ion implantation position is shown in this invention;

[0047] Figure 7 A schematic diagram showing the regions where the fourth to sixth epitaxial layers are disposed and the corresponding ion implantation positions in this invention is shown;

[0048] Figure 8 This diagram illustrates the superjunction pressure-resistant structure formed by thermal diffusion of the first to sixth epitaxial layers in this invention.

[0049] Figure 9 A schematic diagram of the area where the slotted gate structure is set in this invention is shown;

[0050] Figure 10 A schematic diagram of the second base region setting area in this invention is shown;

[0051] Figure 11 This diagram illustrates the regions where the first base region and source region are located in this invention.

[0052] Figure 12 A schematic diagram of the etched regions of the first base region and the second base region in this invention is shown;

[0053] Figure 13 A schematic diagram comparing the breakdown voltage of the present invention with that of a conventional superjunction MOSFET in the prior art is shown.

[0054] Figure 14 A schematic diagram comparing the reverse recovery current waveforms of the present invention with those of a conventional superjunction MOSFET in the prior art is shown.

[0055] Icons: 1-Drain conductor; 2-Gate conductor; 3-Source ohmic contact conductor; 4-Source Schottky contact conductor; 10-Substrate; 11-High-dose ion implantation source of the first conductivity type; 12-Low-dose ion implantation source of the first conductivity type; 20-Auxiliary layer; 21-High-dose ion implantation source of the second conductivity type; 22-Low-dose ion implantation source of the second conductivity type; 30-First breakdown voltage region; 31-Second breakdown voltage region; 32-Third breakdown voltage region; 33-Fourth breakdown voltage region; 40-Source region; 41-First base region; 42-Second base region; 43-Stop layer; 50-Gate structure; 51-Conductive polysilicon; 52-Gate oxide layer; 201-First epitaxial layer; 202-Second epitaxial layer; 203-Third epitaxial layer; 204-Fourth epitaxial layer; 205-Fifth epitaxial layer; 206-Sixth epitaxial layer. Detailed Implementation

[0056] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0057] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0058] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0059] For ease of understanding, some of the structural names in this invention will be explained below.

[0060] Substrate: A clean single-crystal wafer with specific crystal planes and appropriate electrical, optical and mechanical properties used for growing epitaxial layers.

[0061] Auxiliary layer: In this invention, it refers to an auxiliary layer of the first conductivity type, which is used to withstand an applied voltage of no more than 20% when the device is in a blocking state.

[0062] Doping concentration refers to the concentration of dopant added to a semiconductor material. Dopant is a small amount of impurity added to a semiconductor material to alter its electrical properties. Doping concentration is usually expressed in units of per centimeter ( / cm²). 3 The conductivity of a semiconductor is expressed as follows: when the doping concentration is low, the semiconductor's conductivity is poor. As the doping concentration increases, the semiconductor's conductivity gradually improves.

[0063] Ohmic contact: This refers to a contact between a metal and a semiconductor material where there is a pure resistance at the contact point. The lower the resistance, the better, so that during component operation, most of the voltage drop occurs in the active region rather than at the contact surface. Therefore, its I / O characteristic is linear; the steeper the slope, the lower the contact resistance. The magnitude of the contact resistance directly affects the device's performance specifications.

[0064] Source Ohmic Contact Conductor: When a metal and a semiconductor material come into contact, an ohmic contact is formed, and the metal conductor that serves as the source is called a source ohmic contact conductor.

[0065] Schottky contact: This refers to the contact between metal and semiconductor materials, where the energy bands of the semiconductor bend at the interface, forming a Schottky barrier. The presence of this barrier leads to a large interface resistance.

[0066] Source Schottky contact conductor: When a metal and a semiconductor material come into contact, a Schottky contact can be formed, and the metal conductor that serves as the source is called a source Schottky contact conductor.

[0067] Source region: In the basic structure of a superjunction semiconductor, two regions of the second conductivity type are created on the semiconductor material of the first conductivity type. One is called the source region of the MOSFET, and the other is called the drain region of the MOSFET.

[0068] Base region: Two closely spaced PN junctions are fabricated on a semiconductor substrate. The two PN junctions divide the entire semiconductor into three parts: the two outer parts are the emitter and collector regions, and the middle part is the base region.

[0069] As described in the background section, the alternating n-pillar and p-pillar regions in the lateral arrangement of the superjunction structure in the prior art significantly increase the PN junction area of ​​the body diode. This results in more charge carriers being stored inside the device during forward injection, leading to increased reverse recovery charge (Q0). rr The reverse recovery performance of the body diode increases significantly. Furthermore, the n-pillar and p-pillar regions are rapidly depleted during reverse recovery, resulting in a stiffer reverse recovery and a low softness factor (S). This further leads to voltage overshoot and oscillation during reverse recovery, ultimately causing device failure. Poor reverse recovery performance of the body diode is detrimental to device reliability and EMI (electromagnetic interference) immunity.

[0070] Based on this, a superjunction semiconductor structure and its fabrication method are provided, which can improve the number of non-equilibrium carriers in the body diode without affecting the breakdown voltage of the device, and at the same time improve the softness of the body diode.

[0071] The following is an exemplary description of the superjunction semiconductor fabrication method provided in this application:

[0072] As an optional implementation, please refer to Figure 1 , Figure 1 This diagram illustrates a step-by-step flowchart of a superjunction semiconductor fabrication method; the method includes the following steps:

[0073] S100 provides a substrate structure.

[0074] S200, a voltage withstand region is provided on one side based on the substrate structure; the voltage withstand region includes an alternately arranged first voltage withstand region and a second voltage withstand region.

[0075] The first and second withstand voltage regions have different conductivity types.

[0076] S300, a third pressure zone is set on top of each second pressure zone.

[0077] The third withstand voltage region has the same conductivity type as the second withstand voltage region.

[0078] S400, a fourth pressure zone is set on top of each first pressure zone.

[0079] The first and fourth withstand voltage regions have the same conductivity type.

[0080] S500, a trench gate structure and a second base region are provided on the side of each first withstand voltage region away from the substrate structure.

[0081] The second base region is located on both sides of the trench gate structure.

[0082] S600, a first base region is set on the side of each second base region that is away from the substrate structure.

[0083] The second base region and the first base region form a boss structure, and the upper surface of the boss structure is flush with the upper surface of the slot gate structure.

[0084] S700, a cutoff layer is provided on the side of each second withstand voltage region away from the substrate structure.

[0085] There is a preset height difference between the cut-off layer and the boss structure.

[0086] The doping concentration in the third withstand voltage region is lower than that in the second withstand voltage region; the doping concentration in the fourth withstand voltage region is lower than that in the first withstand voltage region.

[0087] Based on the above preparation method, please refer to Figure 2 , Figure 2A schematic diagram of a superjunction semiconductor structure is shown. The superjunction semiconductor structure includes: a substrate structure; a breakdown voltage region located on one side of the substrate structure; the breakdown voltage region includes alternating first breakdown voltage regions 30 and second breakdown voltage regions 31; wherein the first breakdown voltage regions 30 and second breakdown voltage regions 31 have different conductivity types; a third breakdown voltage region 32 located on top of each second breakdown voltage region 31; wherein the third breakdown voltage region 32 has the same conductivity type as the second breakdown voltage regions 31; and a fourth breakdown voltage region 33 located on top of each first breakdown voltage region 30; wherein the first breakdown voltage regions 30 and fourth breakdown voltage regions 33... The conductivity types are the same; a trench gate structure 50 and a second base region 42 are located on the side of each first withstand voltage region 30 away from the substrate structure; wherein the second base region 42 is disposed on both sides of the trench gate structure 50; a first base region 41 is located on the side of each second base region 42 away from the substrate structure; wherein the second base region 42 and the first base region 41 form a boss structure, and the upper surface of the boss structure is flush with the upper surface of the trench gate structure 50; a stop layer 43 is located on the side of each second withstand voltage region 31 away from the substrate structure; wherein there is a preset height difference between the stop layer 43 and the boss structure.

[0088] In this structure, a first voltage-resistant region 30 and a second voltage-resistant region 31 are arranged alternately on the substrate structure. The first voltage-resistant region 30 and the second voltage-resistant region 31 have different conductivity types to form a basic superjunction structure. On this basis, a fourth voltage-resistant region 33 is provided on the top of each first voltage-resistant region 30, and a third voltage-resistant region 32 is provided on the top of each second voltage-resistant region 31. The first voltage-resistant region 30 and the fourth voltage-resistant region 33 have the same conductivity type, and the third voltage-resistant region 32 and the second voltage-resistant region 31 have the same conductivity type. Taking the conductivity type of the first voltage-resistant region 30 as the first conductivity type and the conductivity type of the second voltage-resistant region 31 as the second conductivity type, the first voltage-resistant region 30 and the fourth voltage-resistant region 33 constitute a voltage-resistant region of the first conductivity type; the third voltage-resistant region 32 and the second voltage-resistant region 31 constitute a voltage-resistant region of the second conductivity type.

[0089] It should be noted that, in order to improve the reverse recovery softness and suppress reverse recovery oscillation, the doping concentration of the third breakdown voltage region is lower than that of the second breakdown voltage region in this embodiment; the doping concentration of the fourth breakdown voltage region is lower than that of the first breakdown voltage region. Based on this, the overall equivalent resistance of the third breakdown voltage region and the second breakdown voltage region can be increased, thereby increasing the resistance on the hole extraction path during the reverse recovery process of the body diode and slowing down the hole extraction speed during the reverse recovery process.

[0090] Meanwhile, since the structures of the first and second base regions are improved by setting the third and fourth breakdown regions, the superjunction breakdown structure can maintain overall and local charge balance, thereby ensuring that the breakdown voltage of the superjunction breakdown structure is not affected by the doping concentration of the first and second breakdown regions, the third breakdown region, and the fourth breakdown region. That is, taking the breakdown region of the second conductivity type formed by the third breakdown region 32 and the second breakdown region 31 as an example, in this embodiment, the ratio of the number of layers in the third breakdown region 32 to the number of layers in the second breakdown region 31 (i.e., the depth ratio of the two) and the ratio of their concentrations will not affect the breakdown voltage of the device.

[0091] In this embodiment, the substrate structure includes at least a substrate 10 and an auxiliary layer 20. The substrate 10 may be disposed on one side of the drain conductor 1, and the auxiliary layer 20 is disposed on the side of the substrate 10 away from the drain conductor 1.

[0092] Please continue to refer to Figure 2 When the second base region 42 and the first base region 41 are prepared, a boss structure with a certain height difference from the cut-off layer 43 is formed by the second base region 42, the first base region 41 and the groove gate structure 50, so that the top area of ​​the second withstand voltage region 31 forms a groove structure.

[0093] This invention improves the structure of the first breakdown voltage region 30, the second breakdown voltage region 31, the first base region 41, and the second base region 42. This reduces the hole injection efficiency on the source side when the semiconductor device (hereinafter referred to as the device) corresponding to the superjunction semiconductor structure is in reverse conduction, thereby reducing the reverse recovery charge during the reverse recovery stage. Furthermore, during the reverse recovery process of the body diode, it increases the resistance on the hole extraction path during reverse recovery, slowing down the hole extraction speed and thus improving reverse recovery softness and suppressing reverse recovery oscillations.

[0094] In this embodiment, when the first conductivity type is n-type doping, the second conductivity type is p-type doping. When the first conductivity type is p-type doping, the second conductivity type is n-type doping.

[0095] Please refer to Figure 3 In this embodiment, S100 provides a substrate structure, which includes a substrate 10 and an auxiliary layer 20 disposed on one side of the substrate 10. The auxiliary layer 20 can withstand an applied voltage of no more than 20% in the device blocking state. In one possible implementation, the auxiliary layer 20 is of a first conductivity type.

[0096] In this embodiment, the superjunction voltage-resistant structure (i.e., the voltage-resistant structure formed by thermal diffusion of the first voltage-resistant region 30, the second voltage-resistant region 31, the third voltage-resistant region 32, and the fourth voltage-resistant region 33) is formed through multiple epitaxial techniques and ion implantation techniques. This allows multiple epitaxial layers to be generated on the substrate structure, and then different doses of ion implantation sources are implanted into each epitaxial layer. Finally, thermal diffusion is performed on all epitaxial layers. When six epitaxial layers are included, please... Figure 3 Based on, refer to Figure 4 , Figure 5 , Figure 6 as well as Figure 7 ,in, Figure 4 A schematic diagram showing the region where the first epitaxial layer is disposed and the corresponding ion implantation position in the pressure-resistant structure of the present invention is shown; Figure 5 A schematic diagram showing the region where the second epitaxial layer is disposed and the corresponding ion implantation position in the pressure-resistant structure of the present invention is shown; Figure 6 A schematic diagram showing the region where the third epitaxial layer is disposed and the corresponding ion implantation position in the pressure-resistant structure of the present invention is shown; Figure 7 This diagram illustrates the regions where the fourth to sixth epitaxial layers are disposed and the corresponding ion implantation locations in the pressure-resistant structure of the present invention.

[0097] by Figure 4 For example, a first epitaxial layer 201 can be grown on the substrate structure first, and then a high-dose ion implantation source 11 of the first conductivity type and a high-dose ion implantation source 21 of the second conductivity type can be implanted on the first epitaxial layer 201.

[0098] Continue to refer to Figure 5 Then, a second epitaxial layer 202 is grown on the side of the first epitaxial layer 201 away from the substrate structure. Then, a high-dose ion implantation source 11 of the first conductivity type and a high-dose ion implantation source 21 of the second conductivity type are implanted on the second epitaxial layer 202. The implantation regions of the high-dose ion implantation source 11 of the first conductivity type and the high-dose ion implantation source 21 of the second conductivity type on the first epitaxial layer 201 and the second epitaxial layer 202 are arranged alternately.

[0099] Please continue to refer to the following. Figure 6 A third epitaxial layer 203 is grown on the side of the second epitaxial layer 202 away from the substrate structure, and a high-dose ion implantation source 21 of the second conductivity type, a high-dose ion implantation source 11 of the first conductivity type, a low-dose ion implantation source 12 of the first conductivity type, a high-dose ion implantation source 21 of the second conductivity type, and a low-dose ion implantation source 22 of the second conductivity type are implanted respectively, wherein the above ion implantation sources are implanted at the corresponding positions shown in the figure.

[0100] Please continue to refer to the following. Figure 7In this embodiment, the fourth epitaxial layer 204, the fifth epitaxial layer 205 and the sixth epitaxial layer 206 are injected according to the above injection method.

[0101] exist Figure 7 Based on this, please refer to Figure 8 By performing thermal diffusion on each epitaxial layer, the superjunction pressure-resistant structure in this embodiment can be formed. Figure 8 A schematic diagram of the superjunction withstand voltage structure of the present invention is shown. Based on this, the present invention can suppress lateral doping diffusion at the junction of the first withstand voltage region 30 and the second withstand voltage region 31, thereby ensuring the morphology of the final superjunction withstand voltage structure.

[0102] Based on this, the upper half of the superjunction voltage-resistant structure in this invention is composed of a fourth voltage-resistant region 33, a first voltage-resistant region 30, a second voltage-resistant region 31, and a third voltage-resistant region 32 in the lateral direction; the lower half of the superjunction voltage-resistant structure is composed of a first voltage-resistant region 30 and a second voltage-resistant region 31 in the lateral direction. The upper half of the superjunction voltage-resistant structure satisfies the charge balance condition, and the lower half of the superjunction structure also satisfies the charge balance condition. Based on this, the superjunction voltage-resistant structure maintains both overall charge balance and local charge balance.

[0103] In one possible implementation, to further improve the softness of the body diode and the number of non-equilibrium carriers, thereby enhancing reverse recovery softness and suppressing reverse recovery oscillations, the doping concentration of the first breakdown region 30 is equal to that of the second breakdown region 31; and the doping concentration of the fourth breakdown region 33 is equal to that of the third breakdown region 32.

[0104] Furthermore, the thickness of the first pressure-resistant region 30 is equal to the thickness of the second pressure-resistant region 31; the thickness of the fourth pressure-resistant region 33 is equal to the thickness of the third pressure-resistant region 32.

[0105] After preparing the pressure-resistant zone, please Figure 8 Based on, refer to Figure 9 , Figure 10 , Figure 9 This diagram shows the area where the slotted gate structure is located in this embodiment. Figure 10 This embodiment shows a schematic diagram of the second base region setting area; in this embodiment, a trench gate structure 50 and a second base region 42 are set on the side of each first withstand voltage region 30 away from the substrate structure. The second base region 42 is set on both sides of the trench gate structure 50. In this embodiment, a trench gate structure 50 is set on the side of each first withstand voltage region 30 away from the substrate structure.

[0106] by Figure 9For example, in one possible implementation, a trench can be formed by etching on top of the first withstand voltage region 30. A gate oxide layer 52 is formed by thermal oxidation, followed by deposition and etching of conductive polysilicon 51 to form a trench gate structure 50. Subsequently, with... Figure 10 For example, a second base region 42 can be formed at a first depth by ion implantation on top of the withstand voltage region, wherein the second base region 42 covers the top of the withstand voltage region (the side away from the substrate structure) and exposes the top of the trench gate structure 50 (the side away from the substrate structure).

[0107] exist Figure 10 Based on, refer to Figure 11 , Figure 12 , Figure 11 A schematic diagram showing the areas where the first base region and source region are set is shown. Figure 12 A schematic diagram of the etched areas of the first and second base regions is shown. In this embodiment, the first base region 41 is set on the side of each second base region 42 away from the substrate structure. To form a boss structure with the second base region 42 and the first base region 41, and to ensure that the height of the upper surface of the boss structure is consistent with the height of the upper surface of the trench gate structure 50, in one possible implementation, the first base region 41 and the source region 40 can be formed at a second depth on the second base region 42 by ion implantation, wherein the source region 40 is located around the trench gate structure 50. Then, the first base region 41 and the second base region 42 in the top region of the second withstand voltage region 31 are etched to form a trench structure. At this time, the top regions of the second withstand voltage region 31 and the third withstand voltage region 32 are re-exposed.

[0108] During the first etching process, in order to ensure that the top of the trench gate structure 50 (the side away from the substrate structure) is exposed, the etching depth can be equal to the second depth mentioned above.

[0109] Please continue to refer to this. Figure 12 In this embodiment, a cutoff layer 43 is also provided on the top surface of the second withstand voltage region 31 and the third withstand voltage region 32. In one possible implementation, the cutoff layer 43 is provided by ion implantation. The cutoff layer 43 is formed by implanting acceptor impurity ions such as boron ions.

[0110] In this embodiment, the doping concentration of the cutoff layer 43 is lower than that of the second base region 42 and / or higher than that of the second breakdown region 31. When the doping concentration of the cutoff layer 43 is lower than that of the second base region 42, the device operates in reverse conduction mode. Electrons can easily be injected from the first breakdown region 30 into the cutoff layer 43 and then collected by the Schottky contact conductor. This reduces the hole injection efficiency in reverse conduction mode, thereby reducing the reverse recovery charge Q of the body diode. rrWhen the doping concentration of the cutoff layer 43 is higher than that of the second breakdown voltage region 31, electrons can pass through the cutoff layer 43, thus preventing punch-through in the device.

[0111] When the doping concentration of the cutoff layer 43 is lower than that of the second base region 42 but higher than that of the second breakdown region 31, and the ratio of the doping concentration of the second breakdown region 31 to that of the third breakdown region 32 is greater than or equal to 3, the softness factor S of the reverse recovery can be significantly reduced, and the current oscillation and voltage oscillation of the reverse recovery process can be suppressed.

[0112] Continue to refer to Figure 12 It can be seen that there is a preset height difference between the stop layer 43 and the boss structure. That is, the first base region 41 and the second base region 42 form a groove structure in the top area of ​​the second pressure-resistant region 31. The upper surface of the stop layer 43 is flush with the lower surface of the first base region 41 and the second base region 42, or the value of the preset height difference can be equal to the sum of the thicknesses of the first base region 41 and the second base region 42. This structure can re-expose the upper surface areas of the second pressure-resistant region 31 and the third pressure-resistant region 32.

[0113] Subsequently Figure 12 Based on this, a source Schottky contact conductor 4, a gate conductor 2, and a source ohmic contact conductor 3 are respectively provided. In one possible implementation, the gate conductor 2 is provided on the surface of the slot gate structure 50. The source ohmic contact conductor 3 is provided on the surface of the source region 40 and the first base region 41 between the two slot gate structures 50. The gate conductor 2 and the source ohmic contact conductor 3 are not connected.

[0114] You can continue to refer to this. Figure 2 In this embodiment, when the first base region 41 and the second base region 42 form a groove structure at the top region of the second withstand voltage region 31, the longitudinal and transverse surfaces of the second base region 42 and the first base region 41 adjacent to the stop layer 43 are exposed. After the source ohmic contact conductor 3 is installed, the transverse and longitudinal surfaces of the first base region 41 and the second base region 42 are covered by the source ohmic contact conductor 3. This arrangement avoids affecting the function of the source ohmic contact conductor 3.

[0115] In this embodiment, the source Schottky contact conductor 4 includes metals such as aluminum, copper, or titanium. In one possible implementation, the source Schottky contact conductor 4 is deposited onto the surface of the stop layer 43. The source ohmic contact conductor 3 includes metals such as aluminum, copper, or titanium. The source ohmic contact conductor 3 is deposited onto the surfaces of the source region 40, the first base region 41, and the second base region 42.

[0116] In this embodiment, the substrate 10, auxiliary layer 20, and first withstand voltage region 30 are structures of the first conductivity type. The second withstand voltage region 31, stop layer 43, first base region 41, and second base region 42 are structures of the second conductivity type.

[0117] Please refer to Figure 13 , Figure 14 , Figure 13 A schematic diagram showing the breakdown voltage comparison between the superjunction semiconductor structure of the present invention (i.e., the superjunction MOSFET provided by the present invention in the figure) and the conventional superjunction MOSFET in the prior art is shown. Figure 14 The diagram shows a comparison of the reverse recovery current waveforms of the superjunction semiconductor structure (i.e., the superjunction MOSFET provided by the present invention shown in the figure) and the conventional superjunction MOSFET of the prior art. It can be seen that during the reverse recovery stage, the conventional superjunction semiconductor structure exhibits the following characteristics: the reverse recovery duration of the conventional superjunction semiconductor structure is longer, the peak reverse recovery current and reverse recovery charge are larger, and obvious current oscillations and voltage oscillations occur, which can cause device failure and are detrimental to the reliability of the device.

[0118] Compared to traditional superjunction semiconductor structures, the reverse recovery peak current of the superjunction semiconductor structure of this invention is reduced by 30%, the reverse recovery charge is reduced by 50%, and no current oscillation or voltage oscillation occurs, thus greatly improving the reverse recovery performance and reliability of the device.

[0119] In summary, the superjunction semiconductor structure and its fabrication method provided by this invention have the following characteristics: the doping concentration of the first and second breakdown voltage regions is equal, and the doping concentration of the fourth and third breakdown voltage regions is equal. The thicknesses of the first and second breakdown voltage regions are also equal, as are the thicknesses of the fourth and third breakdown voltage regions. This ensures that the upper and lower halves of the fabricated superjunction structure maintain charge balance, preventing the device's breakdown voltage from being affected. Furthermore, by using a lower doping concentration in the third breakdown voltage region compared to the second breakdown voltage region, the overall equivalent resistance of the third and second breakdown voltage regions increases. During the reverse recovery process of the body diode, this increases the resistance along the hole extraction path, slowing down the hole extraction speed and thus improving reverse recovery softness and suppressing reverse recovery oscillations. Meanwhile, the doping concentration of the cutoff layer is lower than that of the second base region. When the device is in reverse conduction mode, electrons can be easily injected from the first breakdown voltage region into the cutoff layer and then collected by the Schottky contact conductor. This can reduce the hole injection efficiency of the device in reverse conduction mode, thereby reducing the reverse recovery charge of the body diode.

[0120] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0121] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0122] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method of fabricating a super junction semiconductor, comprising: Comprising: providing a substrate structure; providing a voltage withstanding region based on one side of the substrate structure; the voltage withstanding region comprises first voltage withstanding regions and second voltage withstanding regions arranged alternately; wherein the first voltage withstanding regions and the second voltage withstanding regions are different in conductive type; providing a third voltage withstanding region on top of each of the second voltage withstanding regions; wherein the third voltage withstanding region and the second voltage withstanding region are the same in conductive type; providing a fourth voltage withstanding region on top of each of the first voltage withstanding regions; wherein the first voltage withstanding region and the fourth voltage withstanding region are the same in conductive type; providing a trench gate structure and a second base region based on each of the first voltage withstanding regions away from one side of the substrate structure; wherein the second base region is provided on both sides of the trench gate structure; providing a first base region based on each of the second base regions away from one side of the substrate structure; wherein the second base region and the first base region form a mesa structure; the upper surface of the mesa structure is flush with the upper surface of the trench gate structure; providing a cutoff layer based on each of the second voltage withstanding regions away from one side of the substrate structure; wherein there is a preset height difference between the cutoff layer and the mesa structure; the doping concentration of the third voltage withstanding region is lower than the doping concentration of the second voltage withstanding region; the doping concentration of the fourth voltage withstanding region is lower than the doping concentration of the first voltage withstanding region.

2. The super-junction semiconductor preparation method according to claim 1, wherein: the doping concentration of the first voltage withstanding region is equal to the doping concentration of the second voltage withstanding region; the doping concentration of the fourth voltage withstanding region is equal to the doping concentration of the third voltage withstanding region.

3. The super-junction semiconductor preparation method according to claim 1, wherein: the thickness of the first voltage withstanding region is equal to the thickness of the second voltage withstanding region; the thickness of the fourth voltage withstanding region is equal to the thickness of the third voltage withstanding region.

4. The super junction semiconductor fabrication method of claim 1, wherein a source Schottky contact conductor is provided on the side of the cutoff layer away from the substrate structure.

5. The super junction semiconductor fabrication method of claim 1, wherein the lateral surface and the longitudinal surface of the first base region and the second base region are covered by a source ohmic contact conductor.

6. The super junction semiconductor fabrication method of claim 1, wherein, the doping concentration of the cutoff layer is lower than the doping concentration of the second base region.

7. The super junction semiconductor fabrication method of claim 1 wherein, the doping concentration of the cutoff layer is higher than the doping concentration of the second voltage withstanding region.

8. The super junction semiconductor fabrication method of claim 1 wherein, the ratio of the doping concentration of the second voltage withstanding region to the third voltage withstanding region is greater than or equal to 3.

9. The super-junction semiconductor preparation method according to claim 1, wherein: the ratio of the doping concentration of the first voltage withstanding region to the fourth voltage withstanding region is greater than or equal to 3.

10. A super junction semiconductor structure, comprising: Comprising: a substrate structure; a voltage withstanding region located on one side of the substrate structure; the voltage withstanding region comprises first voltage withstanding regions and second voltage withstanding regions arranged alternately; wherein the first voltage withstanding regions and the second voltage withstanding regions are different in conductive type; a third voltage withstanding region located on top of each of the second voltage withstanding regions; wherein the third voltage withstanding region and the second voltage withstanding region are the same in conductive type; a fourth voltage withstanding region located on top of each of the first voltage withstanding regions; wherein the first voltage withstanding region and the fourth voltage withstanding region are the same in conductive type; a trench gate structure and a second base region located on one side of each of the first voltage withstanding regions away from the substrate structure; wherein the second base region is provided on both sides of the trench gate structure; A first base region located on a side of each of the second base regions away from the substrate structure; wherein the second base regions and the first base regions form a mesa structure, and an upper surface of the mesa structure is flush with an upper surface of the trench gate structure; A cutoff layer located on a side of each of the second withstand voltage regions away from the substrate structure; wherein a preset height difference exists between the cutoff layer and the mesa structure; The doping concentration of the third withstand voltage region is lower than the doping concentration of the second withstand voltage region. The doping concentration of the fourth withstand voltage region is lower than the doping concentration of the first withstand voltage region.

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