Semiconductor device and preparation method thereof, chip and electronic equipment

Abstract

The invention provides a semiconductor device and a preparation method thereof, a chip and electronic equipment, relates to the technical field of semiconductors, and aims to improve the performance of the semiconductor device. The semiconductor device includes a substrate, a first cap layer, a second cap layer, a first gate, a second gate, a first electrode, and a second electrode. The first cap layer and the second cap layer are arranged on one side of the substrate and arranged in a spaced mode in the first direction, and the first direction is parallel to the substrate. At least one of the first cap layer and the second cap layer comprises a first sub-layer and a second sub-layer, and the first sub-layer is arranged on one side of the second sub-layer in the first direction. A thickness of the first sub-layer is greater than a thickness of the second sub-layer. The first gate is arranged on one side of the first cap layer away from the substrate, and the second gate is arranged on one side of the second cap layer away from the substrate. The first electrode and the second electrode are arranged on the two opposite sides of the structure formed by the first cap layer and the second cap layer in the first direction. The semiconductor device is applied to a chip.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a chip, and an electronic device. Background Art

[0002] Gallium nitride (GaN) semiconductor materials are called third-generation semiconductor materials. Compared with first-generation semiconductor materials represented by silicon, they have higher bandgap width, critical breakdown field strength, and electron saturation drift velocity. They have significant advantages in high frequency, high voltage resistance, high power, and low on-resistance, and can be used as core devices in various power conversion systems.

[0003] Gallium nitride (GaN)-based high-electron-mobility transistors (HEMTs) are widely used as power amplifier devices in electronic devices. Summary of the invention

[0004] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, a chip, and an electronic device, aiming to improve the performance of the semiconductor device and increase the service life of the semiconductor device.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] On the one hand, a semiconductor device is provided. The semiconductor device includes a substrate, a first cap layer, a second cap layer, a first gate, a second gate, a first electrode, and a second electrode. The first cap layer and the second cap layer are arranged on one side of the substrate and are arranged at intervals along a first direction, and the first direction is parallel to the substrate. At least one of the first cap layer and the second cap layer includes a first sublayer and a second sublayer, and along the first direction, the first sublayer is arranged on one side of the second sublayer. The thickness of the first sublayer is greater than the thickness of the second sublayer. The first gate is arranged on a side of the first cap layer away from the substrate, and the second gate is arranged on a side of the second cap layer away from the substrate. At least one of the first gate and the second gate is arranged on a side of the first sublayer away from the substrate. The first electrode and the second electrode are arranged on opposite sides of the structure composed of the first cap layer and the second cap layer along the first direction.

[0007] At least one of the first cap layer and the second cap layer in the semiconductor device provided by the above-mentioned embodiment of the present disclosure includes a first sublayer and a second sublayer, and the thickness of the first sublayer is greater than the thickness of the second sublayer. On the one hand, when the semiconductor device is turned on, the first sublayer and the second sublayer can both inject holes toward the side close to the substrate, which is beneficial to improving the range of hole injection and the efficiency of hole injection. The holes will neutralize the negative charge centers in the semiconductor device (for example, the negative charge centers in the buffer layer in the semiconductor device), which can reduce the repulsive effect of the negative charge centers on the two-dimensional electron gas in the semiconductor device, thereby suppressing the degradation of the dynamic on-resistance of the semiconductor device, which is beneficial to reducing the energy loss of the semiconductor device during the switching process.

[0008] On the other hand, when the first capping layer includes a first sublayer and a second sublayer, and the first gate located on the side of the first capping layer away from the substrate is in a forward voltage bias (Forward Voltage Bias) state, the first gate can induce more two-dimensional electron gas in the semiconductor device through the second sublayer, which is beneficial to increase the concentration of the two-dimensional electron gas in the semiconductor device, and then help reduce the on-resistance of the semiconductor device, thereby helping to reduce the energy loss of the semiconductor device when it is in the on state.

[0009] When the second capping layer includes a first sublayer and a second sublayer, and the second gate located on a side of the second capping layer away from the substrate is in a forward voltage bias state, the second gate can induce more two-dimensional electron gas in the semiconductor device through the second sublayer, which is beneficial to increase the concentration of the two-dimensional electron gas in the semiconductor device, and then help reduce the on-resistance of the semiconductor device, thereby helping to reduce the energy loss of the semiconductor device in the on state.

[0010] On the other hand, when the first cap layer and the second cap layer are both arranged on the side of the barrier layer in the semiconductor device away from the substrate, and there are surface traps in the barrier layer, the second sublayer in the first cap layer and / or the second sublayer in the second cap layer can shield the surface traps in the barrier layer, thereby weakening the capture effect of the surface traps in the barrier layer on electrons, thereby suppressing the current collapse effect caused by the capture of electrons by the surface traps in the barrier layer, which is beneficial to improving the performance of the semiconductor device.

[0011] On the other hand, when the first gate in the semiconductor device is in a reverse voltage bias state, the second gate is in a forward voltage bias state, and the voltage at the first electrode is less than the voltage at the second electrode, and the voltage between the first gate and the second electrode is less than the threshold voltage of the semiconductor device, the current in the semiconductor device is cut off. By making the first cap layer include the first sublayer and the second sublayer, and the thickness of the first sublayer is greater than the thickness of the second sublayer, that is, the thickness of the second sublayer is smaller, when the voltage at the second electrode is larger, it is beneficial for the second sublayer to deplete the holes inside it under the action of the electric field, and then a hole depletion region can be formed in the region where the second sublayer in the first cap layer is located, which is beneficial to improving the withstand voltage capability of the semiconductor device, and can reduce the probability of the semiconductor device being broken down, and thus is beneficial to improving the service life of the semiconductor device.

[0012] When the first gate in the semiconductor device is in a forward voltage bias state, the second gate is in a reverse voltage bias state, and the voltage at the first electrode is greater than the voltage at the second electrode, and the voltage between the second gate and the first electrode is less than the threshold voltage of the semiconductor device, the current in the semiconductor device is cut off. By making the second cap layer include a first sublayer and a second sublayer, and the thickness of the first sublayer is greater than the thickness of the second sublayer, that is, the thickness of the second sublayer is smaller, when the voltage at the first electrode is larger, it is beneficial for the second sublayer to deplete the holes inside it under the action of the electric field, and then a hole depletion region can be formed in the area where the second sublayer is located in the second cap layer, which is beneficial to improving the voltage resistance of the semiconductor device, and can reduce the probability of the semiconductor device being broken down, and thus is beneficial to improving the service life of the semiconductor device.

[0013] In some embodiments, the first capping layer and the second capping layer each include a first sub-layer and a second sub-layer. The second sub-layer is closer to the spacing region between the first capping layer and the second capping layer than the first sub-layer.

[0014] In some embodiments, a size of the first sublayer along the first direction is smaller than a size of the second sublayer along the first direction.

[0015] In some embodiments, the second sub-layer has a uniform thickness.

[0016] In some embodiments, at least two regions within the second sub-layer have different thicknesses.

[0017] In some embodiments, along the first direction, the thickness of the second sub-layer gradually decreases.

[0018] In some embodiments, the first capping layer includes a first sublayer and a second sublayer, and in the first capping layer, the thickness of the second sublayer on a side close to the first sublayer is less than the thickness of the second sublayer on a side away from the first sublayer. And / or, the second capping layer includes a first sublayer and a second sublayer, and in the second capping layer, the thickness of the second sublayer on a side close to the first sublayer is less than the thickness of the second sublayer on a side away from the first sublayer.

[0019] In some embodiments, the first capping layer includes a first sublayer and a second sublayer, and in the first capping layer, the thickness of the second sublayer on a side close to the first sublayer is greater than the thickness of the second sublayer on a side away from the first sublayer. And / or, the second capping layer includes a first sublayer and a second sublayer, and in the second capping layer, the thickness of the second sublayer on a side close to the first sublayer is greater than the thickness of the second sublayer on a side away from the first sublayer.

[0020] In some embodiments, a surface of the second sub-layer away from the substrate is arranged in a stepped manner.

[0021] In some embodiments, a surface of the second sub-layer away from the substrate is inclined.

[0022] In some embodiments, at least one of the first capping layer and the second capping layer further includes a third sublayer. The third sublayer is located on a side of the first sublayer away from the second sublayer.

[0023] In another aspect, a method for preparing a semiconductor device is provided. The method for preparing a semiconductor device comprises the following steps:

[0024] A first capping layer and a second capping layer are formed on one side of the substrate. The first capping layer and the second capping layer are spaced apart along a first direction, and the first direction is parallel to the substrate. At least one of the first capping layer and the second capping layer includes a first sublayer and a second sublayer, and along the first direction, the first sublayer is arranged on one side of the second sublayer. The thickness of the first sublayer is greater than the thickness of the second sublayer.

[0025] A first electrode and a second electrode are formed. The first electrode and the second electrode are arranged along a first direction on opposite sides of a structure composed of the first cap layer and the second cap layer.

[0026] A first gate is formed on a side of the first cap layer away from the substrate, and a second gate is formed on a side of the second cap layer away from the substrate. At least one of the first gate and the second gate is disposed on a side of the first sub-layer away from the substrate.

[0027] In some embodiments, forming a first capping layer and a second capping layer on one side of a substrate comprises the following steps:

[0028] An initial capping layer is formed on one side of the substrate.

[0029] Part of the initial capping layer is thinned to form a transitional capping layer.

[0030] The transition cap layer in a partial area is removed to form a first cap layer and a second cap layer respectively.

[0031] In another aspect, a chip is provided, comprising the semiconductor device according to any one of the above embodiments.

[0032] In another aspect, an electronic device is provided. The electronic device comprises a circuit board and a chip as described in the above embodiment. The chip and the circuit board are electrically connected.

[0033] It can be understood that the beneficial effects that can be achieved by the semiconductor device manufacturing method, chip and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor device mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for use in some embodiments of the present disclosure are briefly introduced below.

[0035] Figure 1 is a schematic structural diagram of an electronic device according to some embodiments;

[0036] Figure 2 is a cross-sectional schematic diagram of a chip according to some embodiments;

[0037] Figure 3 FIG. 1 is a cross-sectional view of a semiconductor device according to some embodiments. Figure 1 ;

[0038] Figure 4A A cross-sectional view of a semiconductor device according to some embodiments Figure 2 ;

[0039] Figure 4B A cross-sectional view of a semiconductor device according to some embodiments Figure 3 ;

[0040] Figure 5A FIG4 is a schematic cross-sectional view of a semiconductor device according to some embodiments;

[0041] Figure 5B FIG5 is a cross-sectional schematic diagram of a semiconductor device according to some embodiments;

[0042] Figure 6 FIG. 1 is a cross-sectional view of a semiconductor device according to some embodiments. Figure 6 ;

[0043] Figure 7 FIG. 1 is a cross-sectional view of a semiconductor device according to some embodiments. Figure 7 ;

[0044] Figure 8 FIG. 1 is a cross-sectional view of a semiconductor device according to some embodiments. Figure 8 ;

[0045] Fig. 9 FIG. 1 is a cross-sectional view of a semiconductor device according to some embodiments. Figure 9 ;

[0046] Fig.10 FIG. 1 is a cross-sectional view of a semiconductor device according to some embodiments. Figure 10 ;

[0047] Fig.11 FIG. 1 is a cross-sectional view of a semiconductor device according to some embodiments. Figure 10 one;

[0048] Fig.12 FIG. 1 is a cross-sectional view of a semiconductor device according to some embodiments. Figure 10 two;

[0049] Fig.13 FIG. 1 is a cross-sectional view of a semiconductor device according to some embodiments. Figure 10 three;

[0050] Fig.14 FIG. 1 is a cross-sectional view of a semiconductor device according to some embodiments. Figure 10 Four;

[0051] Fig.15 is a flow chart of a method for preparing a semiconductor device according to some embodiments;

[0052] Fig.16 for Fig.15 The structure of the semiconductor device corresponding to step S1 in the flowchart of the method for preparing the semiconductor device in FIG. Figure 1 ;

[0053] Fig.17 for Fig.15 The structure of the semiconductor device corresponding to step S1 in the flowchart of the method for preparing the semiconductor device in FIG. Figure 2 ;

[0054] Fig.18 for Fig.15 A schematic structural diagram of a semiconductor device corresponding to step S2 in the flowchart of the method for preparing a semiconductor device in FIG. 1 ;

[0055] Fig.19 for Fig.15 A schematic structural diagram of the semiconductor device corresponding to step S3 in the flowchart of the method for preparing the semiconductor device in FIG. DETAILED DESCRIPTION

[0056] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0057] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0058] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0059] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0060] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0061] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0062] The words "exemplarily" or "for example" are used herein to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplarily" or "for example" should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts in a specific way.

[0063] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0064] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0065] For the convenience of the following description, an XYZ coordinate system is established. The third direction Z is the thickness direction of the substrate, the XY plane is perpendicular to the third direction Z, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0066] like Figure 1 As shown, an embodiment of the present application provides an electronic device 1000. The electronic device 1000 may include a power supply device (e.g., a power adapter, etc.), a communication device (e.g., a satellite communication device, a wireless television receiver, etc.), a radar device (e.g., a millimeter wave radar, a weather radar, etc.), a radio navigation device (e.g., a GPS receiver, etc.), and other devices. The embodiment of the present application does not impose any special restrictions on the specific form of the above-mentioned electronic device 1000.

[0067] In some embodiments, please refer to Figure 1 , the electronic device 1000 includes a chip 100 and a circuit board 200. The chip 100 and the circuit board 200 are electrically connected.

[0068] Exemplarily, the circuit board 200 in the electronic device 1000 may include at least one of a printed circuit board (PCB) and an on-chip integrated circuit (On-Chip IC).

[0069] For example, the circuit board 200 in the electronic device 1000 may include a plurality of conductive layers. The plurality of conductive layers in the circuit board 200 may be separated from each other by a dielectric layer.

[0070] The chip 100 is described in detail below.

[0071] In some embodiments, Figure 2 As shown, Figure 2 FIG. 1 is a schematic cross-sectional view of a chip 100 according to some embodiments. The chip 100 includes a semiconductor device 10 .

[0072] Exemplarily, the chip 100 may include a processor chip. For example, the processor chip may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0073] The semiconductor device 10 described above will be described in detail below.

[0074] In some embodiments, please refer to Figure 2 , a semiconductor device 10 may include a substrate 1 .

[0075] By way of example, the material of the substrate 1 in the semiconductor device 10 may include one or more (or more than two) of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), sapphire, diamond, and the like.

[0076] In some embodiments, please refer to Figure 2 The semiconductor device 10 may further include a nucleation layer 5 . The nucleation layer 5 may be disposed on one side of the substrate 1 .

[0077] By way of example, the material of the nucleation layer 5 in the semiconductor device 10 may include one or more of aluminum nitride (AlN), GaN, and aluminum gallium nitride (AlGaN).

[0078] In some embodiments, please refer to Figure 2 The semiconductor device 10 may further include a buffer layer 2. The buffer layer 2 may be disposed on one side of the substrate 1.

[0079] For example, the material of the buffer layer 2 in the semiconductor device 10 may include a plurality of nitride Al x Iny Ga (1-x-y) One or more (greater than or equal to two) of N, (0≤x, y≤1).

[0080] For example, the material of the buffer layer 2 in the semiconductor device 10 may include GaN.

[0081] When the material of the buffer layer 2 in the semiconductor device 10 includes GaN, the material of the buffer layer 2 may be doped with carbon (C), that is, the material of the buffer layer 2 may include carbon-doped GaN.

[0082] The doping concentration of carbon in the material of the buffer layer 2 may be greater than or equal to 1e19 cm -3 , and less than or equal to 1e20 cm -3 .

[0083] For another example, the material of the buffer layer 2 in the semiconductor device 10 may include a superlattice structure formed by one or more of AlN, GaN, and AlGaN.

[0084] For example, the buffer layer 2 in the semiconductor device 10 can be formed by a process such as a metal-organic chemical vapor deposition (MOCVD) process, a molecular beam epitaxy (MBE) process or a physical vapor deposition (PVD) process.

[0085] For example, please refer to Figure 2 In the case where the semiconductor device 10 includes a nucleation layer 5 , the buffer layer 2 may be disposed on a side of the nucleation layer 5 away from the substrate 1 .

[0086] In some embodiments, please refer to Figure 2 The semiconductor device 10 may further include a channel layer 3 . The channel layer 3 may be disposed on one side of the substrate 1 .

[0087] For example, please refer to Figure 2 In the case where the semiconductor device 10 includes a buffer layer 2 , the channel layer 3 in the semiconductor device 10 may be disposed on a side of the buffer layer 2 away from the substrate 1 .

[0088] By way of example, the material of the channel layer 3 in the semiconductor device 10 may include GaN.

[0089] For example, the channel layer 3 in the semiconductor device 10 may be formed by a metal organic chemical vapor deposition process, a molecular beam epitaxy process, a physical vapor deposition process or the like.

[0090] In some embodiments, with continued reference to Figure 2 , the semiconductor device 10 may further include a barrier layer 4. The barrier layer 4 may be disposed on one side of the substrate 1 within the semiconductor device 10.

[0091] Exemplarily, the material of the barrier layer 4 within the semiconductor device 10 may include nitrides Al x In y Ga (1-x-y) N, (0 < x ≤ 1, 0 ≤ y ≤ 1) or one or more of them.

[0092] Exemplarily, the barrier layer 4 within the semiconductor device 10 may be formed by processes such as metalorganic chemical vapor deposition process, molecular beam epitaxy process, or physical vapor deposition process.

[0093] Exemplarily, with continued reference to Figure 2 , the barrier layer 4 within the semiconductor device 10 may be disposed on the side of the channel layer 3 away from the substrate 1. That is, the channel layer 3 may be disposed between the barrier layer 4 and the substrate 1.

[0094] When the barrier layer 4 within the semiconductor device 10 is disposed on the side of the channel layer 3 away from the substrate 1, and the band gap of the material of the barrier layer 4 (e.g., AlGaN) is greater than the band gap of the material of the channel layer 3 (e.g., GaN), due to the different electron affinities and work functions of the materials of the barrier layer 4 and the channel layer 3, a heterojunction structure will be formed at the interface between the barrier layer 4 and the channel layer 3. This heterojunction structure will cause the energy band structure of the channel layer 3 to bend, and then a potential well will be formed in the channel layer 3. In order to balance the charge distribution at the interface between the barrier layer 4 and the channel layer 3, the electrons in the barrier layer 4 will transfer to the potential well in the channel layer 3. The potential well in the channel layer 3 can restrict the electrons, enabling the electrons to move freely only in the direction parallel to the interface between the barrier layer 4 and the channel layer 3, thereby inducing the formation of a two-dimensional electron gas (2DEG) near the interface between the barrier layer 4 and the channel layer 3, which is beneficial to improving the electron mobility and enhancing the performance of the semiconductor device 10.

[0095] The above-mentioned band gap refers to: In a solid, the electron energy cannot take continuous values but forms some discontinuous energy bands, and the energy difference between the conduction band and the valence band is the band gap. Specifically, for a bound electron to become a free electron or a hole, it must obtain sufficient energy to transition from the valence band to the conduction band, and the minimum value of this energy is the band gap.

[0096] For example, please refer to Figure 2 When a two-dimensional electron gas is formed in the semiconductor device 10 , the semiconductor device 10 may be used to form a HEMT.

[0097] In some embodiments, please refer to Figure 2 The semiconductor device 10 may further include a first capping layer 61 and a second capping layer 62. The first capping layer 61 and the second capping layer 62 are disposed on one side of the substrate 1 and are spaced apart along a first direction X, and the first direction X is parallel to the substrate 1.

[0098] For example, please refer to Figure 2 The first capping layer 61 and the second capping layer 62 may both be disposed on a side of the barrier layer 4 in the semiconductor device 10 away from the substrate 1 .

[0099] By making the semiconductor device 10 include a first cap layer 61 and a second cap layer 62, and the first cap layer 61 and the second cap layer 62 are both arranged on the side of the barrier layer 4 away from the substrate 1, on the one hand, the energy band difference between the first cap layer 61 and the barrier layer 4, and the energy band difference between the second cap layer 62 and the barrier layer 4 can be used to regulate the two-dimensional electron gas near the connection interface between the barrier layer 4 and the channel layer 3, which is beneficial to deplete the two-dimensional electron gas below the first cap layer 61 and the second cap layer 62, so that the semiconductor device 10 can achieve an enhanced operating mode.

[0100] On the other hand, due to the depletion effect of the first cap layer 61 and the second cap layer 62 in the semiconductor device 10 on the two-dimensional electron gas located below the first cap layer 61 and the second cap layer 62, the semiconductor device 10 needs to overcome a higher potential barrier when turned on, which is beneficial to increasing the threshold voltage of the semiconductor device 10.

[0101] Exemplarily, the material of the first capping layer 61 and the material of the second capping layer 62 in the semiconductor device 10 may both include P-type doped semiconductor materials.

[0102] For example, the material of the first capping layer 61 and the material of the second capping layer 62 may both include p-type gallium nitride (p-GaN).

[0103] P-type gallium nitride (p-GaN) can be formed by doping GaN materials with elements such as magnesium (Mg). The doping concentration of elements such as magnesium (Mg) in GaN materials can be greater than or equal to 1e19 cm -3 .

[0104] When doping elements such as magnesium (Mg) into GaN material to form p-type gallium nitride (p-GaN), a gas-phase doping process or an ion implantation process may be used.

[0105] In the process of forming the first capping layer 61 and the second capping layer 62 in the semiconductor device 10, by doping P-type material (e.g., Mg) as an impurity into the semiconductor material (e.g., GaN), the first capping layer 61 and the second capping layer 62 can provide hole carriers, thereby adjusting the conductivity of the first capping layer 61 and the second capping layer 62.

[0106] In some embodiments, please refer to Figure 2 The semiconductor device 10 may further include a first gate G1 and a second gate G2. The first gate G1 may be disposed on a side of the first cap layer 61 away from the substrate 1, and the second gate G2 may be disposed on a side of the second cap layer 62 away from the substrate 1.

[0107] The first gate G1 and the second gate G2 in the semiconductor device 10 are key electrodes for controlling the conductivity of the semiconductor device 10. The first gate G1 and the second gate G2 do not directly participate in the conduction of current, but control the carrier concentration in the channel layer 3 in the semiconductor device 10 through the electric field effect, thereby controlling the current in the semiconductor device 10.

[0108] For example, please refer to Figure 2 , the first gate G1 in the semiconductor device 10 can form an ohmic contact with the first cap layer 61. That is, the first gate G1 in the semiconductor device 10 can form a low-resistance, linear electrical contact with the first cap layer 61, which is beneficial to reducing the contact resistance between the first gate G1 and the first cap layer 61, thereby improving the current transmission efficiency and enhancing the performance of the semiconductor device 10.

[0109] Please continue reading Figure 2 , the second gate G2 in the semiconductor device 10 can form an ohmic contact with the second cap layer 62. That is, the second gate G2 in the semiconductor device 10 can form a low-resistance, linear electrical contact with the second cap layer 62, which is beneficial to reducing the contact resistance between the second gate G2 and the second cap layer 62, thereby improving the current transmission efficiency and enhancing the performance of the semiconductor device 10.

[0110] Exemplarily, the material of the first gate G1 and the material of the second gate G2 in the semiconductor device 10 may include one or more conductive materials such as palladium (Pd), nickel (Ni), aluminum (Al), gold (Au), platinum (Pt), titanium (Ti) and titanium nitride (TiN).

[0111] In some embodiments, please refer to Figure 2 The semiconductor device 10 may further include a first electrode J1 and a second electrode J2. The first electrode J1 and the second electrode J2 are disposed along the first direction X at opposite sides of the structure composed of the first capping layer 61 and the second capping layer 62.

[0112] For example, please refer to Figure 2 In the case where a two-dimensional electron gas is formed in the semiconductor device 10, the first electrode J1 and the second electrode J2 in the semiconductor device 10 can form an ohmic contact with the two-dimensional electron gas, which can reduce the contact resistance between the first electrode J1 in the semiconductor device 10 and the two-dimensional electron gas, and the contact resistance between the second electrode J2 in the semiconductor device 10 and the two-dimensional electron gas. A low-impedance current channel can be formed between the first electrode J1, the second electrode J2 and the two-dimensional electron gas in the semiconductor device 10, so that the current can flow smoothly, which is beneficial to improving the performance of the semiconductor device 10.

[0113] Exemplarily, the material of the first electrode J1 and the material of the second electrode J2 in the semiconductor device 10 may include one or more conductive materials such as titanium (Ti), aluminum (Al), gold (Au), silicon (Si), and titanium nitride (TiN).

[0114] Please continue reading Figure 2 , and combined with Figure 3 , Figure 4A , Figure 4B , Figure 5A and Figure 5B , Figure 3 , Figure 4A , Figure 4B , Figure 5A and Figure 5B All of them are cross-sectional schematic diagrams of semiconductor devices 10 according to some embodiments. In the case where the semiconductor device 10 includes a first electrode J1, a second electrode J2, a first gate G1 and a second gate G2, the working principle of the semiconductor device 10 is as follows:

[0115] Please continue reading Figure 2 When the first gate G1 and the second gate G2 in the semiconductor device 10 are both in a reverse voltage bias state, the semiconductor device 10 is in a closed state.

[0116] Please continue reading Figure 3When the first gate G1 and the second gate G2 in the semiconductor device 10 are both in the forward voltage bias state, the semiconductor device 10 is in the on state. The current in the semiconductor device 10 can flow from the first electrode J1 to the second electrode J2, or from the second electrode J2 to the first electrode J1.

[0117] Please continue reading Figure 4A , the first gate G1 in the semiconductor device 10 is in a reverse voltage bias state, the second gate G2 is in a forward voltage bias state, and the voltage V at the first electrode J1 is J1 is greater than the voltage V at the second electrode J2 J2 , the voltage V between the first gate G1 and the second electrode J2 G1J2 is greater than the threshold voltage V of the semiconductor device 10 TH In the case of , the first gate G1 is reversely conductive, and the current in the semiconductor device 10 flows from the first electrode J1 to the second electrode J2.

[0118] Please continue reading Figure 4B , the first gate G1 in the semiconductor device 10 is in a reverse voltage bias state, the second gate G2 is in a forward voltage bias state, and the voltage V at the first electrode J1 is J1 is less than the voltage V at the second electrode J2 J2 , the voltage V between the first gate G1 and the second electrode J2 G1J2 is less than the threshold voltage V of the semiconductor device 10 TH In this case, the current in the semiconductor device 10 is cut off and the semiconductor device 10 is in the off state.

[0119] Please continue reading Figure 5A , the first gate G1 in the semiconductor device 10 is in a forward voltage bias state, the second gate G2 is in a reverse voltage bias state, and the voltage V at the first electrode J1 is J1 is less than the voltage V at the second electrode J2 J2 , the voltage V between the second gate G2 and the first electrode J1 G2J1 is greater than the threshold voltage V of the semiconductor device 10 TH In the case of , the second gate G2 is reversely conductive, and the current in the semiconductor device 10 flows from the second electrode J2 to the first electrode J1.

[0120] Please continue reading Figure 5B , the first gate G1 in the semiconductor device 10 is in a forward voltage bias state, the second gate G2 is in a reverse voltage bias state, and the voltage V at the first electrode J1 is J1 is greater than the voltage V at the second electrode J2 J2, the voltage V between the second gate G2 and the first electrode J1 G2J1 is less than the threshold voltage V of the semiconductor device 10 TH In this case, the current in the semiconductor device 10 is cut off and the semiconductor device 10 is in the off state.

[0121] Please continue reading Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5A and Figure 5B By making the semiconductor device 10 include the first electrode J1, the second electrode J2, the first gate G1 and the second gate G2, and the current in the semiconductor device 10 can use the same conductive channel when flowing from the first electrode J1 to the second electrode J2, or when flowing from the second electrode J2 to the first electrode J1, it is beneficial to optimize the current transmission path in the semiconductor device 10, reduce the space occupied in the semiconductor device 10, and further help to improve the space utilization rate in the semiconductor device 10, thereby facilitating the miniaturization of the semiconductor device 10.

[0122] The structures of the first capping layer 61 and the second capping layer 62 are described in detail below.

[0123] In some embodiments, please refer to Figure 2 , and combined with Figure 6 , Figure 7 , Figure 8 and Fig. 9 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 6 and 61 , which are cross-sectional schematic diagrams of semiconductor devices 10 according to some embodiments. At least one of the first cap layer 61 and the second cap layer 62 may include a first sublayer 611 and a second sublayer 612. Along the first direction X (i.e., the arrangement direction of the first electrode J1 and the second electrode J2 in the semiconductor device 10), the first sublayer 611 is disposed on one side of the second sublayer 612. The thickness h611 of the first sublayer 611 is greater than the thickness h612 of the second sublayer 612.

[0124] It should be noted that the thickness h611 of the first sublayer 611 refers to the dimension of the first sublayer 611 along the third direction Z (i.e., the thickness direction of the substrate 1). The thickness h612 of the second sublayer 612 refers to the dimension of the second sublayer 612 along the third direction Z. The following description of the thickness h611 of the first sublayer 611 and the thickness h612 of the second sublayer 612 also follows this description and will not be repeated.

[0125] By making at least one of the first cap layer 61 and the second cap layer 62 in the semiconductor device 10 include a first sublayer 611 and a second sublayer 612, and the thickness h611 of the first sublayer 611 is greater than the thickness h612 of the second sublayer 612, on the one hand, when the semiconductor device 10 is turned on, the first sublayer 611 and the second sublayer 612 can both inject holes toward the side close to the substrate 1, which is beneficial to improving the range of hole injection and the efficiency of hole injection. The holes will neutralize the negative charge center in the semiconductor device 10 (for example, the negative charge center in the buffer layer 2 in the semiconductor device 10), which can reduce the repulsive effect of the negative charge center on the two-dimensional electron gas in the semiconductor device 10, and then suppress the degradation of the dynamic on-resistance of the semiconductor device 10, which is beneficial to reduce the energy loss of the semiconductor device 10 during the switching process.

[0126] On the other hand, when the first capping layer 61 includes a first sublayer 611 and a second sublayer 612, and the first gate G1 located on the side of the first capping layer 61 away from the substrate 1 is in a forward voltage bias state, the first gate G1 can induce more two-dimensional electron gas in the semiconductor device 10 through the second sublayer 612, which is beneficial to increase the concentration of the two-dimensional electron gas in the semiconductor device 10, and further beneficial to reduce the on-resistance of the semiconductor device 10, thereby helping to reduce the energy loss of the semiconductor device 10 in the on state.

[0127] When the second capping layer 62 includes a first sublayer 611 and a second sublayer 612, and the second gate G2 located on the side of the second capping layer 62 away from the substrate 1 is in a forward voltage bias state, the second gate G2 can induce more two-dimensional electron gas in the semiconductor device 10 through the second sublayer 612, which is beneficial to increase the concentration of the two-dimensional electron gas in the semiconductor device 10, and further beneficial to reduce the on-resistance of the semiconductor device 10, thereby helping to reduce the energy loss of the semiconductor device 10 in the on state.

[0128] On the other hand, when the first cap layer 61 and the second cap layer 62 are both arranged on the side of the barrier layer 4 in the semiconductor device 10 away from the substrate 1, and there are surface traps in the barrier layer 4, the second sublayer 612 in the first cap layer 61 and / or the second sublayer 612 in the second cap layer 62 can shield the surface traps in the barrier layer 4, thereby weakening the capture effect of the surface traps in the barrier layer 4 on electrons, thereby suppressing the current collapse effect caused by the capture of electrons by the surface traps in the barrier layer 4, which is beneficial to improving the performance of the semiconductor device 10.

[0129] On the other hand, when the first gate G1 in the semiconductor device 10 is in a reverse voltage bias state, the second gate G2 is in a forward voltage bias state, and the voltage VJ1 is less than the voltage V at the second electrode J2 J2 , the voltage V between the first gate G1 and the second electrode J2 G1J2 is less than the threshold voltage V of the semiconductor device 10 TH When the voltage V at the second electrode J2 is 0, the current in the semiconductor device 10 is cut off. By making the first cap layer 61 include the first sub-layer 611 and the second sub-layer 612, and the thickness h611 of the first sub-layer 611 is greater than the thickness h612 of the second sub-layer 612, that is, the thickness h612 of the second sub-layer 612 is smaller, when the voltage V at the second electrode J2 is J2 When it is larger, it is beneficial for the second sublayer 612 to exhaust the holes inside it under the action of the electric field, and then a hole depletion region can be formed in the area where the second sublayer 612 is located in the first cap layer 61, which is beneficial to improving the voltage resistance of the semiconductor device 10, and can reduce the probability of the semiconductor device 10 being broken down, and thus is beneficial to improving the service life of the semiconductor device 10.

[0130] When the first gate G1 in the semiconductor device 10 is in a forward voltage bias state, the second gate G2 is in a reverse voltage bias state, and the voltage V J1 is greater than the voltage V at the second electrode J2 J2 , the voltage V between the second gate G2 and the first electrode J1 G2J1 is less than the threshold voltage V of the semiconductor device 10 TH When the voltage V at the first electrode J1 is 0, the current in the semiconductor device 10 is cut off. By making the second cap layer 62 include the first sublayer 611 and the second sublayer 612, and the thickness h611 of the first sublayer 611 is greater than the thickness h612 of the second sublayer 612, that is, the thickness h612 of the second sublayer 612 is smaller, when the voltage V at the first electrode J1 is J1 When it is larger, it is beneficial for the second sublayer 612 to exhaust the holes inside it under the action of the electric field, and then a hole depletion region can be formed in the area where the second sublayer 612 is located in the second cap layer 62, which is beneficial to improving the voltage resistance of the semiconductor device 10, and can reduce the probability of the semiconductor device 10 being broken down, and thus is beneficial to improving the service life of the semiconductor device 10.

[0131] For example, please refer to Figure 2 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 , the thickness h611 of the first sublayer 611 may be greater than or equal to 30 nm and less than or equal to 100 nm.

[0132] For example, see Figure 2 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 The thickness h611 of the first sublayer 611 can be 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm or 100nm, etc.

[0133] For example, please refer to Figure 2 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 , the thickness h612 of the second sublayer 612 may be greater than or equal to 10 nm and less than or equal to 90 nm.

[0134] For example, see Figure 2 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 The thickness h612 of the second sublayer 612 can be 10 nm, 15 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm or 90 nm, etc.

[0135] Exemplarily, one of the first capping layer 61 and the second capping layer 62 may include a first sub-layer 611 and a second sub-layer 612 .

[0136] For example, the first capping layer 61 may include a first sub-layer 611 and a second sub-layer 612 , and the second capping layer 62 may be a film layer structure with uniform thickness.

[0137] For another example, the first capping layer 61 may be a film layer structure with uniform thickness, and the second capping layer 62 may include a first sub-layer 611 and a second sub-layer 612 .

[0138] Alternatively, continue to Figure 2 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 The first capping layer 61 and the second capping layer 62 may each include a first sub-layer 611 and a second sub-layer 612 .

[0139] For example, please refer to Figure 2 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 In the case where at least one of the first capping layer 61 and the second capping layer 62 includes the first sublayer 611 and the second sublayer 612 , at least one of the first gate G1 and the second gate G2 may be disposed on a side of the first sublayer 611 away from the substrate 1 .

[0140] For details, please continue to see Figure 2 , Figure 6, Figure 7 , Figure 8 and Fig. 9 When the first capping layer 61 includes the first sub-layer 611 , the first gate G1 may be disposed on a side of the first sub-layer 611 in the first capping layer 61 away from the substrate 1 .

[0141] Please continue reading Figure 2 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 When the second capping layer 62 includes the first sub-layer 611 , the second gate G2 may be disposed on a side of the first sub-layer 611 in the second capping layer 62 away from the substrate 1 .

[0142] For example, please refer to Figure 2 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 In the case where both the first capping layer 61 and the second capping layer 62 include a first sublayer 611 and a second sublayer 612 , the second sublayer 612 may be closer to the spacing region Q between the first capping layer 61 and the second capping layer 62 than the first sublayer 611 .

[0143] by Figure 2 The semiconductor device 10 shown in FIG. Figure 4B and Figure 5B , when the first gate G1 in the semiconductor device 10 is in a reverse voltage bias state, the second gate G2 is in a forward voltage bias state, and the voltage V at the first electrode J1 is J1 is less than the voltage V at the second electrode J2 J2 , the voltage V between the first gate G1 and the second electrode J2 G1J2 is less than the threshold voltage V of the semiconductor device 10 TH When the voltage V at the second electrode J2 is J2 When the voltage V at the second electrode J2 is larger than the first cap layer 61 and the second cap layer 62, the two-dimensional electron gas below the gap region Q between the first cap layer 61 and the second cap layer 62 is depleted under the action of the electric field, thereby forming a two-dimensional electron gas depletion region below the gap region Q between the first cap layer 61 and the second cap layer 62. When the first cap layer 61 and the second cap layer 62 both include a first sublayer 611 and a second sublayer 612, and the thickness h611 of the first sublayer 611 is greater than the thickness h612 of the second sublayer 612, since the thickness h612 of the second sublayer 612 is smaller, when the voltage V at the second electrode J2 is J2When the voltage V is larger, it is beneficial for the second sublayer 612 in the first cap layer 61 to exhaust the holes in the second sublayer 612 under the action of the electric field, so that a hole depletion region can be formed in the area where the second sublayer 612 is located in the first cap layer 61. By making the second sublayer 612 closer to the spacing region Q between the first cap layer 61 and the second cap layer 62 than the first sublayer 611, the spacing region Q between the first cap layer 61 and the second cap layer 62 is adjacent to the second sublayer 612, so that when the voltage V J2 When the dimension Lm is larger, the voltage-resistant region in the semiconductor device 10 includes the two-dimensional electron gas depletion region formed below the spacing region Q and the hole depletion region formed in the region where the second sublayer 612 in the first cap layer 61 is located, so that the dimension Lm of the voltage-resistant region in the semiconductor device 10 along the first direction X is the sum of the dimension L612 of the second sublayer 612 in the first cap layer 61 along the first direction X and the dimension L1 of the spacing region Q along the first direction X. That is, the dimension Lm of the voltage-resistant region in the semiconductor device 10 along the first direction X is larger, which is conducive to further improving the voltage-resistant capability of the semiconductor device 10, and can further reduce the probability of the semiconductor device 10 being broken down, thereby further improving the service life of the semiconductor device 10.

[0144] When the first gate G1 in the semiconductor device 10 is in a forward voltage bias state, the second gate G2 is in a reverse voltage bias state, and the voltage V J1 is greater than the voltage V at the second electrode J2 J2 , the voltage V between the second gate G2 and the first electrode J1 G2J1 is less than the threshold voltage V of the semiconductor device 10 TH When the voltage V at the first electrode J1 is J1 When the voltage V at the first electrode J1 is larger than the thickness h612 of the second sublayer 612, the two-dimensional electron gas below the gap region Q between the first cap layer 61 and the second cap layer 62 is depleted under the action of the electric field, thereby forming a two-dimensional electron gas depletion region below the gap region Q between the first cap layer 61 and the second cap layer 62. When the first cap layer 61 and the second cap layer 62 both include a first sublayer 611 and a second sublayer 612, and the thickness h611 of the first sublayer 611 is greater than the thickness h612 of the second sublayer 612, since the thickness h612 of the second sublayer 612 is smaller, when the voltage V at the first electrode J1 is J1When the voltage V is larger, it is beneficial for the second sublayer 612 in the second cap layer 62 to exhaust the holes in the second sublayer 612 under the action of the electric field, so that a hole depletion region can be formed in the area where the second sublayer 612 is located in the second cap layer 62. By making the second sublayer 612 closer to the spacing region Q between the first cap layer 61 and the second cap layer 62 than the first sublayer 611, the spacing region Q between the first cap layer 61 and the second cap layer 62 is adjacent to the second sublayer 612, so that when the voltage V J1 When the size Lm of the voltage-resistant region in the semiconductor device 10 is larger, the voltage-resistant region in the semiconductor device 10 includes a two-dimensional electron gas depletion region formed below the spacing region Q and a hole depletion region formed in the region where the second sublayer 612 in the second cap layer 62 is located, so that the size Lm of the voltage-resistant region in the semiconductor device 10 along the first direction X is the sum of the size L612 of the second sublayer 612 in the second cap layer 62 along the first direction X and the size L1 of the spacing region Q along the first direction X. That is, the size Lm of the voltage-resistant region in the semiconductor device 10 along the first direction X is larger, which is conducive to further improving the voltage-resistant capability of the semiconductor device 10, and can further reduce the probability of the semiconductor device 10 being broken down, thereby further improving the service life of the semiconductor device 10.

[0145] Please continue reading Figure 2 The dimension L612 of the second sub-layer 612 in the first capping layer 61 along the first direction X may be equal to the dimension L612 of the second sub-layer 612 in the second capping layer 62 along the first direction X.

[0146] Please continue reading Figure 4B and Figure 5B , when the dimension L612 of the second sublayer 612 in the first cap layer 61 along the first direction X is equal to the dimension L612 of the second sublayer 612 in the second cap layer 62 along the first direction X, when the first gate G1 in the semiconductor device 10 is in a reverse voltage bias state, the second gate G2 is in a forward voltage bias state, and the voltage V at the first electrode J1 is J1 is less than the voltage V at the second electrode J2 J2 , the voltage V between the first gate G1 and the second electrode J2 G1J2 is less than the threshold voltage V of the semiconductor device 10 TH When the size Lm of the withstand voltage region in the semiconductor device 10 along the first direction X is equal to, when the first gate G1 in the semiconductor device 10 is in a forward voltage bias state, the second gate G2 is in a reverse voltage bias state, and the voltage V at the first electrode J1 is J1 is greater than the voltage V at the second electrode J2 J2 , the voltage V between the second gate G2 and the first electrode J1 G2J1 is less than the threshold voltage V of the semiconductor device 10TH When , the dimension Lm of the voltage-resistant region in the semiconductor device 10 along the first direction X is Figure 4B The withstand voltage capability of the semiconductor device 10 in the state shown in FIG. Figure 5B The withstand voltage capabilities of the semiconductor devices 10 in the illustrated state are substantially the same.

[0147] Alternatively, continue to Figure 2 The dimension L612 of the second sub-layer 612 in the first capping layer 61 along the first direction X may be greater than the dimension L612 of the second sub-layer 612 in the second capping layer 62 along the first direction X.

[0148] Please continue reading Figure 4B and Figure 5B , when the dimension L612 of the second sublayer 612 in the first cap layer 61 along the first direction X is greater than the dimension L612 of the second sublayer 612 in the second cap layer 62 along the first direction X, when the first gate G1 in the semiconductor device 10 is in a reverse voltage bias state, the second gate G2 is in a forward voltage bias state, and the voltage V at the first electrode J1 is J1 is less than the voltage V at the second electrode J2 J2 , the voltage V between the first gate G1 and the second electrode J2 G1J2 is less than the threshold voltage V of the semiconductor device 10 TH When the size Lm of the withstand voltage region in the semiconductor device 10 along the first direction X is greater than, when the first gate G1 in the semiconductor device 10 is in a forward voltage bias state, the second gate G2 is in a reverse voltage bias state, and the voltage V at the first electrode J1 is J1 is greater than the voltage V at the second electrode J2 J2 , the voltage V between the second gate G2 and the first electrode J1 G2J1 is less than the threshold voltage V of the semiconductor device 10 TH When , the dimension Lm of the voltage-resistant region in the semiconductor device 10 along the first direction X is Figure 4B The withstand voltage capability of the semiconductor device 10 in the state shown is greater than that in Figure 5B The withstand voltage capability of the semiconductor device 10 in the state shown.

[0149] Alternatively, please continue reading Figure 2 The dimension L612 of the second sub-layer 612 in the first capping layer 61 along the first direction X may be smaller than the dimension L612 of the second sub-layer 612 in the second capping layer 62 along the first direction X.

[0150] Please continue reading Figure 4B and Figure 5B, when the dimension L612 of the second sublayer 612 in the first cap layer 61 along the first direction X is smaller than the dimension L612 of the second sublayer 612 in the second cap layer 62 along the first direction X, when the first gate G1 in the semiconductor device 10 is in a reverse voltage bias state, the second gate G2 is in a forward voltage bias state, and the voltage V at the first electrode J1 is J1 is less than the voltage V at the second electrode J2 J2 , the voltage V between the first gate G1 and the second electrode J2 G1J2 is less than the threshold voltage V of the semiconductor device 10 TH When the size Lm of the withstand voltage region in the semiconductor device 10 along the first direction X is smaller than that of the first gate G1 in the semiconductor device 10 in the forward voltage bias state, the second gate G2 in the reverse voltage bias state, and the voltage V at the first electrode J1 J1 is greater than the voltage V at the second electrode J2 J2 , the voltage V between the second gate G2 and the first electrode J1 G2J1 is less than the threshold voltage V of the semiconductor device 10 TH When , the dimension Lm of the voltage-resistant region in the semiconductor device 10 along the first direction X is Figure 4B The withstand voltage capability of the semiconductor device 10 in the state shown is less than that in Figure 5B The withstand voltage capability of the semiconductor device 10 in the state shown.

[0151] For example, please refer to Figure 2 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 The dimension L611 of the first sublayer 611 along the first direction X may be smaller than the dimension L612 of the second sublayer 612 along the first direction X.

[0152] In some embodiments, please refer to Figure 2 , the thickness h612 of the second sub-layer 612 is uniform.

[0153] The uniform thickness h612 of the second sub-layer 612 means that the difference between the thickness h612 of any two regions in the second sub-layer 612 is within a preset threshold range. The threshold range is a relatively small numerical range, for example, the threshold range can be a process accuracy range when forming the second sub-layer 612 with a uniform thickness h612.

[0154] When the thickness h612 of the second sub-layer 612 is uniform, the difference between the thickness h612 of any two regions in the second sub-layer 612 may be 0-2 nm.

[0155] For example, when the thickness h612 of the second sublayer 612 is uniform, the difference between the thickness h612 of any two regions in the second sublayer 612 may be 0, 0.3 nm, 0.6 nm, 0.9 nm, 1.2 nm, 1.5 nm, 1.8 nm or 2 nm, etc.

[0156] In other embodiments, please refer to Figure 6 , Figure 7 , Figure 8 and Fig. 9 , the thickness h612 of at least two regions within the second sublayer 612 is different.

[0157] For example, please refer to Figure 6 , Figure 7 , Figure 8 and Fig. 9 , along the first direction X, the thickness h612 of the second sublayer 612 may gradually decrease.

[0158] By gradually reducing the thickness h612 of the second sub-layer 612 along the first direction X, it is beneficial to optimize the electric field distribution in the semiconductor device 10 , thereby facilitating the improvement of the performance of the semiconductor device 10 .

[0159] For example, see Figure 6 and Figure 8 When the first capping layer 61 includes a first sublayer 611 and a second sublayer 612 , in the first capping layer 61 , a thickness h612 of the second sublayer 612 on a side close to the first sublayer 611 may be greater than a thickness h612 of the second sublayer 612 on a side away from the first sublayer 611 .

[0160] And / or, when the second capping layer 62 includes a first sublayer 611 and a second sublayer 612, within the second capping layer 62, a thickness h612 of the second sublayer 612 on a side close to the first sublayer 611 may be greater than a thickness h612 of the second sublayer 612 on a side away from the first sublayer 611.

[0161] For another example, please continue to see Figure 7 and Fig. 9 When the first capping layer 61 includes a first sublayer 611 and a second sublayer 612 , in the first capping layer 61 , a thickness h612 of the second sublayer 612 on a side close to the first sublayer 611 may be smaller than a thickness h612 of the second sublayer 612 on a side away from the first sublayer 611 .

[0162] And / or, when the second capping layer 62 includes the first sublayer 611 and the second sublayer 612, within the second capping layer 62, the thickness h612 of the second sublayer 612 on the side close to the first sublayer 611 may be smaller than the thickness h612 of the second sublayer 612 on the side away from the first sublayer 611.

[0163] In the case where the first capping layer 61 includes a first sub-layer 611 and a second sub-layer 612, within the first capping layer 61, by making the thickness h612 of the second sub-layer 612 close to the first sub-layer 611 smaller than the thickness h612 of the second sub-layer 612 away from the first sub-layer 611, that is, the thickness h612 of the second sub-layer 612 close to the first gate G1 is smaller, it is beneficial to increase the depletion speed of the charge stored in the second sub-layer 612, and further facilitate the semiconductor device 10 to switch states quickly and reliably under high voltage.

[0164] In the case where the second capping layer 62 includes a first sub-layer 611 and a second sub-layer 612, within the second capping layer 62, by making the thickness h612 of the second sub-layer 612 close to the first sub-layer 611 smaller than the thickness h612 of the second sub-layer 612 away from the first sub-layer 611, that is, the thickness h612 of the second sub-layer 612 close to the second gate G2 is smaller, it is beneficial to increase the depletion speed of the charge stored in the second sub-layer 612, and further facilitate the semiconductor device 10 to switch states quickly and reliably under high voltage.

[0165] For example, please refer to Figure 6 and Figure 7 When the thickness h612 of the second sub-layer 612 gradually decreases along the first direction X, the surface of the second sub-layer 612 away from the substrate 1 may be arranged in a stepped shape.

[0166] Alternatively, continue to Figure 8 and Fig. 9 When the thickness h612 of the second sub-layer 612 gradually decreases along the first direction X, the surface of the second sub-layer 612 away from the substrate 1 may be arranged in an inclined surface.

[0167] In some embodiments, Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14 As shown, Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14Each of them is a cross-sectional schematic diagram of a semiconductor device 10 according to some embodiments. At least one of the first capping layer 61 and the second capping layer 62 in the semiconductor device 10 further includes a third sublayer 613. The third sublayer 613 may be located on a side of the first sublayer 611 away from the second sublayer 612.

[0168] The method for manufacturing the semiconductor device 10 is described in detail below.

[0169] In some embodiments, Fig.15 As shown, Fig.15 1 and 2 are flowcharts of methods for manufacturing a semiconductor device 10 according to some embodiments. It should be noted that: Fig.15 The method for preparing the semiconductor device 10 shown in FIG. 1 is not exclusive and may also be Fig.15 Other steps are performed before, after or between any steps in the method for manufacturing the semiconductor device 10. The method for manufacturing the semiconductor device 10 includes steps S1 to S3.

[0170] S1: Fig.16 As shown, Fig.16 for Fig.15 A schematic diagram of the structure of the semiconductor device 10 corresponding to step S1 in the flowchart of the method for preparing the semiconductor device 10 in FIG. A first capping layer 61 and a second capping layer 62 are formed on one side of the substrate 1. The first capping layer 61 and the second capping layer 62 are arranged at intervals along a first direction X, and the first direction X is parallel to the substrate 1. At least one of the first capping layer 61 and the second capping layer 62 includes a first sublayer 611 and a second sublayer 612, and along the first direction X, the first sublayer 611 is arranged on one side of the second sublayer 612. The thickness h611 of the first sublayer 611 is greater than the thickness h612 of the second sublayer 612.

[0171] For example, please refer to Fig.15 , step S1 (ie, forming a first capping layer 61 and a second capping layer 62 on one side of the substrate 1 ) in the method for preparing the semiconductor device 10 may include steps S11 to S13 .

[0172] S11: Fig.17 As shown, Fig.17 for Fig.15 The schematic structural diagram of the semiconductor device 10 corresponding to step S1 in the flowchart of the method for preparing the semiconductor device 10 in FIG.

[0173] S12: Please continue reading Fig.17 , a partial area of ​​the initial capping layer 61a is thinned to form a transitional capping layer 61b.

[0174] S13: Please continue reading Fig.17, remove the transition cap layer 61b in a partial area to form a first cap layer 61 and a second cap layer 62 respectively.

[0175] S2: Fig.18 As shown, Fig.18 for Fig.15 The structure diagram of the semiconductor device 10 corresponding to step S2 in the flowchart of the method for preparing the semiconductor device 10 in FIG. The first electrode J1 and the second electrode J2 are formed. The first electrode J1 and the second electrode J2 are arranged along the first direction X on opposite sides of the structure composed of the first cap layer 61 and the second cap layer 62.

[0176] S3: Fig.19 As shown, Fig.19 for Fig.15 A schematic diagram of the structure of the semiconductor device 10 corresponding to step S3 in the flowchart of the method for preparing the semiconductor device 10 in FIG. A first gate G1 is formed on a side of the first cap layer 61 away from the substrate 1, and a second gate G2 is formed on a side of the second cap layer 62 away from the substrate 1. At least one of the first gate G1 and the second gate G2 is disposed on a side of the first sub-layer 611 away from the substrate 1.

[0177] For example, please refer to Fig.19 When the first capping layer 61 includes the first sub-layer 611 , the first gate G1 may be disposed on a side of the first sub-layer 611 in the first capping layer 61 away from the substrate 1 .

[0178] Please continue reading Fig.19 When the second capping layer 62 includes the first sub-layer 611 , the second gate G2 may be disposed on a side of the first sub-layer 611 in the second capping layer 62 away from the substrate 1 .

[0179] It should be noted that Fig.16 , Fig.17 , Fig.18 and Fig.19 The structure diagram of the semiconductor device 10 corresponding to each step in the method for preparing the semiconductor device 10 is only formed Fig. 9 The semiconductor device 10 shown is exemplarily described, forming Figure 2 , Figure 6 , Figure 7 , Figure 8 , Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14 The semiconductor device 10 can also refer to the above steps, which will not be repeated here.

[0180] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A first capping layer and a second capping layer are arranged on one side of the substrate and are spaced apart along a first direction; the first direction is parallel to the substrate; at least one of the first capping layer and the second capping layer includes a first sublayer and a second sublayer, and along the first direction, the first sublayer is arranged on one side of the second sublayer; the thickness of the first sublayer is greater than the thickness of the second sublayer; a first gate and a second gate, wherein the first gate is disposed on a side of the first cap layer away from the substrate, and the second gate is disposed on a side of the second cap layer away from the substrate; at least one of the first gate and the second gate is disposed on a side of the first sub-layer away from the substrate; The first electrode and the second electrode are arranged along the first direction on opposite sides of the structure composed of the first capping layer and the second capping layer.

2. The semiconductor device according to claim 1, wherein: The first capping layer and the second capping layer both include the first sub-layer and the second sub-layer; The second sub-layer is closer to a spacing region between the first capping layer and the second capping layer than the first sub-layer.

3. The semiconductor device according to claim 1, wherein: A size of the first sublayer along the first direction is smaller than a size of the second sublayer along the first direction.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: The second sub-layer has a uniform thickness.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that: At least two regions within the second sublayer have different thicknesses.

6. The semiconductor device according to claim 5, characterized in that Along the first direction, the thickness of the second sub-layer gradually decreases.

7. The semiconductor device according to claim 6, characterized in that The first capping layer includes the first sublayer and the second sublayer; in the first capping layer, the thickness of the second sublayer on a side close to the first sublayer is smaller than the thickness of the second sublayer on a side away from the first sublayer; and / or The second capping layer includes the first sublayer and the second sublayer; in the second capping layer, a thickness of the second sublayer on a side close to the first sublayer is smaller than a thickness of the second sublayer on a side away from the first sublayer.

8. The semiconductor device according to claim 6, characterized in that The first capping layer includes the first sublayer and the second sublayer; in the first capping layer, the thickness of the second sublayer on a side close to the first sublayer is greater than the thickness of the second sublayer on a side away from the first sublayer; and / or The second capping layer includes the first sublayer and the second sublayer; in the second capping layer, a thickness of the second sublayer on a side close to the first sublayer is greater than a thickness of the second sublayer on a side away from the first sublayer.

9. The semiconductor device according to any one of claims 6 to 8, characterized in that: A surface of the second sub-layer away from the substrate is arranged in a step shape.

10. The semiconductor device according to any one of claims 6 to 8, characterized in that: A surface of the second sub-layer away from the substrate is arranged in an inclined surface.

11. The semiconductor device according to any one of claims 1 to 3, characterized in that: At least one of the first capping layer and the second capping layer further includes a third sub-layer located on a side of the first sub-layer away from the second sub-layer.

12. A method for preparing a semiconductor device, characterized in that: include: A first capping layer and a second capping layer are formed on one side of the substrate; the first capping layer and the second capping layer are arranged at intervals along a first direction, and the first direction is parallel to the substrate; at least one of the first capping layer and the second capping layer includes a first sublayer and a second sublayer, and along the first direction, the first sublayer is arranged on one side of the second sublayer; the thickness of the first sublayer is greater than the thickness of the second sublayer; forming a first electrode and a second electrode; the first electrode and the second electrode are arranged along the first direction on opposite sides of the structure composed of the first cap layer and the second cap layer; A first gate is formed on a side of the first cap layer away from the substrate, and a second gate is formed on a side of the second cap layer away from the substrate; at least one of the first gate and the second gate is arranged on a side of the first sublayer away from the substrate.

13. The method for preparing a semiconductor device according to claim 12, characterized in that: The method of forming a first capping layer and a second capping layer on one side of the substrate comprises: forming an initial capping layer on one side of the substrate; Thinning a portion of the initial capping layer to form a transitional capping layer; The transition cap layer is removed from a partial area to form a first cap layer and a second cap layer respectively.

14. A chip, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 11.

15. An electronic device, characterized in that: include: Circuit boards; The chip as claimed in claim 14, wherein the chip is electrically connected to the circuit board.

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