Silicon carbide device, manufacturing method thereof and electronic device

Abstract

The silicon carbide device, its manufacturing method and electronic device disclosed in the present invention can improve the conduction capability, radiation resistance and reverse withstand voltage capability of the device. The silicon carbide device includes a first n-drift layer; a second n-type doped drift layer, located on one side of the first n-drift layer; a p-well layer, located on the side of the second n-type doped drift layer away from the first n-drift layer; an n+ electrode layer, located on the side of the p-well layer away from the second n-type doped drift layer; a plurality of grooves, the grooves penetrate the n+ electrode layer, the p-well layer and the second n-type doped drift layer, and the direction of the grooves is [11 _ 20] crystal direction, a stripe cell region is formed between adjacent grooves; a p-protective layer includes a connecting portion, the connecting portion covers a portion of the side surface of at least one side of the groove of the stripe cell region, and is blankly arranged on a portion of the side surface of at least one side of the groove of the stripe cell region.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a silicon carbide device, a manufacturing method thereof, and an electronic device. Background Art

[0002] As a semiconductor material with a wide bandgap, high breakdown field strength, high thermal conductivity, and mobility similar to that of silicon, silicon carbide has broad prospects in power electronics applications and is widely used in new energy vehicles, charging piles, photovoltaics and other fields. Summary of the invention

[0003] The present disclosure provides a silicon carbide device, a manufacturing method thereof, and an electronic device, which can improve the conduction capability, radiation resistance, and reverse withstand voltage capability of the silicon carbide device.

[0004] The silicon carbide device, the manufacturing method thereof and the electronic device provided in the embodiments of the present disclosure are specifically described as follows:

[0005] In one aspect, an embodiment of the present disclosure provides a silicon carbide device, comprising:

[0006] a first n-drift layer;

[0007] a second n-type doped drift layer, located on one side of the first n-drift layer;

[0008] A p-well layer, located on a side of the second n-type doped drift layer away from the first n-drift layer;

[0009] An n+ electrode layer is located on a side of the p-well layer away from the second n-type doped drift layer;

[0010] A plurality of grooves are provided, wherein the grooves penetrate the n+ electrode layer, the p-well layer and the second n-type doped drift layer, and the directions of the grooves are Crystal direction, the stripe cell area is between the adjacent grooves;

[0011] The p-protection layer includes a connection portion, which covers a portion of the side surface of the groove on at least one side of the stripe cell area and is blankly arranged on a portion of the side surface of the groove on at least one side of the stripe cell area.

[0012] In some embodiments, in the above-mentioned silicon carbide device provided by the embodiments of the present disclosure, the connecting parts are arranged at intervals on the side of the groove on one side of the cell region.

[0013] In some embodiments, in the above-mentioned silicon carbide device provided by the embodiments of the present disclosure, the connecting parts are arranged in parallel on the side surfaces of the grooves on both sides of the strip cell region.

[0014] In some embodiments, in the above-mentioned silicon carbide device provided by the embodiments of the present disclosure, the connecting portions are at least partially staggeredly arranged on the side surfaces of the grooves on both sides of the strip cell region.

[0015] In some embodiments, in the above-mentioned silicon carbide device provided by the embodiments of the present disclosure, the connecting parts are arranged in parallel on two sides of the grooves between the cell regions.

[0016] In some embodiments, in the above-mentioned silicon carbide device provided by the embodiments of the present disclosure, the connecting portion is at least partially staggeredly arranged on two sides of the groove between the cell regions.

[0017] In some embodiments, in the silicon carbide device provided in the embodiments of the present disclosure, the bottom surface of the groove includes a first bottom surface connected to the side surface of the groove, and a second bottom surface located between the first bottom surfaces; the side surface of the groove includes a first side surface covered by the connecting portion, and a second side surface not covered by the connecting portion;

[0018] The p-protective layer also includes a bottom located in the groove, the bottom having a first thickness at the first bottom surface connected to the second side surface, the bottom having a second thickness at the first bottom surface connected to the first side surface, and the bottom having a third thickness at the second bottom surface, the first thickness is less than the second thickness, and the second thickness is greater than or equal to the third thickness.

[0019] In some embodiments, in the silicon carbide device provided in the embodiments of the present disclosure, the side surface of the groove includes a first side surface covered by the connecting portion and a second side surface not covered by the connecting portion, the strip cell region includes an electrode contact region, and the n+ electrode layer includes a first n+ electrode portion and a second n+ electrode portion connected to each other, the first n+ electrode portion is adjacent to the groove, and the second n+ electrode portion is located between the first n+ electrode portion and the electrode contact region;

[0020] The p-protective layer also includes a first terrace portion and a second terrace portion, the first terrace portion covers the first n+ electrode portion and the second n+ electrode portion adjacent to the first side surface, the second terrace portion at least covers the second n+ electrode portion on the side where the second side surface is located, and the thickness of the second terrace portion is less than or equal to the thickness of the first terrace portion.

[0021] In some embodiments, in the above-mentioned silicon carbide device provided by the embodiments of the present disclosure, the second mesa portion covers the first n+ electrode portion and the second n+ electrode portion adjacent to the second side surface, and the thickness of the second mesa portion is less than the thickness of the first mesa portion.

[0022] In some embodiments, in the above-mentioned silicon carbide device provided by the embodiments of the present disclosure, the thickness of the first n+ electrode portion adjacent to the second side surface is equal to the thickness of the second n+ electrode portion connected thereto.

[0023] In some embodiments, in the above-mentioned silicon carbide device provided in the embodiments of the present disclosure, the second table portion covers the second n+ electrode portion on the side where the second side surface is located, and is left blank at the first n+ electrode portion adjacent to the second side surface, and the thickness of the second table portion is equal to the thickness of the first table portion.

[0024] In some embodiments, in the above-mentioned silicon carbide device provided by the embodiments of the present disclosure, the thickness of the first n+ electrode portion adjacent to the second side surface is smaller than the thickness of the second n+ electrode portion connected thereto.

[0025] In some embodiments, in the above-mentioned silicon carbide device provided in the embodiments of the present disclosure, the thickness of the first n+ electrode portion adjacent to the first side surface is equal to the thickness of the second n+ electrode portion connected thereto, and the thickness of the second n+ electrode portion on the side where the first side surface is located is equal to the thickness of the second n+ electrode portion on the side where the second side surface is located.

[0026] In some embodiments, in the above-mentioned silicon carbide device provided by the embodiments of the present disclosure, the n+ electrode layer is an n+ source layer or an n+ emitter layer.

[0027] On the other hand, an embodiment of the present disclosure provides a method for manufacturing the above-mentioned silicon carbide device, comprising:

[0028] A first n-drift layer, a second n-type doped drift layer, a p-well layer and an n+ electrode layer are stacked in sequence, and a plurality of grooves penetrating the n+ electrode layer, the p-well layer and the second n-type doped drift layer are formed by etching, wherein the grooves are directed in the direction of Crystal direction, the stripe cell area is between the adjacent grooves;

[0029] A p-protective layer is formed by epitaxial growth, wherein the p-protective layer includes a connecting portion, the connecting portion covers a portion of the side surface of the groove on at least one side of the stripe cell region, and is blankly arranged on a portion of the side surface of the groove on at least one side of the stripe cell region.

[0030] In some embodiments, in the above-mentioned manufacturing method provided in the embodiment of the present disclosure, a p-protective layer is formed by epitaxial growth, and the p-protective layer includes a connecting portion, and the connecting portion covers a portion of the side surface of the groove on at least one side of the stripe cell area, and is blankly arranged on a portion of the side surface of the groove on at least one side of the stripe cell area, specifically including:

[0031] Using silane, propane, hydrogen, hydrogen chloride and trimethylaluminum, epitaxially forming a p-protective layer extending from the inside of the trench to the side of the n+ electrode layer away from the p-well layer;

[0032] Depositing a hard mask on the p-protective layer, and performing processes such as coating, exposure, development, and etching on the hard mask so that the hard mask covers a portion of the side surface of the groove on at least one side of the stripe cell area, and forms an opening on a portion of the side surface of the groove on at least one side of the stripe cell area;

[0033] Under the shielding of the hard mask, the p-protective layer at the opening of the hard mask is removed by Cl2 thermal chemical etching or capacitively coupled plasma etching, so that the p-protective layer includes a connection portion covering a portion of the side surface of the groove on at least one side of the strip cell area and a blank setting on a portion of the side surface of the groove on at least one side of the strip cell area.

[0034] In some embodiments, in the above-mentioned manufacturing method provided by the embodiments of the present disclosure, the strip cell region includes an edge region adjacent to the groove and an electrode contact region located between the edge regions, the edge region includes a first partition and a second partition arranged at intervals, the electrode contact region includes a first electrode contact region arranged in parallel with the first partition, and a second electrode contact region arranged in parallel with the second partition; the n+ electrode layer includes a first n+ electrode portion and a second n+ electrode portion located in the first partition and the second partition, the first n+ electrode portion is adjacent to the groove, and the second n+ electrode portion is located between the first n+ electrode portion and the first electrode contact region and the second electrode contact region; the bottom surface of the groove includes a first bottom surface connected to the side surface of the groove, and a second bottom surface located between the first bottom surface;

[0035] The hard mask covers a portion of the side surface of the groove on at least one side of the stripe cell region and forms an opening on a portion of the side surface of the groove on at least one side of the stripe cell region, including:

[0036] The hard mask at most covers the first sub-area, the electrode contact area, the first bottom surface between the first sub-areas, and the second bottom surface between the edge areas, and forms an opening at least in the second sub-area and the first bottom surface between the second sub-areas;

[0037] The p-protective layer includes a connection portion covering a portion of the side surface of the groove on at least one side of the stripe cell region and provided blank on a portion of the side surface of the groove on at least one side of the stripe cell region, specifically including:

[0038] The p-protective layer includes a connecting portion, a bottom, a first table portion and a second table portion, wherein the connecting portion covers the side surfaces of the groove on both sides of the first partition, and is blankly arranged on the side surfaces of the groove on both sides of the second partition; the bottom covers the first bottom surface and the second bottom surface, and the first thickness of the bottom at the first bottom surface between the second partitions is less than the second thickness of the bottom at the first bottom surface between the first partitions, and the second thickness of the bottom at the first bottom surface between the first partitions is greater than or equal to the third thickness of the bottom at the second bottom surface; the first table portion covers the first n+ electrode portion and the second n+ electrode portion of the first partition, the second table portion at least covers the second n+ electrode portion of the second partition, the thickness of the second table portion is less than or equal to the thickness of the first table portion, and the thickness of the first n+ electrode portion is less than or equal to the thickness of the second n+ electrode portion.

[0039] In some embodiments, in the above manufacturing method provided by the embodiment of the present disclosure, the hard mask at most covers the first partition, the electrode contact region, the first bottom surface between the first partitions, and the second bottom surface between the edge regions, and at least forms an opening in the second partition and the first bottom surface between the second partitions, specifically comprising:

[0040] The hard mask covers the first sub-area, the electrode contact area, and the first bottom surface and the second bottom surface between the first sub-areas, and forms openings at the second sub-area and the first bottom surface and the second bottom surface between the second sub-areas;

[0041] The first thickness of the bottom at the first bottom surface between the second partitions is less than the second thickness of the bottom at the first bottom surface between the first partitions, and the second thickness of the bottom at the first bottom surface between the first partitions is greater than or equal to the third thickness of the bottom at the second bottom surface, specifically including:

[0042] A first thickness of the bottom at the first bottom surface between the second partitions is equal to a third thickness of the bottom at the second bottom surface between the second partitions, and a second thickness of the bottom at the first bottom surface between the first partitions is greater than the third thickness of the bottom at the second bottom surface between the second partitions;

[0043] The second mesa portion at least covers the second n+ electrode portion of the second partition, the thickness of the second mesa portion is less than or equal to the thickness of the first mesa portion, and the thickness of the first n+ electrode portion is less than or equal to the thickness of the second n+ electrode portion, specifically including:

[0044] The second table portion covers the second n+ electrode portion of the second partition and is left blank at the first n+ electrode portion of the second partition. The thickness of the second table portion is equal to the thickness of the first table portion. The thickness of the first n+ electrode portion on the side where the second table portion is located is less than the thickness of the second n+ electrode portion.

[0045] In some embodiments, in the above manufacturing method provided by the embodiment of the present disclosure, the hard mask at most covers the first partition, the electrode contact region, the first bottom surface between the first partitions, and the second bottom surface between the edge regions, and at least forms an opening in the second partition and the first bottom surface between the second partitions, specifically comprising:

[0046] The hard mask covers the first sub-area, the first electrode contact area, and the first bottom surface and the second bottom surface between the first sub-areas, and forms openings at the second sub-area, the second electrode contact area, and the first bottom surface and the second bottom surface between the second sub-area;

[0047] The first thickness of the bottom at the first bottom surface between the second partitions is less than the second thickness of the bottom at the first bottom surface between the first partitions, and the second thickness of the bottom at the first bottom surface between the first partitions is greater than or equal to the third thickness of the bottom at the second bottom surface, specifically including:

[0048] A first thickness of the bottom at the first bottom surface between the second partitions is equal to a third thickness of the bottom at the second bottom surface between the second partitions, and a second thickness of the bottom at the first bottom surface between the first partitions is greater than the third thickness of the bottom at the second bottom surface between the second partitions;

[0049] The second mesa portion at least covers the second n+ electrode portion of the second partition, the thickness of the second mesa portion is less than or equal to the thickness of the first mesa portion, and the thickness of the first n+ electrode portion is less than or equal to the thickness of the second n+ electrode portion, specifically including:

[0050] The second mesa portion covers the first n+ electrode portion and the second n+ electrode portion of the second partition, the thickness of the second mesa portion is smaller than the thickness of the first mesa portion, and the thickness of the first n+ electrode portion is equal to the thickness of the second n+ electrode portion.

[0051] On the other hand, an embodiment of the present disclosure further provides an electronic device, including the above-mentioned silicon carbide device provided by an embodiment of the present disclosure.

[0052] The beneficial effects of the present disclosure are as follows:

[0053] The silicon carbide device, the manufacturing method thereof and the electronic device provided by the present disclosure include: a first n-drift layer; a second n-type doped drift layer, located on one side of the first n-drift layer; a p-well layer, located on the side of the second n-doped drift layer away from the first n-drift layer; an n+ electrode layer, located on the side of the p-well layer away from the second n-doped drift layer; a plurality of grooves, the grooves penetrate the n+ electrode layer, the p-well layer and the second n-doped drift layer, and the grooves point to crystal direction, the stripe cell region is between adjacent grooves; the p-protective layer includes a connecting portion, the connecting portion covers a portion of the side surface of the groove on at least one side of the stripe cell region, and is blankly arranged on a portion of the side surface of the groove on at least one side of the stripe cell region. In the present disclosure, the side surface of the groove without the connecting portion is used as the main conductive area, and the side surface of the groove covered by the connecting portion is used as the secondary conductive area, which can effectively improve the conduction capability, radiation resistance and reverse withstand voltage capability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 A top view of a silicon carbide device provided in an embodiment of the present disclosure;

[0055] Figure 2 For along Figure 1 A cross-sectional view of the line I-I';

[0056] Figure 3 For along Figure 1 Another cross-sectional view of the line I-I';

[0057] Figure 4 For along Figure 1 Another cross-sectional view of the line I-I';

[0058] Figure 5 For along Figure 1 A cross-sectional view of the line II-II';

[0059] Figure 6 For along Figure 1 Another cross-sectional view of line II-II';

[0060] Figure 7 For along Figure 1 Another cross-sectional view of line II-II';

[0061] Figure 8 Another top view of a silicon carbide device provided in an embodiment of the present disclosure;

[0062] Fig. 9 Another top view of a silicon carbide device provided in an embodiment of the present disclosure;

[0063] Fig.10 A curve characterizing the radiation resistance characteristics of a silicon carbide device provided in an embodiment of the present disclosure;

[0064] Fig.11 A flow chart of a method for manufacturing a silicon carbide device provided in an embodiment of the present disclosure;

[0065] Fig.12 A schematic diagram of an opening structure of a hard mask provided in an embodiment of the present disclosure;

[0066] Fig.13 A schematic diagram of another opening structure of a hard mask provided in an embodiment of the present disclosure;

[0067] Fig.14 A schematic diagram of another opening structure of a hard mask provided in an embodiment of the present disclosure;

[0068] Fig.15 A schematic diagram of another opening structure of a hard mask provided in an embodiment of the present disclosure;

[0069] Fig.16 A schematic diagram of another opening structure of a hard mask provided in an embodiment of the present disclosure;

[0070] Fig.17 A schematic diagram of another opening structure of a hard mask provided in an embodiment of the present disclosure;

[0071] Fig.18 A schematic diagram of another opening structure of a hard mask provided in an embodiment of the present disclosure;

[0072] Fig.19 A schematic diagram of another opening structure of a hard mask provided in an embodiment of the present disclosure;

[0073] Fig. 20 A schematic diagram of another opening structure of a hard mask provided in an embodiment of the present disclosure;

[0074] Fig.21 for Figure 12 to Figure 14 A cross-sectional view along line III-III' after the connection portion at the opening is removed by etching;

[0075] Fig. 22 For along Figures 12 to 20 Sectional view of line IV-IV';

[0076] Fig.23 For along Figures 15 to 17 A cross-sectional view along line V-V' after the connection portion at the opening is removed by etching;

[0077] Fig.24 For along Figures 18 to 20 A cross-sectional view along line VI-VI' after the connection portion at the opening is removed by etching;

[0078] Fig.25 A schematic diagram of a structure of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0079] Fig.26 Another structural schematic diagram of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0080] Fig. 27 Another structural schematic diagram of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0081] Fig.28 Another structural schematic diagram of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0082] Fig.29 Another structural schematic diagram of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0083] Fig.30 Another structural schematic diagram of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0084] Fig.31 Another structural schematic diagram of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0085] Fig.32 Another structural schematic diagram of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0086] Fig.33 Another structural schematic diagram of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0087] Fig.34 Another structural schematic diagram of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0088] Fig.35 Another structural schematic diagram of a silicon carbide device during the manufacturing process provided by an embodiment of the present disclosure;

[0089] Fig.36 Another schematic diagram of the structure of the silicon carbide device during the manufacturing process provided by the embodiment of the present disclosure. DETAILED DESCRIPTION

[0090] In order to make the purpose, technical solution and advantages of the embodiment of the present disclosure clearer, the technical solution of the embodiment of the present disclosure will be clearly and completely described in conjunction with the drawings of the embodiment of the present disclosure. It should be noted that in the drawings, the thickness of the layer, film, panel, area, etc. is magnified for clarity. In the present disclosure, exemplary embodiments are described with reference to cross-sectional views of schematic diagrams of idealized embodiments. In this way, deviations from the shape of the figure as a result of, for example, manufacturing technology and / or tolerances will be expected. Therefore, the embodiments described in the present disclosure should not be interpreted as being limited to the specific shape of the area shown in the present disclosure, but include deviations in shape caused by, for example, manufacturing. For example, an area illustrated or described as flat may typically have rough and / or nonlinear features; the illustrated sharp corners may be rounded, etc. Therefore, the areas shown in the figures are schematic in nature, and their sizes and shapes are not intended to illustrate the exact shape of the area, do not reflect the true proportion, and the purpose is only to illustrate the content of the present disclosure. And the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0091] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" and the like mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0092] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer may be directly on, directly connected to, or there may be an intermediate element or intermediate layer. When an element or layer is referred to as being "disposed on one side of" another element or layer, the element or layer may be directly on one side of, directly connected to, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0093] In some embodiments, the gate oxide layer covering the trench in the silicon carbide device is subjected to a large electric field stress, which causes the gate oxide layer on the bottom surface of the trench to be easily broken down, resulting in reduced reliability of the silicon carbide device. In order to improve reliability, a protective layer can be added between the trench and the gate oxide layer, but the protective layer on the side of the trench affects the conduction ability of the silicon carbide device to a certain extent.

[0094] In order to improve the above technical problems, the present disclosure provides a silicon carbide device, such as Figures 1 to 5 As shown, including:

[0095] n+ substrate 101, because the direction is The backfill symmetry of the connection portion pc on the groove side in the crystal direction is good, so the present disclosure does not need to limit the off-axis angle of the n+ substrate 101 to be less than 0.5° or even close to 0°. The off-axis off-axis angle is the angle between the normal direction of the wafer and the

[0001] crystal direction of silicon carbide during the process of cutting the wafer from the silicon carbide ingot.

[0096] The first n-drift layer 102 is located on one side of the n+ substrate 101 . In some embodiments, the first n-drift layer 102 may be formed by an epitaxial process, an ion implantation process, or an ion implantation process superimposed on an epitaxial process.

[0097] The second n-type doped drift layer 103 is located on a side of the first n- drift layer 102 away from the n+ substrate 101; the second n-type doped drift layer 103 may be Figures 2 to 5 As shown, the first n-drift layer 101 is integrally arranged, for example, the doping concentration of both is 1e 14 / cm 3 ~1e 16 / cm 3 Alternatively, the second n-type doped drift layer 103 may also be Figure 6The n+ drift layer (high nitrogen doping layer) is shown to form a super junction structure and charge balance with the p-protection layer 106; optionally, the doping concentration of the first n-drift layer 101 is 1e 14 / cm 3 ~1e 16 / cm 3 , the doping concentration of the second n-type doped drift layer 103 is 1e 16 / cm 3 ~5e 17 / cm 3 In some embodiments, the second n-type doped drift layer 103 may be formed by an epitaxial process, an ion implantation process, or an ion implantation process superimposed on an epitaxial process.

[0098] The p-well layer 104 is located on a side of the second n-type doped drift layer 103 away from the first n-drift layer 102 . In some embodiments, the p-well layer 104 may be formed by an epitaxial process, an ion implantation process, or an ion implantation process superimposed on an epitaxial process.

[0099] The n+ electrode layer 105 is located on the side of the p-well layer 104 away from the second n-type doped drift layer 103; in some embodiments, the n+ electrode layer 105 can be formed by an epitaxial process, an ion implantation process, or an ion implantation process superimposed on an epitaxial process. Figures 2 to 6 The MOSFET device shown can also be Figure 7 In the IGBT device shown, the n+ electrode layer 105 may be an n+ source layer of a MOSFET device or an n+ emitter layer of an IGBT device.

[0100] A plurality of trenches T penetrate the n+ electrode layer 105, the p-well layer 104 and the second n-type doped drift layer 103. The trenches T are oriented in the direction of Crystal direction, the stripe region S is between adjacent trenches T. Figure 1 The schematic diagram shows three stripe cell regions S. In a specific implementation, the total number of stripe cell regions S may be less than 3 or greater than 3, and the present disclosure does not limit this. In some embodiments, a groove T may be formed by dry etching. The groove T may be a U-shaped groove. Considering the influence of factors such as process and measurement, the direction is The crystal orientation of the trench T can be understood as the deviation of the direction of the trench T from the

[1120] crystal orientation is within 0.2°.

[0101] The p-protection layer 106 includes a connection portion pc, which covers a portion of the side surface of the groove T on at least one side of the cell region S, and is blankly arranged on a portion of the side surface of the groove T on at least one side of the cell region S. The inventors found that in order for the connection portion pc to completely cover the sides of the groove T on both sides of the cell region S, the connection portion pc must be relatively thin (for example, less than 40 nm) to ensure excellent conduction performance, and a thinner connection portion pc is not easy to manufacture. The present disclosure can improve the conduction capability of the silicon carbide device by removing the connection portion c on the portion of the side surface of the groove T on at least one side of the cell region S. On this basis, the thickness of the connection portion pc does not need to be thin (for example, not limited to less than 40 nm), thereby reducing the process difficulty of the connection portion pc, while also taking into account the reverse voltage withstand capability and radiation resistance of the silicon carbide device. In addition, at voltage levels below 1200V, the specific on-resistance of the MOSFET silicon carbide device is in the range of about 3mΩ·cm 2 ~6mΩ·cm 2 The channel resistance accounts for a high proportion of the on-resistance, accounting for a large proportion of the conduction loss, contributing ~0.5mΩ·cm 2 The present invention uses silicon carbide Compared with

[0001] , The mobility of the crystal plane is 2 to 3 times that of the silicon carbide device, which can effectively reduce the specific on-resistance of the silicon carbide device.

[0102] In some embodiments, in the above silicon carbide device provided in the embodiments of the present disclosure, if Figure 1 As shown, the connection parts pc are arranged at intervals on the side of the groove T on one side of the cell region S. In other words, the connection parts pc have notches on one side of the groove T, and the connection parts pc and the notches are arranged alternately. Figure 1 It can be seen that the connection portion pc can be arranged side by side on the sides of the grooves T on both sides of the cell region S, that is, the connection portion pc on the right side of the groove T on the left side of the cell region S is arranged side by side with the connection portion pc on the left side of the groove T on the right side of the cell region S. Figure 8 As shown, the connection portion pc may also be at least partially staggered on the sides of the grooves T on both sides of the cell region S, for example, the connection portion pc on the right side of the groove T on the left side of the cell region S and the connection portion pc on the left side of the groove T on the right side of the cell region S are completely staggered. Figure 1 As shown, the connection part pc can be arranged in parallel on the two sides of the groove T between the strip cell areas S; or Figure 8 and Fig. 9 As shown, the connection part pc can also be at least partially staggered on the two sides of the groove T between the cell areas S, for example, the connection parts pc on the left and right sides of the groove T between the cell areas S are staggered. The advantage of the staggered arrangement of the connection parts pc is that the conductive channel area is staggered, so that when a large current is conducted, the hot spots can be staggered.

[0103] In some embodiments, Figure 1 As shown, the strip cell area S may include an edge area S1, and an electrode contact area CT located between the edge areas S1, the edge area S1 includes a first partition S11 and a second partition S12 that are alternately arranged, a connecting portion pc is provided on the side of the groove T adjacent to the first partition S11, and there is no connecting portion pc on the side of the groove T adjacent to the second partition S12. In the process of etching away the connecting portion pc on the side adjacent to the second partition S12, the present disclosure may simultaneously etch away a certain thickness of the bottom pb on the first bottom surface b1 adjacent to the second partition S12, but has no etching effect on the bottom pb on the second bottom surface b2 between the first bottom surfaces b1. Therefore, the bottom pb in the groove T is raised in the middle and has low sides. In other words, in the groove T between the second partitions S12, the thickness h3 of the bottom pb at the second bottom surface b2 is greater than its thickness h1 at the first bottom surface b1. In other embodiments, such as Figure 2 and Figure 4 As shown, in the process of etching the connecting portion pc on the side of the groove T between the second sub-areas S12, the present disclosure may simultaneously etch away a bottom pb of a certain thickness on the first bottom surface b1 and the second bottom surface b2 between the second sub-areas S12. Therefore, in the groove T between the second sub-areas S12, the thickness h3 of the bottom pb at the second bottom surface b2 is equal to the thickness h1 of the bottom pb at the first bottom surface b1. In other embodiments, such as Figure 5 As shown, the present disclosure does not etch the connection portion pc on the side of the trench T between the first partitions S11, so in the trench T between the first partitions S11, the thickness h2 of the bottom pb at the first bottom surface b1 may be equal to its thickness h3 at the second bottom surface b2. Figure 5 The thickness h3 of the bottom pb at the second bottom surface b2 between the first partitions S11 is greater than Figure 2 , Figure 4 The bottom pb shown has a thickness h3 at the second bottom surface b2 between the second partitions, and Figure 5 The thickness h3 of the bottom pb at the second bottom surface b2 between the first partitions S11 is equal to Figure 3 The bottom portion pb is shown to have a thickness h3 at the second bottom surface b2 between the second subareas S12.

[0104] Based on this, in some embodiments, in the above silicon carbide device provided in the embodiments of the present disclosure, if Figures 2 to 5As shown, the bottom surface of the groove T includes a first bottom surface b1 connected to the side surface of the groove T, and a second bottom surface b2 located between the first bottom surface b1, and the side surface of the groove T includes a first side surface w1 covering the connection portion pc, and a second side surface w2 not covering the connection portion pc; the p-protection layer 106 may also include a bottom pb located in the groove T, the bottom pb has a first thickness h1 at the first bottom surface b1 connected to the second side surface w2 of the groove T not covering the connection portion pc, the bottom pb has a second thickness h2 at the first bottom surface b1 connected to the first side surface w1 of the groove T covering the connection portion pc, and the bottom pb has a third thickness h3 at the second bottom surface b2, the first thickness h1 is less than the second thickness h2, and the second thickness h2 is greater than or equal to the third thickness h3.

[0105] In some embodiments, in the above silicon carbide device provided in the embodiments of the present disclosure, if Figure 1 , Figure 2 and Figure 5 As shown, the n+ electrode layer 105 includes a first n+ electrode portion n1 and a second n+ electrode portion n2 connected to each other, the first n+ electrode portion n2 is adjacent to the trench T, and the second n+ electrode portion n2 is located between the first n+ electrode portion n1 and the electrode contact region CT, and optionally, the first n+ electrode portion n1 and the second n+ electrode portion n2 are arranged in the first partition S11 and the second partition S12. The p-protection layer 106 may also include a first terrace portion pm1 and a second terrace portion pm2, the first terrace portion pm1 covers the first n+ electrode portion n1 and the second n+ electrode portion n2 adjacent to the first side w1, and the second terrace portion pm2 covers the first n+ electrode portion n1 and the second n+ electrode portion n2 adjacent to the second side w2.

[0106] In some embodiments, during the process of etching away the connection portion pc on the second side w2, a portion of the second terrace portion pm2 may be etched away, while the connection portion pc on the first side w1 is not etched, so the thickness of the first terrace portion pm1 will not be affected by the etching of the connection portion pc. Figure 2 and Figure 5 As shown, the thickness h4 of the first platform portion pm1 can be greater than the thickness h5 of the second platform portion pm2; and thanks to the protection of the first platform portion pm1 and the second platform portion pm2, the thickness of the n+ electrode layer 105 is protected from the etching effect of removing the connecting portion pc on the first side w1, which means that the thickness h6 of the first n+ electrode portion n1 and the thickness h7 of the second n+ electrode portion n2 can be equal.

[0107] In some embodiments, during the process of etching away the connection portion pc on the second side surface w2, the edge of the second terrace portion pm2 close to the second side surface w2 may be etched away, but the thickness of the remaining portion of the second terrace portion pm2 remains unchanged, while the connection portion pc on the first side surface w1 is not etched, so the thickness of the first terrace portion pm1 will not be affected by the etching of the connection portion pc. Figures 3 to 5 As shown, the first table portion pm1 can cover the first n+ electrode portion n1 and the second n+ electrode portion n2 adjacent to the first side w1, the second table portion pm2 covers the second n+ electrode portion n2 connected to the first n+ electrode portion n1 adjacent to the second side w2, and is left blank at the first n+ electrode portion n1 adjacent to the second side w2, and the thickness h5 of the second table portion pm2 is equal to the thickness h4 of the first table portion pm1; thanks to the protection of the first table portion pm1 and the second table portion pm2, the thickness h6 of the first n+ electrode portion n1 on the side where the first side w1 is located, the thickness h7 of the second n+ electrode portion n2, and the thickness h7 of the second n+ electrode portion n2 on the side where the second side w2 is located will not be affected by the etching of removing the connecting portion pc on the first side w1, which means that the thickness h6 of the first n+ electrode portion n1 on the side where the first side w1 is located, the thickness h7 of the second n+ electrode portion n2, and the thickness h7 of the second n+ electrode portion n2 on the side where the second side w2 is located can be equal and greater than the thickness h6 of the first n+ electrode portion n1 on the side where the second side w2 is located.

[0108] In some embodiments, in the above silicon carbide device provided in the embodiments of the present disclosure, if Figures 1 to 6 As shown, it may also include a gate oxide layer 107, a gate 108 (for example, the gate 108 is made of polysilicon), a dielectric layer 109, a first metal layer 110, a p+ structure 111, a second metal layer 112 and an n-buffer layer 113; wherein the gate 108 and the first metal layer 110 are passivated and isolated by the dielectric layer 109, the dielectric layer 109, the gate oxide layer 107, and the p-protection layer 106 include contact holes that are connected and arranged, and the first metal layer 110 can be filled into the n+ electrode layer 105 or the p-well layer 104 through the contact holes. When the first metal layer 110 is filled into the n+ electrode layer 105 through the contact holes, the bottom pb is connected to the n+ electrode layer 105 through the connection part pc and the first mesa part pm1 to form an electric field shielding for the gate oxide layer 107. When the first metal layer 110 is filled into the p-well layer 104 through the contact hole, when the device is in the off state (reverse withstand voltage state), the parasitic PMOS clamps the bottom pb region of the device, and the bottom pb can directly form a connection with the n+ electrode layer 105 through the parasitic PMOS and the p-well layer 104 in sequence, thereby achieving a better electric field shielding effect on the gate oxide layer 107.

[0109] In addition, when the device withstands reverse voltage, the silicon carbide device forms an equivalent PMOS clamp transistor (accumulation type device, the conductive channel is realized by the connection part pc) at the bottom pb, the second n-type doped drift layer 103 and the p-well layer 104 along II-II' (secondary conductive area). Since the gate 108 is grounded, the potential of the second n-type doped drift layer 103 in the area below the p-well layer 104 is relatively high, and the PMOS clamp transistor is turned on, so that the bottom pb can be grounded through the parasitic PMOS designed here, increasing the protection of the corner of the gate oxide layer 107 and improving the gate oxide reliability. The silicon carbide device etches the connection part pc along the I-I' direction to improve the conductivity, so that the I-I' direction is the main conductive area.

[0110] The present disclosure also performs 2D TCAD radiation resistance simulation on the cross section along line II-II', such as Fig.10 As shown. Among them, Fig.10 The conditions corresponding to the black inverted triangle simulation curve are: Figure 5 In the cross section shown, the incident point of the irradiated particles is x0=5 μm (corresponding to the incident point at the interface between the gate oxide layer 107 and the connecting portion pc in the model), the voltage VD of the second metal layer 112 is 500 V, and the thickness of the connecting portion pc is Depend on Fig.10 It can be seen that the device lattice temperature at the peak of the black inverted triangle simulation curve is as high as 1770 K. The difference between the conditions of the blue diamond simulation curve and the black inverted triangle simulation curve is that the thickness of the connection part pc is The peak temperature of the blue diamond simulation curve is 1616K, which is 8.7% lower than that of the black inverted triangle simulation curve. The conditions corresponding to the brown cross simulation curve are: cross section of a classic trench gate device (not including the p-protective layer 106 disclosed in the present invention and the thickness of the gate oxide layer 107 is uniform), the VD voltage is 500V, and the peak temperature of the brown cross simulation curve is greater than 2000K. The difference between the conditions of the black equilateral triangle simulation curve and the black inverted triangle simulation curve is that the voltage VD of the second metal layer 112 is 400V, and its peak temperature is 1336K. The difference between the conditions of the brown asterisk simulation curve and the conditions of the brown cross simulation curve is that the VD voltage is 400V, and the peak temperature of the brown asterisk simulation curve is 1548K.

[0111] It can be seen that, assuming that the SEU failure peak temperature of the silicon carbide device is 1500K, Fig.10 The thickness of the connecting part pc is When the SEU is 1500K, the VSEB is ~500V; for the classic trench gate 2-D device, the VSEB is ~400V when the SEU failure peak temperature is 1500K. The present disclosure increases the SEB voltage threshold of the device for single particle irradiation by more than 20%. In addition, increasing the thickness of the connection part pc can enhance the radiation resistance of the device. The conductive part of the present disclosure can improve the conduction capability in the I-I' direction, and the II-II' direction can mainly provide gate oxide protection and enhance the radiation resistance as a protective structure, so there is no need to limit the thickness of the connection part pc to less than 40nm. In other words, the thickness of the connection part pc of the present disclosure can be greater than or equal to 40nm to improve the radiation resistance.

[0112] In some embodiments, in the above silicon carbide device provided in the embodiments of the present disclosure, if Figure 7 As shown, a p+ collector 114 may also be included, thereby retaining Figures 2 to 6 The device structure of the MOSFET shown in the figure realizes the structure and function of the IGBT at the same time. When the IGBT device is in the off state, the voltage of the top of the second n-type doped drift layer 103 and the contact area of ​​the p-well layer 104 is relatively high. At this time, the base voltage of the parasitic PMOS (accumulation type) is higher than the gate 108, thereby clamping the bottom pb area of ​​the device. This clamped bottom pb area reflects a strong electric field shielding effect, which greatly improves the reliability of the gate oxide layer 107 in the reverse withstand voltage scenario. Furthermore, when the device is forward-conducted and works in the saturation region, the VCE is low, and there is a parasitic transistor PNP structure formed by the p+ collector 114 (parasitic PNP transistor emitter), the second n-doped drift layer 103 and the n-buffer layer 113 (parasitic PNP transistor base) under the trench T, and the bottom pb (parasitic PNP transistor collector). When the gate 108 injects a large number of electrons into the second n-type doped drift layer 103, the parasitic transistor PNP emitter injects a large number of holes. The holes are blocked by the bottom pb. At the same time, due to the low VCE, the parasitic PMOS at the edge of the gate 108 is also in the off state, resulting in a large number of holes in the bottom pb area (charge storage effect), which reduces Von. The above mechanism explains Figure 1 Both the secondary conductive region in the II-II' direction and the primary conductive region in the II-I' direction are established.

[0113] Based on the same inventive concept, the present disclosure provides a method for manufacturing the above-mentioned silicon carbide device, such as Fig.11 As shown, the following steps may be included:

[0114] S1101, forming a first n-drift layer, a second n-type doped drift layer, a p-well layer and an n+ electrode layer stacked in sequence, and etching to form a plurality of grooves penetrating the n+ electrode layer, the p-well layer and the second n-type doped drift layer, the direction of the grooves being Crystal direction, the stripe area is between adjacent grooves.

[0115] S1102, epitaxially forming a p-protective layer, the p-protective layer comprising a connecting portion, the connecting portion covering a portion of the side surface of at least one side of the groove in the stripe cell region, and being blankly arranged on a portion of the side surface of at least one side of the groove in the stripe cell region.

[0116] In some embodiments, in the above-mentioned manufacturing method provided by the embodiment of the present disclosure, the above-mentioned step S1102 forms a p-protective layer by epitaxial growth, and the p-protective layer includes a connecting portion, and the connecting portion covers a portion of the side surface of at least one side of the groove of the stripe cell area, and is blankly arranged on a portion of the side surface of at least one side of the groove of the stripe cell area. Specifically, the following steps may be included:

[0117] Firstly, silane, propane, hydrogen, hydrogen chloride and trimethylaluminum are used to epitaxially form a p-protective layer extending from the inside of the trench to the side of the n+ electrode layer away from the p-well layer.

[0118] Then, a hard mask is deposited on the p-protective layer, and a coating, exposure, development and etching process are performed on the hard mask so that the hard mask covers part of the side surface of at least one side of the groove in the stripe cell area and forms an opening on part of the side surface of at least one side of the groove in the stripe cell area.

[0119] Finally, under the shielding of the hard mask, the p-protective layer at the opening of the hard mask is removed by Cl2 thermal chemical etching or capacitively coupled plasma etching, so that the p-protective layer includes a portion of the side surface of the groove covering at least one side of the strip cell area, and a blank connection portion on the portion of the side surface of the groove on at least one side of the strip cell area.

[0120] In some embodiments, in the above-mentioned manufacturing method provided in the embodiment of the present disclosure, in order to completely etch away the connecting portion on the side of the groove T between the second partitions, the above-mentioned hard mask covers a portion of the side of the groove on at least one side of the strip cell area, and forms an opening on a portion of the side of the groove on at least one side of the strip cell area. Specifically, it may include: the hard mask covers at most the first partition, the electrode contact area, the first bottom surface between the first partitions, and the second bottom surface between the edge areas, and forms an opening at least in the second partition and the first bottom surface between the second partitions.

[0121] For example, Figure 12 to Figure 14 In the embodiment, the hard mask hm covers the first partition S11, the electrode contact region ET, the first bottom surface b1 between the first partitions S11, and the second bottom surface b2 between the edge regions S1, and forms an opening O at the second partition S12 and the first bottom surface b1 between the second partitions S12. Figures 15 to 17 and Figure 12 to Figure 14In comparison, the opening O of the hard mask hm is enlarged, and the specific difference is that the hard mask hm does not cover the second bottom surfaces b2 between the second partitions S12, but the opening O is formed at the second bottom surfaces b2 between the second partitions S12. Figures 18 to 20 and Figures 15 to 17 In comparison, the opening O of the hard mask hm is further enlarged, and the specific difference is that the hard mask hm does not cover the second electrode contact area ET2, but forms an opening O at the second electrode contact area ET2. A larger opening O can effectively reduce the difficulty of the opening process.

[0122] Since the p-protective layer 106 at the opening O is etched away, the above-mentioned p-protective layer includes a connection portion that covers a portion of the side surface of the groove on at least one side of the strip cell area, and is blankly set on a portion of the side surface of the groove on at least one side of the strip cell area. Specifically, it can be: the p-protective layer includes a connection portion, a bottom, a first table portion, and a second table portion, wherein the connection portion covers the side surfaces of the grooves on both sides of the first partition, and is blankly set on the side surfaces of the grooves on both sides of the second partition; the bottom covers the first bottom surface and the second bottom surface, and the first thickness of the bottom at the first bottom surface between the second partitions is less than the second thickness of the bottom at the first bottom surface between the first partitions, and the second thickness of the bottom at the first bottom surface between the first partitions is greater than or equal to the third thickness of the bottom at the second bottom surface; the first table portion covers the first n+ electrode portion and the second n+ electrode portion of the first partition, the second table portion covers at least the second n+ electrode portion of the second partition, the thickness of the second table portion is less than or equal to the thickness of the first table portion, and the thickness of the first n+ electrode portion is less than or equal to the thickness of the second n+ electrode portion.

[0123] For example, in the etching process, Figure 12 to Figure 14 After the p-protection layer 106 at the opening O is formed, Fig.21 and Fig. 22As shown, the p-protection layer 106 includes a connection portion pc, a bottom portion pb, a first table portion pm1, and a second table portion pm2, wherein the connection portion pc covers the side surfaces of the groove T on both sides of the first partition S11 (i.e., the first side surface w1), and is blankly arranged on the side surfaces of the groove T on both sides of the second partition S12 (i.e., the second side surface w2); the bottom pb covers the first bottom surface b1 and the second bottom surface b2, and the first thickness h1 of the bottom pb at the first bottom surface b1 between the second partitions S12 is less than the third thickness h3 of the bottom pb at the second bottom surface b2 between the second partitions S12, and the second thickness h2 of the bottom pb at the first bottom surface b1 between the first partitions S11 is equal to the third thickness h3 of the bottom pb at the second bottom surface b2 between the edge regions S1 The thickness of the first mesa portion pm1 is h3; the first mesa portion pm1 covers the first n+ electrode portion n1 and the second n+ electrode portion n2 of the first partition S11, the second mesa portion pm2 covers the second n+ electrode portion n2 of the second partition S12, and is blank at the first n+ electrode portion n1 of the second partition S12, the thickness h5 of the second mesa portion pm2 is equal to the thickness h4 of the first mesa portion pm1, the thickness h6 of the first n+ electrode portion n1 of the second partition S12 is less than the thickness h7 of the second n+ electrode portion n2 of the second partition S12, and the thickness h7 of the second n+ electrode portion n2 of the second partition S12, the thickness h6 of the first n+ electrode portion n1 of the first partition S11, and the thickness h7 of the second n+ electrode portion n2 of the first partition S11 are the same. In this embodiment, the bottom pb thickness at the second bottom surface b2 of the groove T is relatively large, which ensures a better hole extraction capability and can improve the reverse withstand voltage capability of the device.

[0124] In etching removal Figure 12 to Figure 14 Device cross section after the p-protection layer 106 at the opening O is removed by etching Figures 15 to 17 In the device cross section after the p-protection layer 106 at the opening O, the transverse cross sections are different but the longitudinal cross sections are the same. Fig.23 For etching removal Figures 15 to 17 The transverse cross section behind the p-protection layer 106 at the opening O, Fig.21 For etching removal Figure 12 to Figure 14 Transverse cross section after the p-protection layer 106 at the opening O. Fig.21 and Fig.23 visible, Fig.23 The thickness h1 of the bottom pb at the first bottom surface b1 and the thickness h3 at the second bottom surface b2 between the second side surface w2 are the same, and both are less than Fig.21 The middle bottom portion pb has a thickness h2 at the first bottom surface b1 between the first side surfaces w1 .

[0125] In etching removal Figures 18 to 20 Device cross section after the p-protection layer 106 at the opening O is removed by etching Figures 15 to 17In the device cross section after the p-protection layer 106 at the opening O, the transverse cross sections are different but the longitudinal cross sections are the same. Fig.24 For etching removal Figures 18 to 20 The transverse cross section behind the p-protection layer 106 at the opening O, Fig.23 For etching removal Figures 15 to 17 Transverse cross section after the p-protection layer 106 at the opening O. Fig.23 and Fig.24 visible: Fig.24 The second mesa portion pm2 covers the first n+ electrode portion n1 and the second n+ electrode portion n2 near the second side surface w2, and the thickness h5 of the second mesa portion pm2 is less than Fig.23 The thickness h4 of the first mesa portion pm1 in the middle; the thickness h6 of the first n+ electrode portion n1 near the second side w2 is equal to the thickness h7 of the second n+ electrode portion n2, and is equal to Fig.23 The thickness h7 of the second n+ electrode portion n2 near the first side surface w1.

[0126] It should be noted that in the embodiments provided in the present disclosure, due to the limitations of process conditions or the influence of other factors such as measurement, the "same", "equal" and "equal to" in the present disclosure may be completely equivalent, or there may be some deviations. Therefore, the relationship of "same", "equal" and "equal to" between the above features, as long as the error is allowed, belongs to the protection scope of the present disclosure.

[0127] In order to better understand the above-mentioned production method provided by the present disclosure, the following Figure 1 , Figure 2 and Figure 5 The manufacturing process of the silicon carbide device shown in FIG. 1 is described in detail as an example. In some embodiments, Figure 1 , Figure 2 and Figure 5 The manufacturing process of the MOSFET silicon carbide device shown may include the following steps:

[0128] The first step, such as Fig.25 As shown, an n-buffer layer 113, an n-drift layer (including the first n-drift layer 102 and the second n-drift layer 103), a p-well layer 104, and an n+ electrode layer 105 (for example, an n+ source layer) are sequentially stacked from bottom to top on an n+ substrate 101 by multiple epitaxy. In some embodiments, the n-buffer layer 113, the n-drift layer (including the first n-drift layer 102 and the second n-drift layer 103), the p-well layer 104, and the n+ electrode layer 105 may also be formed by an ion implantation process or an ion implantation process superimposed on an epitaxial process. In some embodiments, a p+ structure 111 that penetrates the n+ electrode layer 105 and is at least partially embedded in the p-well layer 105 may also be formed. In some embodiments, the p+ structure 111 may not be provided, and the present disclosure does not specifically limit this.

[0129] The second step is, Fig.26 As shown, dry etching can be used to etch a pattern pointing to The crystal direction trench T has a surface CD of 0.5 μm to 2 μm and a depth of 5 μm to 25 μm.

[0130] In the third step, the trench T is backfilled with p-type silicon carbide by secondary epitaxy to obtain the initial pattern of the p-protective layer 106. At this time, the backfill morphology of the p-protective layer 106 in the trench T is as follows: Fig. 22 As shown. In some embodiments, epitaxial backfill uses a standard silicon carbide epitaxial process: silane, propane, and hydrogen are used as carrier gases. Trimethylaluminum (TMA) is used as a source gas for p-type doping, and the silicon-carbon ratio of the source gas is 1:1; the growth temperature and pressure are 1650°C and 60kPa, respectively, and the growth time is 3h to 6h. The gas flow rates of silane, propane, hydrogen chloride (HCl), and H2 are 36sccm, 12sccm, 1.8slm, and 40slm, respectively. Silane, propane, and hydrogen are used as carrier gases, and trimethylaluminum is used as a source gas for p-type doping. The addition of hydrogen chloride is to have a certain etching effect on the surface of the trench T during the epitaxial process to prevent the trench from closing prematurely during the backfill process, while keeping the p-protective layer 106 thinner on the side of the trench T and the n+ electrode layer 105.

[0131] The fourth step is Fig.18 As shown, a hard mask hm is deposited on the p-protection layer 106, and the hard mask hm is subjected to coating, exposure, development, and etching processes so that the hard mask hm covers the first partition S11, the first electrode contact area ET1, the first bottom surface b1 and the second bottom surface b2 between the first partition S11, and forms an opening O at the first bottom surface b1 and the second bottom surface b2 between the second partition S12, the second electrode contact area ET2, and the second partition S12.

[0132] Step 5: Under the shielding of the hard mask hm, the p-protective layer 106 at the opening O of the hard mask hm is removed by Cl2 thermochemical etching or CCP etching to form the final pattern of the p-protective layer 106. Under the protection of the hard mask hm, the morphology of the connection portion pc on the first side w1 is maintained. Fig. 22 The morphology shown remains unchanged; while the connecting portion pc located in the opening O on the second side surface w2 is etched away, as shown in FIG. Fig.24 As shown. At the same time, during the etching process, Fig.24 The bottom pb between the second side faces w2 and the second mesa portion pm2 are partially etched, so that the thickness of the bottom pb between the second side faces w2 is reduced (ie, less than Fig. 22 The thickness of the bottom pb between the first side faces w1 shown in the figure is reduced, and the thickness of the second terrace portion pm2 is also reduced (ie, less than Fig. 22The thickness of the first surface pm1 is shown).

[0133] In some embodiments, the thermal chemical etching process can use OX as a hard mask and Cl2 as an etching gas to achieve isotropic chemical etching. The process temperature is 900°C, and Cl2 reacts on the surface with the SiC material connection part pc located in the opening O on the side of the second trench T2 to generate C and SiCl4. The generated C reacts with O2 to become CO2 gas. SiCl4 (boiling point 56.8°C) and CO2 become gas at high temperature and leave the surface of the trench T. The etching reaction time needs to be controlled within 15 minutes to ensure that the etching thickness is low and will not have a significant impact on the morphology of the trench T. At the same time, the sub-trench structure that may be generated by the third step of etching can be repaired. In a normal pressure chlorine environment, at a temperature of 900°C, hot etching is performed for 15 minutes, and the lateral etching depth of the sidewall caused by etching is about 0.2μm, and the bottom etching depth is about 0.7μm. If the etching of the corresponding 40nm thick connection part pc is taken as an example, the etching time is 3 minutes. The CCP etching conditions are preferably: 0.4 mbar, 10 sccm, SF6, 100 W, 450°C.

[0134] Step 6: Fig. 27 and Fig.28 As shown, the gate oxide layer 107 is deposited by LPCVD, using tetraethyl orthosilicate (TEOS, Si(OC2H5)4) and oxygen as reactive gaseous precursors, and 50nm to 100nm of silicon dioxide is deposited at 700℃ to 800℃, followed by high-temperature annealing at 1150℃ in a nitric oxide environment (PDA) for 1.5h.

[0135] Step 7: Fig.29 and Fig.30 As shown, polysilicon is deposited by LPCVD, and SiH4 is used as a source gas at a low temperature (600°C) to deposit the polysilicon layer. A thermal chemical vapor deposition method can also be used to deposit the polysilicon layer, and then dry etching is performed so that the polysilicon layer is only retained in the first trench T1 and the second trench T2 as the gate 108. In addition, from the perspective of the device structure, the horizontal position of the bottom surface of the gate 108 is lower than the horizontal position of the bottom surface of the p-well layer 104.

[0136] Step 8: Fig.31 and Fig.32 As shown, an oxide layer (eg, silicon dioxide) is deposited on the surface of the device as a dielectric layer 109 , so as to achieve passivation isolation between the gate 108 and the subsequent first metal layer 110 through the dielectric layer 109 .

[0137] Step 9: Fig.33 and Fig.34As shown, the electrode contact area CT on the surface of the device is defined by the "resin coating-exposure-development" method on the surface of the dielectric layer 109; further, etching is performed in two steps, the first step is to remove the dielectric layer 109 and the gate oxide layer 107 in the CT area, and the second step is to etch the silicon carbide epitaxial layer in the CT area. The etching depth must penetrate the first terrace pm1 and the second terrace pm2 of the surface layer according to the by time mode, and reach (or penetrate) the n+ electrode layer 105. The lateral CD of the first terrace pm1 and the second terrace pm2 must be greater than the lateral opening CD of the etching. Further, polysilicon is interconnected at the bottom of the dielectric layer 109 and gathered in the polysilicon pad and the polysilicon bar; the openings of the polysilicon pad and the polysilicon bar can also be obtained on the surface of the dielectric layer 109 by the "resin coating-exposure-development" method, and further interconnected with the surface gate metal pad in the subsequent process.

[0138] Step 10: Fig.35 and Fig.36 As shown, a first metal layer 110 (e.g., a source metal layer) is deposited, and the first metal layer 110 is filled into the electrode contact region CT etched in the previous step, and annealing is performed to achieve ohmic contact between the first metal layer 110 and the n+ electrode layer 105. Then, the source pad and gate pad of the device are defined by dry etching of the surface.

[0139] Step 11: Figure 1 , Figure 2 and Figure 5 As shown, on the back side of the device, the n+ substrate 101 is subjected to CMP thinning, back side metallization and laser annealing to form an ohmic contact second metal layer 112 (eg, drain ohmic metal layer), thereby completing the device manufacturing.

[0140] against Figure 7 The IGBT silicon carbide device shown, based on the above-mentioned MOSFET silicon carbide device manufacturing process, can form a p+ collector 114 on the n+ substrate 101 through a standard epitaxial process / flipped wafer process before epitaxially forming an n-buffer layer 113 on the n+ substrate 101 in the first step, and in the eleventh step, in order to enhance the ohmic contact effect, the n+ substrate 101 can be thinned or even removed through CMP, so that the p+ collector 114 directly forms an ohmic contact with the second metal layer 112 (for example, the collector metal layer).

[0141] It should be noted that in the above-mentioned manufacturing method provided in the embodiment of the present invention, the patterning process involved in forming each layer structure may include not only deposition, photoresist coating, masking, exposure, development, etching, photoresist stripping and other partial or complete process, but also other process, which is subject to the pattern of the required composition formed in the actual manufacturing process and is not limited here. For example, a post-baking process may also be included after development and before etching.

[0142] Based on the same inventive concept, an embodiment of the present invention further provides an electronic device, including the above-mentioned silicon carbide device provided by the embodiment of the present disclosure. Since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the above-mentioned silicon carbide device, the implementation of the electronic device provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned silicon carbide device provided by the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0143] In some embodiments, the electronic device of the disclosed embodiment may be an on-board chip of different specifications such as 650V, 750V, 1200V, etc. Further, the silicon carbide device designed based on this scheme can also be applied to high-voltage solid-state transformers of high-speed railways, power grids (distribution and transmission grids), high-voltage photovoltaics, and other scenarios. The electronic devices include but are not limited to: AC motors, inverters, switching power supplies, lighting circuits, etc.

[0144] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A silicon carbide device, characterized in that: include: a first n-drift layer; a second n-type doped drift layer, located on one side of the first n-drift layer; A p-well layer, located on a side of the second n-type doped drift layer away from the first n-drift layer; An n+ electrode layer is located on a side of the p-well layer away from the second n-type doped drift layer; A plurality of grooves, wherein the grooves penetrate the n+ electrode layer, the p-well layer and the second n-type doped drift layer, and the directions of the grooves are [11 _ 20] crystal direction, the stripe cell region is between the adjacent grooves; The p-protection layer includes a connection portion, which covers a portion of the side surface of the groove on at least one side of the stripe cell area and is blankly arranged on a portion of the side surface of the groove on at least one side of the stripe cell area.

2. The silicon carbide device according to claim 1, characterized in that: The connecting parts are arranged at intervals on the side of the groove at one side of the strip cell area.

3. The silicon carbide device according to claim 2, characterized in that: The connecting parts are arranged in parallel on the sides of the grooves at both sides of the strip cell area.

4. The silicon carbide device according to claim 2, characterized in that: The connecting parts are at least partially staggeredly arranged on the side surfaces of the grooves on both sides of the strip cell area.

5. The silicon carbide device according to any one of claims 2 to 4, characterized in that: The connecting parts are arranged in parallel on two sides of the groove between the strip cell areas.

6. The silicon carbide device according to any one of claims 2 to 4, characterized in that: The connecting parts are at least partially staggeredly arranged on two sides of the groove between the strip cell areas.

7. The silicon carbide device according to any one of claims 2 to 4, characterized in that: The bottom surface of the groove includes a first bottom surface connected to the side surfaces of the groove, and a second bottom surface located between the first bottom surfaces; the side surfaces of the groove include a first side surface covered by the connecting portion, and a second side surface not covered by the connecting portion; The p-protective layer also includes a bottom located in the groove, the bottom having a first thickness at the first bottom surface connected to the second side surface, the bottom having a second thickness at the first bottom surface connected to the first side surface, and the bottom having a third thickness at the second bottom surface, the first thickness is less than the second thickness, and the second thickness is greater than or equal to the third thickness.

8. The silicon carbide device according to any one of claims 2 to 4, characterized in that: The side surface of the groove includes a first side surface covered by the connecting portion and a second side surface not covered by the connecting portion, the strip cell region includes an electrode contact region, the n+ electrode layer includes a first n+ electrode portion and a second n+ electrode portion connected to each other, the first n+ electrode portion is adjacent to the groove, and the second n+ electrode portion is located between the first n+ electrode portion and the electrode contact region; The p-protective layer also includes a first terrace portion and a second terrace portion, the first terrace portion covers the first n+ electrode portion and the second n+ electrode portion adjacent to the first side surface, the second terrace portion at least covers the second n+ electrode portion on the side where the second side surface is located, and the thickness of the second terrace portion is less than or equal to the thickness of the first terrace portion.

9. The silicon carbide device according to claim 8, characterized in that: The second mesa portion covers the first n+ electrode portion and the second n+ electrode portion adjacent to the second side surface, and a thickness of the second mesa portion is smaller than a thickness of the first mesa portion.

10. The silicon carbide device according to claim 9, characterized in that: The thickness of the first n+ electrode portion adjacent to the second side surface is equal to the thickness of the second n+ electrode portion connected thereto.

11. The silicon carbide device according to claim 8, characterized in that: The second mesa portion covers the second n+ electrode portion on the side where the second side surface is located, and is left blank at the first n+ electrode portion adjacent to the second side surface. The thickness of the second mesa portion is equal to the thickness of the first mesa portion.

12. The silicon carbide device according to claim 11, characterized in that: The thickness of the first n+ electrode portion adjacent to the second side surface is smaller than the thickness of the second n+ electrode portion connected thereto.

13. The silicon carbide device according to claim 9 or 11, characterized in that: The thickness of the first n+ electrode portion adjacent to the first side surface is equal to the thickness of the second n+ electrode portion connected thereto, and the thickness of the second n+ electrode portion on the side where the first side surface is located is equal to the thickness of the second n+ electrode portion on the side where the second side surface is located.

14. The silicon carbide device according to any one of claims 1 to 4 and 9 to 12, characterized in that: The n+ electrode layer is an n+ source layer or an n+ emitter layer.

15. A method for manufacturing a silicon carbide device according to any one of claims 1 to 14, characterized in that: include: A first n-drift layer, a second n-type doped drift layer, a p-well layer and an n+ electrode layer are stacked in sequence, and a plurality of grooves penetrating the n+ electrode layer, the p-well layer and the second n-type doped drift layer are formed by etching, wherein the grooves are directed to [11 _ 20] crystal direction, the stripe cell region is between the adjacent grooves; A p-protective layer is formed by epitaxial growth, wherein the p-protective layer includes a connecting portion, the connecting portion covers a portion of the side surface of the groove on at least one side of the stripe cell region, and is blankly arranged on a portion of the side surface of the groove on at least one side of the stripe cell region.

16. The method of claim 15, wherein: Epitaxially forming a p-protective layer, the p-protective layer comprising a connecting portion, the connecting portion covering a portion of the side surface of the groove on at least one side of the stripe cell region, and being blankly arranged on a portion of the side surface of the groove on at least one side of the stripe cell region, specifically comprising: Using silane, propane, hydrogen, hydrogen chloride and trimethylaluminum, epitaxially forming a p-protective layer extending from the inside of the trench to the side of the n+ electrode layer away from the p-well layer; Depositing a hard mask on the p-protective layer, and performing processes such as coating, exposure, development, and etching on the hard mask so that the hard mask covers a portion of the side surface of the groove on at least one side of the stripe cell area, and forms an opening on a portion of the side surface of the groove on at least one side of the stripe cell area; Under the shielding of the hard mask, the p-protective layer at the opening of the hard mask is removed by Cl2 thermal chemical etching or capacitively coupled plasma etching, so that the p-protective layer includes a connection portion covering a portion of the side surface of the groove on at least one side of the strip cell area and a blank setting on a portion of the side surface of the groove on at least one side of the strip cell area.

17. The method of claim 16, wherein: The strip cell region includes an edge region adjacent to the groove and an electrode contact region located between the edge regions, the edge region includes a first partition and a second partition arranged at intervals, the electrode contact region includes a first electrode contact region arranged in parallel with the first partition, and a second electrode contact region arranged in parallel with the second partition; the n+ electrode layer includes a first n+ electrode portion and a second n+ electrode portion located in the first partition and the second partition, the first n+ electrode portion is adjacent to the groove, and the second n+ electrode portion is located between the first n+ electrode portion and the first electrode contact region and the second electrode contact region; the bottom surface of the groove includes a first bottom surface connected to the side surface of the groove, and a second bottom surface located between the first bottom surfaces; The hard mask covers a portion of the side surface of the groove on at least one side of the stripe cell region and forms an opening on a portion of the side surface of the groove on at least one side of the stripe cell region, including: The hard mask at most covers the first sub-area, the electrode contact area, the first bottom surface between the first sub-areas, and the second bottom surface between the edge areas, and forms an opening at least in the second sub-area and the first bottom surface between the second sub-areas; The p-protective layer includes a connection portion covering a portion of the side surface of the groove on at least one side of the stripe cell region and provided blank on a portion of the side surface of the groove on at least one side of the stripe cell region, specifically including: The p-protective layer includes a connecting portion, a bottom, a first table portion and a second table portion, wherein the connecting portion covers the side surfaces of the groove on both sides of the first partition, and is blankly arranged on the side surfaces of the groove on both sides of the second partition; the bottom covers the first bottom surface and the second bottom surface, and the first thickness of the bottom at the first bottom surface between the second partitions is less than the second thickness of the bottom at the first bottom surface between the first partitions, and the second thickness of the bottom at the first bottom surface between the first partitions is greater than or equal to the third thickness of the bottom at the second bottom surface; the first table portion covers the first n+ electrode portion and the second n+ electrode portion of the first partition, the second table portion at least covers the second n+ electrode portion of the second partition, the thickness of the second table portion is less than or equal to the thickness of the first table portion, and the thickness of the first n+ electrode portion is less than or equal to the thickness of the second n+ electrode portion.

18. The method of claim 17, wherein: The hard mask at most covers the first partition, the electrode contact region, the first bottom surface between the first partitions, and the second bottom surface between the edge regions, and forms an opening at least in the second partition and at the first bottom surface between the second partitions, specifically comprising: The hard mask covers the first sub-area, the electrode contact area, and the first bottom surface and the second bottom surface between the first sub-areas, and forms openings at the second sub-area and the first bottom surface and the second bottom surface between the second sub-areas; The first thickness of the bottom at the first bottom surface between the second partitions is less than the second thickness of the bottom at the first bottom surface between the first partitions, and the second thickness of the bottom at the first bottom surface between the first partitions is greater than or equal to the third thickness of the bottom at the second bottom surface, specifically including: A first thickness of the bottom at the first bottom surface between the second partitions is equal to a third thickness of the bottom at the second bottom surface between the second partitions, and a second thickness of the bottom at the first bottom surface between the first partitions is greater than the third thickness of the bottom at the second bottom surface between the second partitions; The second mesa portion at least covers the second n+ electrode portion of the second partition, the thickness of the second mesa portion is less than or equal to the thickness of the first mesa portion, and the thickness of the first n+ electrode portion is less than or equal to the thickness of the second n+ electrode portion, specifically including: The second table portion covers the second n+ electrode portion of the second partition and is left blank at the first n+ electrode portion of the second partition. The thickness of the second table portion is equal to the thickness of the first table portion. The thickness of the first n+ electrode portion on the side where the second table portion is located is less than the thickness of the second n+ electrode portion.

19. The method of claim 17, wherein: The hard mask at most covers the first partition, the electrode contact region, the first bottom surface between the first partitions, and the second bottom surface between the edge regions, and forms an opening at least in the second partition and at the first bottom surface between the second partitions, specifically comprising: The hard mask covers the first sub-area, the first electrode contact area, and the first bottom surface and the second bottom surface between the first sub-areas, and forms openings at the second sub-area, the second electrode contact area, and the first bottom surface and the second bottom surface between the second sub-area; The first thickness of the bottom at the first bottom surface between the second partitions is less than the second thickness of the bottom at the first bottom surface between the first partitions, and the second thickness of the bottom at the first bottom surface between the first partitions is greater than or equal to the third thickness of the bottom at the second bottom surface, specifically including: A first thickness of the bottom at the first bottom surface between the second partitions is equal to a third thickness of the bottom at the second bottom surface between the second partitions, and a second thickness of the bottom at the first bottom surface between the first partitions is greater than the third thickness of the bottom at the second bottom surface between the second partitions; The second mesa portion at least covers the second n+ electrode portion of the second partition, the thickness of the second mesa portion is less than or equal to the thickness of the first mesa portion, and the thickness of the first n+ electrode portion is less than or equal to the thickness of the second n+ electrode portion, specifically including: The second mesa portion covers the first n+ electrode portion and the second n+ electrode portion of the second partition, the thickness of the second mesa portion is smaller than the thickness of the first mesa portion, and the thickness of the first n+ electrode portion is equal to the thickness of the second n+ electrode portion.

20. An electronic device, characterized in that: A silicon carbide device comprising any one of claims 1 to 14.

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