Semiconductor device and preparation method thereof

Abstract

The invention relates to a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, an epitaxial layer, a gate and a gate insulating layer. The epitaxial layer is arranged on one side of the substrate, the epitaxial layer comprises two doped regions which are oppositely arranged along a first direction, and the first direction intersects with the thickness direction of the semiconductor device. The gate insulating layer is located between the epitaxial layer and the gate, the gate insulating layer comprises a first gate insulating part and a second gate insulating part, the orthographic projection of the first gate insulating part on the substrate is located between the orthographic projections of the two doped regions on the substrate, and the second gate insulating part is at least located between the doped regions and the gate; and the second gate insulation part is positioned on the peripheral side of the first gate insulation part. Wherein the thickness of the first gate insulation portion close to the doped region is smaller than the thickness of the first gate insulation portion away from the doped region, and the minimum thickness of the first gate insulation portion is larger than or equal to the thickness of the second gate insulation portion. The reliability of the semiconductor device can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] Vertical Double Diffused Metal-Oxide-Semiconductor (VDMOS) has the characteristics of high switching speed, high withstand voltage, low on-resistance, wide safe operating area and good thermal stability. It is widely used in power integrated circuits and power integrated systems such as switching power supplies, automotive electronics, aerospace, etc.

[0003] In the development of VDMOS device technology, how to improve the reliability of semiconductor devices has always been a research direction in semiconductor device technology. Summary of the invention

[0004] The semiconductor device and the method for manufacturing the same provided by the embodiments of the present application can improve the reliability of the semiconductor device.

[0005] In the first aspect, a semiconductor device is proposed according to an embodiment of the present application, and the semiconductor device includes a substrate, an epitaxial layer, a gate, and a gate insulating layer. The epitaxial layer is arranged on one side of the substrate, and the epitaxial layer includes two doped regions arranged opposite to each other along a first direction, and the first direction intersects with the thickness direction of the semiconductor device. The gate insulating layer is located between the epitaxial layer and the gate, and the gate insulating layer includes a first gate insulating portion and a second gate insulating portion. The orthographic projection of the first gate insulating portion on the substrate is located between the orthographic projections of the two doped regions on the substrate, and the second gate insulating portion is at least located between the doped region and the gate, and the second gate insulating portion is located on the peripheral side of the first gate insulating portion. Among them, the thickness of the first gate insulating portion close to the doped region is less than the thickness of the first gate insulating portion away from the doped region, and the minimum thickness of the first gate insulating portion is greater than or equal to the thickness of the second gate insulating portion.

[0006] According to a first aspect of the embodiment of the present application, the thickness of the first gate insulating portion gradually increases from the doping region to the first gate insulating portion.

[0007] According to a first aspect of an embodiment of the present application, the first gate insulating portion includes a first sub-portion and two second sub-portions, the two second sub-portions are arranged in sequence along a first direction, and the first sub-portion is arranged between the two second sub-portions, the thickness of the first sub-portion is greater than the thickness of at least part of the second sub-portion, and the orthographic projection of the second sub-portion on the substrate is located on the side of the first sub-portion close to the doping region.

[0008] According to a first aspect of the embodiment of the present application, the first sub-portion is symmetrically arranged along a perpendicular bisector of the shortest connecting line of the two doping regions along the first direction.

[0009] According to a first aspect of the embodiment of the present application, the two second sub-sections are symmetrically arranged about a perpendicular midline of the shortest connecting line of the two doping regions along the first direction.

[0010] According to a first aspect of an embodiment of the present application, the epitaxial layer includes a recessed portion, which is formed by a depression of a side of the epitaxial layer away from the substrate, and at least a portion of the first gate insulating portion is disposed in the recessed portion.

[0011] According to a first aspect of the embodiment of the present application, the first gate insulating portion and the second gate insulating portion are arranged flush with each other on a side facing the substrate.

[0012] In the second aspect, according to an embodiment of the present application, a method for preparing a semiconductor device is proposed, comprising: forming an epitaxial layer on one side of a substrate. Forming a first gate insulating portion on the side of the epitaxial layer facing away from the substrate. Forming a second gate insulating portion on the peripheral side of the first gate insulating portion, the first gate insulating portion and the second gate insulating portion form a gate insulating layer, and the minimum thickness of the first gate insulating portion is greater than or equal to the thickness of the second gate insulating portion. The first gate insulating portion and the second gate insulating portion form a gate insulating layer. Two doping regions arranged opposite to each other along a first direction are formed in the epitaxial layer, and the first direction intersects with the thickness direction of the semiconductor device. Among them, the orthographic projection of the first gate insulating portion on the substrate is located between the orthographic projections of the two doping regions on the substrate, the second gate insulating portion is located at least between the doping region and the gate, and the thickness of the first gate insulating portion close to the doping region is less than the thickness of the gate insulating portion away from the doping region.

[0013] According to the second aspect of the embodiment of the present application, the step of forming a first gate insulating portion on the side of the epitaxial layer facing away from the substrate includes: forming a first mask layer on the side of the epitaxial layer facing away from the substrate, the first mask layer including a first opening, the first opening exposing a first area of ​​the surface of the epitaxial layer facing away from the substrate. Forming a first dielectric portion in the first area and removing the first mask layer. In the case where the opening width of the first opening is less than the preset width, forming a second mask layer on the side of the epitaxial layer facing away from the substrate, the second mask layer including a second opening, the opening width of the first opening is less than the opening width of the second opening, the second opening exposing the first dielectric portion and a second area of ​​the surface of the epitaxial layer facing away from the substrate, the second area being located on the peripheral side of the first dielectric portion. Forming a second dielectric portion at least in the second area and removing the second mask layer, the thickness of the second dielectric portion being less than the thickness of the first dielectric portion. When the opening width of the second opening is smaller than the preset width, the second mask layer is determined to be the first mask layer, the second opening is determined to be the first opening, the first dielectric portion and the second dielectric portion are determined to be the first dielectric portion together, and the step of forming the second mask layer on the side of the epitaxial layer facing away from the substrate when the opening width of the first opening is smaller than the preset width is returned to be executed until the opening width of the first opening is equal to the preset width, the first dielectric portion and the second dielectric portion form a first gate insulating portion, the size of the two doping regions along the first direction is greater than or equal to the preset width, and the direction of the opening width is parallel to the first direction.

[0014] According to a second aspect of the embodiment of the present application, the step of forming the first dielectric portion in the first region includes: performing a heat treatment process on the epitaxial layer so that the epitaxial layer material in the first region forms the first dielectric portion. The step of forming the second dielectric portion in at least the second region includes: performing a heat treatment process on the epitaxial layer so that the epitaxial layer material in the second region forms the second dielectric portion, and increasing the thickness of the first dielectric portion so that the thickness of the second dielectric portion is less than the thickness of the first dielectric portion.

[0015] According to the semiconductor device and its preparation method provided by the present application, the minimum thickness of the first gate insulating part is greater than or equal to the thickness of the second gate insulating part, so that the first gate insulating part forms a local thick oxygen structure (LOCOS, Local Oxidation of Silicon), and the thickness of the end of the first gate insulating part close to the doping region is smaller than the thickness of the first gate insulating part away from the doping region, so that the thickness of the end of the first gate insulating part close to the doping region is smaller, thereby reducing the segregation effect during the formation of the first gate insulating part, thereby reducing the impact on the semiconductor device channel, and improving the semiconductor channel concentration and channel length. In addition, the thickness of the first gate insulating part away from the doping region is thicker, which is conducive to improving the accuracy of the dynamic parameters of the semiconductor device and improving the reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The features, advantages and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings.

[0017] Figure 1 A schematic cross-sectional structure diagram of a semiconductor device provided in some embodiments of the present application; Figure 2 A schematic cross-sectional structure diagram of another semiconductor device provided in some embodiments of the present application; Figure 3 A schematic cross-sectional structure diagram of another semiconductor device provided in some embodiments of the present application; Figure 4 A flowchart of a method for manufacturing a semiconductor device provided in some embodiments of the present application; Figures 5 to 11 A schematic diagram of the process structure of a method for manufacturing a semiconductor device provided in some embodiments of the present application.

[0018] Marking Description: 10. substrate; 20. epitaxial layer; 21. recess; 30, gate insulating layer; 31, first gate insulating portion; 311, first sub-portion; 312, second sub-portion; 32, second gate insulating portion; 40, gate; 50, doping region; 51, first doping portion; 52, second doping portion; 53, third doping portion; 60, first electrode; 70, isolation dielectric layer; 80, second electrode; 1. First mask layer; 2. First photoresist layer; 3. Transition layer; 4. Second mask layer; 5. Second photoresist layer; 6. First dielectric portion; 7. Second dielectric portion; K1, first opening; K2, second opening; X, first direction; Z, thickness direction.

[0019] In the drawings, the same reference numerals are used for the same components. The drawings are not drawn to scale. DETAILED DESCRIPTION

[0020] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0021] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0022] In order to better understand the present application, on the one hand, the following Figures 1 to 11 A semiconductor device and a method for manufacturing the same according to an embodiment of the present application are described in detail.

[0023] Figure 1 A schematic cross-sectional structure diagram of a semiconductor device provided for some embodiments of the present application.

[0024] like Figure 1 As shown, an embodiment of the present application provides a semiconductor device, which includes a substrate 10, an epitaxial layer 20, a gate 40, and a gate insulating layer 30. The epitaxial layer 20 is disposed on one side of the substrate 10, and the epitaxial layer 20 includes two doping regions 50 disposed opposite to each other along a first direction X, and the first direction X intersects with the thickness direction Z of the semiconductor device. The gate insulating layer 30 is located between the epitaxial layer 20 and the gate 40, and the gate insulating layer 30 includes a first gate insulating portion 31 and a second gate insulating portion 32, the orthographic projection of the first gate insulating portion 31 on the substrate 10 is located between the orthographic projections of the two doping regions 50 on the substrate 10, the second gate insulating portion 32 is at least located between the doping regions 50 and the gate 40, and the second gate insulating portion 32 is located on the peripheral side of the first gate insulating portion 31. Among them, the thickness of the first gate insulating portion 31 close to the doping region 50 is less than the thickness of the first gate insulating portion 31 away from the doping region 50, and the minimum thickness of the first gate insulating portion 31 is greater than or equal to the thickness of the second gate insulating portion 32.

[0025] Optionally, the semiconductor device may include a lateral conductive semiconductor power device and a vertical conductive semiconductor power device. The embodiments of the present application are exemplified below by a vertical conductive semiconductor power device. For example, a drain, a substrate 10, an epitaxial layer 20, a gate 40, and a source are sequentially stacked along a thickness direction Z of the semiconductor device.

[0026] Optionally, the semiconductor device includes a vertical double diffusion metal-oxide-semiconductor field effect transistor (VDMOS) and an insulated gate bipolar transistor (IGBT). VDMOS includes silicon-based VDMOS and silicon carbide-based VDMOS.

[0027] Optionally, the overall shape of the semiconductor device may be a strip, a block, or other shapes. For example, the shape of the semiconductor device may be a cuboid, a cube, a pentagonal strip, or the like.

[0028] Optionally, the substrate 10 mainly plays a supporting role, and other film layers are stacked on the substrate 10 in sequence. The stacking arrangement mentioned here means that other film layers are stacked in sequence along the thickness direction Z of the substrate 10. And the thickness direction Z of other film layers located on one side of the substrate 10 is usually consistent with the thickness direction Z of the substrate 10 itself. Therefore, for the convenience of expression, the thickness direction Z of the substrate 10 or the thickness direction Z of other film layers mentioned later in the embodiments of this application are all illustrated in the same direction. The material of the substrate 10 may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3) and other materials.

[0029] The material type of the epitaxial layer 20 is the same as that of the substrate 10 , and the epitaxial layer 20 can be formed on the substrate 10 by epitaxial growth.

[0030] Optionally, the shape of the epitaxial layer 20 may be the same as the shape of the semiconductor device, for example, the shape of the epitaxial layer 20 is a cuboid, and the center of the epitaxial layer 20 may be the geometric center of the cuboid. Optionally, the projection shape of the epitaxial layer 20 along the thickness direction Z may include a rectangle, a square, a pentagon or other polygons, and the two doping regions 50 may be symmetrically distributed about the center point of the epitaxial layer 20. Taking the projection shape of the epitaxial layer 20 along the thickness direction Z as a rectangle as an example, the line connecting the midpoints of the two long opposite sides of the rectangle is the first straight line, and the two doping regions 50 are symmetrically arranged along the first straight line, that is, the epitaxial layer 20 is divided into two parts along the first straight line, each part includes a doping region 50, and the doping region 50 in each part includes a first doping portion 51, a second doping portion 52 and a third doping portion 53.

[0031] Optionally, a portion of the first doping portion 51 may be located on a side of the second doping portion 52 and the third doping portion 53 facing the substrate 10 , and another portion of the first doping portion 51 may be located on a side of the second doping portion 52 facing away from the third doping portion 53 .

[0032] Optionally, the second doping portion 52 and the third doping portion 53 are arranged side by side along the first direction X, and the portion where the second doping portion 52 contacts the third doping portion 53 forms a PN junction. The first direction X intersects with the thickness direction Z of the epitaxial layer 20. The second doping portion 52 is located on the side of the third doping portion 53 facing the center of the epitaxial layer 20.

[0033] Optionally, the doping concentration of the first doping portion 51 is less than the doping concentration of the third doping portion 53 .

[0034] Optionally, the substrate 10 may be of a first doping type.

[0035] Optionally, the epitaxial layer 20 may be of the first doping type.

[0036] Optionally, the first doping type is opposite to the second doping type, which can be understood as the first doping type is one of N-type or P-type, and the second doping type is the other of N-type or P-type. For example, when the first doping type is N-type, the second doping type is P-type. For another example, when the first doping type is P-type, the second doping type is N-type.

[0037] The embodiment of the present application is described by taking the first doping type as N type and the second doping type as P type as an example. In other embodiments, the first doping type may be P type and the second doping type may be N type.

[0038] Optionally, the material of the gate 40 includes polysilicon.

[0039] Optionally, the orthographic projection of the gate 40 on the substrate 10 overlaps with the orthographic projection of the doping region 50 on the substrate 10. Exemplarily, the orthographic projections of the gate 40 at both ends along the first direction X on the substrate 10 overlap with the orthographic projections of the two doping regions 50 on the substrate 10 respectively.

[0040] Optionally, an orthographic projection of the gate 40 on the substrate 10 is arranged to partially overlap with an orthographic projection of the second doping portion 52 on the substrate 10 .

[0041] The gate insulating layer 30 is located between the epitaxial layer 20 and the gate 40 . The gate insulating layer 30 can play an isolation role and reduce the direct electrical connection between the gate 40 and the epitaxial layer 20 .

[0042] Optionally, the material of the gate insulating layer 30 includes one or more combinations of silicon dioxide (SiO 2 ) and silicon nitride (Si 3 N 4 ).

[0043] Optionally, the materials of the first gate insulating portion 31 and the second gate insulating portion 32 may be the same or different.

[0044] As an example, the materials of the first gate insulating portion 31 and the second gate insulating portion 32 are both silicon dioxide. Alternatively, the material of the first gate insulating portion 31 is silicon dioxide, and the material of the second gate insulating portion 32 is silicon nitride.

[0045] Optionally, the size of the first gate insulating portion 31 along the first direction X may be the same as or different from that of the second gate insulating portion 32 .

[0046] Optionally, the number of the second gate insulating portions 32 includes two, one of the two second gate insulating portions 32 is located between one of the two doping regions 50 and the gate 40, and the other of the two second gate insulating portions 32 is located between the other of the two doping regions 50 and the gate 40.

[0047] Optionally, the second gate insulating portion 32 may be located only between the doping region 50 and the gate 40. Alternatively, a portion of the second gate insulating portion 32 is located between the doping region 50 and the gate 40, the doping region 50 is spaced apart from the orthographic projection of the substrate 10 and the orthographic projection of the first gate insulating portion 31 on the substrate 10, and another portion of the second gate insulating portion 32 is located between the spacer region between the doping region 50 and the first gate insulating portion 31 and the gate 40.

[0048] The orthographic projection of the first gate insulating portion 31 on the substrate 10 is located between the orthographic projections of the two doping regions 50 on the substrate 10 . It can be understood that the orthographic projection of the first gate insulating portion 31 on the substrate 10 and the orthographic projections of the two doping regions 50 on the substrate 10 are arranged at intervals, or the orthographic projection of the first gate insulating portion 31 on the substrate 10 is arranged tangent to the edges of the orthographic projections of the two doping regions 50 on the substrate 10 , or the orthographic projection of the first gate insulating portion 31 on the substrate 10 is arranged at intervals from the orthographic projection of one doping region 50 on the substrate 10 , and the orthographic projection of the first gate insulating portion 31 on the substrate 10 is arranged tangent to the edge of the orthographic projection of the other doping region 50 on the substrate 10 .

[0049] The thickness of the first gate insulating portion 31 close to the doping region 50 and the thickness of the first gate insulating portion 31 away from the doping region 50 can be understood as follows: the two ends of the first gate insulating portion 31 along the first direction X are the regions of the first gate insulating portion 31 close to the doping region 50, and the middle region of the first gate insulating portion 31 along the first direction X is the region of the first gate insulating portion 31 away from the doping region 50. The thickness of the first gate insulating portion 31 close to the doping region 50 is less than the thickness of the first gate insulating portion 31 away from the doping region 50, that is, the thickness of the two ends of the first gate insulating portion 31 along the first direction X is less than the middle region of the first gate insulating portion 31 along the first direction X.

[0050] Optionally, the thicknesses of two ends of the first gate insulating portion 31 along the first direction X may be the same or different.

[0051] Optionally, the thickness change from the end of the first gate insulating portion 31 along the first direction X to the middle area of ​​the first gate insulating portion 31 along the first direction X can be a step thickness change or a gradual thickness change. For example, the thickness of the end of the first gate insulating portion 31 along the first direction X is the first thickness, and the thickness of the first gate insulating portion 31 along the middle area of ​​the first direction X is the second thickness, and the first thickness is less than the second thickness.

[0052] The minimum thickness of the first gate insulating portion 31 may be understood as the thickness of the end of the first gate insulating portion 31 along the first direction X. In some examples, the minimum thickness of the first gate insulating portion 31 is greater than the thickness of the second gate insulating portion 32. In other examples, the minimum thickness of the first gate insulating portion 31 is equal to the thickness of the second gate insulating portion 32.

[0053] It is understandable that the local thick oxygen structure (LOCOS) in the semiconductor device can improve the dynamic parameters of the semiconductor device such as switching speed, response time, transient current, noise performance, power consumption, etc., thereby improving the reliability of the semiconductor device. However, the closer the distance between the local thick oxygen structure and the doping region 50 in the semiconductor device is, and the thicker the thickness of the local thick oxygen structure close to the doping region 50 is, the more obvious the segregation effect in the preparation process of the local thick oxygen structure is, resulting in a decrease in channel concentration and a shortened channel length. A low channel concentration is prone to punch-through leakage, and a shortened channel length is prone to short channel effect. In the semiconductor device in the embodiment of the present application, the minimum thickness of the first gate insulating part 31 is greater than or equal to the thickness of the second gate insulating part 32, so that the first gate insulating part 31 forms a local thick oxygen structure (LOCOS, Local Oxidation of Silicon), and the thickness of the first gate insulating part 31 close to the doping region 50 is smaller than the thickness of the first gate insulating part 31 away from the doping region 50, so that the thickness of the first gate insulating part 31 close to the doping region 50 is smaller, thereby reducing the segregation effect during the formation of the first gate insulating part 31, thereby reducing the impact on the semiconductor device channel, and improving the semiconductor channel concentration and channel length. In addition, the first gate insulating part 31 is thicker away from the doping region 50, which is conducive to improving the accuracy of the dynamic parameters of the semiconductor device and improving the reliability of the semiconductor device.

[0054] In some optional embodiments, Figure 1 As shown, from the direction of the doping region 50 to the first gate insulating portion 31 , the thickness of the first gate insulating portion 31 gradually increases.

[0055] As an example, the thickness of the first gate insulating portion 31 gradually increases from the direction of the doping region 50 to the first gate insulating portion 31, that is, from the end of the first gate insulating portion 31 along the first direction X to the middle region of the first gate insulating portion 31 along the first direction X. Here, "gradually increasing thickness" may refer to linear thickening, exponential thickening, logarithmic thickening, parabolic thickening, nonlinear thickening, progressive thickening, etc.

[0056] In these optional embodiments, through the above configuration, the overall structure of the first gate insulating portion 31 can be made smooth, thereby optimizing the electric field distribution in the key area of ​​the semiconductor device and improving the performance of the semiconductor device.

[0057] Figure 2 A schematic diagram of the cross-sectional structure of another semiconductor device provided for some embodiments of the present application.

[0058] In some optional embodiments, Figure 2As shown, the first gate insulating portion 31 includes a first sub-portion 311 and two second sub-portions 312, the two second sub-portions 312 are arranged in sequence along the first direction X, and the first sub-portion 311 is arranged between the two second sub-portions 312, the thickness of the first sub-portion 311 is greater than the thickness of at least part of the second sub-portion 312, and the orthographic projection of the second sub-portion 312 on the substrate 10 is located on the side of the first sub-portion 311 close to the doping region 50.

[0059] Exemplarily, the first second sub-portion 312 is adjacent to the first doping region 50 , the second second sub-portion 312 is adjacent to the second doping region 50 , and the first sub-portion 311 is located between the first second sub-portion 312 and the second second sub-portion 312 .

[0060] In some examples, the thickness of the first subsection 311 is greater than the entire thickness of any second subsection 312 of the two second subsections 312. In other examples, the thickness of the first subsection 311 is greater than the thickness of a portion of any second subsection 312 of the two second subsections 312, and the thickness of the first subsection 311 is equal to the thickness of another portion of any second subsection 312 of the two second subsections 312.

[0061] Optionally, the thickness of the first sub-portion 311 may be uniform, or may gradually increase in a direction from the doped portion to the first gate insulating portion 31 .

[0062] Optionally, the thickness of the second sub-portion 312 may be uniform, or may gradually increase in a direction from the doped portion to the first gate insulating portion 31 .

[0063] Optionally, the thicknesses of the two second sub-portions 312 may be the same or different.

[0064] Optionally, the sizes of the two second sub-portions 312 along the first direction X may be the same or different.

[0065] Optionally, the thickness of the second sub-portion 312 and the thickness of the second gate insulating portion 32 may be the same or different.

[0066] Through the above arrangement in the embodiment of the present application, the structure in the first gate insulating portion 31 can form a stepped structure, thereby simplifying the difficulty of preparing the first gate insulating portion 31, improving the preparation yield of the semiconductor device, and reducing the preparation cost of the semiconductor device.

[0067] In some optional embodiments, Figure 1 and Figure 2As shown, the first sub-portion 311 is symmetrically arranged along the perpendicular midline of the shortest connecting line of the two doping regions 50 in the first direction X, thereby improving the structural symmetry of the first gate insulating portion 31, thereby optimizing the electric field distribution of the semiconductor device, improving the voltage resistance of the semiconductor device, and improving the reliability of the semiconductor device.

[0068] As an example, the shortest connecting line between two doping regions 50 along the first direction X may be the shortest distance between the two doping regions 50 , and the perpendicular bisector of the shortest connecting line between the two doping regions 50 along the first direction X may be the perpendicular bisector of the midpoint of the shortest connecting line.

[0069] In some examples, the two doping regions 50 are symmetrically arranged about a perpendicular bisector of a shortest connecting line of the two doping regions 50 along the first direction X.

[0070] In some optional embodiments, Figure 1 and Figure 2 As shown, the two second sub-portions 312 are symmetrically arranged along the perpendicular midline of the shortest connecting line of the two doping regions 50 along the first direction X, further improving the structural symmetry of the first gate insulating portion 31, optimizing the electric field distribution of the semiconductor device, reducing parasitic parameters, and improving the overall performance of the semiconductor device.

[0071] In some optional embodiments, Figure 1 and Figure 2 As shown, the epitaxial layer 20 includes a recess 21 , which is formed by a depression of one side of the epitaxial layer 20 away from the substrate 10 , and at least a portion of the first gate insulating portion 31 is disposed in the recess 21 .

[0072] A portion of the first gate insulating portion 31 is disposed in the recess 21 , and another portion of the first gate insulating portion 31 is located outside the recess 21 . Alternatively, the entire first gate insulating portion 31 may be located in the recess 21 .

[0073] Optionally, the bottom surface of the recess 21 may be flat or may be an arc-shaped surface, for example, an arc-shaped bottom surface that is recessed toward the substrate 10 .

[0074] The above configuration of the embodiment of the present application is helpful to reduce the size of the first gate insulating portion 31 in the thickness direction Z of the semiconductor device, thereby reducing the overall thickness of the semiconductor device.

[0075] Figure 3 A schematic diagram of the cross-sectional structure of another semiconductor device provided for some embodiments of the present application.

[0076] In some optional embodiments, Figure 3 As shown, the first gate insulating portion 31 and the second gate insulating portion 32 are arranged flush with each other on a side facing the substrate 10 .

[0077] It can be understood that the first gate insulating portion 31 and the second gate insulating portion 32 are arranged flush toward one side of the substrate 10, that is, the first sub-portion 311 and the second sub-portion 312 are arranged flush toward one side of the substrate 10, and the first sub-portion 311 and the second gate insulating portion 32 are arranged flush toward one side of the substrate 10.

[0078] Optionally, a surface of the epitaxial layer 20 facing away from the substrate 10 is a plane.

[0079] Optionally, the semiconductor device may further include a first electrode 60 and a second electrode 80, wherein the first electrode 60 is located on a side of the epitaxial layer 20 facing away from the substrate 10, and the second electrode 80 is located on a side of the substrate 10 facing away from the epitaxial layer 20. Optionally, the gate 40 is located between a portion of the first electrode 60 and the epitaxial layer 20.

[0080] The embodiment of the present application reduces the etching of the epitaxial layer 20 through the above-mentioned configuration, and reduces the influence of the gate 40 on the doped region 50 and the drift region in the epitaxial layer 20 during the preparation process, thereby improving the preparation yield and overall performance of the semiconductor device.

[0081] Figure 4 A flowchart of a method for manufacturing a semiconductor device provided in some embodiments of the present application. Figures 5 to 11 A schematic diagram of the process structure of a method for manufacturing a semiconductor device provided in some embodiments of the present application.

[0082] like Figures 4 to 11 As shown, an embodiment of the present application provides a method for preparing a semiconductor device, and the preparation method includes the following steps: S100 , forming an epitaxial layer 20 on one side of the substrate 10 .

[0083] Specifically, in step S100, an epitaxial layer 20 may be formed on the substrate 10 by an epitaxial growth process. Optionally, the conductivity type of the substrate 10 and the conductivity type of the epitaxial layer 20 are the same.

[0084] S200 , forming a first gate insulating portion on a side of the epitaxial layer 20 facing away from the substrate 10 .

[0085] Specifically, in step S200 , the first gate insulating portion 31 may be formed by a thermal oxidation process or a deposition process.

[0086] S300, forming a second gate insulating portion around the first gate insulating portion, the first gate insulating portion 31 and the second gate insulating portion 32 form a gate insulating layer 30, and the minimum thickness of the first gate insulating portion 31 is greater than or equal to the thickness of the second gate insulating portion 32. The first gate insulating portion and the second gate insulating portion form a gate insulating layer.

[0087] Specifically, in step S300 , the second gate insulating portion 32 may be formed by a mask process.

[0088] Optionally, when the material of the second gate insulating portion 32 is silicon oxide, the second gate insulating portion 32 may be formed by a thermal oxidation process.

[0089] S400, forming two doping regions 50 arranged opposite to each other along a first direction X in the epitaxial layer 20, wherein the first direction X intersects with the thickness direction Z of the semiconductor device; wherein the orthographic projection of the first gate insulating portion 31 on the substrate 10 is located between the orthographic projections of the two doping regions 50 on the substrate 10, the second gate insulating portion 32 is located at least between the doping region 50 and the gate 40, and the thickness of the first gate insulating portion 31 close to the doping region 50 is less than the thickness of the insulating portion of the gate 40 away from the doping region 50.

[0090] Specifically, in step S400, the doping region 50 may include a first doping portion 51, a second doping portion 52, and a third doping portion 53, and the preparation of the doping region 50 may be performed after the preparation of the gate 40 is completed. After the preparation of the gate insulating layer 30 is completed, the gate 40 is prepared by a deposition process and an etching process. After the gate 40 is prepared, an ion implantation process and a thermal diffusion process may be performed on the epitaxial layer 20 using the gate as a shielding structure to form the first doping portion 51. The third doping portion 53 and the second doping portion 52 are sequentially prepared by an ion implantation process. Optionally, the doping type of the first doping portion 51 is the same as the doping type of the third doping portion 53, that is, the ions implanted in the first doping portion 51 and the ions implanted in the third doping portion 53 may be the same.

[0091] Optionally, the doping region 50 may be prepared before the gate insulating layer 30 is prepared.

[0092] Alternatively, if Figure 1 As described above, after the doping region 50 is prepared, an isolation dielectric layer 70 and a first electrode 60 may be sequentially prepared on a surface of the epitaxial layer 20 facing away from the substrate 10 and a surface of the gate 40 facing away from the substrate 10. The isolation dielectric layer 70 is used to isolate the direct electrical connection between the first electrode 60 and the gate 40. Optionally, the first electrode 60 is arranged in contact with both the second doping portion 52 and the third doping portion 53.

[0093] The embodiment of the present application prepares a semiconductor device by the above-mentioned preparation method, and the minimum thickness of the first gate insulating part 31 is greater than or equal to the thickness of the second gate insulating part 32, so that the first gate insulating part 31 forms a local thick oxygen structure, and the thickness of the end of the first gate insulating part 31 close to the doping region 50 is made smaller by making the thickness of the first gate insulating part 31 close to the doping region 50 smaller than the thickness of the first gate insulating part 31 away from the doping region 50, thereby reducing the segregation effect during the formation of the first gate insulating part 31, thereby reducing the impact on the channel of the semiconductor device and improving the semiconductor channel concentration and channel length. In addition, the thickness of the first gate insulating part 31 away from the doping region 50 is thicker, which is conducive to improving the accuracy of the dynamic parameters of the semiconductor device and improving the reliability of the semiconductor device.

[0094] In some optional embodiments, Figures 5 to 10 As shown, the step of forming a first gate insulating portion on the side of the epitaxial layer 20 facing away from the substrate 10 includes: S210 , forming a first mask layer 1 on the side of the epitaxial layer 20 facing away from the substrate 10 , wherein the first mask layer 1 comprises a first opening K1 , and the first opening exposes a first area on the surface of the epitaxial layer 20 facing away from the substrate 10 .

[0095] Specifically, in step S210, the first opening K1 on the first mask layer 1 can be formed by photolithography, for example, a first photoresist layer 2 with a preset pattern is formed on the side of the first mask layer 1 facing away from the substrate 10, and the first mask layer 1 is formed by etching. Optionally, after the first mask layer 1 is prepared, the photoresist layer is removed to reduce the possibility of the photoresist material falling into the first opening K1.

[0096] Optionally, a transition layer 3 may be provided between the first mask layer 1 and the epitaxial layer 20, and the transition layer is used to increase the connection strength between the first mask layer 1 and the epitaxial layer 20 and reduce the possibility of separation of the first mask layer 1 and the epitaxial layer 20 during the preparation process.

[0097] S220 , forming a first dielectric portion 6 in the first region and removing the first mask layer 1 .

[0098] Specifically, in step S220, the epitaxial layer 20 material in the first region may be oxidized by a heat treatment process to form the first dielectric portion 6. After the first dielectric portion 6 is prepared, the first mask layer 1 may be removed by etching or other processes. Alternatively, the first mask layer 1 may be removed by a wet etching process.

[0099] S230. When the opening width of the first opening K1 is smaller than the preset width, a second mask layer 4 is formed on the side of the epitaxial layer 20 facing away from the substrate 10. The second mask layer includes a second opening K2. The opening width of the first opening K1 is smaller than the opening width of the second opening K2. The second opening K2 exposes the first dielectric portion 6 and a second area on the surface of the epitaxial layer 20 facing away from the substrate 10. The second area is located on the peripheral side of the first dielectric portion 6.

[0100] Specifically, in step S230, after the first dielectric portion 6 is prepared, the opening width of the first opening K1 is smaller than the preset width, that is, the width of the first dielectric portion 6 (the dimension in the first direction X) is smaller than the preset width, and then the second dielectric portion 7 is prepared. The second opening K2 in the second mask layer 4 exposes the second region of the epitaxial layer 20, and the second dielectric portion 7 is formed at least in the second region.

[0101] Optionally, the second opening K2 on the second mask layer 4 can be formed by photolithography, for example, a second photoresist layer 5 with a preset pattern is formed on the side of the second mask layer 4 facing away from the substrate 10, and the second mask layer 4 is formed by an etching process. Optionally, after the second mask layer 4 is prepared, the photoresist layer is removed to reduce the possibility of the photoresist material falling into the second opening K2.

[0102] The fact that the opening width of the first opening K1 is smaller than the opening width of the second opening K2 can be understood as the size of the first opening K1 along the first direction X is smaller than the size of the second opening K2 along the first direction X.

[0103] Optionally, the second area may be divided into two parts, and the two parts of the second area are respectively located on two sides of the first dielectric portion 6 along the first direction X.

[0104] Optionally, the preset width may be less than or equal to the distance between the orthographic projections of the two doping regions 50 on the substrate 10 .

[0105] Optionally, a transition layer 3 may be provided between the second mask layer 4 and the epitaxial layer 20, and the transition layer is used to increase the connection strength between the second mask layer 4 and the epitaxial layer 20, and reduce the possibility of separation of the first mask layer 1 and the epitaxial layer 20 during the preparation process. Optionally, the transition layer 3 may be retained when the first mask layer 1 is removed to facilitate the preparation of the second mask layer 4.

[0106] S240 , forming a second dielectric portion 7 at least in the second region and removing the second mask layer 4 , wherein the thickness of the second dielectric portion 7 is smaller than the thickness of the first dielectric portion 6 .

[0107] Specifically, in step S240, the epitaxial layer 20 material in the second region can be oxidized by a heat treatment process to form the second dielectric portion 7. After the second dielectric portion 7 is prepared, the second mask layer 4 can be removed by a wet etching process. Optionally, the transition layer 3 can be removed when the second mask layer 4 is removed.

[0108] Optionally, the second dielectric portion 7 may be formed only in the second region, or dielectric structures may be formed in both the second region and the first region, the first dielectric portion 6 and the dielectric structure in the first region forming a thicker first dielectric portion 6 , and the dielectric structure in the second region forming the second dielectric portion 7 .

[0109] S250. When the opening width of the second opening K2 is smaller than the preset width, determine that the second mask layer 4 is the first mask layer 1, determine that the second opening K2 is the first opening K1, determine that the first dielectric portion 6 and the second dielectric portion 7 are collectively the first dielectric portion 6, and return to the step of forming the second mask layer 4 on the side of the epitaxial layer 20 facing away from the substrate 10 when the opening width of the first opening K1 is smaller than the preset width, until the opening width of the first opening K1 is equal to the preset width, the first dielectric portion 6 and the second dielectric portion 7 form a first gate insulating portion 31, and the size of the two doping regions 50 along the first direction X is greater than or equal to the preset width, and the direction of the opening width is parallel to the first direction X.

[0110] Specifically, in step S250, the preset width is the size of the first gate insulating portion 31 along the first direction X. When the opening width of the second opening K2 is less than the preset width, the sum of the sizes of the first dielectric portion 6 and the second dielectric portion 7 along the first direction X is less than the size of the first gate insulating portion 31 along the first direction X, and the dielectric structure needs to be further prepared to form the first gate insulating portion 31. At this time, the second mask layer 4 is determined as the first mask layer 1, the second opening K2 is determined as the first opening K1, and the first dielectric portion 6 and the second dielectric portion 7 are jointly determined as the first dielectric portion 6. When the steps S230 and S240 are continued to be performed, when the width of the first opening K1 is equal to the preset width, that is, the sum of the sizes of the prepared second dielectric portion 7 and the new first dielectric portion 6 along the first direction X is equal to the sum of the sizes of the first gate insulating portion 31 along the first direction X, so that the second dielectric portion 7 and the first dielectric portion 6 form the first gate insulating portion 31.

[0111] Optionally, the first gate insulating portion 31 may be formed by performing step S230 and step S240 once or more times.

[0112] Through the above-mentioned configuration, the embodiment of the present application can adjust the preparation process steps according to design requirements, thereby simplifying the preparation process of the first gate insulating portion 31, improving the preparation yield of the semiconductor device, and reducing the preparation cost of the semiconductor device.

[0113] In some other embodiments, two ends of the first gate insulating portion 31 along the first direction X may be formed first, the ends may be covered by a mask structure, and then the middle region of the first gate insulating portion 31 along the first direction X (the first region of the epitaxial layer 20) may be prepared.

[0114] In some optional embodiments, the step of forming the first dielectric portion 6 in the first region includes: S221, performing a heat treatment process on the epitaxial layer 20 so that the epitaxial layer 20 material in the first region forms the first dielectric portion 6. The step of forming the second dielectric portion 7 in at least the second region includes: S241, performing a heat treatment process on the epitaxial layer 20 so that the epitaxial layer 20 material in the second region forms the second dielectric portion 7, and increasing the thickness of the first dielectric portion 6, so that the thickness of the second dielectric portion 7 is less than the thickness of the first dielectric portion 6.

[0115] Specifically, the thickness of the first dielectric portion 6 prepared in step S221 may be D1, and the thickness of the first dielectric portion 6 prepared in step S241 may be D2, where D2>D1, that is, the first dielectric portion 6 is prepared by two heat treatment processes.

[0116] Optionally, the heat treatment processes of the two heat treatment processes may be the same, for example, the heat treatment temperature and the heat treatment time may be the same. Of course, they may also be different.

[0117] The above configuration of the embodiment of the present application is helpful to simplify the preparation process of the first dielectric part 6 and the second dielectric part 7, improve the control accuracy of the thickness of each position of the first gate insulating part 31, and improve the reliability of the semiconductor device.

[0118] It should be noted that the semiconductor device provided in the embodiment of the present application has the beneficial effects of the semiconductor device preparation method in any of the aforementioned embodiments. For specific details, please refer to the aforementioned description of the beneficial effects of the semiconductor device preparation method, and the embodiment of the present application will not repeat them.

[0119] Although the present application has been described with reference to preferred embodiments, various modifications may be made thereto and parts thereof may be replaced with equivalents without departing from the scope of the present application. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there are no structural conflicts. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; An epitaxial layer is arranged on one side of the substrate, the epitaxial layer comprising two doping regions arranged opposite to each other along a first direction, wherein the first direction intersects with a thickness direction of the semiconductor device; Gate; a gate insulating layer, the gate insulating layer being located between the epitaxial layer and the gate, the gate insulating layer comprising a first gate insulating portion and a second gate insulating portion, the first gate insulating portion having an orthographic projection on the substrate being located between the orthographic projections of the two doped regions on the substrate, the second gate insulating portion being located at least between the doped regions and the gate, and the second gate insulating portion being located on a peripheral side of the first gate insulating portion; The thickness of the first gate insulating portion close to the doping region is smaller than the thickness of the first gate insulating portion away from the doping region, and the minimum thickness of the first gate insulating portion is greater than or equal to the thickness of the second gate insulating portion.

2. The semiconductor device according to claim 1, wherein: The thickness of the first gate insulating portion gradually increases from the doping region to the first gate insulating portion.

3. The semiconductor device according to claim 1, wherein: The first gate insulating portion includes a first sub-portion and two second sub-portions, the two second sub-portions are arranged in sequence along the first direction, and the first sub-portion is arranged between the two second sub-portions, the thickness of the first sub-portion is greater than the thickness of at least part of the second sub-portion, and the orthographic projection of the second sub-portion on the substrate is located on a side of the first sub-portion close to the doping region.

4. The semiconductor device according to claim 3, characterized in that The first sub-portion is symmetrically arranged about a perpendicular midline of the shortest connecting line of the two doping regions along the first direction.

5. The semiconductor device according to claim 3, characterized in that The two second sub-sections are symmetrically arranged about a perpendicular midline of the shortest connecting line of the two doping regions along the first direction.

6. The semiconductor device according to claim 1, wherein: The epitaxial layer comprises a concave portion, wherein the concave portion is formed by a depression of a side of the epitaxial layer away from the substrate, and at least a portion of the first gate insulating portion is disposed in the concave portion.

7. The semiconductor device according to claim 1, wherein: The first gate insulating portion and the second gate insulating portion are arranged flush with each other on a side facing the substrate.

8. A method for preparing a semiconductor device, characterized in that: include: forming an epitaxial layer on one side of the substrate; forming a first gate insulating portion on a side of the epitaxial layer facing away from the substrate; forming a second gate insulating portion on a peripheral side of the first gate insulating portion, the first gate insulating portion and the second gate insulating portion forming a gate insulating layer, and a minimum thickness of the first gate insulating portion being greater than or equal to a thickness of the second gate insulating portion; Two doped regions are formed in the epitaxial layer and are arranged opposite to each other along a first direction, wherein the first direction intersects with the thickness direction of the semiconductor device; wherein the orthographic projection of the first gate insulating portion on the substrate is located between the orthographic projections of the two doped regions on the substrate, the second gate insulating portion is located at least between the doped region and the gate, and the thickness of the first gate insulating portion close to the doped region is less than the thickness of the gate insulating portion away from the doped region.

9. The preparation method according to claim 8, characterized in that: The step of forming a first gate insulating portion on a side of the epitaxial layer facing away from the substrate includes: forming a first mask layer on a side of the epitaxial layer facing away from the substrate, wherein the first mask layer comprises a first opening, and the first opening exposes a first area of ​​a surface of the epitaxial layer facing away from the substrate; forming a first dielectric portion in the first region and removing the first mask layer; In a case where the opening width of the first opening is smaller than a preset width, a second mask layer is formed on a side of the epitaxial layer facing away from the substrate, the second mask layer includes a second opening, the opening width of the first opening is smaller than the opening width of the second opening, the second opening exposes the first dielectric portion and a second region on a surface of the epitaxial layer facing away from the substrate, and the second region is located on a peripheral side of the first dielectric portion; forming a second dielectric portion at least in the second region and removing the second mask layer, wherein the thickness of the second dielectric portion is smaller than the thickness of the first dielectric portion; When the opening width of the second opening is smaller than the preset width, the second mask layer is determined to be the first mask layer, the second opening is determined to be the first opening, the first dielectric portion and the second dielectric portion are determined to be the first dielectric portion together, and the step of forming a second mask layer on the side of the epitaxial layer facing away from the substrate when the opening width of the first opening is smaller than the preset width is returned to be executed until the opening width of the first opening is equal to the preset width, the first dielectric portion and the second dielectric portion form a first gate insulating portion, the size of the two doped regions along the first direction is greater than or equal to the preset width, and the direction of the opening width is parallel to the first direction.

10. The preparation method according to claim 9, characterized in that: The step of forming the first dielectric portion in the first region includes: Performing a heat treatment process on the epitaxial layer so that the epitaxial layer material in the first region forms a first dielectric portion; The step of forming the second dielectric portion at least in the second region includes: The epitaxial layer is subjected to a heat treatment process so that the epitaxial layer material in the second region forms a second dielectric portion and the thickness of the first dielectric portion is increased so that the thickness of the second dielectric portion is smaller than the thickness of the first dielectric portion.

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