Semiconductor device and method of manufacturing the same

Abstract

The application relates to a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, an epitaxial layer, a gate and a gate insulating layer. The epitaxial layer is arranged on one side of the substrate, and the epitaxial layer comprises two doped regions arranged oppositely along a first direction intersecting with a thickness direction of the semiconductor device. The gate insulating layer is located between the epitaxial layer and the gate, and the gate insulating layer comprises a first gate insulating part and a second gate insulating part. The first gate insulating part is located between the projections of the two doped regions on the substrate. The second gate insulating part is located between at least one of the doped regions and the gate, and the second gate insulating part is located on the side of the first gate insulating part. The thickness of the first gate insulating part close to the doped region is smaller than the thickness of the first gate insulating part away from the doped region. The minimum thickness of the first gate insulating part is greater than or equal to the thickness of the second gate insulating part. The application can improve the reliability of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a semiconductor device and a method for fabricating the same. Background Technology

[0002] Vertical double-diffused metal-oxide-semiconductor (VDMOS) transistors feature high switching speed, high voltage withstand capability, low on-resistance, wide safe operating area, and good thermal stability, and are widely used in power integrated circuits and power integrated systems in switching power supplies, automotive electronics, aerospace, and other fields.

[0003] In the development of VDMOS device technology, how to improve the reliability of semiconductor devices has always been a research direction in semiconductor device technology. Summary of the Invention

[0004] The semiconductor devices and their fabrication methods provided in this application can improve the reliability of semiconductor devices.

[0005] In a first aspect, an embodiment of this application provides a semiconductor device comprising a substrate, an epitaxial layer, a gate, and a gate insulating layer. The epitaxial layer is disposed on one side of the substrate and includes two doped regions disposed opposite each other along a first direction, which intersects the thickness direction of the semiconductor device. The gate insulating layer is located between the epitaxial layer and the gate, and includes a first gate insulating portion and a second gate insulating portion. The orthographic projection of the first gate insulating portion onto the substrate lies between the orthographic projections of the two doped regions onto the substrate. The second gate insulating portion is located at least between the doped regions and the gate, and is located on the periphery of the first gate insulating portion. The thickness of the first gate insulating portion near the doped region is less than the thickness of the first gate insulating portion away from the doped region, and the minimum thickness of the first gate insulating portion is greater than or equal to the thickness of the second gate insulating portion.

[0006] According to a first aspect of the embodiments of this application, the thickness of the first gate insulating portion gradually increases from the direction of the doped region toward the first gate insulating portion.

[0007] According to a first aspect of the embodiments of this application, the first gate insulating portion includes a first sub-portion and two second sub-portions, the two second sub-portions are arranged sequentially along a first direction, and the first sub-portion is disposed between the two second sub-portions. The thickness of the first sub-portion is greater than the thickness of at least a portion of the second sub-portions, and the orthogonal projection of the second sub-portion onto the substrate is located on the side of the first sub-portion closer to the doped region.

[0008] According to a first aspect of the embodiments of this application, the first sub-part is symmetrically arranged with respect to the perpendicular bisector of the shortest line connecting the two doped regions along a first direction.

[0009] According to a first aspect of the embodiments of this application, the two second sub-parts are symmetrically arranged with respect to the perpendicular bisector of the shortest line connecting the two doped regions along the first direction.

[0010] According to a first aspect of the present application, the epitaxial layer includes a recess formed by a recess in the epitaxial layer away from the substrate, and at least a portion of the first gate insulating portion is disposed within the recess.

[0011] According to a first aspect of the embodiments of this application, the first gate insulating portion and the second gate insulating portion are disposed flush with the side facing the substrate.

[0012] Secondly, according to embodiments of this application, a method for fabricating a semiconductor device is provided, comprising: forming an epitaxial layer on one side of a substrate; forming a first gate insulating portion on the side of the epitaxial layer facing away from the substrate; forming a second gate insulating portion on the periphery of the first gate insulating portion; the first gate insulating portion and the second gate insulating portion forming a gate insulating layer; the minimum thickness of the first gate insulating portion being greater than or equal to the thickness of the second gate insulating portion; and the first gate insulating portion and the second gate insulating portion forming the gate insulating layer. Two doped regions are formed in the epitaxial layer and disposed opposite to each other along a first direction, the first direction intersecting the thickness direction of the semiconductor device. Wherein, the orthogonal projection of the first gate insulating portion onto the substrate is located between the orthogonal projections of the two doped regions onto the substrate, the second gate insulating portion is located at least between the doped regions and the gate, and the thickness of the first gate insulating portion near the doped region is less than the thickness of the gate insulating portion away from the doped region.

[0013] According to a second aspect of the present application, the step of forming a first gate insulating portion on the side of the epitaxial layer facing away from the substrate includes: forming a first mask layer on the side of the epitaxial layer facing away from the substrate, the first mask layer including a first opening, the first opening exposing a first region of the surface of the epitaxial layer facing away from the substrate. A first dielectric portion is formed in the first region and the first mask layer is removed. If the opening width of the first opening is less than a predetermined width, a second mask layer is formed on the side of the epitaxial layer facing away from the substrate, the second mask layer including a second opening, the opening width of the first opening being less than the opening width of the second opening, the second opening exposing the first dielectric portion and a second region of the surface of the epitaxial layer facing away from the substrate, the second region being located around the periphery of the first dielectric portion. At least a second dielectric portion is formed in the second region and the second mask layer is removed, the thickness of the second dielectric portion being less than the thickness of the first dielectric portion. If the opening width of the second opening is less than the preset width, the second mask layer is determined to be the first mask layer, the second opening is determined to be the first opening, the first dielectric portion and the second dielectric portion are determined to be the first dielectric portion together, and the process returns to the step of forming the second mask layer on the side of the epitaxial layer facing away from the substrate if the opening width of the first opening is less than the preset width, until the opening width of the first opening is equal to the preset width, the first dielectric portion and the second dielectric portion form the first gate insulating portion, the size of the two doped regions along the first direction is greater than or equal to the preset width, and the direction of the opening width is parallel to the first direction.

[0014] According to a second aspect of the embodiments of this application, the step of forming a first dielectric portion in a first region includes: performing a heat treatment process on an epitaxial layer to form the first dielectric portion from the epitaxial layer material in the first region. At least the step of forming a second dielectric portion in a second region includes: performing a heat treatment process on an epitaxial layer to form the second dielectric portion from the epitaxial layer material in the second region, and increasing the thickness of the first dielectric portion so that the thickness of the second dielectric portion is less than the thickness of the first dielectric portion.

[0015] According to the semiconductor device and its fabrication method provided in this application, the minimum thickness of the first gate insulating portion is greater than or equal to the thickness of the second gate insulating portion, resulting in a localized thick oxide structure (LOCOS) of silicon formed in the first gate insulating portion. By making the thickness of the end of the first gate insulating portion near the doped region smaller than the thickness of the first gate insulating portion away from the doped region, the thickness of the end of the first gate insulating portion near the doped region is reduced, thereby reducing the segregation effect during the formation of the first gate insulating portion, thus reducing the impact on the semiconductor device channel and increasing the semiconductor channel concentration and channel length. Furthermore, the greater thickness of the first gate insulating portion away from the doped region is beneficial for improving the accuracy of the dynamic parameters of the semiconductor device and improving the reliability of the semiconductor device. Attached Figure Description

[0016] The features, advantages, and technical effects of exemplary embodiments of this application will now be described with reference to the accompanying drawings.

[0017] Figure 1 A cross-sectional structural schematic diagram of a semiconductor device provided for some embodiments of this application;

[0018] Figure 2 A cross-sectional structural schematic diagram of another semiconductor device provided in some embodiments of this application;

[0019] Figure 3 A cross-sectional structural schematic diagram of another semiconductor device provided in some embodiments of this application;

[0020] Figure 4 A flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of this application;

[0021] Figures 5 to 11 This is a schematic diagram illustrating the process structure of a method for fabricating a semiconductor device according to some embodiments of this application.

[0022] Marker explanation:

[0023] 10. Substrate; 20. Epitaxial layer; 21. Recess;

[0024] 30. Gate insulating layer; 31. First gate insulating portion; 311. First sub-portion; 312. Second sub-portion; 32. Second gate insulating portion;

[0025] 40. Gate; 50. Doped region; 51. First doped portion; 52. Second doped portion; 53. Third doped portion; 60. First electrode; 70. Isolation dielectric layer; 80. Second electrode;

[0026] 1. First mask layer; 2. First photoresist layer; 3. Transition layer; 4. Second mask layer; 5. Second photoresist layer; 6. First dielectric section; 7. Second dielectric section; K1. First opening; K2. Second opening; X. First direction; Z. Thickness direction.

[0027] In the accompanying drawings, the same parts use the same reference numerals. The drawings are not drawn to scale. Detailed Implementation

[0028] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present application and not to limit it. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating examples.

[0029] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0030] To better understand this application, on the one hand, the following will combine... Figures 1 to 11 The semiconductor devices and their fabrication methods according to embodiments of this application will be described in detail.

[0031] Figure 1 This is a cross-sectional structural diagram of a semiconductor device provided for some embodiments of this application.

[0032] like Figure 1 As shown, this application provides a semiconductor device including a substrate 10, an epitaxial layer 20, a gate 40, and a gate insulating layer 30. The epitaxial layer 20 is disposed on one side of the substrate 10 and includes two doped regions 50 disposed opposite each other along a first direction X, which intersects the thickness direction Z of the semiconductor device. The gate insulating layer 30 is located between the epitaxial layer 20 and the gate 40. The gate insulating layer 30 includes a first gate insulating portion 31 and a second gate insulating portion 32. The orthographic projection of the first gate insulating portion 31 onto the substrate 10 lies between the orthographic projections of the two doped regions 50 onto the substrate 10. The second gate insulating portion 32 is located at least between the doped regions 50 and the gate 40, and is located around the periphery of the first gate insulating portion 31. The thickness of the first gate insulating portion 31 near the doped region 50 is less than the thickness of the first gate insulating portion 31 away from the doped region 50, and the minimum thickness of the first gate insulating portion 31 is greater than or equal to the thickness of the second gate insulating portion 32.

[0033] Optionally, the semiconductor device may include a lateral conductivity semiconductor power device and a vertical conductivity semiconductor power device. The embodiments of this application will be illustrated below using a vertical conductivity semiconductor power device as an example. Exemplarily, a drain, a substrate 10, an epitaxial layer 20, a gate 40, and a source are sequentially stacked along the thickness direction Z of the semiconductor device.

[0034] Optionally, the semiconductor device includes a Vertical Double Diffusion Metal-Oxide-Semiconductor Field Effect Transistor (VDMOS) and an Insulated-Gate Bipolar Transistor (IGBT). VDMOS includes silicon-based VDMOS and silicon carbide-based VDMOS.

[0035] Optionally, the overall shape of the semiconductor device can be elongated, block-shaped, or other shapes. For example, the shape of the semiconductor device can be cuboid, cube, pentagonal elongated, etc.

[0036] Optionally, the substrate 10 primarily serves a supporting and load-bearing function, with other film layers sequentially stacked on the substrate 10. Here, "stacked" refers to the other film layers being sequentially stacked along the thickness direction Z of the substrate 10. Furthermore, the thickness direction Z of other film layers located on one side of the substrate 10 is typically consistent with the thickness direction Z of the substrate 10 itself. Therefore, for ease of description, the thickness direction Z of the substrate 10 or other film layers mentioned later in this application will be indicated using the same direction. The material of the substrate 10 may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), etc.

[0037] The epitaxial layer 20 is made of the same material as the substrate 10, and the epitaxial layer 20 can be formed on the substrate 10 by epitaxial growth.

[0038] Optionally, the shape of the epitaxial layer 20 can be the same as the shape of the semiconductor device. For example, the shape of the epitaxial layer 20 is a cuboid, and the center of the epitaxial layer 20 can be the geometric center of the cuboid. Optionally, the projection shape of the epitaxial layer 20 along the thickness direction Z can include a rectangle, a square, a pentagon, or other polygons, and the two doped regions 50 can be symmetrically distributed at the center point of the epitaxial layer 20. Taking the projection shape of the epitaxial layer 20 along the thickness direction Z as a rectangle as an example, the line connecting the midpoints of the two long opposite sides of the rectangle is the first straight line, and the two doped regions 50 are symmetrically arranged along the first straight line. That is, the epitaxial layer 20 is divided into two parts along the first straight line, and each part includes a doped region 50. The doped region 50 in each part includes a first doped part 51, a second doped part 52, and a third doped part 53.

[0039] Optionally, a portion of the first doped portion 51 may be located on the side of the second doped portion 52 and the third doped portion 53 facing the substrate 10, and another portion of the first doped portion 51 may be located on the side of the second doped portion 52 facing away from the third doped portion 53.

[0040] Optionally, the second doped portion 52 and the third doped portion 53 are arranged side by side along the first direction X, and the portion where the second doped portion 52 and the third doped portion 53 contact each other forms a PN junction. The first direction X intersects with the thickness direction Z of the epitaxial layer 20. The second doped portion 52 is located on the side of the third doped portion 53 facing the center of the epitaxial layer 20.

[0041] Optionally, the doping concentration of the first doped portion 51 is less than the doping concentration of the third doped portion 53.

[0042] Optionally, the substrate 10 can be of a first doping type.

[0043] Optionally, the epitaxial layer 20 can be of the first doping type.

[0044] Optionally, the first doping type is the opposite of the second doping type. This can be understood as the first doping type being either N-type or P-type, and the second doping type being either N-type or P-type. For example, when the first doping type is N-type, the second doping type is P-type. Or, for another example, when the first doping type is P-type, the second doping type is N-type.

[0045] This application uses an example where the first doping type is N-type and the second doping type is P-type. In other embodiments, the first doping type can be P-type and the second doping type can be N-type.

[0046] Alternatively, the material of the gate 40 may include polysilicon.

[0047] Optionally, the orthographic projection of the gate 40 onto the substrate 10 overlaps with the orthographic projection of the doped region 50 onto the substrate 10. For example, the orthographic projections of the two ends of the gate 40 along the first direction X onto the substrate 10 overlap with the orthographic projections of the two doped regions 50 onto the substrate 10, respectively.

[0048] Optionally, the orthogonal projection of the gate 40 onto the substrate 10 overlaps with the orthogonal projection of the second doped portion 52 onto the substrate 10.

[0049] The gate insulating layer 30 is located between the epitaxial layer 20 and the gate 40. The gate insulating layer 30 can play an isolation role and reduce the direct electrical connection between the gate 40 and the epitaxial layer 20.

[0050] Optionally, the material of the gate insulating layer 30 includes one or more combinations of silicon dioxide (SiO2) and silicon nitride (Si3N4).

[0051] Optionally, the materials of the first gate insulating portion 31 and the second gate insulating portion 32 can be the same or different.

[0052] As an example, both the first gate insulating portion 31 and the second gate insulating portion 32 are made of silicon dioxide. Alternatively, the first gate insulating portion 31 is made of silicon dioxide and the second gate insulating portion 32 is made of silicon nitride.

[0053] Optionally, the dimensions of the first gate insulating portion 31 along the first direction X and the second gate insulating portion 32 may be the same or different.

[0054] Optionally, the number of second gate insulating portions 32 includes two, one of which is located between one of the two doped regions 50 and the gate 40, and the other is located between the other doped region 50 and the gate 40.

[0055] Optionally, the second gate insulating portion 32 may be located only between the doped region 50 and the gate 40. Alternatively, a portion of the second gate insulating portion 32 may be located between the doped region 50 and the gate 40, with the orthographic projection of the doped region 50 onto the substrate 10 and the orthographic projection of the first gate insulating portion 31 onto the substrate 10 spaced apart, and another portion of the second gate insulating portion 32 located between the spaced region between the doped region 50 and the first gate insulating portion 31 and the gate 40.

[0056] The orthographic projection of the first gate insulating portion 31 onto the substrate 10 is located between the orthographic projections of the two doped regions 50 onto the substrate 10. This can be understood as follows: the orthographic projection of the first gate insulating portion 31 onto the substrate 10 is spaced apart from the orthographic projections of the two doped regions 50 onto the substrate 10; or the orthographic projection of the first gate insulating portion 31 onto the substrate 10 is tangent to the edges of the orthographic projections of the two doped regions 50 onto the substrate 10; or the orthographic projection of the first gate insulating portion 31 onto the substrate 10 is spaced apart from the orthographic projection of one doped region 50 onto the substrate 10, and the orthographic projection of the first gate insulating portion 31 onto the substrate 10 is tangent to the edge of the orthographic projection of the other doped region 50 onto the substrate 10.

[0057] The thickness of the first gate insulating portion 31 near the doped region 50 and the thickness of the first gate insulating portion 31 away from the doped region 50 can be understood as follows: the two ends of the first gate insulating portion 31 along the first direction X are the regions of the first gate insulating portion 31 near the doped region 50, and the middle region of the first gate insulating portion 31 along the first direction X is the region of the first gate insulating portion 31 away from the doped region 50. The thickness of the first gate insulating portion 31 near the doped region 50 is less than the thickness of the first gate insulating portion 31 away from the doped region 50, that is, the thickness of the two ends of the first gate insulating portion 31 along the first direction X is less than the thickness of the middle region of the first gate insulating portion 31 along the first direction X.

[0058] Optionally, the thickness of the two ends of the first gate insulating portion 31 along the first direction X can be the same or different.

[0059] Optionally, the thickness variation of the first gate insulating portion 31 from the end of the first gate insulating portion 31 along the first direction X to the middle region of the first gate insulating portion 31 along the first direction X can be a stepped thickness variation or a gradual thickness variation. For example, the thickness of the end of the first gate insulating portion 31 along the first direction X is the first thickness, and the thickness of the middle region of the first gate insulating portion 31 along the first direction X is the second thickness, and the first thickness is less than the second thickness.

[0060] The minimum thickness of the first gate insulating portion 31 can be understood as the thickness of the end of the first gate insulating portion 31 along the first direction X. In some examples, the minimum thickness of the first gate insulating portion 31 is greater than the thickness of the second gate insulating portion 32. In other examples, the minimum thickness of the first gate insulating portion 31 is equal to the thickness of the second gate insulating portion 32.

[0061] It is understandable that localized thick oxide structures (LOCOS) in semiconductor devices can improve dynamic parameters such as switching speed, response time, transient current, noise performance, and power consumption, thereby enhancing the reliability of semiconductor devices. However, the closer the localized thick oxide structure is to the doped region 50, and the thicker the localized thick oxide structure is near the doped region 50, the more pronounced the segregation effect during the fabrication process becomes. This leads to a decrease in channel concentration and a shorter channel length. Low channel concentration increases the likelihood of punch-through leakage, while a shorter channel length increases the likelihood of short-channel effects. In the semiconductor device of this embodiment, the minimum thickness of the first gate insulating portion 31 is greater than or equal to the thickness of the second gate insulating portion 32, causing the first gate insulating portion 31 to form a localized thick oxide structure (LOCOS, Local Oxidation of Silicon). By making the thickness of the first gate insulating portion 31 near the doped region 50 smaller than the thickness of the first gate insulating portion 31 away from the doped region 50, the thickness of the first gate insulating portion 31 near the doped region 50 is smaller, thereby reducing the segregation effect during the formation of the first gate insulating portion 31, thus reducing the impact on the semiconductor device channel and increasing the semiconductor channel concentration and channel length. Furthermore, the thickness of the first gate insulating portion 31 away from the doped region 50 is thicker, which is beneficial to improving the accuracy of the dynamic parameters of the semiconductor device and improving the reliability of the semiconductor device.

[0062] In some alternative embodiments, such as Figure 1 As shown, the thickness of the first gate insulating portion 31 gradually increases from the doped region 50 toward the first gate insulating portion 31.

[0063] As an example, in the direction from the doped region 50 to the first gate insulating portion 31, that is, from the end of the first gate insulating portion 31 along the first direction X to the middle region of the first gate insulating portion 31 along the first direction X, the thickness of the first gate insulating portion 31 gradually increases. Here, "gradually increasing thickness" can refer to linear thickening, exponential thickening, logarithmic thickening, parabolic thickening, nonlinear thickening, progressive thickening, etc.

[0064] In these alternative embodiments, the above-described configuration can make the overall structure of the first gate insulating portion 31 a smooth structure, thereby optimizing the electric field distribution in the critical region of the semiconductor device and improving the performance of the semiconductor device.

[0065] Figure 2 This is a cross-sectional structural schematic diagram of another semiconductor device provided in some embodiments of this application.

[0066] In some alternative embodiments, such as Figure 2As shown, the first gate insulating portion 31 includes a first sub-portion 311 and two second sub-portions 312. The two second sub-portions 312 are arranged sequentially along the first direction X, and the first sub-portion 311 is disposed between the two second sub-portions 312. The thickness of the first sub-portion 311 is greater than the thickness of at least a portion of the second sub-portions 312. The orthogonal projection of the second sub-portion 312 onto the substrate 10 is located on the side of the first sub-portion 311 near the doped region 50.

[0067] For example, the first second sub-section 312 is adjacent to the first doped region 50, the second second sub-section 312 is adjacent to the second doped region 50, and the first sub-section 311 is located between the first second sub-section 312 and the second second sub-section 312.

[0068] In some examples, the thickness of the first sub-part 311 is greater than the overall thickness of either of the two second sub-parts 312. In other examples, the thickness of the first sub-part 311 is greater than a portion of the thickness of either of the two second sub-parts 312, and the thickness of the first sub-part 311 is equal to another portion of the thickness of either of the two second sub-parts 312.

[0069] Optionally, the thickness of the first sub-part 311 can be a uniform thickness or it can gradually increase in the direction from the doped part to the first gate insulating part 31.

[0070] Optionally, the thickness of the second sub-part 312 can be a uniform thickness or it can gradually increase in the direction from the doped part to the first gate insulating part 31.

[0071] Optionally, the thicknesses of the two second sub-parts 312 can be the same or different.

[0072] Optionally, the dimensions of the two second sub-parts 312 along the first direction X can be the same or different.

[0073] Optionally, the thickness of the second sub-part 312 and the thickness of the second gate insulating part 32 can be the same or different.

[0074] Through the above-described configuration, the structure in the first gate insulating portion 31 can form a stepped structure, thereby simplifying the fabrication difficulty of the first gate insulating portion 31, improving the fabrication yield of semiconductor devices, and reducing the fabrication cost of semiconductor devices.

[0075] In some alternative embodiments, such as Figure 1 and Figure 2As shown, the first sub-part 311 is symmetrically arranged with the perpendicular bisector of the shortest line connecting the two doped regions 50 along the first direction X, which improves the structural symmetry of the first gate insulating part 31, thereby optimizing the electric field distribution of the semiconductor device, improving the withstand voltage capability of the semiconductor device, and improving the reliability of the semiconductor device.

[0076] As an example, the shortest line connecting the two doped regions 50 along the first direction X can be the shortest distance between the two doped regions 50, and the perpendicular bisector of the shortest line connecting the two doped regions 50 along the first direction X is the perpendicular line to the midpoint of the shortest line.

[0077] In some examples, the two doped regions 50 are symmetrically arranged with respect to the perpendicular bisector of the shortest line connecting the two doped regions 50 along the first direction X.

[0078] In some alternative embodiments, such as Figure 1 and Figure 2 As shown, the two second sub-parts 312 are symmetrically arranged with the perpendicular bisector of the shortest line connecting the two doped regions 50 along the first direction X, which further improves the structural symmetry of the first gate insulating part 31, optimizes the electric field distribution of the semiconductor device, reduces parasitic parameters, and improves the overall performance of the semiconductor device.

[0079] In some alternative embodiments, such as Figure 1 and Figure 2 As shown, the epitaxial layer 20 includes a recess 21, which is formed by recessing the epitaxial layer 20 on the side away from the substrate 10, and at least a portion of the first gate insulating portion 31 is disposed in the recess 21.

[0080] A portion of the first gate insulating portion 31 is disposed within the recess 21, and another portion of the first gate insulating portion 31 is located outside the recess 21. Alternatively, the entire first gate insulating portion 31 may be located within the recess 21.

[0081] Optionally, the bottom surface of the recess 21 can be flat or curved, such as a curved bottom surface that is recessed toward the substrate 10.

[0082] The embodiments of this application, through the above-described configuration, facilitate the reduction of the dimension of the first gate insulating portion 31 in the thickness direction Z of the semiconductor device, thereby reducing the overall thickness dimension of the semiconductor device.

[0083] Figure 3 This is a cross-sectional structural schematic diagram of another semiconductor device provided in some embodiments of this application.

[0084] In some alternative embodiments, such as Figure 3 As shown, the first gate insulating portion 31 and the second gate insulating portion 32 are flush with each other on the side facing the substrate 10.

[0085] It is understood that the first gate insulating portion 31 and the second gate insulating portion 32 are flush with each other on the side facing the substrate 10, that is, the first sub-portion 311 and the second sub-portion 312 are flush with each other on the side facing the substrate 10, and the first sub-portion 311 and the second gate insulating portion 32 are flush with each other on the side facing the substrate 10.

[0086] Optionally, the surface of the epitaxial layer 20 facing away from the substrate 10 is planar.

[0087] Optionally, the semiconductor device may further include a first electrode 60 and a second electrode 80, wherein the first electrode 60 is located on the side of the epitaxial layer 20 facing away from the substrate 10, and the second electrode 80 is located on the side of the substrate 10 facing away from the epitaxial layer 20. Optionally, a gate 40 is located between a portion of the first electrode 60 and the epitaxial layer 20.

[0088] The embodiments of this application reduce the etching of the epitaxial layer 20 through the above settings, and reduce the impact of the gate 40 on the doped region 50 and drift region in the epitaxial layer 20 during the fabrication process, thereby improving the fabrication yield and overall performance of the semiconductor device.

[0089] Figure 4 This is a flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of this application. Figures 5 to 11 This is a schematic diagram illustrating the process structure of a method for fabricating a semiconductor device according to some embodiments of this application.

[0090] like Figures 4 to 11 As shown in the figure, this application provides a method for fabricating a semiconductor device, which includes the following steps:

[0091] S100, An epitaxial layer 20 is formed on one side of the substrate 10.

[0092] Specifically, in step S100, an epitaxial layer 20 can be formed on the substrate 10 by an epitaxial growth process. Optionally, the conductivity type of the substrate 10 and the conductivity type of the epitaxial layer 20 are the same.

[0093] S200, A first gate insulating portion is formed on the side of the epitaxial layer 20 facing away from the substrate 10.

[0094] Specifically, in step S200, the first gate insulating portion 31 can be formed by a thermal oxidation process or by a deposition process.

[0095] S300, a second gate insulating portion is formed on the periphery of the first gate insulating portion, and the first gate insulating portion 31 and the second gate insulating portion 32 form a gate insulating layer 30, wherein the minimum thickness of the first gate insulating portion 31 is greater than or equal to the thickness of the second gate insulating portion 32. The first gate insulating portion and the second gate insulating portion form a gate insulating layer.

[0096] Specifically, in step S300, the second gate insulating portion 32 can be formed by a mask process.

[0097] Optionally, when the material of the second gate insulating portion 32 is silicon oxide, the second gate insulating portion 32 can be formed by a thermal oxidation process.

[0098] S400, Two doped regions 50 are formed in the epitaxial layer 20 and disposed opposite to each other along a first direction X, the first direction X intersecting the thickness direction Z of the semiconductor device; wherein, the orthogonal projection of the first gate insulating portion 31 on the substrate 10 is located between the orthogonal projections of the two doped regions 50 on the substrate 10, the second gate insulating portion 32 is located at least between the doped region 50 and the gate 40, and the thickness of the first gate insulating portion 31 near the doped region 50 is less than the thickness of the gate 40 insulating portion away from the doped region 50.

[0099] Specifically, in step S400, the doped region 50 may include a first doped region 51, a second doped region 52, and a third doped region 53. The doped region 50 can be prepared after the gate 40 is prepared. After the gate insulating layer 30 is prepared, the gate 40 is prepared by deposition and etching processes. After the gate 40 is prepared, the epitaxial layer 20 can be subjected to ion implantation and thermal diffusion processes using the gate as a shielding structure to form the first doped region 51. The third doped region 53 and the second doped region 52 are then prepared sequentially by ion implantation. Optionally, the doping type of the first doped region 51 and the doping type of the third doped region 53 are the same, that is, the ions implanted in the first doped region 51 and the ions implanted in the third doped region 53 can be the same.

[0100] Alternatively, the doped region 50 can be prepared before the gate insulating layer 30 is prepared.

[0101] Optionally, such as Figure 1 After the doped region 50 is fabricated, an isolation dielectric layer 70 and a first electrode 60 can be sequentially fabricated on the surface of the epitaxial layer 20 facing away from the substrate 10 and on the surface of the gate 40 facing away from the substrate 10. The isolation dielectric layer 70 is used to isolate the direct electrical connection between the first electrode 60 and the gate 40. Optionally, the first electrode 60 is in contact with both the second doped portion 52 and the third doped portion 53.

[0102] In this embodiment, a semiconductor device is fabricated using the above-described method. The minimum thickness of the first gate insulating portion 31 is greater than or equal to the thickness of the second gate insulating portion 32, resulting in a locally thick oxide structure in the first gate insulating portion 31. By making the thickness of the end of the first gate insulating portion 31 near the doped region 50 smaller than the thickness of the end of the first gate insulating portion 31 away from the doped region 50, the thickness of the end of the first gate insulating portion 31 near the doped region 50 is reduced, thereby reducing the segregation effect during the formation of the first gate insulating portion 31, thus reducing the impact on the semiconductor device channel and increasing the semiconductor channel concentration and channel length. Furthermore, the greater thickness of the first gate insulating portion 31 away from the doped region 50 is beneficial for improving the accuracy of the dynamic parameters of the semiconductor device and enhancing its reliability.

[0103] In some alternative embodiments, such as Figures 5 to 10 As shown, the step of forming a first gate insulating portion on the side of the epitaxial layer 20 facing away from the substrate 10 includes:

[0104] S210. A first mask layer 1 is formed on the side of the epitaxial layer 20 facing away from the substrate 10. The first mask layer includes a first opening K1, which exposes a first region of the surface of the epitaxial layer 20 facing away from the substrate 10.

[0105] Specifically, in step S210, the first opening K1 on the first mask layer 1 can be formed by photolithography. For example, a first photoresist layer 2 with a preset pattern is formed on the side of the first mask layer 1 facing away from the substrate 10, and the first mask layer 1 is formed by etching. Optionally, after the first mask layer 1 is prepared, the photoresist layer is removed, thereby reducing the possibility of photoresist material falling into the first opening K1.

[0106] Optionally, a transition layer 3 may be provided between the first mask layer 1 and the epitaxial layer 20. The transition layer is used to increase the connection strength between the first mask layer 1 and the epitaxial layer 20 and reduce the possibility of separation between the first mask layer 1 and the epitaxial layer 20 during the fabrication process.

[0107] S220, A first dielectric portion 6 is formed in the first region and the first mask layer 1 is removed.

[0108] Specifically, in step S220, the epitaxial layer 20 material in the first region can be oxidized to form the first dielectric portion 6 through a heat treatment process. After the first dielectric portion 6 is prepared, the first mask layer 1 can be removed by a process such as etching. Optionally, the first mask layer 1 can be removed by a wet etching process.

[0109] S230, when the opening width of the first opening K1 is less than the preset width, a second mask layer 4 is formed on the side of the epitaxial layer 20 facing away from the substrate 10. The second mask layer includes a second opening K2. The opening width of the first opening K1 is less than the opening width of the second opening K2. The second opening K2 exposes the first dielectric portion 6 and a second region on the surface of the epitaxial layer 20 facing away from the substrate 10. The second region is located on the periphery of the first dielectric portion 6.

[0110] Specifically, in step S230, after the first dielectric portion 6 is fabricated, the opening width of the first opening K1 is less than a preset width, that is, the width of the first dielectric portion 6 (the dimension in the first direction X) is less than the preset width, and then the second dielectric portion 7 is fabricated. The second opening K2 in the second mask layer 4 exposes the second region of the epitaxial layer 20, and the second dielectric portion 7 is formed at least in the second region.

[0111] Optionally, the second opening K2 on the second mask layer 4 can be formed by photolithography. For example, a second photoresist layer 5 with a preset pattern is formed on the side of the second mask layer 4 facing away from the substrate 10, and the second mask layer 4 is formed by etching. Optionally, after the second mask layer 4 is formed, the photoresist layer is removed, thereby reducing the possibility of photoresist material falling into the second opening K2.

[0112] The fact that the opening width of the first opening K1 is smaller than the opening width of the second opening K2 can be understood as the size of the first opening K1 along the first direction X being smaller than the size of the second opening K2 along the first direction X.

[0113] Optionally, the second region can be two parts, with the two parts of the second region located on both sides of the first medium part 6 along the first direction X.

[0114] Optionally, the preset width can be less than or equal to the distance between the orthographic projections of the two doped regions 50 onto the substrate 10.

[0115] Optionally, a transition layer 3 may be provided between the second mask layer 4 and the epitaxial layer 20. The transition layer is used to increase the connection strength between the second mask layer 4 and the epitaxial layer 20, reducing the possibility of separation between the first mask layer 1 and the epitaxial layer 20 during the fabrication process. Optionally, the transition layer 3 may be retained when the first mask layer 1 is removed to facilitate the fabrication of the second mask layer 4.

[0116] S240, at least in the second region, a second dielectric portion 7 is formed and the second mask layer 4 is removed, wherein the thickness of the second dielectric portion 7 is less than the thickness of the first dielectric portion 6.

[0117] Specifically, in step S240, the epitaxial layer 20 material in the second region can be oxidized to form the second dielectric portion 7 through a heat treatment process. After the second dielectric portion 7 is prepared, the second mask layer 4 can be removed by a process such as wet etching. Optionally, the transition layer 3 can be removed at the same time as the second mask layer 4.

[0118] Optionally, the second dielectric portion 7 may be formed only in the second region, or a dielectric structure may be formed in both the second region and the first region, with the first dielectric portion 6 and the dielectric structure in the first region forming a thicker first dielectric portion 6, and the dielectric structure in the second region forming the second dielectric portion 7.

[0119] S250, if the opening width of the second opening K2 is less than the preset width, determine that the second mask layer 4 is the first mask layer 1, determine that the second opening K2 is the first opening K1, determine that the first dielectric portion 6 and the second dielectric portion 7 are both the first dielectric portion 6, and return to execute the step of forming the second mask layer 4 on the side of the epitaxial layer 20 facing away from the substrate 10 when the opening width of the first opening K1 is less than the preset width, until the opening width of the first opening K1 is equal to the preset width, the first dielectric portion 6 and the second dielectric portion 7 form the first gate insulating portion 31, the size of the two doped regions 50 along the first direction X is greater than or equal to the preset width, and the direction of the opening width is parallel to the first direction X.

[0120] Specifically, in step S250, the preset width is the dimension of the first gate insulating portion 31 along the first direction X. When the opening width of the second opening K2 is less than the preset width, and the sum of the dimensions of the first dielectric portion 6 and the second dielectric portion 7 along the first direction X is less than the dimension of the first gate insulating portion 31 along the first direction X, it is necessary to continue fabricating a dielectric structure to form the first gate insulating portion 31. At this time, the second mask layer 4 is determined as the first mask layer 1, the second opening K2 is determined as the first opening K1, and the first dielectric portion 6 and the second dielectric portion 7 are jointly determined as the first dielectric portion 6. Steps S230 and S240 are then executed. When the width of the first opening K1 is equal to the preset width, that is, the sum of the dimensions of the fabricated second dielectric portion 7 and the new first dielectric portion 6 along the first direction X is equal to the sum of the dimensions of the first gate insulating portion 31 along the first direction X, so that the second dielectric portion 7 and the first dielectric portion 6 form the first gate insulating portion 31.

[0121] Optionally, the first gate insulating portion 31 can be formed by performing one or more steps S230 and S240.

[0122] Through the above-described settings, the fabrication process steps can be adjusted according to design requirements, thereby simplifying the fabrication process of the first gate insulating portion 31, improving the yield of semiconductor device fabrication, and reducing the fabrication cost of semiconductor device.

[0123] In some other embodiments, the two ends of the first gate insulating portion 31 along the first direction X can be formed first, and the ends can be blocked by a mask structure. Then, the middle region of the first gate insulating portion 31 (the first region of the epitaxial layer 20) along the first direction X can be prepared.

[0124] In some alternative embodiments, the step of forming the first dielectric portion 6 in the first region includes: S221, performing a heat treatment process on the epitaxial layer 20 to form the first dielectric portion 6 from the epitaxial layer 20 material in the first region. At least the step of forming the second dielectric portion 7 in the second region includes: S241, performing a heat treatment process on the epitaxial layer 20 to form the second dielectric portion 7 from the epitaxial layer 20 material in the second region, and increasing the thickness of the first dielectric portion 6 so that the thickness of the second dielectric portion 7 is less than the thickness of the first dielectric portion 6.

[0125] Specifically, the thickness of the first dielectric part 6 prepared in step S221 can be D1, and the thickness of the first dielectric part 6 prepared in step S241 can be D2, where D2 > D1, meaning that the first dielectric part 6 is formed by two heat treatment processes.

[0126] Optionally, the two heat treatment processes can be the same, for example, the same heat treatment temperature and the same heat treatment time. Of course, they can also be different.

[0127] The embodiments of this application, through the above-described configuration, facilitate the simplification of the fabrication process of the first dielectric portion 6 and the second dielectric portion 7, improve the control accuracy of the thickness of the first gate insulating portion 31 at various locations, and enhance the reliability of the semiconductor device.

[0128] It should be noted that the semiconductor device provided in this application has the beneficial effects of the semiconductor device preparation method in any of the foregoing embodiments. For details, please refer to the foregoing description of the beneficial effects of the semiconductor device preparation method. This application will not repeat the details in this application.

[0129] Although this application has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of this application. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Drain; A substrate is disposed on one side of the drain electrode; An epitaxial layer is disposed on the side of the substrate away from the drain electrode, and the epitaxial layer includes two doped regions disposed opposite to each other along a first direction, the first direction intersecting the thickness direction of the semiconductor device; Gate; A gate insulating layer is located between the epitaxial layer and the gate. The gate insulating layer includes a first gate insulating portion and a second gate insulating portion. The orthogonal projection of the first gate insulating portion onto the substrate is located between the orthogonal projections of the two doped regions onto the substrate. The second gate insulating portion is located at least between the doped regions and the gate, and the second gate insulating portion is located on the periphery of the first gate insulating portion. The doped region and the first gate insulating portion are alternately arranged in the substrate. The thickness of the first gate insulating portion near the doped region is less than the thickness of the first gate insulating portion away from the doped region. The minimum thickness of the first gate insulating portion is greater than or equal to the thickness of the second gate insulating portion.

2. The semiconductor device according to claim 1, characterized in that, The thickness of the first gate insulating portion gradually increases from the direction of the doped region toward the first gate insulating portion.

3. The semiconductor device according to claim 1, characterized in that, The first gate insulating portion includes a first sub-portion and two second sub-portions, the two second sub-portions are arranged sequentially along the first direction, and the first sub-portion is disposed between the two second sub-portions. The thickness of the first sub-portion is greater than the thickness of at least a portion of the second sub-portions, and the orthographic projection of the second sub-portion on the substrate is located on the side of the first sub-portion closer to the doped region.

4. The semiconductor device according to claim 3, characterized in that, The first sub-section is symmetrically arranged with respect to the perpendicular bisector of the shortest line connecting the two doped regions along the first direction.

5. The semiconductor device according to claim 3, characterized in that, The two second sub-regions are symmetrically arranged with respect to the perpendicular bisector of the shortest line connecting the two doped regions along the first direction.

6. The semiconductor device according to claim 1, characterized in that, The epitaxial layer includes a recess formed by a depression in the epitaxial layer away from the substrate, and at least a portion of the first gate insulating portion is disposed within the recess.

7. The semiconductor device according to claim 1, characterized in that, The first gate insulating portion and the second gate insulating portion are flush with each other on the side facing the substrate.

8. A method for fabricating a semiconductor device, used to fabricate the semiconductor device as described in any one of claims 1 to 7, characterized in that, Preparation methods include: An epitaxial layer is formed on one side of the substrate; A first gate insulating portion is formed on the side of the epitaxial layer opposite to the substrate; A second gate insulating portion is formed on the periphery of the first gate insulating portion, the minimum thickness of the first gate insulating portion is greater than or equal to the thickness of the second gate insulating portion, and the first gate insulating portion and the second gate insulating portion form a gate insulating layer. Two doped regions are formed in the epitaxial layer and disposed opposite to each other along a first direction, which intersects the thickness direction of the semiconductor device; wherein, the orthogonal projection of the first gate insulating portion on the substrate is located between the orthogonal projections of the two doped regions on the substrate, the second gate insulating portion is located at least between the doped regions and the gate, and the thickness of the first gate insulating portion near the doped region is less than the thickness of the gate insulating portion away from the doped region.

9. The preparation method according to claim 8, characterized in that, The step of forming a first gate insulating portion on the side of the epitaxial layer opposite to the substrate includes: A first mask layer is formed on the side of the epitaxial layer facing away from the substrate. The first mask layer includes a first opening that exposes a first region of the surface of the epitaxial layer facing away from the substrate. A first dielectric portion is formed in the first region and the first mask layer is removed; When the opening width of the first opening is less than a preset width, a second mask layer is formed on the side of the epitaxial layer facing away from the substrate. The second mask layer includes a second opening. The opening width of the first opening is less than the opening width of the second opening. The second opening exposes the first dielectric portion and a second region of the surface of the epitaxial layer facing away from the substrate. The second region is located on the periphery of the first dielectric portion. At least in the second region, a second dielectric portion is formed and the second mask layer is removed, wherein the thickness of the second dielectric portion is less than the thickness of the first dielectric portion; If the opening width of the second opening is less than the preset width, the second mask layer is determined to be the first mask layer, the second opening is determined to be the first opening, the first dielectric portion and the second dielectric portion are determined to be the first dielectric portion, and the process returns to the step of forming a second mask layer on the side of the epitaxial layer facing away from the substrate when the opening width of the first opening is less than the preset width, until the opening width of the first opening is equal to the preset width, the first dielectric portion and the second dielectric portion form a first gate insulating portion, the dimensions of the two doped regions along the first direction are greater than or equal to the preset width, and the direction of the opening width is parallel to the first direction.

10. The preparation method according to claim 9, characterized in that, The step of forming the first dielectric portion in the first region includes: The epitaxial layer is subjected to a heat treatment process to form a first dielectric portion from the epitaxial layer material in the first region; The step of forming at least the second medium portion in the second region includes: The epitaxial layer is subjected to a heat treatment process to form a second dielectric portion from the epitaxial layer material in the second region, and the thickness of the first dielectric portion is increased so that the thickness of the second dielectric portion is less than the thickness of the first dielectric portion.

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