Junction field effect transistor device, preparation method thereof and electronic equipment

Abstract

According to the junction field effect transistor device, the preparation method thereof and the electronic equipment provided by the invention, the p-type gate region is formed on one side, far away from the n + substrate, of the n-drift layer through the injection type ions, so that the p-type gate region does not need to be realized through high-energy p-type ion deep injection, and the production efficiency is improved; and the n-type channel layer can be formed by using homoepitaxy, so that the design flexibility and the channel mobility of the device can be improved. Therefore, compared with Figure 1, the invention avoids the use of p-type deep ion implantation to form a bottom p-type gate region and the use of n-type deep ion implantation to form an n-type channel layer, thereby improving the design flexibility, production efficiency and channel mobility of the device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a junction field effect transistor device, a preparation method thereof, and an electronic device. Background Art

[0002] Junction field effect transistor (JFET) is widely used as an electrically controlled switch structure in electronic devices based on wide bandgap semiconductors, such as silicon carbide (SiC) and gallium nitride (GaN). JFET is a unipolar electronic device, that is, in the on state, there is basically only one type of carrier flowing in the channel of the semiconductor device to form a conduction current between the source and drain of the device. The gate of the JFET forms a pn junction with the channel. In a normally-on JFET, by applying a voltage to the gate, the pn junction is reverse biased to the channel pinch-off voltage to turn off the device.

[0003] Existing JFET devices can be divided into vertical and planar types according to the position of the channel relative to the wafer. Among them, the planar JFET is also called the lateral JFET, whose channel is horizontal to the wafer surface, and the width of the channel is determined by two upper and lower semiconductor gates that are also horizontal to the wafer and have opposite channel doping types. The variability of the spacing between these lateral semiconductor gates is determined by the change in the depth difference of the doping between the two. In semiconductor processing, the doping depth can be relatively simply and uniformly controlled between a few nanometers and a few microns by controlling the injection energy or epitaxial time. Therefore, the use of a planar channel can effectively improve the manufacturing capability of the device.

[0004] The most common manufacturing method for planar JFET is the injection method, which forms a channel and a semiconductor gate sandwiching the channel above and below through multiple ion injections. Figure 1 As shown, Figure 1 The planar triple-injection JFET and the corresponding manufacturing method proposed in the prior art (application number: 201680061749.4) form a top gate region 605a, a channel region 604 and a bottom gate region 605b by performing three ion implantations on the drift region, that is, forming a pnp structure of the JFET, and realizing the channel of the planar JFET. However, the lateral channel realized by this method has undergone multiple high-energy ion implantations, and the channel crystal quality is poor and the mobility is low. At the same time, high-dose deep ion implantation takes a long time, the semiconductor gate resistivity is large, and the gate resistance of the formed device is large. At the same time, there is a correlation between the ion implantation depth of the semiconductor gate and the device channel width and the turn-off voltage, so the on-resistance and turn-off voltage of the device are also limited by ion implantation.

[0005] like Figure 2 As shown, Figure 2The second prior art proposes a SiC JFET device with integrated Schottky diode and its manufacturing method (publication number: CN106783851B). This patent forms a p+ well layer by first implanting on the n-drift layer, and then performs secondary epitaxy to form an n channel, and then implants again to form p+ and n+ / p+ source contacts, and then connects the bottom p+ well to the p+ source contact area by p-type implantation. Because the bottom p+ well is connected to the source, when the device is turned off, the channel can only be unidirectionally cut off by the top gate / source pn junction depletion region, and the threshold voltage is relatively low. Figure 1 The more negative the voltage is, the larger the turn-off voltage of the device becomes, making it very difficult for the device to achieve a positive threshold voltage (i.e., a normally-off device) with a low on-resistance. Therefore, its Schottky junction design cannot achieve the desired reverse freewheeling effect. Figure 2 The integrated Schottky junction is not actually functional and wastes device area. Figure 2 The capacitance between the source and drain terminals of the device shown is much larger than Figure 1 The capacitance between the source and drain terminals of the device shown, if applied to a common cascode device, would increase its output capacitance, cause oscillation and increase switching losses.

[0006] Based on the above reasons, the existing JFET devices need to be improved. Summary of the invention

[0007] The embodiments of the present disclosure provide a junction field effect transistor device, a method for preparing the same, and an electronic device, which utilize homoepitaxial growth to form an n-type channel layer of the junction field effect transistor device, thereby improving the design flexibility and channel mobility of the device, and eliminating the need for high-energy p-type ion deep implantation to realize a p-type gate region, thereby improving production efficiency.

[0008] The embodiments of the present disclosure provide a junction field effect transistor device, a method for manufacturing the same, and an electronic device, the specific scheme of which is as follows:

[0009] In one aspect, an embodiment of the present disclosure provides a junction field effect transistor device, comprising an active region, wherein a cell structure of the active region comprises:

[0010] n+ substrate;

[0011] An n-drift layer, located on one side of the n+ substrate;

[0012] A p-type gate region is located in the n-drift layer and close to a side of the n-drift layer away from the n+ substrate;

[0013] An n-type channel layer, located on a side of the p-type gate region away from the n+ substrate;

[0014] The p+ gate region is located in the n-type channel layer and close to a side of the n-type channel layer away from the n+ substrate.

[0015] In some embodiments, in the above-mentioned junction field effect transistor device provided by the embodiments of the present disclosure, the cell structure of the active region further includes:

[0016] a p+ connection region, wherein a side of the p+ connection region away from the n+ substrate is located in the p+ gate region, a middle portion of the p+ connection region is located in the n-type channel layer, and a side of the p+ connection region close to the n+ substrate is located in the p-type gate region;

[0017] An n+ source region is located in the n-type channel layer and close to a side of the n-type channel layer away from the n+ substrate. The n+ source region is isolated from the p+ gate region by the n-type channel layer, and the n+ source region is spaced apart from the p+ connection region.

[0018] In some embodiments, in the above-mentioned junction field effect transistor device provided by the embodiments of the present disclosure, the cell structure of the active region further includes a first n-type current diffusion layer and a second n-type current diffusion layer located in the n-drift layer and arranged at intervals, the first n-type current diffusion layer and the second n-type current diffusion layer are both close to a side of the n-drift layer away from the n+ substrate, and the first n-type current diffusion layer and the second n-type current diffusion layer are respectively located on both sides of the p-type gate region;

[0019] The p-type gate region includes: a first surface and a second surface oppositely arranged and parallel to the n+ substrate, and a first side surface and a second side surface connecting the first surface and the second surface and oppositely arranged; the first n-type current diffusion layer covers the first side surface, and the second n-type current diffusion layer covers the second side surface.

[0020] In some embodiments, in the above-mentioned junction field effect transistor device provided by the embodiments of the present disclosure, the first surface of the p-type gate region is close to the n+ substrate, the first n-type current diffusion layer also covers a portion of the first surface, and the second n-type current diffusion layer also covers a portion of the first surface.

[0021] In some embodiments, in the above-mentioned junction field effect transistor device provided by the embodiments of the present disclosure, the orthographic projection of the p+ gate region on the n+ substrate completely covers the orthographic projections of the first n-type current diffusion layer and the second n-type current diffusion layer on the n+ substrate.

[0022] In some embodiments, in the above-mentioned junction field effect transistor device provided by the embodiments of the present disclosure, the cell structure of the active region further includes:

[0023] a dielectric layer, located at a side of the p+ gate region away from the n+ substrate, the dielectric layer having a first contact region corresponding to the p+ gate region and a second contact region corresponding to the n+ source region;

[0024] a gate ohmic contact layer, located on a side of the p+ gate region away from the n+ substrate and in the first contact region, the gate ohmic contact layer being electrically connected to the p+ gate region;

[0025] A source ohmic contact layer, located on a side of the n+ source region away from the n+ substrate and located in the second contact region;

[0026] A gate electrode, located on a side of the dielectric layer away from the n+ substrate and electrically connected to the gate ohmic contact layer;

[0027] A source electrode, located on a side of the dielectric layer away from the n+ substrate and electrically connected to the source ohmic contact layer;

[0028] The drain electrode is located on a side of the n+ substrate away from the n-drift layer.

[0029] In some embodiments, in the above-mentioned junction field effect transistor device provided by the embodiments of the present disclosure, the orthographic projection of the first contact region on the n+ substrate is located within the orthographic projection range of the p+ connection region on the n+ substrate;

[0030] Alternatively, the orthographic projection of the first contact region on the n+ substrate does not overlap with the orthographic projection of the p+ connection region on the n+ substrate;

[0031] Alternatively, the orthographic projection of the first contact region on the n+ substrate overlaps with the orthographic projections of the p+ connection region and the p+ gate region on the n+ substrate.

[0032] In some embodiments, the above-mentioned junction field effect transistor device provided by the embodiments of the present disclosure further includes a terminal region located at the periphery of the active region, the terminal region includes a plurality of field limiting ring structures arranged at intervals, the field limiting ring structure includes a first field limiting ring and a second field limiting ring arranged in stacked contact, the first field limiting ring is arranged in the same layer and material as the p-type gate region, and the second field limiting ring is arranged in the same layer and material as the p+ connection region.

[0033] In some embodiments, the above-mentioned junction field effect transistor device provided by the embodiments of the present disclosure further includes a terminal region located at the periphery of the active region, the terminal region includes a field limiting ring structure, the field limiting ring structure includes a plurality of first field limiting rings arranged at intervals and a plurality of second field limiting rings arranged at intervals, the first field limiting rings are arranged in the same layer and material as the p-type gate region, the second field limiting rings are arranged in the same layer and material as the p+ gate region, and the orthographic projection of the second field limiting ring on the n+ substrate covers the orthographic projections of two adjacent first field limiting rings on the n+ substrate.

[0034] In some embodiments, the above-mentioned junction field effect transistor device provided in the embodiments of the present disclosure further includes a terminal region located at the periphery of the active region, the terminal region includes a junction terminal extension structure, the junction terminal extension structure includes a first junction terminal extension, a second junction terminal extension and a third junction terminal extension arranged in a stacked manner, the first junction terminal extension and the p-type gate region are an integral structure, the second junction terminal extension and the p+ connection region are an integral structure, and the third junction terminal extension is arranged in the same layer and material as the p+ gate region.

[0035] On the other hand, the present disclosure also provides a method for preparing a junction field effect transistor device, which is used to prepare the above-mentioned junction field effect transistor device provided in the present disclosure, and the preparation method comprises:

[0036] epitaxially forming an n-drift layer on one side of the n+ substrate;

[0037] Implanting p-type ions on a side of the n-drift layer away from the n+ substrate to form a p-type gate region;

[0038] epitaxially forming an n-type channel layer on a side of the p-type gate region away from the n+ substrate;

[0039] P-type ions are implanted into a side of the n-type channel layer away from the n+ substrate to form a p+ gate region.

[0040] In some embodiments, the above preparation method provided in the embodiments of the present disclosure further includes:

[0041] Injecting p-type ions into a side of the p+ gate region away from the n+ substrate to form a p+ connection region, wherein the side of the p+ connection region away from the n+ substrate is located in the p+ gate region, the middle part of the p+ connection region is located in the n-type channel layer, and the side of the p+ connection region close to the n+ substrate is located in the p-type gate region;

[0042] N-type ions are implanted on a side of the p+ gate region away from the n+ substrate to form an n+ source region, an n-type channel layer is provided between the n+ source region and the p+ gate region, and the n+ source region is spaced apart from the p+ connection region.

[0043] In some embodiments, in the above-mentioned preparation method provided by the embodiments of the present disclosure, before the p-type ions are injected into the side of the n-drift layer away from the n+ substrate to form the p-type gate region, the method further includes: injecting n-type ions into the side of the n-drift layer away from the n+ substrate to form a first n-type current diffusion layer and a second n-type current diffusion layer spaced apart;

[0044] When p-type ions are implanted on a side of the n-drift layer away from the n+ substrate to form a p-type gate region, the first n-type current diffusion layer covers a first side surface and a portion of a first surface of the p-type gate region, and the second n-type current diffusion layer covers a second side surface and a portion of the first surface of the p-type gate region.

[0045] On the other hand, an embodiment of the present disclosure further provides an electronic device, comprising the above-mentioned junction field effect transistor device provided by an embodiment of the present disclosure.

[0046] The beneficial effects of the present disclosure are as follows:

[0047] The embodiments of the present disclosure provide a junction field effect transistor device, a method for manufacturing the same, and an electronic device. The p-type gate region is formed by implanting ions on the side of the n-drift layer away from the n+ substrate, so there is no need to use high-energy p-type ion deep implantation to realize the p-type gate region, thereby improving production efficiency; the n-type channel layer can be formed by homoepitaxial growth, which can improve the design flexibility and channel mobility of the device. Therefore, the present disclosure and Figure 1 In comparison, the present disclosure avoids using p-type deep ion implantation to form a bottom p-type gate region and using n-type deep ion implantation to form an n-type channel layer, thereby improving the design flexibility, production efficiency and channel mobility of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 A schematic diagram of the structure of a JFET provided by prior art 1;

[0049] Figure 2 A schematic diagram of the structure of a JFET provided by the second prior art;

[0050] Figure 3 A schematic diagram of a structure of a junction field effect transistor device provided in an embodiment of the present disclosure;

[0051] Figure 4 for Figure 3 Schematic diagram of the cross section along the AA' direction;

[0052] Figure 5 for Figure 3 Schematic diagram of the cross section along the BB' direction;

[0053] Figure 6 for Figure 3 A top view of the structure shown after a dielectric layer, a gate ohmic contact layer, a source ohmic contact layer, a gate electrode and a source electrode are sequentially formed above the structure;

[0054] Figure 7 A schematic diagram of another structure of a junction field effect transistor device provided in an embodiment of the present disclosure;

[0055] Figure 8 A schematic diagram of another structure of a junction field effect transistor device provided in an embodiment of the present disclosure;

[0056] Fig. 9 A schematic diagram of another structure of a junction field effect transistor device provided in an embodiment of the present disclosure;

[0057] Fig.10 For the prior art II Figure 2 The present disclosure Figure 3 Corresponding transfer characteristic curve of simulated device;

[0058] Fig.11 For the prior art Figure 1 , prior art II Figure 2 The present disclosure Figure 3 Schematic diagram of device specific on-resistance simulation of n-drift layer at different doping concentrations;

[0059] Fig. 12A Another structural schematic diagram provided for prior art 1;

[0060] Fig. 12B For the prior art II Figure 2 Schematic diagram with high field distribution areas marked;

[0061] Fig. 12C for Fig. 12A and Fig. 12B Corresponding drain withstand voltage electric field distribution diagram;

[0062] Fig.12D This is a diagram of the electric field distribution of the drain electrode withstand voltage disclosed in the present invention;

[0063] Fig.12E for Fig. 12A , Fig. 12B The electric field strength distribution curve along the Y direction of the edge of the top p+ gate region according to the present disclosure;

[0064] Fig.13 A flow chart of a method for preparing a junction field effect transistor device provided in an embodiment of the present disclosure;

[0065] Fig.14 A flow chart of another method for preparing a junction field effect transistor device provided in an embodiment of the present disclosure;

[0066] Fig.15 A flow chart of another method for preparing a junction field effect transistor device provided in an embodiment of the present disclosure;

[0067] Fig.16A for Figure 3 A schematic diagram of a structure of a junction field effect transistor device during the preparation process shown;

[0068] Fig. 16B for Figure 3 Another structural schematic diagram of a junction field effect transistor device during the preparation process shown;

[0069] Fig. 16C for Figure 3 Another structural schematic diagram of a junction field effect transistor device during the preparation process shown;

[0070] Fig.16D for Figure 3 Another structural schematic diagram of a junction field effect transistor device during the preparation process shown;

[0071] Fig.16E for Figure 3 Another structural schematic diagram of a junction field effect transistor device during the preparation process shown;

[0072] Fig.16F for Figure 3 Another structural schematic diagram of a junction field effect transistor device during the preparation process shown;

[0073] Figure 16G for Figure 3 Another structural schematic diagram of a junction field effect transistor device during the preparation process shown;

[0074] Fig.16H for Figure 16G A top view of a junction field effect transistor device shown;

[0075] Fig.16I for Figure 3 Another structural schematic diagram of a junction field effect transistor device during the preparation process shown;

[0076] Fig.16J for Figure 3 Another structural schematic diagram of a junction field effect transistor device during the preparation process shown;

[0077] Figure 16K for Figure 3Another structural schematic diagram of a junction field effect transistor device during the preparation process shown;

[0078] Figure 16L for Figure 3 Another structural schematic diagram of a junction field effect transistor device during the preparation process is shown. DETAILED DESCRIPTION

[0079] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described in conjunction with the drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thickness of the layers, films, panels, regions, etc. is magnified for clarity. In the present disclosure, exemplary embodiments are described with reference to cross-sectional views of schematic diagrams of idealized embodiments. In this way, deviations from the shapes of the figures as a result of, for example, manufacturing technology and / or tolerances will be expected. Therefore, the embodiments described in the present disclosure should not be interpreted as being limited to the specific shapes of the regions shown in the present disclosure, but include deviations in shape caused by, for example, manufacturing. For example, an area illustrated or described as flat may typically have rough and / or nonlinear features; the illustrated sharp corners may be rounded, etc. Therefore, the areas shown in the figures are schematic in nature, and their sizes and shapes do not represent the exact shapes of the illustrated areas, do not reflect the true proportions, and the purpose is only to illustrate the contents of the present disclosure. And the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0080] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" and the like mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0081] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer may be directly on, directly connected to, or there may be an intermediate element or intermediate layer. When an element or layer is referred to as being "disposed on one side of" another element or layer, the element or layer may be directly on one side of, directly connected to, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0082] The present disclosure provides a junction field effect transistor device, such as Figure 3-Figure 5 As shown, Figure 3 is a three-dimensional schematic diagram of a junction field effect transistor device. Figure 4 for Figure 3 Schematic diagram of the cross section along the AA' direction, Figure 5 for Figure 3 The cross-sectional schematic diagram along the BB' direction in FIG. 1 , the junction field effect transistor device includes an active region, and the cell structure of the active region includes:

[0083] n+ substrate 1; optionally, n+ substrate 1 is a substrate such as silicon carbide (SiC) or gallium nitride (GaN);

[0084] The n-drift layer 2 is located on one side of the n+ substrate 1. Optionally, the thickness of the n-drift layer 2 can be between 1 μm and 500 μm, such as 1 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 200 μm, 300 μm, 400 μm, 500 μm, etc., and the doping concentration can be between 1×10 14 cm -3 to 1×10 17 cm -3 Between, for example 1×10 14 cm -3 , 1×10 15 cm -3 , 1×10 16 cm -3 , 1×10 17 cm -3 wait;

[0085] The p-type gate region 3 is located in the n-drift layer 2 and close to the side of the n-drift layer 2 away from the n+ substrate 1. Specifically, the p-type gate region 3 is formed by injecting p-type ions on the side of the n-drift layer 2 away from the n+ substrate 1. Optionally, the p-type ions can be aluminum, boron, etc. The thickness of the p-type gate region 3 can be between 100nm and 1μm, for example, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, etc., and the doping concentration can be between 1×10 16 cm -3 to 1×10 20 cm -3 Between, for example 1×10 16 cm -3 , 1×10 17 cm -3 , 1×10 18 cm -3 , 1×10 19 cm -3 , 1×10 20 cm -3 wait;

[0086] The n-type channel layer 4 is located on the side of the p-type gate region 3 away from the n+ substrate 1; optionally, the thickness of the n-type channel layer 4 can be between 200 nm and 2 μm, such as 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1 μm, 2 μm, etc., and the doping concentration can be between 1×10 16 cm -3 to 1×10 20 cm -3 Between, for example 1×10 16 cm -3 , 1×10 17 cm -3 , 1×10 18 cm -3 , 1×10 19 cm -3 , 1×10 20 cm -3 wait;

[0087] The p+ gate region 5 is located in the n-type channel layer 4 and close to the side of the n-type channel layer 4 away from the n+ substrate 1. Specifically, the p+ gate region 5 is formed by injecting p-type ions on the side of the n-type channel layer 4 away from the n+ substrate 1. Optionally, the p-type ions can be aluminum, boron, magnesium, etc. The thickness of the p+ gate region 5 can be between 100nm and 1μm, for example, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, etc., and the doping concentration can be between 1×10 17 cm -3 to 1×10 20 cm -3 Between, for example 1×10 17 cm -3 , 1×10 18 cm -3 , 1×10 19 cm -3 , 1×10 20 cm -3 wait.

[0088] In the above-mentioned junction field effect transistor device provided by the embodiment of the present disclosure, the p-type gate region is formed by injecting p-type ions on the side of the n-drift layer away from the n+ substrate 1, so it is not necessary to use high-energy p-type ion deep implantation to realize the p-type gate region, thereby improving production efficiency; the n-type channel layer can be formed by homoepitaxial growth, which can improve the design flexibility and channel mobility of the device. Figure 1 In comparison, the present disclosure avoids using p-type deep ion implantation to form a bottom p-type gate region and using n-type deep ion implantation to form an n-type channel layer, thereby improving the design flexibility, production efficiency and channel mobility of the device.

[0089] In some embodiments, the above-mentioned junction field effect transistor device provided in the embodiments of the present disclosure is as follows: Figure 3-Figure 5 As shown, the distance between the edge of the p-type gate region 3 and the edge of the cell structure may be between 0.5 μm and 5 μm.

[0090] In some embodiments, the above-mentioned junction field effect transistor device provided in the embodiments of the present disclosure is as follows: Figure 3-Figure 5 As shown, the cellular structure of the active area also includes:

[0091] p+ connection region 6, the side of p+ connection region 6 away from n+ substrate 1 is located in p+ gate region 5, the middle part of p+ connection region 6 is located in n-type channel layer 4, and the side of p+ connection region 6 close to n+ substrate 1 is located in p-type gate region 3; thus, p+ gate region 5 and p-type gate region 3 are connected through periodically distributed p+ connection regions 6, and p+ connection region 6 can be arranged inside or at the edge of the active region. Figure 2 Compared with the structure shown in FIG. 1 , the p-type gate region 3 of the present invention is electrically connected to the gate (described later) through the p+ connection region 6 and the p+ gate region 5, so that the threshold voltage of the device can be corrected when the on-resistance is the same, which is beneficial to the shutdown of the device; specifically, the p+ connection region 6 is formed by injecting p-type ions on the side of the p+ gate region 5 away from the n+ substrate 1, and the specific position of the p+ connection region 6 is affected by the ion implantation process; optionally, the p-type ions can use aluminum, boron and other ions; the thickness of the p+ connection region 6 can be between 100nm and 3μm, for example, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 2μm, 3μm, etc., and the doping concentration can be between 1×10 17 cm -3 to 1×10 20 cm -3 Between, for example 1×10 17 cm -3 , 1×10 18 cm -3 , 1×10 19 cm -3 , 1×10 20 cm -3 wait;

[0092] The n+ source region 7 is located in the n-type channel layer 4 and close to the side of the n-type channel layer 4 away from the n+ substrate 1. The n+ source region 7 is isolated from the p+ gate region 5 by the n-type channel layer 4, and the n+ source region 7 is spaced apart from the p+ connection region 6. Specifically, the n+ source region 7 is formed by injecting n-type ions on the side of the n-type channel layer 4 away from the n+ substrate 1, and the n+ source region 7 and the p+ connection region 6 are arranged alternately. The n+ source region 7 of the device is surrounded by the p+ gate region 5, and there is a buffer zone of the n-type channel layer 4 at a certain distance between the n+ source region 7 and the p+ gate region 5, that is, when the p+ gate region 5 is formed by ion implantation, the n+ source region 7 and the buffer zone to be formed are shielded, and this buffer zone can effectively improve the reverse breakdown voltage of the gate. Optionally, the n-type ions may be nitrogen, phosphorus, silicon, arsenic, etc.; the thickness of the n+ source region 7 may be between 100 nm and 500 nm, for example, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, and the doping concentration may be between 1×10 17 cm -3 to 1×10 20 cm -3 Between, for example 1×10 17 cm -3 , 1×10 18 cm -3 , 1×10 19 cm -3, 1×10 20 cm -3 wait.

[0093] In some embodiments, the above-mentioned junction field effect transistor device provided in the embodiments of the present disclosure is as follows: Figure 3-Figure 5 As shown, the orthographic projection of the p+ connection region 6 on the n+ substrate 1 is located between the orthographic projections of the bottom p-type gate region 3 and the p+ gate region 5 on the n+ substrate 1 , so that the p-type gate region 3 and the p+ gate region 5 can be connected through the p+ connection region 6 .

[0094] In some embodiments, the above-mentioned junction field effect transistor device provided in the embodiments of the present disclosure is as follows: Figure 3-Figure 5 As shown, the cell structure of the active region further includes a first n-type current diffusion layer 81 and a second n-type current diffusion layer 82 which are located in the n-drift layer 2 and are spaced apart from each other. The first n-type current diffusion layer 81 and the second n-type current diffusion layer 82 are both close to a side of the n-drift layer 2 away from the n+ substrate 1, and the first n-type current diffusion layer 81 and the second n-type current diffusion layer 82 are respectively located on both sides of the p-type gate region 3;

[0095] The p-type gate region 3 includes: a first surface 31 and a second surface 32 that are oppositely disposed and parallel to the n+ substrate 1, and a first side surface 33 and a second side surface 34 that are oppositely disposed and connected to the first surface 31 and the second surface 32; a first n-type current diffusion layer 81 covers the first side surface 33, and a second n-type current diffusion layer 82 covers the second side surface 34. The present disclosure can reduce the specific on-resistance of the device by introducing the first n-type current diffusion layer 81 and the second n-type current diffusion layer 82, so that the specific on-resistance of the device is relatively Figure 1 and Figure 2 It is greatly reduced, which is helpful to reduce device cost.

[0096] In some embodiments, the above-mentioned junction field effect transistor device provided in the embodiments of the present disclosure is as follows: Figure 3-Figure 5 As shown, the first surface 31 of the p-type gate region 3 is close to the n+ substrate 1, the first n-type current diffusion layer 81 also covers a portion of the first surface 31, and the second n-type current diffusion layer 82 also covers a portion of the first surface 31. This can further reduce the specific on-resistance of the device. The specific on-resistance of the device disclosed in the present invention is relatively Figure 1 and Figure 2 The reduction ratio is about 25% to 40%.

[0097] Specifically, Figure 3-Figure 5As shown, the first n-type current diffusion layer 81 and the second n-type current diffusion layer 82 are formed by injecting n-type ions on the side of the n-drift layer 2 away from the n+ substrate 1 before ion implantation to form the p-type gate region 3; optionally, the n-type ions can use nitrogen, phosphorus and other ions; the thickness of the first n-type current diffusion layer 81 and the second n-type current diffusion layer 82 can be between 100nm and 2μm, for example, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 2μm, etc., and the doping concentration can be between 1×10 14 cm -3 to 1×10 20 cm -3 Between, for example 1×10 14 cm -3 , 1×10 15 cm -3 , 1×10 16 cm -3 , 1×10 17 cm -3 , 1×10 18 cm -3 , 1×10 19 cm -3 , 1×10 20 cm -3 wait.

[0098] In some embodiments, the above-mentioned junction field effect transistor device provided in the embodiments of the present disclosure is as follows: Figure 3-Figure 5 As shown, the orthographic projection of the p+ gate region 5 on the n+ substrate 1 completely covers the orthographic projections of the first n-type current diffusion layer 81 and the second n-type current diffusion layer 82 on the n+ substrate 1 .

[0099] In some embodiments, the above-mentioned junction field effect transistor device provided in the embodiments of the present disclosure is as follows: Figure 3-Figure 5 As shown, the cellular structure of the active area also includes:

[0100] The dielectric layer 9 is located on a side of the p+ gate region 5 away from the n+ substrate 1. The dielectric layer 9 has a first contact region V1 corresponding to the p+ gate region 5 and a second contact region V2 corresponding to the n+ source region 7. Optionally, the first contact region V1 and the second contact region V2 are through holes that penetrate the thickness of the dielectric layer 9 and are formed by an etching process. The thickness of the dielectric layer 9 can be between 20nm and 2μm, for example, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 2μm, etc. The material of the dielectric layer 9 can be a dielectric material such as silicon dioxide and silicon nitride.

[0101] The gate ohmic contact layer 10 is located on a side of the p+ gate region 5 away from the n+ substrate 1 and in the first contact region V1, and the gate ohmic contact layer 10 is electrically connected to the p+ gate region 5; optionally, the material of the gate ohmic contact layer 10 may be a metal such as nickel, aluminum, titanium, tungsten, and alloys thereof, and the thickness of the gate ohmic contact layer 10 may be between 20 nm and 200 nm, for example, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 200 nm, etc.;

[0102] The source ohmic contact layer 11 is located on a side of the n+ source region 7 away from the n+ substrate 1 and in the second contact region V2; optionally, the source ohmic contact layer 11 and the gate ohmic contact layer 10 can be formed by a single deposition process, and the material of the source ohmic contact layer 11 can be nickel, aluminum, titanium, tungsten and other metals and alloys thereof, and the thickness of the source ohmic contact layer 11 can be between 20nm and 200nm, for example, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 200nm, etc.;

[0103] The gate electrode 12 is located on the side of the dielectric layer 9 away from the n+ substrate 1, and is electrically connected to the gate ohmic contact layer 10; thus, the p+ gate region 5 is electrically connected to the gate electrode 12 through the gate ohmic contact layer 10, that is, the gate electrode 12 is electrically connected to the p-type gate region 3, the p+ connection region 6, and the p+ gate region 5; optionally, the material of the gate electrode 12 can be titanium, aluminum, gold, silver, copper and other metals and alloys thereof, or can be heavily doped polysilicon, titanium nitride, indium tin oxide and other conductive materials;

[0104] The source electrode 13 is located on the side of the dielectric layer 9 away from the n+ substrate 1 and is electrically connected to the source ohmic contact layer 11; thus, the n+ source region 7 is electrically connected to the source electrode 13 through the source ohmic contact layer 11, the source electrode 13 and the gate electrode 12 are isolated from the underlying semiconductor structure through the dielectric layer 9, and different cell structures in the active region of the device are connected through the source electrode 13 and the gate electrode 12; optionally, the source electrode 13 and the gate electrode 12 can be formed by a single etching process, and the material of the source electrode 13 can be metals such as titanium, aluminum, gold, silver, copper, and alloys thereof, or can be conductive materials such as heavily doped polysilicon, titanium nitride, indium tin oxide, etc.;

[0105] The drain electrode 14 is located on the side of the n+ substrate 1 away from the n- drift layer 2; optionally, the material of the drain electrode 14 can be nickel, aluminum, titanium, tungsten and other metals and their alloys, and the thickness of the drain electrode 14 can be between 20nm and 2μm, for example, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 2μm, etc.

[0106] Specifically, Figure 6 As shown, Figure 6 for Figure 3 The structure shown is a top view after a dielectric layer 9, a gate ohmic contact layer 10, a source ohmic contact layer 11, a gate electrode 12 and a source electrode 13 are formed in sequence. A dielectric layer 9 of a certain width is provided between the source electrode 13 and the gate electrode 12 to prevent leakage between the source electrode 13 and the gate electrode 12.

[0107] Specifically, Figure 3-Figure 5 As shown, when the device is working, electrons flow from the source electrode 13 first through the n-type channel layer 4, then enter the n-drift layer 2 through the first n-type current diffusion layer 81 and the second n-type current diffusion layer 82, and finally reach the drain electrode 14 to form current.

[0108] In some embodiments, the above-mentioned junction field effect transistor device provided in the embodiments of the present disclosure is as follows: Figure 4 As shown, the orthographic projection of the first contact region V1 on the n+ substrate 1 is located within the orthographic projection range of the p+ connection region 6 on the n+ substrate 1; of course, the orthographic projection of the first contact region V1 on the n+ substrate 1 may not overlap with the orthographic projection of the p+ connection region 6 on the n+ substrate 1; or the orthographic projection of the first contact region V1 on the n+ substrate 1 may overlap with the orthographic projections of the p+ connection region 6 and the p+ gate region 5 on the n+ substrate 1. In this way, the gate ohmic contact layer 10 can be electrically connected to the p+ gate region 5, thereby achieving electrical connection between the gate electrode 12 and the p+ gate region 5.

[0109] In some embodiments, the above-mentioned junction field effect transistor device provided in the embodiments of the present disclosure is as follows: Figure 7 As shown, it also includes a terminal area BB located at the periphery of the active area AA, and the terminal area BB includes a plurality of field limiting ring structures 20 arranged at intervals. The field limiting ring structure 20 includes a first field limiting ring 21 and a second field limiting ring 22 arranged in stacked contact. The first field limiting ring 21 is arranged in the same layer and material as the p-type gate area 3, and the second field limiting ring 22 is arranged in the same layer and material as the p+ connection area 6, that is, the first field limiting ring 21 at the bottom is formed by sharing the photolithography mask and injection process steps with the aforementioned p-type gate area 3, and the second field limiting ring 22 at the top is formed by sharing the photolithography mask and injection process steps with the aforementioned p+ connection area 6.

[0110] In some embodiments, the above-mentioned junction field effect transistor device provided in the embodiments of the present disclosure is as follows: Figure 8 As shown, it also includes a terminal area BB located at the periphery of the active area AA, and the terminal area BB includes a field limiting ring structure 20. The field limiting ring structure 20 includes a plurality of first field limiting rings 21 arranged at intervals and a plurality of second field limiting rings 22 arranged at intervals. The first field limiting rings 21 are arranged in the same layer and material as the p-type gate area 3, and the second field limiting rings 22 are arranged in the same layer and material as the p+ gate area 5. The orthographic projection of the second field limiting ring 22 on the n+ substrate 1 covers the orthographic projections of the two adjacent first field limiting rings 21 on the n+ substrate 1, that is, the first field limiting ring 21 at the bottom is formed by sharing the photolithography mask and the injection process steps with the aforementioned p-type gate area 3, and the second field limiting ring 22 at the top is formed by sharing the photolithography mask and the injection process steps with the aforementioned p+ gate area 5.

[0111] In some embodiments, the above-mentioned junction field effect transistor device provided in the embodiments of the present disclosure is as follows: Fig. 9 As shown, it also includes a terminal area BB located at the periphery of the active area AA, the terminal area BB includes a junction terminal extension structure 30, the junction terminal extension structure 30 includes a first junction terminal extension 31, a second junction terminal extension 32 and a third junction terminal extension 33 which are stacked, the first junction terminal extension 31 and the p-type gate area 3 are an integral structure, the second junction terminal extension 32 and the p+ connection area 6 are an integral structure, the third junction terminal extension 33 and the p+ gate area 5 are arranged in the same layer and with the same material, that is, the first junction terminal extension 31 at the bottom is formed by sharing the photolithography mask and injection process steps with the aforementioned p-type gate area 3, the second junction terminal extension 32 in the middle is formed by sharing the photolithography mask and injection process steps with the aforementioned p+ connection area 6, and the third junction terminal extension 33 at the top is formed by sharing the photolithography mask and injection process steps with the aforementioned p+ gate area 5.

[0112] Specifically, Figure 7-Figure 9As shown, the terminal region BB is located at the periphery of the active region AA. By arranging a field limiting ring structure 20 or a junction terminal extension structure 30 in the terminal region BB, the electric field concentration phenomenon can be weakened. At the same time, the electric field distribution in the terminal region BB can improve the overall withstand voltage level of the junction field effect transistor device.

[0113] In some embodiments, in the above-mentioned junction field effect transistor device provided in the embodiments of the present disclosure, the planar structure of the unit cell structure can be a strip, a rectangle or a hexagon, etc. After the gate electrode and the source electrode are completed, the device can be formed into a complete device by forming different units such as strip cells, square cells, hexagonal cells, etc. Figure 3 The planar structure of the cellular structure is a rectangle as an example. Of course, it can also be a hexagonal cellular structure layout, which can make the layout of the p+ connection area more uniform and reduce the gate electrode resistance.

[0114] In some embodiments, the junction field effect transistor device provided by the embodiments of the present disclosure may be made of wide bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) through processes such as epitaxy and ion implantation.

[0115] The inventor of the present disclosure has made a Figure 2 and the present disclosure Figure 3 The corresponding threshold voltage is simulated, such as Fig.10 As shown, Fig.10 For the prior art II Figure 2 The present disclosure Figure 3 The corresponding simulated device transfer characteristic curve, the horizontal axis is the threshold voltage (V GS ), the vertical axis is the drain electrode current (I D ), it can be seen that, compared with the prior art 2, since the present disclosure uses the p-type gate region 3 to be electrically connected to the gate electrode 12, the threshold voltage of the device is corrected when the on-resistance is the same, which is beneficial to the shutdown of the device.

[0116] like Fig.11 As shown, Fig.11 For the prior art Figure 1 , prior art II Figure 2 With the present disclosure Figure 3 From the simulation diagram of the device specific on-resistance of the n-drift layer at different doping concentrations, it can be seen that the present application can greatly reduce the specific on-resistance of the device compared with the prior art one and the prior art two due to the provision of the first n-type current diffusion layer 81 and the second n-type current diffusion layer 82, with a reduction ratio of about 25% to 40%, which is beneficial to reducing the device cost.

[0117] like Figure 12A-12E As shown, Fig. 12A It is another structural diagram of the prior art. Fig. 12AThe high field distribution area is marked. Fig. 12B For the prior art II Figure 2 Schematic diagram with high field distribution areas marked. Fig. 12C for Fig. 12A and Fig. 12B The corresponding drain withstand voltage electric field distribution diagram, Fig.12D is the electric field distribution diagram of the drain electrode withstand voltage disclosed in the present invention, Fig.12E for Fig. 12A , Fig. 12B From the electric field strength distribution curve along the Y direction of the top p+ gate region edge of the present invention, it can be seen that Fig. 12A and Fig. 12B The corresponding top p-type gate angle and bottom p-type gate angle have high electric fields, and the present disclosure effectively suppresses the electric field strength of the top p+ gate region and the bottom p-type gate region angle, and the present disclosure can achieve a higher breakdown voltage. Compared with the prior art 1 and the prior art 2, the electric field strength suppressed by the present disclosure can reach 1MV / cm.

[0118] In summary, the junction field effect transistor device provided by the present invention does not need to use high-energy p-type ion deep implantation to realize the p-type gate region, thereby improving production efficiency; the n-type channel layer is formed by epitaxial growth, thereby ensuring the mobility of the channel; the first n-type current diffusion layer and the second n-type current diffusion layer are formed by n-type ion implantation, thereby reducing the device's specific on-resistance.

[0119] Based on the same inventive concept, an embodiment of the present disclosure provides a method for preparing the above-mentioned junction field effect transistor device. Since the principle of solving the problem by the preparation method is similar to the principle of solving the problem by the above-mentioned junction field effect transistor device, the implementation of the preparation method provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned junction field effect transistor device provided by the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0120] In some embodiments, the method for preparing the above-mentioned junction field effect transistor device provided by the embodiments of the present disclosure is as follows: Fig.13 As shown, it may include:

[0121] S1301, epitaxially forming an n-drift layer on one side of the n+ substrate;

[0122] S1302, injecting p-type ions into a side of the n-drift layer away from the n+ substrate to form a p-type gate region;

[0123] S1303, epitaxially forming an n-type channel layer on a side of the p-type gate region away from the n+ substrate;

[0124] S1304 , implanting p-type ions into a side of the n-type channel layer away from the n+ substrate to form a p+ gate region.

[0125] In some embodiments, in the above-mentioned preparation method provided in the embodiments of the present disclosure, if Fig.14 As shown, it also includes:

[0126] S1401, injecting p-type ions into a side of the p+ gate region away from the n+ substrate to form a p+ connection region, wherein the side of the p+ connection region away from the n+ substrate is located in the p+ gate region, the middle part of the p+ connection region is located in the n-type channel layer, and the side of the p+ connection region close to the n+ substrate is located in the p-type gate region;

[0127] S1402, injecting n-type ions into a side of the p+ gate region away from the n+ substrate to form an n+ source region, wherein an n-type channel layer is provided between the n+ source region and the p+ gate region, and the n+ source region and the p+ connection region are spaced apart.

[0128] In some embodiments, in the above-mentioned preparation method provided by the embodiment of the present disclosure, before performing step S1302 to implant p-type ions on the side of the n-drift layer away from the n+ substrate to form a p-type gate region, as Fig.15 As shown, it also includes: S1501, forming a first n-type current diffusion layer and a second n-type current diffusion layer spaced apart by injecting n-type ions on a side of the n-drift layer away from the n+ substrate;

[0129] When performing step S1302 to implant p-type ions on a side of the n-drift layer away from the n+ substrate to form a p-type gate region, the first n-type current diffusion layer covers a first side surface and a portion of the first surface of the p-type gate region, and the second n-type current diffusion layer covers a second side surface and a portion of the first surface of the p-type gate region.

[0130] In order to better understand the above preparation method provided in the embodiments of the present disclosure, Figure 3 Taking the junction field effect transistor device shown as an example, the preparation process of the junction field effect transistor device is described in detail.

[0131] In some embodiments, Figure 3 The preparation process of the junction field effect transistor device shown may specifically include the following steps:

[0132] (1) Fig.16A As shown, an n- drift layer 2 is epitaxially grown on one side of an n+ substrate 1 .

[0133] (2) Fig. 16B As shown, photolithography masking is performed on the side of the n- drift layer 2 away from the n+ substrate 1 to leave a mask 100, and then ion implantation (as shown by the arrows) is performed to form a first n-type current diffusion layer 81 and a second n-type current diffusion layer 82.

[0134] (3) Fig. 16CAs shown, after removing the mask 100 , photolithography masking is performed again, leaving the mask 200 , and then ion implantation (as shown by the arrow) is performed to form the p-type gate region 3 .

[0135] (4) Fig.16D As shown, after removing the mask 200, the wafer surface is fully cleaned, and then an n-type channel layer 4 is epitaxially grown on the formed structure.

[0136] (5) Fig.16E As shown, a photolithography mask is formed on the side of the epitaxial n-type channel layer 4 away from the n+ substrate 1, leaving a mask 300, and then ion implantation (as shown by the arrow) is performed to form a p+ gate region 5. Optionally, the orthographic projection of the mask 300 on the n+ substrate 1 is located inside the orthographic projection of the p-type gate region 3 on the n+ substrate 1.

[0137] (6) Fig.16F As shown, after removing the mask 300, the mask is photolithographically removed again, leaving the mask 400, and then ion implantation (as shown by the arrow) is performed to form the p+ connection region 6. Optionally, the orthographic projection of the p+ connection region 6 on the n+ substrate 1 is located between the orthographic projections of the p-type gate region 3 and the p+ gate region 5 on the n+ substrate 1.

[0138] (7) Figure 16G As shown, after removing the mask 400, the mask is photolithographically removed again, leaving the mask 500, and then ion implantation is performed (as shown by the arrow) to form the n+ source region 7. At this time, the top view of the device after the epitaxy and ion implantation is completed is as shown in FIG. Fig.16H As shown, the n+ source region 7 of the device is surrounded by the top p+ gate region 5, and there is a buffer zone of the n-type channel layer 4 at a certain distance between the two. This buffer zone can effectively improve the reverse breakdown voltage of the gate.

[0139] (8) Fig.16I and Fig.16J As shown, after removing the mask 500, the dielectric layer 9 is deposited, and then the photolithography mask is performed. After leaving the mask, the dielectric layer 9 is etched, and the etching area can be located above the p+ gate area 5 and the n+ source area 7 to form the first contact area V1 and the second contact area V2 (i.e., the through hole). After the etching is completed, the dielectric layer 9 is left, and then the ohmic metal is deposited, and the deposition area is located above the p+ gate area 5 and the n+ source area 7. Then, high-temperature annealing is performed to form the gate ohmic contact layer 10 and the source ohmic contact layer 11.

[0140] (9) Figure 16K and Figure 16L As shown, after forming the gate ohmic contact layer 10 and the source ohmic contact layer 11 , a conductive interconnect layer is deposited to form a gate electrode 12 and a source electrode 13 .

[0141] (10) After the interconnection deposition is completed, the drain electrode 14 is deposited and the ohmic contact is annealed to form the drain electrode 14, such as Figure 4 and Figure 5 shown.

[0142] Through the above steps (1) to (10), Figure 3 The junction field effect transistor device shown.

[0143] It should be noted that in the above-mentioned preparation method provided in the embodiment of the present disclosure, the patterning process involved in forming each layer structure may include not only part or all of the process such as deposition, photoresist coating, mask masking, exposure, development, etching, photoresist stripping, etc., but also other process, which is subject to the graphics of the required composition formed in the actual production process, and is not limited here. For example, a post-baking process may also be included after development and before etching. Among them, the deposition process may be chemical vapor deposition, plasma enhanced chemical vapor deposition or physical vapor deposition, which is not limited here; the mask used in the mask process may be a half-tone mask (Half Tone Mask), a single slit diffraction mask (Single Slit Mask) or a gray tone mask (Gray Tone Mask), which is not limited here; etching may be dry etching or wet etching, which is not limited here.

[0144] Based on the same inventive concept, an embodiment of the present disclosure provides an electronic device, including the above-mentioned junction field effect transistor device provided by the embodiment of the present disclosure. Since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the above-mentioned junction field effect transistor device, the implementation of the electronic device provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned junction field effect transistor device provided by the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0145] In some embodiments, the electronic devices provided by the embodiments of the present disclosure may include, but are not limited to: radio frequency amplifiers, mixers, radars, satellites, power supplies, automotive electronics, energy-saving lamps, household appliances, etc. Of course, in addition to junction field effect transistor devices, the electronic devices provided by the present disclosure may also include other structures, for example, when the electronic device is a radar, it also includes: transmitters, antennas, receivers, etc.; when the electronic device is a mixer, it also includes: input ports, output ports, etc.

[0146] The embodiments of the present disclosure provide a junction field effect transistor device, a method for manufacturing the same, and an electronic device. The p-type gate region is formed by implanting ions on the side of the n-drift layer away from the n+ substrate, so there is no need to use high-energy p-type ion deep implantation to realize the p-type gate region, thereby improving production efficiency; the n-type channel layer can be formed by homoepitaxial growth, which can improve the design flexibility and channel mobility of the device. Therefore, the present disclosure and Figure 1 In comparison, the present disclosure avoids using p-type deep ion implantation to form a bottom p-type gate region and using n-type deep ion implantation to form an n-type channel layer, thereby improving the design flexibility, production efficiency and channel mobility of the device.

[0147] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0148] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A junction field effect transistor device, characterized in that: The invention comprises an active region, wherein the cellular structure of the active region comprises: n+ substrate; An n-drift layer, located on one side of the n+ substrate; A p-type gate region is located in the n-drift layer and close to a side of the n-drift layer away from the n+ substrate; An n-type channel layer, located on a side of the p-type gate region away from the n+ substrate; The p+ gate region is located in the n-type channel layer and close to a side of the n-type channel layer away from the n+ substrate.

2. The junction field effect transistor device according to claim 1, characterized in that: The cellular structure of the active region further comprises: a p+ connection region, wherein a side of the p+ connection region away from the n+ substrate is located in the p+ gate region, a middle portion of the p+ connection region is located in the n-type channel layer, and a side of the p+ connection region close to the n+ substrate is located in the p-type gate region; An n+ source region is located in the n-type channel layer and close to a side of the n-type channel layer away from the n+ substrate. The n+ source region is isolated from the p+ gate region by the n-type channel layer, and the n+ source region is spaced apart from the p+ connection region.

3. The junction field effect transistor device according to claim 2, characterized in that: The cell structure of the active region further includes a first n-type current diffusion layer and a second n-type current diffusion layer located in the n-drift layer and spaced apart from each other, the first n-type current diffusion layer and the second n-type current diffusion layer both being close to a side of the n-drift layer away from the n+ substrate, and the first n-type current diffusion layer and the second n-type current diffusion layer being located at two sides of the p-type gate region respectively; The p-type gate region includes: a first surface and a second surface oppositely arranged and parallel to the n+ substrate, and a first side surface and a second side surface connecting the first surface and the second surface and oppositely arranged; the first n-type current diffusion layer covers the first side surface, and the second n-type current diffusion layer covers the second side surface.

4. The junction field effect transistor device according to claim 3, characterized in that: The first surface of the p-type gate region is close to the n+ substrate, the first n-type current diffusion layer also covers a portion of the first surface, and the second n-type current diffusion layer also covers a portion of the first surface.

5. The junction field effect transistor device according to claim 4, characterized in that: The orthographic projection of the p+ gate region on the n+ substrate completely covers the orthographic projections of the first n-type current diffusion layer and the second n-type current diffusion layer on the n+ substrate.

6. The junction field effect transistor device according to claim 5, characterized in that: The cellular structure of the active region further comprises: a dielectric layer, located at a side of the p+ gate region away from the n+ substrate, the dielectric layer having a first contact region corresponding to the p+ gate region and a second contact region corresponding to the n+ source region; a gate ohmic contact layer, located on a side of the p+ gate region away from the n+ substrate and in the first contact region, the gate ohmic contact layer being electrically connected to the p+ gate region; A source ohmic contact layer, located on a side of the n+ source region away from the n+ substrate and located in the second contact region; A gate electrode, located on a side of the dielectric layer away from the n+ substrate and electrically connected to the gate ohmic contact layer; A source electrode, located on a side of the dielectric layer away from the n+ substrate and electrically connected to the source ohmic contact layer; The drain electrode is located on a side of the n+ substrate away from the n-drift layer.

7. The junction field effect transistor device according to claim 6, characterized in that: The orthographic projection of the first contact region on the n+ substrate is located within the orthographic projection range of the p+ connection region on the n+ substrate; Alternatively, the orthographic projection of the first contact region on the n+ substrate does not overlap with the orthographic projection of the p+ connection region on the n+ substrate; Alternatively, the orthographic projection of the first contact region on the n+ substrate overlaps with the orthographic projections of the p+ connection region and the p+ gate region on the n+ substrate.

8. The junction field effect transistor device according to any one of claims 2 to 7, characterized in that: It also includes a terminal area located at the periphery of the active area, the terminal area includes a plurality of field limiting ring structures arranged at intervals, the field limiting ring structure includes a first field limiting ring and a second field limiting ring arranged in stacked contact, the first field limiting ring is arranged in the same layer and material as the p-type gate area, and the second field limiting ring is arranged in the same layer and material as the p+ connection area.

9. The junction field effect transistor device according to any one of claims 1 to 7, characterized in that: It also includes a terminal area located at the periphery of the active area, the terminal area includes a field limiting ring structure, the field limiting ring structure includes a plurality of first field limiting rings arranged at intervals and a plurality of second field limiting rings arranged at intervals, the first field limiting rings are arranged in the same layer and material as the p-type gate area, the second field limiting rings are arranged in the same layer and material as the p+ gate area, and the orthographic projection of the second field limiting ring on the n+ substrate covers the orthographic projections of two adjacent first field limiting rings on the n+ substrate.

10. The junction field effect transistor device according to any one of claims 2 to 7, characterized in that: It also includes a terminal area located at the periphery of the active area, the terminal area includes a junction terminal extension structure, the junction terminal extension structure includes a first junction terminal extension, a second junction terminal extension and a third junction terminal extension arranged in a stacked manner, the first junction terminal extension and the p-type gate area are an integral structure, the second junction terminal extension and the p+ connection area are an integral structure, and the third junction terminal extension is arranged in the same layer and material as the p+ gate area.

11. A method for preparing a junction field effect transistor device, characterized in that: For preparing a junction field effect transistor device according to any one of claims 1 to 10, the preparation method comprising: epitaxially forming an n-drift layer on one side of the n+ substrate; Implanting p-type ions on a side of the n-drift layer away from the n+ substrate to form a p-type gate region; epitaxially forming an n-type channel layer on a side of the p-type gate region away from the n+ substrate; P-type ions are implanted into a side of the n-type channel layer away from the n+ substrate to form a p+ gate region.

12. The preparation method according to claim 11, characterized in that: Also includes: Injecting p-type ions into a side of the p+ gate region away from the n+ substrate to form a p+ connection region, wherein the side of the p+ connection region away from the n+ substrate is located in the p+ gate region, the middle part of the p+ connection region is located in the n-type channel layer, and the side of the p+ connection region close to the n+ substrate is located in the p-type gate region; N-type ions are implanted on a side of the p+ gate region away from the n+ substrate to form an n+ source region, an n-type channel layer is provided between the n+ source region and the p+ gate region, and the n+ source region is spaced apart from the p+ connection region.

13. The preparation method according to claim 11, characterized in that: Before the p-type ions are injected into the side of the n-drift layer away from the n+ substrate to form the p-type gate region, the method further comprises: injecting n-type ions into the side of the n-drift layer away from the n+ substrate to form a first n-type current diffusion layer and a second n-type current diffusion layer spaced apart from each other; When p-type ions are implanted on a side of the n-drift layer away from the n+ substrate to form a p-type gate region, the first n-type current diffusion layer covers a first side surface and a portion of a first surface of the p-type gate region, and the second n-type current diffusion layer covers a second side surface and a portion of the first surface of the p-type gate region.

14. An electronic device, characterized in that: The device comprises a junction field effect transistor device as claimed in any one of claims 1 to 10.

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