Semiconductor discharge tube and power supply circuit

Abstract

The invention discloses a semiconductor discharge tube and a power supply circuit, and the semiconductor discharge tube comprises a first part and a second part of a semiconductor body, each of the first part and the second part comprises a first region, a second region, a third region and a fourth region, and the first region and the second region are in the same layer and are arranged at intervals of the third region; the fourth area comprises a plurality of fourth sub-areas arranged at intervals, the fourth area is in contact with the third area, and the fourth area is located in the vertical projection of the third area in the fourth area; the first region is in contact with the third region, the vertical projection of the first region in the third region is located in the third region, and the vertical projection of the first region in the fourth region is not overlapped with the fourth sub-region; the second region is in contact with the third region, and the vertical projection of the second region in the fourth region is not overlapped with the fourth sub-region; the first part and the second part are symmetrically arranged, and the vertical projection of the fourth area of the first part in the fourth area of the second part is not overlapped with the fourth area of the second part. The initial conduction area of the device can be increased, and the reliability of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor discharge tube and a power supply circuit. Background Art

[0002] The semiconductor discharge tube (TSS) is a PNPN junction four-layer structure device made by semiconductor technology. Its internal structure contains three PN junctions: J1 (N1P1), J2 (P1N2) and J3 (N2P2). When positive electricity is connected to P2 and negative electricity is connected to N1, the J1 and J3 junctions are forward biased, and the J2 junction is reverse biased. Since the heavily doped J1 junction has a very low breakdown voltage, the J3 junction withstands almost all external voltage. This structural design allows the TSS to quickly turn on under overvoltage conditions and protect the back-end circuit from damage. Figure 1 This is a schematic diagram of the structure of a semiconductor discharge tube in the prior art. Figure 1 , Figure 1 The TSS in the device adopts an antisymmetric structure, and the P region 1 and the N+ region 2 are antisymmetric structures. However, the initial conduction area of ​​the existing structure is small and the reliability of the device is poor. Summary of the invention

[0003] The present invention provides a semiconductor discharge tube and a power supply circuit, which can increase the initial conduction area of ​​the device and improve the reliability of the device.

[0004] According to one aspect of the present invention, there is provided a semiconductor discharge tube, comprising:

[0005] A semiconductor body, the semiconductor body is of a first conductivity type, the semiconductor body includes a first surface and a second surface arranged opposite to each other; along a first direction, the semiconductor body is divided into a first part and a second part, the surface of the first part away from the second part is the first surface, and the surface of the second part away from the first part is the second surface; the first part and the second part both include a first region, a second region, a third region and a fourth region, the first region and the second region are in the same layer, and are arranged with the third region spaced apart; the first region is located on the first surface, and the fourth region is located on a side of the third region away from the first region; the fourth region includes a plurality of fourth sub-regions spaced apart, and the fourth region is in contact with the third region , the vertical projection of the fourth area on the third area is located in the third area; the first area is in contact with the third area, the vertical projection of the first area on the third area is located in the third area, and the vertical projection of the first area on the fourth area does not overlap with the fourth sub-area; the second area is in contact with the third area, the vertical projection of the second area on the third area partially overlaps with the third area, and the vertical projection of the second area on the fourth area does not overlap with the fourth sub-area; the first area and the second area are of the first conductivity type, and the third area and the fourth area are of the second conductivity type; the first part and the second part are symmetrically arranged, and the vertical projection of the fourth area of ​​the first part on the fourth area of ​​the second part does not overlap with the fourth area of ​​the second part;

[0006] A first electrode, the first electrode is located on the first surface, the first electrode is in contact with the first area of ​​the first portion and a portion of the third area, and the first electrode is insulated from the second area of ​​the first portion;

[0007] The second electrode is located on the second surface, the second electrode is in contact with the first area of ​​the second part and part of the third area, and the second electrode is insulated from the second area of ​​the second part.

[0008] Optionally, the second region includes a first diffusion region, a plurality of second diffusion regions and a plurality of third diffusion regions; along the second direction, the second diffusion region is located between the first diffusion region and the third diffusion region, and the second direction is a direction from the first diffusion region to the third diffusion region;

[0009] The first diffusion region is located at an edge of the first surface of the semiconductor body, the first diffusion region surrounds the first region, and a vertical projection of the first diffusion region on the third region does not overlap with the third region;

[0010] The plurality of second diffusion regions have a first side and a second side that are oppositely disposed, the first side is in contact with the first diffusion region, and the second side is in contact with the third region; a vertical projection of the second diffusion region on the third region partially overlaps with the third region;

[0011] Along the first diagonal direction, a plurality of third diffusion regions are arranged at intervals; a vertical projection of the third diffusion region on the third region is located in the third region.

[0012] Optionally, the plurality of fourth sub-regions include a plurality of edge fourth sub-regions and a plurality of other fourth sub-regions, the plurality of edge fourth sub-regions surround the other fourth sub-regions; the other fourth sub-regions are located on a side of the edge fourth sub-region away from a vertical projection of the second diffusion region on the fourth region;

[0013] The vertical projection of the second diffusion region on the fourth region is located on the perpendicular bisector of a line connecting the centers of adjacent edge fourth sub-regions.

[0014] Optionally, the plurality of fourth sub-regions include a plurality of fourth diffusion regions and a plurality of fifth diffusion regions;

[0015] Along the second diagonal direction, a plurality of fourth diffusion regions are arranged in sequence, each fourth diffusion region corresponds to a third diffusion region; the center of the fourth diffusion region and the center of the vertical projection of the corresponding third diffusion region on the fourth region are located on a first straight line; the first straight line is parallel to the second direction;

[0016] The vertical projection of the third diffusion region of the first part on the fourth diffusion region of the second part is located inside the fourth diffusion region of the second part; the vertical projection of the third diffusion region of the second part on the fourth diffusion region of the first part is located inside the fourth diffusion region of the first part.

[0017] Optionally, an area of ​​each third diffusion region is smaller than an area of ​​each fourth diffusion region.

[0018] Optionally, the shape of the third diffusion region includes a circle; and a diameter of the circle is greater than 100 μm.

[0019] Optionally, the semiconductor discharge tube further comprises:

[0020] The insulating layer is located on one side of the first surface and the second surface of the semiconductor body; the insulating layer at least covers the third diffusion region, and a vertical projection of the insulating layer in the first region does not overlap with the first region.

[0021] Optionally, the distance between adjacent fourth sub-regions is greater than 200 μm; the distance between adjacent fourth sub-regions is the same.

[0022] Optionally, the doping concentration of the third region is greater than the doping concentration of the second region, and the doping concentration of the first region is greater than the doping concentration of the semiconductor body.

[0023] According to another aspect of the present invention, there is provided a power supply circuit, comprising the semiconductor discharge tube according to any embodiment of the present invention.

[0024] The semiconductor body provided by the technical solution of the embodiment of the present invention is of the first conductivity type, and the semiconductor body includes a first surface and a second surface arranged opposite to each other; along the first direction, the semiconductor body is divided into a first part and a second part, the surface of the first part away from the second part is the first surface, and the surface of the second part away from the first part is the second surface; the first part and the second part both include a first region, a second region, a third region and a fourth region, the first region and the second region are in the same layer, and are arranged with the third region in between; the first region is located on the first surface, and the fourth region is located on a side of the third region away from the first region; the fourth region includes a plurality of fourth sub-regions arranged at intervals, the fourth region is in contact with the third region, and the vertical projection of the fourth region on the third region is located within the third region; the first region is in contact with the third region, and the vertical projection of the first region on the third region is located within the third region, The vertical projection of the first area in the fourth area does not overlap with the fourth sub-area; the second area contacts the third area, the vertical projection of the second area in the third area partially overlaps with the third area, and the vertical projection of the second area in the fourth area does not overlap with the fourth sub-area; the first area and the second area are of the first conductivity type, and the third area and the fourth area are of the second conductivity type; the first part and the second part are symmetrically arranged, and the vertical projection of the fourth area of ​​the first part in the fourth area of ​​the second part does not overlap with the fourth area of ​​the second part; the first electrode, the first electrode is located on the first surface, the first electrode contacts the first area of ​​the first part and part of the third area, and the first electrode is insulated from the second area of ​​the first part; the second electrode, the second electrode is located on the second surface, the second electrode contacts the first area of ​​the second part and part of the third area, and the second electrode is insulated from the second area of ​​the second part. In the embodiment of the present invention, by setting the parts in the second area that contact the third area to be breakdown points, the breakdown points are increased, so that the initial conduction area of ​​the device is increased, the current in the middle of the edge of the breakdown point distribution is uniform, and the reliability of the device is improved.

[0025] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 The diagram is a schematic diagram of the structure of a semiconductor discharge tube in the prior art.

[0028] Figure 2 It is a structural schematic diagram of a semiconductor discharge tube provided by an embodiment of the present invention.

[0029] Figure 3 yes Figure 2 Schematic diagram of the cross-sectional structure along section line A1A2.

[0030] Figure 4 It is a schematic diagram of the intermediate structure of a semiconductor discharge tube according to an embodiment of the present invention.

[0031] Figure 5 It is a schematic diagram of the intermediate structure of another semiconductor discharge tube according to an embodiment of the present invention.

[0032] Figure 6 It is a schematic diagram of the intermediate structure of another semiconductor discharge tube according to an embodiment of the present invention.

[0033] Figure 7 It is a schematic diagram of the intermediate structure of another semiconductor discharge tube according to an embodiment of the present invention.

[0034] Figure 8 yes Figure 6 Schematic diagram of the cross-sectional structure along section line B1B2. DETAILED DESCRIPTION

[0035] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0036] It should be noted that the terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0037] An embodiment of the present invention provides a semiconductor discharge tube. Figure 2 is a schematic structural diagram of a semiconductor discharge tube provided by an embodiment of the present invention, Figure 3 yes Figure 2 Schematic diagram of the cross-section structure along the section line A1A2, Figure 4is a schematic diagram of the intermediate structure of a semiconductor discharge tube according to an embodiment of the present invention, Figure 5 is a schematic diagram of the intermediate structure of another semiconductor discharge tube according to an embodiment of the present invention, Figure 6 is a schematic diagram of the intermediate structure of another semiconductor discharge tube according to an embodiment of the present invention, Figure 7 is a schematic diagram of the intermediate structure of another semiconductor discharge tube according to an embodiment of the present invention, referring to Figure 2-Figure 7 , semiconductor discharge tube includes:

[0038] The semiconductor body 10 is of the first conductivity type, and the semiconductor body 10 includes a first surface 01 and a second surface 02 that are arranged opposite to each other; along the first direction X, the semiconductor body 10 is evenly divided into a first part 03 and a second part 04, the surface of the first part 03 away from the second part 04 is the first surface 01, and the surface of the second part 04 away from the first part 03 is the second surface 02; the first part 11 and the second part 12 both include a first area 11, a second area 12, a third area 13 and a fourth area 14, the first area 11 and the second area 12 are in the same layer, and are arranged in interval with the third area 13; the first area 11 is located on the first surface 01, and the fourth area 14 is located on a side of the third area 13 away from the first area 11; the fourth area 14 includes a plurality of fourth sub-areas 15 that are arranged in intervals, and the fourth area 14 and the third area 13 are arranged in intervals. The first area 11 is in contact with the third area 13, and the vertical projection of the first area 11 on the third area 13 is located in the third area 13; the first area 11 is in contact with the third area 13, and the vertical projection of the first area 11 on the third area 13 is located in the third area 13, and the vertical projection of the first area 11 on the fourth area 14 does not overlap with the fourth sub-area 15; the second area 12 is in contact with the third area 13, and the vertical projection of the second area 12 on the third area 13 partially overlaps with the third area 13, and the vertical projection of the second area 12 on the fourth area 14 does not overlap with the fourth sub-area 15; the first area 11 and the second area 12 are of the first conductivity type, and the third area 13 and the fourth area 14 are of the second conductivity type; the first part 03 and the second part 04 are symmetrically arranged, and the vertical projection of the fourth area 14 of the first part 03 on the fourth area 14 of the second part 04 does not overlap with the fourth area 14 of the second part 04;

[0039] A first electrode 20, the first electrode 20 is located on the first surface 01, the first electrode 20 is in contact with the first area 11 of the first portion 03 and a portion of the third area 13, and the first electrode 20 is insulated from the second area 12 of the first portion 03;

[0040] The second electrode 30 is located on the second surface 02 . The second electrode 30 contacts the first area 11 and part of the third area 13 of the second portion 04 . The second electrode 30 is insulated from the second area 12 of the second portion 04 .

[0041] Wherein, the first conductivity type is N type, the second conductivity type is P type, the first electrode 20 is connected to negative electricity, and the second electrode 30 is connected to positive electricity; or, the first conductivity type is P type, the second conductivity type is N type, the first electrode 20 is connected to positive electricity, and the second electrode 30 is connected to negative electricity. Exemplarily, the conductivity type of the semiconductor body is N type, the first region 11, the second region 12, the third region 13 and the fourth region 14 are all formed by performing different ion doping in the semiconductor body, the first region 11 and the second region 12 are formed at the same time, and the conductivity type of the first region 11 and the second region 12 are both N+ type, the conductivity type of the third region 13 is P+ type, the conductivity type of the fourth region 14 is P type, and the implantation depth of the fourth region 14 is greater than the implantation depth of the third region 13.

[0042] The first direction X is the thickness direction of the semiconductor discharge tube, and the semiconductor body 10 is evenly divided into two upper and lower parts, namely, the first part 03 and the second part 04. The first part 03 and the second part 04 are symmetrically arranged and flipped 180° to each other, that is, the first part 03 is a structure in which the second part 04 is flipped 180°, and the second part 04 is a structure in which the first part 03 is flipped 180°. The first part 03 and the second part 04 are centrally symmetrically arranged; for example, refer to Figure 6 and Figure 7 , Figure 6 is a schematic diagram of a top view of the first surface of the semiconductor body 10, Figure 7 It is a schematic diagram of the top view of the second surface of the semiconductor body, in which the first part 03 and the fourth part 04 are symmetrically arranged.

[0043] refer to Figure 3 , along the direction from the second surface 02 to the first surface 01, that is, the first direction X, the semiconductor body 10 sequentially arranges the first area 11 and the second area 12 of the second part 04, the third area 13 of the second part 04, the fourth area 14 of the second part 04, the fourth area 14 of the first part 03, the third area 13 of the first part and the first area 11 and the second area 12 of the first part 03; the first part 03 and the second part 04 have the same structure but different positions and are symmetrically arranged.

[0044] Specifically, the first part 03 includes a first area 11, a second area 12, a third area 13 and a fourth area 14, and the second part 04 includes a first area 11, a second area 12, a third area 13 and a fourth area 14, and the first area 11, the second area 12, the third area 13 and the fourth area 14 of the second part 04 are obtained by flipping the first area 11, the second area 12, the third area 13 and the fourth area 14 of the first part 03; the vertical projection of the fourth area 14 of the first part 03 in the fourth area 14 of the second part 04 does not overlap with the fourth area 14 of the second part 04, and the vertical projection of each fourth area 14 of the second part 04 in the fourth area 14 of the first part 03 is located between adjacent fourth sub-areas 15; the parts of the second area 12 that contact the third area 13 are all breakdown points, which increases the area of ​​the breakdown points, thereby increasing the initial conduction area of ​​the device, and the initial conduction area of ​​the device determines the current carrying capacity, which can improve the current carrying capacity of the device, so that the current in the middle of the edge of the breakdown point distribution is uniform, thereby improving the reliability of the device.

[0045] Semiconductor discharge tubes in the prior art often adopt a half-side symmetrical layout mode. Although this structural shape is simple and intuitive, it is difficult to achieve the optimal spatial configuration when encountering size restrictions or special performance requirements. In addition, the half-side symmetrical layout may also introduce design imbalances, affecting the overall performance of the chip. The new drawing method proposed in the embodiment of the present invention when designing a semiconductor discharge tube adopts a matrix alignment method to draw the layout, which can realize matrix arrangement and maximize the use of the area of ​​the active area, thereby achieving efficient space utilization.

[0046] refer to Figure 4 When designing a semiconductor discharge tube, the dimensions of the device around it, i.e., the peripheral dimensions of the device, must be clearly defined as the basis for subsequent layout; the dimensions of the second area 12, i.e., the large blank area along the first diagonal direction Z1, are pre-designed; the range of the fourth area 14 is designed according to the reserved dimensions of the second area 12, and the fourth area 14 is designed to be arranged in a matrix manner, and multiple graphics can be removed by an equidistant staggered manner to ensure that the fourth area can effectively utilize space and avoid waste; illustratively, multiple graphics can be removed by an equidistant staggered manner, and multiple fourth sub-areas 15 can be set at equal intervals, and the multiple fourth sub-areas 15 include a fourth sub-area 1, a fourth sub-area 2, and a fourth sub-area 3. Under the condition of ensuring the normal operation of the device, the adjacent spacings of the fourth sub-area 1, the fourth sub-area 2, and the fourth sub-area 3 are set to be the same, and the fourth sub-area 2 of the first part 03 can be removed, and the position of the removed fourth sub-area 2 corresponds to a fourth sub-area 15 of the second part 04, which can ensure effective utilization of space and symmetrical arrangement of the first part 03 and the second part 04.

[0047] In semiconductor discharge tubes, reference Figure 5The third area 13 covers the fourth area 14, and reserved space is designed for the third area 13 and the fourth area 14. The reserved space of the third area 13 is smaller than the reserved space of the fourth area 14, and the second area 12 is subsequently formed in the reserved space. If the second area 12 is an N+ area, electrons can be emitted in the reserved space to form a part of the pattern of the second area 12, and the fourth area 14 and the second area 12 are separated by the third area 13, so as to ensure that the areas do not interfere with each other and have a compact layout, thereby further improving space utilization.

[0048] The semiconductor body 10 provided by the technical solution of the embodiment of the present invention is of the first conductivity type, and the semiconductor body 10 includes a first surface 01 and a second surface 02 arranged opposite to each other; along the first direction X, the semiconductor body 10 is evenly divided into a first part 03 and a second part 04, the surface of the first part 03 away from the second part 04 is the first surface 01, and the surface of the second part 04 away from the first part 03 is the second surface 02; the first part 11 and the second part 12 both include a first area 11, a second area 12, a third area 13 and a fourth area 14, the first area 11 and the second area 12 are in the same layer, and are arranged with the third area 13 in between; the first area 11 is located on the first surface 01, and the fourth area 14 is located on a side of the third area 13 away from the first area 11; the fourth area 14 includes a plurality of fourth sub-areas 15 arranged at intervals, the fourth area 14 is in contact with the third area 13, and the vertical projection of the fourth area 14 on the third area 13 is located in the third area 13; the first area 11 is in contact with the third area 13, and the vertical projection of the first area 11 on the third area 13 is located in the third area 13, and the first area The vertical projection of the second area 11 on the fourth area 14 does not overlap with the fourth sub-area 15; the second area 12 contacts the third area 13, the vertical projection of the second area 12 on the third area 13 partially overlaps with the third area 13, and the vertical projection of the second area 12 on the fourth area 14 does not overlap with the fourth sub-area 15; the first area 11 and the second area 12 are of the first conductivity type, and the third area 13 and the fourth area 14 are of the second conductivity type; the first part 03 and the second part 04 are symmetrically arranged, and the fourth area 14 of the first part 03 is in the fourth area 14 of the second part 04 4 does not overlap with the fourth area 14 of the second part 04; the first electrode 20, the first electrode 20 is located on the first surface 01, the first electrode 20 is in contact with the first area 11 and part of the third area 13 of the first part 03, and the first electrode 20 is insulated from the second area 12 of the first part 03; the second electrode 30, the second electrode 30 is located on the second surface 02, the second electrode 30 is in contact with the first area 11 and part of the third area 13 of the second part 04, and the second electrode 30 is insulated from the second area 12 of the second part 04. In the embodiment of the present invention, by setting the parts of the second area 12 that are in contact with the third area 13 as breakdown points, the breakdown points are increased, the initial conduction area of ​​the device is increased, the current in the middle of the edge of the breakdown point distribution is uniform, and the reliability of the device is improved.

[0049] Optional, Figure 8 yes Figure 6 Schematic diagram of the cross-section structure along the section line B1B2, reference Figure 6 and Figure 8 , the second region 12 includes a first diffusion region 121, a plurality of second diffusion regions 122 and a plurality of third diffusion regions 123; along the second direction Y, the second diffusion region 122 is located between the first diffusion region 121 and the third diffusion region 123, and the second direction Y is the direction from the first diffusion region 121 to the third diffusion region 123;

[0050] The first diffusion region 121 is located at the edge of the first surface 01 of the semiconductor body 10, and the first diffusion region 121 surrounds the first region 11. The vertical projection of the first diffusion region 121 in the third region 13 does not overlap with the third region 13; the plurality of second diffusion regions 122 have a first side and a second side that are relatively arranged, the first side contacts the first diffusion region 121, and the second side contacts the third region 13; the vertical projection of the second diffusion region 122 in the third region 13 partially overlaps with the third region 13; along the first diagonal line Z1 direction, the plurality of third diffusion regions 123 are arranged at intervals; the vertical projection of the third diffusion region 123 in the third region 13 is located in the third region 13.

[0051] Among them, the second direction Y is the length direction of the semiconductor discharge tube; the first diffusion region 121 contacts the multiple second diffusion regions 122, the multiple second diffusion regions 122 are arranged at intervals, the first diffusion region 121 and the multiple second diffusion regions 122 in contact form a pattern that surrounds the first region, the first diffusion region 121 and the multiple second diffusion regions 122 are arranged at intervals from the third diffusion region 123; the spacing between adjacent third diffusion regions 123 is set according to the preset size of the semiconductor discharge tube, and the spacing between adjacent third diffusion regions 123 can be the same or different.

[0052] The first diffusion region 121 can effectively enhance the current diffusion capability, prevent the current from being excessively concentrated in a local area, and improve the reliability of the device under high current conditions. Moreover, since the current is more evenly distributed, damage due to excessive local temperature of the device can be avoided, thereby extending the service life of the device. When the voltage reaches the transition voltage or breakdown voltage, the second diffusion region 122 and the third diffusion region 123 are both breakdown points, and an initial conduction channel can be formed in the device, thereby increasing the initial conduction area of ​​the device, and the current in the middle of the edge of the breakdown point distribution is uniform, thereby improving the reliability of the device.

[0053] Optional, reference Figure 4 and Figure 6The multiple fourth sub-regions 15 include multiple edge fourth sub-regions and multiple other fourth sub-regions, and the multiple edge fourth sub-regions surround the other fourth sub-regions; the other fourth sub-regions are located on the side of the edge fourth sub-region away from the vertical projection of the second diffusion region 122 on the fourth region 14; the vertical projection of the second diffusion region 122 on the fourth region 14 is located on the perpendicular bisector of the line connecting the centers of adjacent edge fourth sub-regions.

[0054] Among them, the outermost circle of fourth sub-regions is the edge fourth sub-region 15, and multiple other fourth sub-regions are located inside the figure surrounded by multiple edge fourth sub-regions. The reserved area of ​​the fourth region 14 in the first diagonal direction Z1 can be used to form a third diffusion region 123 later; the vertical projection of the second diffusion region 122 on the fourth region 14 is located on the perpendicular bisector of the line connecting the centers of adjacent edge fourth sub-regions; the initial conduction area of ​​the semiconductor discharge tube can be larger, thereby improving the reliability of the device.

[0055] Optional, reference Figure 6 and Figure 8 , the plurality of fourth sub-regions 15 include a plurality of fourth diffusion regions 151 and a plurality of fifth diffusion regions 152; along the second diagonal direction Z2, the plurality of fourth diffusion regions 151 are arranged in sequence, and each fourth diffusion region 151 corresponds to a third diffusion region 123; the center of the fourth diffusion region 151 and the center of the vertical projection of the corresponding third diffusion region 123 in the fourth region 14 are located on the first straight line C1C2; the first straight line C1C2 is parallel to the second direction Y; the vertical projection of the third diffusion region 123 of the first part 03 on the fourth diffusion region 151 of the second part 04 is located inside the fourth diffusion region 151 of the second part 04; the vertical projection of the third diffusion region 123 of the second part 04 on the fourth diffusion region 151 of the first part 03 is located inside the fourth diffusion region 151 of the first part 03.

[0056] Among them, the size of the fifth diffusion region 152 is 100μm-200μm, and the spacing between adjacent fifth diffusion regions 152 can be equal, so that the array arrangement of the fifth diffusion regions 152 can be realized; the area of ​​the third diffusion region 123 needs to reserve space when designing the third region 13 and the fourth region 14, and the reserved space is used to form the third diffusion region 123, the third diffusion region 123 in the first part 03 corresponds to the fourth diffusion region 151 of the second part 04, and the third diffusion region 123 in the second part 04 corresponds to the fourth diffusion region 151 of the first part 03, and the area of ​​the fourth diffusion region 151 is larger than the area of ​​the third diffusion region 123. If the shape of the third diffusion region 123 is circular, the shape of the fourth diffusion region 151 can be the area of ​​multiple fifth diffusion regions 152 connected together, and the area of ​​the third diffusion region 123 is smaller than the maximum circular area included in the fourth diffusion region 151, ensuring that the regions do not interfere with each other and the layout is compact, and the third diffusion region 123 is a breakdown point, which can be the initial conduction area of ​​the device, thereby improving the reliability of the device.

[0057] Optionally, an area of ​​each third diffusion region is smaller than an area of ​​each fourth diffusion region.

[0058] The area of ​​each third diffusion region is smaller than the area of ​​each fourth diffusion region, which can ensure that the regions do not interfere with each other and have a compact layout.

[0059] Optionally, the shape of the third diffusion region includes a circle; and a diameter of the circle is greater than 100 μm.

[0060] Among them, the shape of the third diffusion zone includes a circle, which is a regular shape and has a simple process; if the diameter of the circle is less than 100μm, the initial conduction area will be small, which will lead to poor reliability of the device and the device will be easily damaged. Therefore, setting the diameter of the circle to be greater than 100μm can ensure that the initial conduction area of ​​the device is larger and the reliability of the device is guaranteed.

[0061] Optional, reference Figure 3 , Figure 6 and Figure 8 The semiconductor discharge tube further includes: an insulating layer 40, which is located on one side of the first surface 01 and the second surface 02 of the semiconductor body 10; the insulating layer 40 at least covers the third diffusion region 123, and the vertical projection of the insulating layer 40 on the first region 11 does not overlap with the first region 11.

[0062] Among them, the material of the insulating layer 40 includes silicon nitride or silicon oxide, which is used to isolate the first electrode 20 and the second electrode 30 from the second area 12; the insulating layer 40 can be covered on the first surface 01 and the second surface 02, and then the hole area of ​​the insulating layer 40 is formed by patterning, and the electrode is designed according to the position area of ​​the first area 11, the second area 12 and the third area 13. The first electrode 20 and the second electrode 30 are electrically connected to the first area 11 through the hole area, and the first electrode 20 and the second electrode 30 are both metal electrodes.

[0063] Optionally, the distance between adjacent fourth sub-regions is greater than 200 μm; the distance between adjacent fourth sub-regions is the same.

[0064] The distance between adjacent fourth sub-areas is greater than 200 μm; the distance between adjacent fourth sub-areas is the same, so that the fourth sub-areas can be arranged in an array, further improving space utilization.

[0065] Optionally, the doping concentration of the third region is greater than the doping concentration of the second region, and the doping concentration of the first region is greater than the doping concentration of the semiconductor body.

[0066] The doping concentration of the third region is greater than that of the second region, and the doping concentration of the first region is greater than that of the semiconductor body. The doping concentration of each region is set according to requirements to adjust the conduction characteristics of the semiconductor discharge tube.

[0067] An embodiment of the present invention provides a power supply circuit based on the above embodiment, including the semiconductor discharge tube described in any embodiment of the present invention.

[0068] The power supply circuit provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor discharge tube described in any embodiment of the present invention.

[0069] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0070] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor discharge tube, characterized in that: include: A semiconductor body, the semiconductor body being of a first conductivity type, and comprising a first surface and a second surface arranged opposite to each other; Along a first direction, the semiconductor body is divided into a first part and a second part, the surface of the first part away from the second part is a first surface, and the surface of the second part away from the first part is a second surface; the first part and the second part each include a first region, a second region, a third region and a fourth region, the first region and the second region are in the same layer and are arranged with the third region spaced apart; the first region is located on the first surface, and the fourth region is located on a side of the third region away from the first region; the fourth region includes a plurality of fourth sub-regions spaced apart, the fourth region is in contact with the third region, and a vertical projection of the fourth region on the third region is located within the third region; the first The first area is in contact with the third area, the vertical projection of the first area in the third area is located in the third area, and the vertical projection of the first area in the fourth area does not overlap with the fourth sub-area; the second area is in contact with the third area, the vertical projection of the second area in the third area partially overlaps with the third area, and the vertical projection of the second area in the fourth area does not overlap with the fourth sub-area; the first area and the second area are of the first conductivity type, and the third area and the fourth area are of the second conductivity type; the first part and the second part are symmetrically arranged, and the vertical projection of the fourth area of ​​the first part in the fourth area of ​​the second part does not overlap with the fourth area of ​​the second part; A first electrode, the first electrode is located on the first surface, the first electrode is in contact with the first area of ​​the first portion and a portion of the third area, and the first electrode is insulated from the second area of ​​the first portion; A second electrode is disposed on the second surface, the second electrode is in contact with the first region and a portion of the third region of the second portion, and the second electrode is insulated from the second region of the second portion.

2. The semiconductor discharge tube according to claim 1, characterized in that: The second region includes a first diffusion region, a plurality of second diffusion regions and a plurality of third diffusion regions; along a second direction, the second diffusion region is located between the first diffusion region and the third diffusion region, and the second direction is a direction from the first diffusion region to the third diffusion region; The first diffusion region is located at an edge of the first surface of the semiconductor body, the first diffusion region surrounds the first region, and a vertical projection of the first diffusion region in the third region does not overlap with the third region; The plurality of second diffusion regions have a first side and a second side that are oppositely disposed, the first side is in contact with the first diffusion region, and the second side is in contact with the third region; a vertical projection of the second diffusion region on the third region partially overlaps with the third region; Along the first diagonal direction, a plurality of the third diffusion regions are arranged at intervals; and a vertical projection of the third diffusion region on the third region is located within the third region.

3. The semiconductor discharge tube according to claim 2, characterized in that: The plurality of fourth sub-regions include a plurality of edge fourth sub-regions and a plurality of other fourth sub-regions, wherein the plurality of edge fourth sub-regions surround the other fourth sub-regions; the other fourth sub-regions are located at a side of the edge fourth sub-region away from a vertical projection of the second diffusion region on the fourth region; The vertical projection of the second diffusion region on the fourth region is located on the perpendicular bisector of a line connecting the centers of adjacent edge fourth sub-regions.

4. The semiconductor discharge tube according to claim 2, characterized in that: The plurality of fourth sub-regions include a plurality of fourth diffusion regions and a plurality of fifth diffusion regions; Along the second diagonal direction, a plurality of fourth diffusion regions are arranged in sequence, each of which corresponds to one of the third diffusion regions; the center of the fourth diffusion region and the center of the vertical projection of the corresponding third diffusion region on the fourth region are located on a first straight line; the first straight line is parallel to the second direction; A vertical projection of the third diffusion region of the first portion on the fourth diffusion region of the second portion is located inside the fourth diffusion region of the second portion; a vertical projection of the third diffusion region of the second portion on the fourth diffusion region of the first portion is located inside the fourth diffusion region of the first portion.

5. The semiconductor discharge tube according to claim 4, characterized in that: The area of ​​each of the third diffusion regions is smaller than the area of ​​each of the fourth diffusion regions.

6. The semiconductor discharge tube according to claim 5, characterized in that: The shape of the third diffusion region includes a circle; the diameter of the circle is greater than 100 μm.

7. The semiconductor discharge tube according to claim 2, characterized in that: Also includes: an insulating layer, the insulating layer being located on one side of the first surface and the second surface of the semiconductor body; The insulating layer at least covers the third diffusion region, and a vertical projection of the insulating layer in the first region does not overlap with the first region.

8. The semiconductor discharge tube according to claim 1, characterized in that: The distance between adjacent fourth sub-regions is greater than 200 μm; the distance between adjacent fourth sub-regions is the same.

9. The semiconductor discharge tube according to claim 1, characterized in that: The doping concentration of the third region is greater than the doping concentration of the second region, and the doping concentration of the first region is greater than the doping concentration of the semiconductor body.

10. A power supply circuit, characterized in that: A semiconductor discharge tube comprising any one of claims 1 to 9.

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