Power semiconductor device

Abstract

The invention provides a power semiconductor device which comprises a cellular area, a transition area and a terminal area, and the transition area is located between the cellular area and the terminal area of the device. The bottoms of the device cellular region, the transition region and the terminal region are jointly provided with a first conductive type substrate, a first conductive type epitaxial layer located above the first conductive type substrate and a first conductive type buffer layer located in the first conductive type epitaxial layer; under the application of large current, as the cellular region is the region with the maximum area proportion in the chip, if breakdown can occur in the cellular region, the current is discharged through the cellular region, and the robustness of the device is greatly improved; on the basis of ensuring the withstand voltage of the terminal region, the breakdown point is transferred to the large-area cellular region by adjusting the widths of the transition region and the N / P column of the terminal region and optimizing the electric field distribution of the terminal region, so that the EAS performance of the device is improved, the reverse withstand voltage characteristic of the device is optimized, the charge balance sensitivity of the terminal region of the device is reduced, and the robustness of the device is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a super junction power semiconductor device. Background Art

[0002] Power MOS devices are one of the main devices for power processing and conversion. They have the advantages of high input impedance and easy driving, so they are widely used in automotive electronics, industrial electronics, consumer electronics and other fields. Ideal power MOS devices often require high breakdown voltage (Breakdown Voltage, BV) and low specific on resistance (Specific on resistance, R on,sp ), thereby minimizing conduction losses. However, due to the "silicon limit" relationship, the R on,sp There is a restrictive relationship between R and BV. Therefore, super junction devices were invented in the 1880s. The introduction of super junction structure greatly alleviated the problem of R on,sp -BV contradictory relationship. Super junction devices achieve charge compensation by using alternating P-type and N-type regions, thereby obtaining a lower specific on-resistance R on,sp Superjunction devices have good performance and a higher breakdown voltage BV, but the terminal structure of superjunction devices is very sensitive to charge balance and has a small optimization window. Therefore, it is very important to design the terminal structure, improve the terminal structure's withstand voltage capability, and reduce the terminal withstand voltage sensitivity for the application of superjunction. Under high voltage and high current applications, the breakdown occurs in a large active area, which is more beneficial to the application of the device, while small current devices are more inclined to breakdown in a larger non-active area. Based on high current application devices, the present invention designs the transition zone and terminal zone structure of the device to transfer the breakdown position to the inside of the cell, so that the N / P column widths of the transition zone and the terminal zone are smaller than the cell zone, so as to improve the breakdown characteristics and improve the device E AS Characteristics and reliability. If the current is small, the same principle can be used, but the design direction can be reversed to achieve the transfer of the breakdown point. Summary of the invention

[0003] The present invention proposes a power semiconductor device for optimizing the withstand voltage of terminal design.

[0004] To achieve the above-mentioned purpose of the invention, the technical solution of the present invention is as follows:

[0005] The present invention provides a first power semiconductor device, comprising a cell region 100, a transition region 101 and a terminal region 102, wherein the transition region 101 is located between the cell region 100 and the terminal region 102 of the device, and the cell region 100, the transition region 101 and the terminal region 102 of the device have a common bottom structure, wherein the bottom structure comprises a drain metal 17, a first conductive type substrate 1 located above the drain metal 17, a first conductive type epitaxial layer 2 located above the first conductive type substrate 1, and a first conductive type buffer layer 3 located at the bottom of the first conductive type epitaxial layer 2; definition: the direction from the first conductive type epitaxial layer 2 to the first conductive type substrate 1 is the longitudinal direction of the device, and the direction from the cell region 100 to the terminal region 102 is the lateral direction of the device;

[0006] In the cell region 100, a first conductive type epitaxial layer 2 is provided with first conductive type longitudinal strip regions 4 and second conductive type longitudinal strip regions 5 which are alternately distributed in the transverse direction, a second conductive type body region 9 is provided on top of the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5, a first conductive type heavily doped region 11 and a second conductive type body contact region 10 are provided in the second conductive type body region 9; the first conductive type heavily doped region 11 is located on the left and right sides of the second conductive type body contact region 10; the first conductive type heavily doped region 11 and the second conductive type body contact region 10 are both connected to a source metal 16; a gate oxide layer 12 is provided above the second conductive type body region 9; a gate polysilicon 13 is provided above the gate oxide layer 12, and a dielectric layer 14 and a source metal 16 are provided above the gate polysilicon 13;

[0007] In the transition region 101, the first conductive type epitaxial layer 2 is provided with first conductive type longitudinal strip regions 4 and second conductive type longitudinal strip regions 5 which are alternately distributed in the transverse direction, and a second conductive type isolation layer body region 6 is provided on top of the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5 in the transition region, and the second conductive type longitudinal strip regions 5 and the first conductive type longitudinal strip regions 4 are both connected to the second conductive type isolation layer body region 6; a dielectric layer 14 is provided above the second conductive type isolation layer body region 6;

[0008] The terminal region 102 includes first conductive type longitudinal strip regions 4 and second conductive type longitudinal strip regions 5 which are alternately distributed in the transverse direction. A second conductive type transverse strip region 7 is provided on top of the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5 in the terminal region. The upper left boundary of the second conductive type transverse strip region 7 is connected to the lower right boundary of the second conductive type isolation layer body region 6 in the transition region. The lower boundary of the second conductive type isolation layer body region 6 is not lower than the lower boundary of the second conductive type body region 9.

[0009] The widths of the first conductive type longitudinal strip region 4 and the second conductive type longitudinal strip region 5 in the transition region are both smaller than the first conductive type longitudinal strip region 4 and the second conductive type longitudinal strip region 5 in the cell region;

[0010] The widths of the first conductive type longitudinal strip region 4 and the second conductive type longitudinal strip region 5 in the terminal region are both smaller than the first conductive type longitudinal strip region 4 and the second conductive type longitudinal strip region 5 in the cell region;

[0011] The lower boundary of the second conductive type transverse strip region 7 is connected to a plurality of first conductive type longitudinal strip regions 4 and a second conductive type longitudinal strip region 5; a first conductive type transverse strip region 8 is provided above the second conductive type transverse strip region 7, and a dielectric layer 14 is provided above the first conductive type transverse strip region 8, a drain polysilicon field plate 15 is provided in the dielectric layer 14 at the rightmost end of the device, and a first conductive type heavily doped region 11 is provided below the drain polysilicon field plate 15 and is short-circuited with the drain polysilicon field plate 15.

[0012] The present invention provides a second power semiconductor device, comprising a cell region 100, a transition region 101 and a terminal region 102.

[0013] The transition region 101 is located between the device cell region 100 and the terminal region 102. The device cell region 100, the transition region 101 and the terminal region 102 have a common bottom structure, which includes a drain metal 17, a first conductive type substrate 1 located above the drain metal 17, a first conductive type epitaxial layer 2 located above the first conductive type substrate 1, and a first conductive type buffer layer 3 located at the bottom of the first conductive type epitaxial layer 2; definition: the direction from the first conductive type epitaxial layer 2 to the first conductive type substrate 1 is the device longitudinal direction, and the direction from the cell region 100 to the terminal region 102 is the device lateral direction;

[0014] In the cell region 100, a first conductive type longitudinal strip region 4 and a second conductive type longitudinal strip region 5 are provided in the first conductive type epitaxial layer 2, which are alternately distributed in the transverse direction. A second conductive type body region 9 is provided on the top of the first conductive type epitaxial layer 2. A groove extending to the first conductive type longitudinal strip region 4 below is provided in the second conductive type body region 9. The groove is filled with a gate oxide layer 12 and a gate polysilicon 13. First conductive type heavily doped regions 11 are provided on both sides of the groove. The first conductive type heavily doped region 11 and the second conductive type body contact region 10 are connected to a source metal 16. A second conductive type implantation region 19 is provided in the first conductive type epitaxial layer 2 at the bottom of the groove.

[0015] In the transition region 101, the first conductive type epitaxial layer 2 is provided with first conductive type longitudinal strip regions 4 and second conductive type longitudinal strip regions 5 which are alternately distributed in the transverse direction, and a second conductive type isolation layer body region 6 is provided on top of the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5 in the transition region, and the second conductive type longitudinal strip regions 5 and the first conductive type longitudinal strip regions 4 are both connected to the second conductive type isolation layer body region 6; a dielectric layer 14 is provided above the second conductive type isolation layer body region 6;

[0016] The terminal region 102 includes first conductive type longitudinal strip regions 4 and second conductive type longitudinal strip regions 5 which are alternately distributed in the transverse direction. A second conductive type transverse strip region 7 is provided on top of the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5 in the terminal region. The upper left boundary of the second conductive type transverse strip region 7 is connected to the lower right boundary of the second conductive type isolation layer body region 6 in the transition region. The lower boundary of the second conductive type isolation layer body region 6 is not lower than the lower boundary of the second conductive type body region 9.

[0017] The widths of the first conductive type longitudinal strip region 4 and the second conductive type longitudinal strip region 5 in the transition region are both smaller than the first conductive type longitudinal strip region 4 and the second conductive type longitudinal strip region 5 in the cell region;

[0018] The widths of the first conductive type longitudinal strip region 4 and the second conductive type longitudinal strip region 5 in the terminal region are both smaller than the first conductive type longitudinal strip region 4 and the second conductive type longitudinal strip region 5 in the cell region;

[0019] The lower boundary of the second conductive type transverse strip region 7 is connected to a plurality of first conductive type longitudinal strip regions 4 and a second conductive type longitudinal strip region 5; a first conductive type transverse strip region 8 is provided above the second conductive type transverse strip region 7, and a dielectric layer 14 is provided above the first conductive type transverse strip region 8, a drain polysilicon field plate 15 is provided in the dielectric layer 14 at the rightmost end of the device, and a first conductive type heavily doped region 11 is provided below the drain polysilicon field plate 15 and is short-circuited with the drain polysilicon field plate 15.

[0020] The present invention provides a third power semiconductor device, comprising a cell region 100, a transition region 101 and a terminal region 102.

[0021] The transition region 101 is located between the device cell region 100 and the terminal region 102. The device cell region 100, the transition region 101 and the terminal region 102 have a common bottom structure, which includes a drain metal 17, a first conductive type substrate 1 located above the drain metal 17, a first conductive type epitaxial layer 2 located above the first conductive type substrate 1, and a first conductive type buffer layer 3 located at the bottom of the first conductive type epitaxial layer 2; definition: the direction from the first conductive type epitaxial layer 2 to the first conductive type substrate 1 is the device longitudinal direction, and the direction from the cell region 100 to the terminal region 102 is the device lateral direction;

[0022] In the cell region 100, a first conductive type epitaxial layer 2 is provided with first conductive type longitudinal strip regions 4 and second conductive type longitudinal strip regions 5 which are alternately distributed in the transverse direction, a second conductive type body region 9 is provided on top of the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5, a first conductive type heavily doped region 11 and a second conductive type body contact region 10 are provided in the second conductive type body region 9; the first conductive type heavily doped region 11 is located on the left and right sides of the second conductive type body contact region 10; the first conductive type heavily doped region 11 and the second conductive type body contact region 10 are both connected to a source metal 16; a gate oxide layer 12 is provided above the second conductive type body region 9; a gate polysilicon 13 is provided above the gate oxide layer 12, and a dielectric layer 14 and a source metal 16 are provided above the gate polysilicon 13;

[0023] In the transition region 101, the first conductive type epitaxial layer 2 is provided with first conductive type longitudinal strip regions 4 and second conductive type longitudinal strip regions 5 which are alternately distributed in the transverse direction, and a second conductive type isolation layer body region 6 is provided on top of the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5 in the transition region, and the second conductive type longitudinal strip regions 5 and the first conductive type longitudinal strip regions 4 are both connected to the second conductive type isolation layer body region 6; a dielectric layer 14 is provided above the second conductive type isolation layer body region 6;

[0024] The terminal region 102 includes first conductivity type longitudinal strip regions 4 and second conductivity type longitudinal strip regions 5 which are alternately distributed in the transverse direction, and the tops of the first conductivity type longitudinal strip regions 4 and the second conductivity type longitudinal strip regions 5 are directly connected to the dielectric layer 14; the lower boundary of the second conductivity type isolation layer body region 6 is not lower than the lower boundary of the second conductivity type body region 9; a dielectric layer 14 is provided above the second conductivity type isolation layer body region 6, a drain polysilicon field plate 15 is provided in the dielectric layer 14 at the rightmost end of the device, and a first conductivity type heavily doped region 11 is provided below the drain polysilicon field plate 15 and is short-circuited with the drain polysilicon field plate 15;

[0025] The widths of the first conductive type longitudinal strip region 4 and the second conductive type longitudinal strip region 5 in the transition region are both smaller than the first conductive type longitudinal strip region 4 and the second conductive type longitudinal strip region 5 in the cell region;

[0026] The widths of the first conductivity type longitudinal strip regions 4 and the second conductivity type longitudinal strip regions 5 in the terminal region are both smaller than those of the first conductivity type longitudinal strip regions 4 and the second conductivity type longitudinal strip regions 5 in the cell region.

[0027] The present invention provides a fourth power semiconductor device, comprising a cell region 100, a transition region 101 and a terminal region 102.

[0028] The transition region 101 is located between the device cell region 100 and the terminal region 102. The device cell region 100, the transition region 101 and the terminal region 102 have a common bottom structure, which includes a drain metal 17, a first conductive type substrate 1 located above the drain metal 17, a first conductive type epitaxial layer 2 located above the first conductive type substrate 1, and a first conductive type buffer layer 3 located at the bottom of the first conductive type epitaxial layer 2; definition: the direction from the first conductive type epitaxial layer 2 to the first conductive type substrate 1 is the device longitudinal direction, and the direction from the cell region 100 to the terminal region 102 is the device lateral direction;

[0029] In the cell region 100, a first conductive type epitaxial layer 2 is provided with first conductive type longitudinal strip regions 4 and second conductive type longitudinal strip regions 5 which are alternately distributed in the transverse direction, a second conductive type body region 9 is provided on top of the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5, a first conductive type heavily doped region 11 and a second conductive type body contact region 10 are provided in the second conductive type body region 9; the first conductive type heavily doped region 11 is located on the left and right sides of the second conductive type body contact region 10; the first conductive type heavily doped region 11 and the second conductive type body contact region 10 are both connected to a source metal 16; a gate oxide layer 12 is provided above the second conductive type body region 9; a gate polysilicon 13 is provided above the gate oxide layer 12, and a dielectric layer 14 and a source metal 16 are provided above the gate polysilicon 13;

[0030] In the transition region 101, the first conductive type epitaxial layer 2 is provided with first conductive type longitudinal strip regions 4 and second conductive type longitudinal strip regions 5 which are alternately distributed in the transverse direction, and a second conductive type isolation layer body region 6 is provided on top of the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5 in the transition region, and the second conductive type longitudinal strip regions 5 and the first conductive type longitudinal strip regions 4 are both connected to the second conductive type isolation layer body region 6; a dielectric layer 14 is provided above the second conductive type isolation layer body region 6;

[0031] The widths of the first conductive type longitudinal strip region 4 and the second conductive type longitudinal strip region 5 in the transition region are both smaller than the first conductive type longitudinal strip region 4 and the second conductive type longitudinal strip region 5 in the cell region;

[0032] The terminal region 102 includes first conductivity type longitudinal strip regions 4 and second conductivity type longitudinal strip regions 5 which are alternately distributed in the transverse direction, and a second conductivity type transverse strip region 7 is provided on top of the first conductivity type longitudinal strip regions 4 and the second conductivity type longitudinal strip regions 5 in the terminal region, and the lower boundary of the second conductivity type transverse strip region 7 is flush with the lower boundary of the second conductivity type isolation layer body region 6, and the lower boundary of the second conductivity type isolation layer body region 6 is flush with the lower boundary of the second conductivity type body region 9;

[0033] The widths of the first conductive type longitudinal strip region 4 and the second conductive type longitudinal strip region 5 in the terminal region are both smaller than the first conductive type longitudinal strip region 4 and the second conductive type longitudinal strip region 5 in the cell region;

[0034] The lower boundary of the second conductive type horizontal strip region 7 in the terminal area is connected to a plurality of first conductive type vertical strip regions 4 and second conductive type vertical strip regions 5; a dielectric layer 14 is provided above the second conductive type horizontal strip region 7, a drain polysilicon field plate 15 is provided in the dielectric layer 14 at the rightmost end of the device, and a first conductive type heavily doped region 11 is provided below the drain polysilicon field plate 15 and is short-circuited with the drain polysilicon field plate 15.

[0035] As a preferred embodiment, the widths of the first conductivity type longitudinal strip regions 4 and the second conductivity type longitudinal strip regions 5 in the transition region and the terminal region decrease progressively from the cell region to the terminal region.

[0036] As a preferred embodiment, the widths of the first conductivity type longitudinal strip regions 4 and the second conductivity type longitudinal strip regions 5 in the terminal region are smaller than those of the first conductivity type longitudinal strip regions 4 and the second conductivity type longitudinal strip regions 5 in the transition region.

[0037] The present invention provides a fifth power semiconductor device, comprising a cell region 100, a transition region 101 and a terminal region 102.

[0038] The transition region 101 is located between the device cell region 100 and the terminal region 102. The device cell region 100, the transition region 101 and the terminal region 102 have a common bottom structure, which includes a drain metal 17, a first conductive type substrate 1 located above the drain metal 17, a first conductive type epitaxial layer 2 located above the first conductive type substrate 1, and a first conductive type buffer layer 3 located at the bottom of the first conductive type epitaxial layer 2; definition: the direction from the first conductive type epitaxial layer 2 to the first conductive type substrate 1 is the device longitudinal direction, and the direction from the cell region 100 to the terminal region 102 is the device lateral direction;

[0039] In the cell region 100, a first conductive type epitaxial layer 2 is provided with first conductive type longitudinal strip regions 4 and second conductive type longitudinal strip regions 5 which are alternately distributed in the transverse direction, a second conductive type body region 9 is provided on top of the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5, a first conductive type heavily doped region 11 and a second conductive type body contact region 10 are provided in the second conductive type body region 9; the first conductive type heavily doped region 11 is located on the left and right sides of the second conductive type body contact region 10; the first conductive type heavily doped region 11 and the second conductive type body contact region 10 are both connected to a source metal 16; a gate oxide layer 12 is provided above the second conductive type body region 9; a gate polysilicon 13 is provided above the gate oxide layer 12, and a dielectric layer 14 and a source metal 16 are provided above the gate polysilicon 13;

[0040] In the transition region 101, the first conductive type epitaxial layer 2 is provided with first conductive type longitudinal strip regions 4 and second conductive type longitudinal strip regions 5 which are alternately distributed in the transverse direction, and a second conductive type isolation layer body region 6 is provided on top of the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5 in the transition region, and the second conductive type longitudinal strip regions 5 and the first conductive type longitudinal strip regions 4 are both connected to the second conductive type isolation layer body region 6; a dielectric layer 14 is provided above the second conductive type isolation layer body region 6;

[0041] The terminal region 102 includes first conductive type longitudinal strip regions 4 and second conductive type longitudinal strip regions 5 which are alternately distributed in the transverse direction. A second conductive type transverse strip region 7 is provided on top of the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5 in the terminal region. The upper left boundary of the second conductive type transverse strip region 7 is connected to the lower right boundary of the second conductive type isolation layer body region 6 in the transition region. The lower boundary of the second conductive type isolation layer body region 6 is not lower than the lower boundary of the second conductive type body region 9.

[0042] The widths of the first conductivity type longitudinal strip regions 4 and the second conductivity type longitudinal strip regions 5 of the cell near the transition region in the cell region 100 are the same as those of the first conductivity type longitudinal strip regions 4 and the second conductivity type longitudinal strip regions 5 of the transition region 101 and the terminal region 102, and are smaller than the widths of the remaining first conductivity type longitudinal strip regions 4 and the second conductivity type longitudinal strip regions 5 in the cell;

[0043] The lower boundary of the second conductive type transverse strip region 7 in the terminal area is connected to a plurality of first conductive type longitudinal strip regions 4 and a second conductive type longitudinal strip region 5; a first conductive type transverse strip region 8 is provided above the second conductive type transverse strip region 7, a dielectric layer 14 is provided above the first conductive type transverse strip region 8, a drain polysilicon field plate 15 is provided in the dielectric layer 14 at the rightmost end of the device, a first conductive type heavily doped region 11 is provided below the drain polysilicon field plate 15 and is short-circuited with the drain polysilicon field plate 15.

[0044] As a preferred embodiment, the widths of the first conductive type longitudinal strip region 4 and the second conductive type longitudinal strip region 5 in the terminal region decrease progressively from the cell region to the terminal region and are both smaller than the first conductive type longitudinal strip region 4 and the second conductive type longitudinal strip region 5 in the transition region.

[0045] As a preferred embodiment, a stepped oxide layer which is thick in the middle and thin on both sides is provided above the second conductive type body region 9 in the cell region 100 , and the thin oxide layer above the channel regions on both sides is a gate oxide layer 12 .

[0046] As a preferred embodiment, a plurality of first conductivity type longitudinal strip regions 4 and second conductivity type longitudinal strip regions 5 which are not connected to the second conductivity type transverse strip region 7 are provided at the lower right side of the second conductivity type transverse strip region 7 .

[0047] As a preferred embodiment, the first conductive type longitudinal strip region 4 and the second conductive type longitudinal strip region 5 are of a trapezoidal structure.

[0048] As a preferred embodiment, the structure includes an N-type power semiconductor device and its terminal structure and a P-type power semiconductor device and its terminal structure. For the terminal structure of the N-type power semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type. For the terminal structure of the P-type semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type.

[0049] The inventive principle of the present invention is: the N-column and P-column in the transition zone and the terminal zone of the device are narrower than that in the cell zone, the electric field distribution in the transition zone and the terminal zone is more uniform, and the depletion distribution in the terminal zone is improved, so a higher withstand voltage can be obtained relative to the cell zone, or the NP column in the narrower transition zone and the terminal zone is doped at a higher concentration than that in the cell zone, thereby improving the overall electric field distribution, and further improving the withstand voltage level of the transition zone and the terminal zone, so as to achieve the purpose of transferring the breakdown position of the device to the cell zone.

[0050] The beneficial effects of the present invention are as follows: based on the optimization of breakdown voltage and on-resistance of the super junction as a switching device, the N column and P column of the device transition region and the terminal region are narrower than the cell region, and the electric field distribution in the transition region and the terminal region is more uniform, so a higher withstand voltage can be obtained relative to the cell region, or the NP column in the narrower transition region and the terminal region is doped at a higher concentration than the cell region to improve the overall electric field distribution, and further improve the withstand voltage level of the transition region and the terminal region, so as to achieve the purpose of transferring the device breakdown position to the cell region. The withstand voltage of the transition region and the terminal region is made higher than that of the cell region, forcing the breakdown point position to shift to the cell region, so that all the current is discharged through the large area of ​​the cell region, which not only overcomes the problem that the device terminal charge balance is sensitive and easy to break down at the boundary between the transition region and the terminal region, but also improves the E AS Performance and robustness. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a schematic diagram of the original structure of a power semiconductor device in the prior art;

[0052] Figure 2 This is a schematic diagram of the structure of a power semiconductor device according to Embodiment 1 of the present invention;

[0053] Figure 3 It is a schematic diagram of simulation comparison between Embodiment 1 of the present invention and the existing original structure;

[0054] Figure 4 This is a schematic diagram of the structure of a power semiconductor device according to Embodiment 2 of the present invention;

[0055] Figure 5 This is a schematic diagram of the structure of a power semiconductor device according to Embodiment 3 of the present invention;

[0056] Figure 6 This is a schematic diagram of the structure of a power semiconductor device according to Embodiment 4 of the present invention;

[0057] Figure 7 This is a schematic diagram of the structure of a power semiconductor device according to Embodiment 5 of the present invention;

[0058] Figure 8 This is a schematic diagram of the structure of a power semiconductor device according to Embodiment 6 of the present invention;

[0059] Fig. 9 This is a schematic diagram of the structure of a power semiconductor device according to Embodiment 7 of the present invention;

[0060] Fig.10 This is a schematic diagram of the structure of a power semiconductor device according to Embodiment 8 of the present invention;

[0061] Fig.11 This is a schematic diagram of the structure of a power semiconductor device according to Embodiment 9 of the present invention;

[0062] Fig.12 This is a schematic diagram of the structure of a power semiconductor device according to Embodiment 10 of the present invention;

[0063] Fig.13 This is a schematic diagram of the structure of a power semiconductor device according to Embodiment 11 of the present invention;

[0064] 100 is a cell region, 101 is a transition region, 102 is a terminal region, 1 is a first conductive type substrate, 2 is a first conductive type epitaxial layer, 3 is a first conductive type buffer layer, 4 is a first conductive type longitudinal strip region, 5 is a second conductive type longitudinal strip region, 6 is a second conductive type isolation layer body region, 7 is a second conductive type lateral strip region, 8 is a first conductive type lateral strip region, 9 is a second conductive type body region, 10 is a second conductive type body contact region, 11 is a first conductive type heavily doped region, 12 is a gate oxide layer, 13 is a gate polysilicon, 14 is a dielectric layer, 15 is a drain polysilicon field plate, 16 is a source metal, 17 is a drain metal, and 19 is a second conductive type injection region. DETAILED DESCRIPTION

[0065] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0066] like Figure 1 The figure shows the original structure of the existing power semiconductor device. Its terminal structure uses the top horizontal first / second conductive type strips for auxiliary depletion in the off state. Based on the adjustable length and doping characteristics of the second conductive type horizontal strip area, the voltage resistance level of the terminal area can be flexibly adjusted. The second conductive type horizontal strip area in the terminal area connects the vertical strips together, which plays a role in supplementing holes and optimizing the dynamic characteristics of the device. Figure 1In the structure shown, the device is prone to breakdown at the boundary of the transition zone in the off state, and the charge balance and voltage resistance optimization of the terminal structure will be limited. At the same time, if the breakdown point is located in the transition zone, since the transition zone accounts for a very small proportion of the device area, it is not conducive to improving the robustness of the device.

[0067] Embodiment 1:

[0068] This embodiment proposes an optimized structure of a power semiconductor device, such as Figure 2 As shown: comprising a cell region 100, a transition region 101 and a terminal region 102;

[0069] The transition region 101 is located between the device cell region 100 and the terminal region 102. The device cell region 100, the transition region 101 and the terminal region 102 have a common bottom structure, which includes a drain metal 17, a first conductive type substrate 1 located above the drain metal, a first conductive type epitaxial layer 2 located above the first conductive type substrate 1, and a first conductive type buffer layer 3 located at the bottom of the first conductive type epitaxial layer 2; definition: the direction from the first conductive type epitaxial layer 2 to the first conductive type substrate 1 is the device longitudinal direction, and the direction from the cell region 100 to the terminal region 102 is the device lateral direction;

[0070] In the cell region 100, a first conductive type epitaxial layer 2 is provided with first conductive type longitudinal strip regions 4 and second conductive type longitudinal strip regions 5 which are alternately distributed in the transverse direction, a second conductive type body region 9 is provided on top of the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5, a first conductive type heavily doped region 11 and a second conductive type body contact region 10 are provided in the second conductive type body region 9; the first conductive type heavily doped region 11 is located on the left and right sides of the second conductive type body contact region 10; the first conductive type heavily doped region 11 and the second conductive type body contact region 10 are both connected to a source metal 16; a gate oxide layer 12 is provided above the second conductive type body region 9; a gate polysilicon 13 is provided above the gate oxide layer 12, and a dielectric layer 14 and a source metal 16 are provided above the gate polysilicon 13;

[0071] In the transition zone 101, the first conductive type epitaxial layer 2 is provided with first conductive type longitudinal strip regions 4 and second conductive type longitudinal strip regions 5 which are alternately distributed in the transverse direction, the widths of the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5 in the transition zone are smaller than the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5 in the cell region, a second conductive type isolation layer body region 6 is provided on the top of the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5, the second conductive type longitudinal strip regions 5 and the first conductive type longitudinal strip regions 4 are both connected to the second conductive type isolation layer body region 6; a dielectric layer 14 is provided above the second conductive type isolation layer body region 6;

[0072] The terminal region 102 includes first conductive type longitudinal strip regions 4 and second conductive type longitudinal strip regions 5 which are alternately distributed in the transverse direction. The widths of the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5 in the terminal region are smaller than those of the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5 in the cell region. A second conductive type transverse strip region 7 is provided on the top of the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5 in the terminal region. The upper left boundary of the second conductive type transverse strip region 7 is connected to the lower right boundary of the second conductive type isolation layer body region 6 in the transition region. The lower boundary of the second conductive type isolation layer body region 6 is not lower than the lower boundary of the second conductive type body region 9.

[0073] The lower boundary of the second conductive type transverse strip region 7 is connected to a plurality of first conductive type longitudinal strip regions 4 and a second conductive type longitudinal strip region 5; a first conductive type transverse strip region 8 is provided above the second conductive type transverse strip region 7, and a dielectric layer 14 is provided above the first conductive type transverse strip region 8, a drain polysilicon field plate 15 is provided in the dielectric layer 14 at the rightmost end of the device, and a first conductive type heavily doped region 11 is provided below the drain polysilicon field plate 15 and is short-circuited with the drain polysilicon field plate 15.

[0074] Preferably, the first conductivity type longitudinal strip region 4 in the cell region 100 has a different concentration from that of the first conductivity type epitaxial layer 2 , and / or a first conductivity type JFET injection region is provided on the top of the first conductivity type longitudinal strip region 4 .

[0075] Preferably, the first conductive type longitudinal strip region 4, the second conductive type longitudinal strip region 5, the first conductive type transverse strip region 8, the second conductive type isolation layer body region 6 and the second conductive type transverse strip region 7 are obtained by multiple epitaxy and ion implantation methods;

[0076] Preferably, the structure includes an N-type power semiconductor device and its terminal structure and a P-type power semiconductor device and its terminal structure. For the terminal structure of the N-type power semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type. For the terminal structure of the P-type semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type.

[0077] The working principle of this embodiment is as follows: in this embodiment, the N column and P column in the transition region and the terminal region are narrower than that in the cell region, the electric field distribution in the transition region and the terminal region is more uniform, and the terminal depletion is improved, so that a higher withstand voltage can be obtained relative to the cell region, or a higher concentration of doping is performed in the NP column in the narrower transition region and the terminal region than in the cell region, so as to further optimize the withstand voltage of the terminal region, so that the collision ionization position is almost completely transferred to the cell region, such as Figure 3 As shown in the collision ionization rate distribution diagram, compared with structure A, structure B has a transition zone and a terminal zone NP column that becomes narrower, and the collision ionization is completely transferred to the cell area. This optimized structure transfers the current discharge path when the device breaks down to a large area of ​​the cell area, thereby improving the avalanche tolerance of the device. According to the depletion boundary distribution diagram, the proposed structure B is more conducive to the depletion of the terminal area, thereby reducing the charge balance sensitivity of the terminal structure and improving the reliability of the device.

[0078] Embodiment 2:

[0079] like Figure 4 As shown, the difference between this embodiment and embodiment 1 is that the width of the first conductivity type longitudinal strip region 4 and the width of the second conductivity type longitudinal strip region 5 in the transition region decreases from the cell region to the terminal region. This embodiment adjusts the electric field distribution in the transition region and the terminal region, further transfers the breakdown position to the cell region, and improves the off-state withstand voltage capability of the device. According to different withstand voltage requirements, the change amount of the area position width can be adjusted automatically.

[0080] Embodiment 3:

[0081] like Figure 5 As shown, the difference between this embodiment and embodiment 1 is that the width of the first conductive type longitudinal strip region 4 and the width of the second conductive type longitudinal strip region 5 in the cell region are greater than the width of the first conductive type longitudinal strip region 4 and the width of the second conductive type longitudinal strip region 5 in the transition region, and the width of the first conductive type longitudinal strip region 4 and the width of the second conductive type longitudinal strip region 5 in the transition region are greater than the width of the first conductive type longitudinal strip region 4 and the width of the second conductive type longitudinal strip region 5 in the terminal region, which is beneficial to improving the withstand voltage of the transition region and the terminal region, and the breakdown position is transferred to the cell region. According to different withstand voltage requirements, the change in the width of the regional position can be adjusted automatically.

[0082] Embodiment 4:

[0083] like Figure 6As shown, the difference between this embodiment and embodiment 1 is that the width of the first conductivity type longitudinal strip region 4 and the second conductivity type longitudinal strip region 5 in the cell region near the transition region is the same as the first conductivity type longitudinal strip region 4 and the second conductivity type longitudinal strip region 5 in the transition region and the terminal region, and is smaller than the width of the remaining first conductivity type longitudinal strip region 4 and the second conductivity type longitudinal strip region 5 in the cell. This is conducive to further shifting the breakdown position to the inside of the cell region, and the change in the width of the region position can be adjusted automatically according to different withstand voltage requirements.

[0084] Embodiment 5:

[0085] like Figure 7 As shown, the difference between this embodiment and embodiment 1 is that the width of the first conductive type longitudinal strip region 4 and the width of the second conductive type longitudinal strip region 5 in the terminal area gradually decrease in the horizontal direction and are smaller than the width of the first conductive type longitudinal strip region 4 and the width of the second conductive type longitudinal strip region 5 in the transition area, which is beneficial to further optimize the depletion distribution of the terminal area, and the breakdown position is further transferred to the cell area. According to different withstand voltage requirements, the change in the width of the area position can be adjusted automatically.

[0086] Embodiment 6:

[0087] like Figure 8 As shown, the lower boundary of the second conductivity type lateral strip region 7 is flush with the lower boundary of the second conductivity type isolation layer body region 6 , and the lower boundary of the second conductivity type isolation layer body region 6 is flush with the lower boundary of the second conductivity type body region 9 .

[0088] This embodiment uses the second conductive type isolation layer body region 6 and the second conductive type lateral strip region 7 on the top of the silicon layer, which is beneficial for the transition zone and the terminal zone to have the same withstand voltage length as the cell zone, and at the same time has a shielding effect on the positive charge in the dielectric layer, which is beneficial for improving the radiation resistance.

[0089] Embodiment 7:

[0090] like Fig. 9 As shown, the difference between this embodiment and embodiment 1 is that: above the second conductive type body region 9 in the cell region 100, a stepped oxide layer with a thick middle and thin sides is provided, and the thin oxide layers on both sides above the channel region are gate oxide layers 12. The oxide layer thickness under the middle section polysilicon gate is greater, and the gate oxide layer thickness on both sides is smaller.

[0091] This embodiment adopts a special gate structure. Under the condition that the gate oxide thickness on both sides is sufficient to enable the channel to open normally, the thickness of the middle gate oxide is increased to reduce the capacitance and gate charge, which helps to reduce the requirements of the gate drive circuit and reduce power loss, and further optimize the dynamic characteristics of the device.

[0092] Embodiment 8:

[0093] like Fig.10 As shown, the difference between this embodiment and embodiment 1 is that the planar gate in the cell region 100 is replaced by a trench gate structure, and a second conductive type injection region 19 is added at the bottom of the trench gate. A second conductive type body region 9 is provided on the top of the first conductive type epitaxial layer 3 in the cell region 100, and a groove extending to the first conductive type longitudinal strip region 4 below is provided in the second conductive type body region 9, and the groove is filled with a gate oxide layer 12 and a gate polysilicon 13, and a first conductive type heavily doped region 11 is provided on both sides of the groove, and the first conductive type heavily doped region 11 and the second conductive type body contact region 10 are connected to the source metal 16, and a second conductive type injection region 19 is provided in the first conductive type epitaxial layer 2 at the bottom of the groove.

[0094] This embodiment adopts a groove gate structure, which can further reduce the cell size, reduce the on-resistance of the device, reduce the parasitic capacitance, increase the switching speed, reduce the switching loss, and improve the current capacity of the device; at the same time, a second conductive type doping region is introduced at the bottom of the groove gate to further optimize the dynamic characteristics of the device while avoiding preferential breakdown of the gate oxide layer.

[0095] Embodiment 9:

[0096] like Fig.11 As shown, the difference between this embodiment and embodiment 1 is that the length of the second conductive type transverse strip region 7 and the number of the second conductive type longitudinal strip regions 5 in the terminal region 102 are adjustable, and a plurality of first conductive type longitudinal strip regions 4 and second conductive type longitudinal strip regions 5 that are not connected to the second conductive type transverse strip region 7 are provided at the lower right side of the second conductive type transverse strip region 7, and the second conductive type longitudinal strip regions 5 that are not connected to the transverse strip regions 7 are floating.

[0097] This embodiment can flexibly adjust the terminal voltage-withstanding length according to the voltage-withstanding requirements of the device. By increasing or decreasing the number of floating bars, the electric field and potential distribution of the device can be optimized on the basis of meeting the voltage-withstanding requirements of the device, thereby obtaining more optimized off-state characteristics.

[0098] Embodiment 10:

[0099] like Fig.12 As shown, the difference between this embodiment and embodiment 1 is that the first conductivity type longitudinal strip region 4 and the second conductivity type longitudinal strip region 5 are both distributed in a trapezoidal shape in the cell region transition region and terminal region.

[0100] The present embodiment adopts a trapezoidal P column structure. The trapezoidal P column can be obtained by increasing the implantation dose from bottom to top. The variable doping P column is beneficial to stabilizing the process window and improving the process tolerance.

[0101] Embodiment 11:

[0102] like Fig.13 As shown, the difference between this embodiment and embodiment 1 is that the tops of the first conductivity type longitudinal strip regions 4 and the second conductivity type longitudinal strip regions 5 in the terminal region are not provided with second conductivity type transverse strip regions 7 and are directly connected to the dielectric layer 14 .

[0103] A power semiconductor device includes a cell region 100, a transition region 101 and a terminal region 102.

[0104] The transition region 101 is located between the device cell region 100 and the terminal region 102. The device cell region 100, the transition region 101 and the terminal region 102 have a common bottom structure, which includes a drain metal 17, a first conductive type substrate 1 located above the drain metal 17, a first conductive type epitaxial layer 2 located above the first conductive type substrate 1, and a first conductive type buffer layer 3 located at the bottom of the first conductive type epitaxial layer 2; definition: the direction from the first conductive type epitaxial layer 2 to the first conductive type substrate 1 is the device longitudinal direction, and the direction from the cell region 100 to the terminal region 102 is the device lateral direction;

[0105] In the cell region 100, a first conductive type epitaxial layer 2 is provided with first conductive type longitudinal strip regions 4 and second conductive type longitudinal strip regions 5 which are alternately distributed in the transverse direction, a second conductive type body region 9 is provided on top of the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5, a first conductive type heavily doped region 11 and a second conductive type body contact region 10 are provided in the second conductive type body region 9; the first conductive type heavily doped region 11 is located on the left and right sides of the second conductive type body contact region 10; the first conductive type heavily doped region 11 and the second conductive type body contact region 10 are both connected to a source metal 16; a gate oxide layer 12 is provided above the second conductive type body region 9; a gate polysilicon 13 is provided above the gate oxide layer 12, and a dielectric layer 14 and a source metal 16 are provided above the gate polysilicon 13;

[0106] In the transition region 101, the first conductive type epitaxial layer 2 is provided with first conductive type longitudinal strip regions 4 and second conductive type longitudinal strip regions 5 which are alternately distributed in the transverse direction, and a second conductive type isolation layer body region 6 is provided on top of the first conductive type longitudinal strip regions 4 and the second conductive type longitudinal strip regions 5 in the transition region, and the second conductive type longitudinal strip regions 5 and the first conductive type longitudinal strip regions 4 are both connected to the second conductive type isolation layer body region 6; a dielectric layer 14 is provided above the second conductive type isolation layer body region 6;

[0107] The terminal region 102 includes first conductivity type longitudinal strip regions 4 and second conductivity type longitudinal strip regions 5 which are alternately distributed in the transverse direction, and the tops of the first conductivity type longitudinal strip regions 4 and the second conductivity type longitudinal strip regions 5 are directly connected to the dielectric layer 14; the lower boundary of the second conductivity type isolation layer body region 6 is not lower than the lower boundary of the second conductivity type body region 9; a dielectric layer 14 is provided above the second conductivity type isolation layer body region 6, a drain polysilicon field plate 15 is provided in the dielectric layer 14 at the rightmost end of the device, and a first conductivity type heavily doped region 11 is provided below the drain polysilicon field plate 15 and is short-circuited with the drain polysilicon field plate 15;

[0108] The widths of the first conductive type longitudinal strip region 4 and the second conductive type longitudinal strip region 5 in the transition region are both smaller than the first conductive type longitudinal strip region 4 and the second conductive type longitudinal strip region 5 in the cell region;

[0109] The widths of the first conductivity type longitudinal strip regions 4 and the second conductivity type longitudinal strip regions 5 in the terminal region are both smaller than those of the first conductivity type longitudinal strip regions 4 and the second conductivity type longitudinal strip regions 5 in the cell region.

[0110] This embodiment adopts a conventional P-column top-to-top structure, and the terminal withstand voltage length is longer, further transferring the breakdown position to the inside of the cell area.

[0111] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A power semiconductor device, comprising a cell region (100), a transition region (101) and a terminal region (102), characterized in that: The transition region (101) is located between the device cell region (100) and the terminal region (102); the device cell region (100), the transition region (101) and the terminal region (102) have a common bottom structure, the bottom structure comprising a drain metal (17), a first conductive type substrate (1) located above the drain metal (17), a first conductive type epitaxial layer (2) located above the first conductive type substrate (1), and a first conductive type buffer layer (3) located at the bottom of the first conductive type epitaxial layer (2); the direction from the first conductive type epitaxial layer (2) to the first conductive type substrate (1) is the longitudinal direction of the device, and the direction from the cell region (100) to the terminal region (102) is the lateral direction of the device; In the cell region (100), a first conductive type epitaxial layer (2) is provided with first conductive type longitudinal strip regions (4) and second conductive type longitudinal strip regions (5) that are alternately distributed in the transverse direction; a second conductive type body region (9) is provided on top of the first conductive type longitudinal strip regions (4) and the second conductive type longitudinal strip regions (5); a first conductive type heavily doped region (11) and a second conductive type body contact region (10) are provided in the second conductive type body region (9); the first conductive type heavily doped region (11) is located on the left and right sides of the second conductive type body contact region (10); the first conductive type heavily doped region (11) and the second conductive type body contact region (10) are both connected to a source metal (16); a gate oxide layer (12) is provided above the second conductive type body region (9); a gate polysilicon (13) is provided above the gate oxide layer (12); a dielectric layer (14) and a source metal (16) are provided above the gate polysilicon (13); In the transition region (101), first conductive type longitudinal strip regions (4) and second conductive type longitudinal strip regions (5) are arranged in the first conductive type epitaxial layer (2) and are alternately distributed in the transverse direction; a second conductive type isolation layer body region (6) is arranged on top of the first conductive type longitudinal strip regions (4) and the second conductive type longitudinal strip regions (5) in the transition region; the second conductive type longitudinal strip regions (5) and the first conductive type longitudinal strip regions (4) are both connected to the second conductive type isolation layer body region (6); and a dielectric layer (14) is arranged above the second conductive type isolation layer body region (6); The terminal region (102) comprises first conductive type longitudinal strip regions (4) and second conductive type longitudinal strip regions (5) which are alternately distributed in the transverse direction; a second conductive type transverse strip region (7) is provided on top of the first conductive type longitudinal strip regions (4) and the second conductive type longitudinal strip regions (5) in the terminal region; the upper left boundary of the second conductive type transverse strip region (7) is connected to the lower right boundary of the second conductive type isolation layer body region (6) in the transition region; and the lower boundary of the second conductive type isolation layer body region (6) is not lower than the lower boundary of the second conductive type body region (9); The widths of the first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) in the transition region are both smaller than the widths of the first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) in the cell region; The widths of the first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) in the terminal region are both smaller than the widths of the first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) in the cell region; The lower boundary of the second conductive type transverse strip region (7) is connected to a plurality of first conductive type longitudinal strip regions (4) and a second conductive type longitudinal strip region (5); a first conductive type transverse strip region (8) is provided above the second conductive type transverse strip region (7); a dielectric layer (14) is provided above the first conductive type transverse strip region (8); a drain polysilicon field plate (15) is provided in the dielectric layer (14) at the rightmost end of the device; and a first conductive type heavily doped region (11) is provided below the drain polysilicon field plate (15) and is short-circuited with the drain polysilicon field plate (15).

2. A power semiconductor device, characterized in that: It includes a cellular region (100), a transition region (101) and a terminal region (102), The transition region (101) is located between the device cell region (100) and the terminal region (102); the device cell region (100), the transition region (101) and the terminal region (102) have a common bottom structure, the bottom structure comprising a drain metal (17), a first conductive type substrate (1) located above the drain metal (17), a first conductive type epitaxial layer (2) located above the first conductive type substrate (1), and a first conductive type buffer layer (3) located at the bottom of the first conductive type epitaxial layer (2); the direction from the first conductive type epitaxial layer (2) to the first conductive type substrate (1) is the longitudinal direction of the device, and the direction from the cell region (100) to the terminal region (102) is the lateral direction of the device; In the cell region (100), a first conductive type epitaxial layer (2) is provided with first conductive type longitudinal strip regions (4) and second conductive type longitudinal strip regions (5) that are alternately distributed in the transverse direction, a second conductive type body region (9) is provided on the top of the first conductive type epitaxial layer (2), a groove extending to the first conductive type longitudinal strip region (4) below is provided in the second conductive type body region (9), the groove is filled with a gate oxide layer (12) and a gate polysilicon (13), first conductive type heavily doped regions (11) are provided on both sides of the groove, the first conductive type heavily doped region (11) and the second conductive type body contact region (10) are connected to a source metal (16), and a second conductive type implantation region (19) is provided in the first conductive type epitaxial layer (2) at the bottom of the groove; In the transition region (101), first conductive type longitudinal strip regions (4) and second conductive type longitudinal strip regions (5) are arranged in the first conductive type epitaxial layer (2) and are alternately distributed in the transverse direction; a second conductive type isolation layer body region (6) is arranged on top of the first conductive type longitudinal strip regions (4) and the second conductive type longitudinal strip regions (5) in the transition region; the second conductive type longitudinal strip regions (5) and the first conductive type longitudinal strip regions (4) are both connected to the second conductive type isolation layer body region (6); and a dielectric layer (14) is arranged above the second conductive type isolation layer body region (6); The terminal region (102) comprises first conductive type longitudinal strip regions (4) and second conductive type longitudinal strip regions (5) which are alternately distributed in the transverse direction; a second conductive type transverse strip region (7) is provided on top of the first conductive type longitudinal strip regions (4) and the second conductive type longitudinal strip regions (5) in the terminal region; the upper left boundary of the second conductive type transverse strip region (7) is connected to the lower right boundary of the second conductive type isolation layer body region (6) in the transition region; and the lower boundary of the second conductive type isolation layer body region (6) is not lower than the lower boundary of the second conductive type body region (9); The widths of the first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) in the transition region are both smaller than the widths of the first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) in the cell region; The widths of the first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) in the terminal region are both smaller than the widths of the first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) in the cell region; The lower boundary of the second conductive type transverse strip region (7) is connected to a plurality of first conductive type longitudinal strip regions (4) and a second conductive type longitudinal strip region (5); a first conductive type transverse strip region (8) is provided above the second conductive type transverse strip region (7); a dielectric layer (14) is provided above the first conductive type transverse strip region (8); a drain polysilicon field plate (15) is provided in the dielectric layer (14) at the rightmost end of the device; and a first conductive type heavily doped region (11) is provided below the drain polysilicon field plate (15) and is short-circuited with the drain polysilicon field plate (15).

3. A power semiconductor device, characterized in that: It includes a cellular region (100), a transition region (101) and a terminal region (102), The transition region (101) is located between the device cell region (100) and the terminal region (102); the device cell region (100), the transition region (101) and the terminal region (102) have a common bottom structure, the bottom structure comprising a drain metal (17), a first conductive type substrate (1) located above the drain metal (17), a first conductive type epitaxial layer (2) located above the first conductive type substrate (1), and a first conductive type buffer layer (3) located at the bottom of the first conductive type epitaxial layer (2); the direction from the first conductive type epitaxial layer (2) to the first conductive type substrate (1) is the longitudinal direction of the device, and the direction from the cell region (100) to the terminal region (102) is the lateral direction of the device; In the cell region (100), a first conductive type epitaxial layer (2) is provided with first conductive type longitudinal strip regions (4) and second conductive type longitudinal strip regions (5) that are alternately distributed in the transverse direction; a second conductive type body region (9) is provided on top of the first conductive type longitudinal strip regions (4) and the second conductive type longitudinal strip regions (5); a first conductive type heavily doped region (11) and a second conductive type body contact region (10) are provided in the second conductive type body region (9); the first conductive type heavily doped region (11) is located on the left and right sides of the second conductive type body contact region (10); the first conductive type heavily doped region (11) and the second conductive type body contact region (10) are both connected to a source metal (16); a gate oxide layer (12) is provided above the second conductive type body region (9); a gate polysilicon (13) is provided above the gate oxide layer (12); a dielectric layer (14) and a source metal (16) are provided above the gate polysilicon (13); In the transition region (101), first conductive type longitudinal strip regions (4) and second conductive type longitudinal strip regions (5) are arranged in the first conductive type epitaxial layer (2) and are alternately distributed in the transverse direction; a second conductive type isolation layer body region (6) is arranged on top of the first conductive type longitudinal strip regions (4) and the second conductive type longitudinal strip regions (5) in the transition region; the second conductive type longitudinal strip regions (5) and the first conductive type longitudinal strip regions (4) are both connected to the second conductive type isolation layer body region (6); and a dielectric layer (14) is arranged above the second conductive type isolation layer body region (6); The terminal region (102) comprises first conductive type longitudinal strip regions (4) and second conductive type longitudinal strip regions (5) which are alternately distributed in the transverse direction, the tops of the first conductive type longitudinal strip regions (4) and the second conductive type longitudinal strip regions (5) being directly connected to the dielectric layer (14); the lower boundary of the second conductive type isolation layer body region (6) is not lower than the lower boundary of the second conductive type body region (9); a dielectric layer (14) is provided above the second conductive type isolation layer body region (6), a drain polysilicon field plate (15) is provided in the dielectric layer (14) at the rightmost end of the device, and a first conductive type heavily doped region (11) is provided below the drain polysilicon field plate (15) and is short-circuited with the drain polysilicon field plate (15); The widths of the first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) in the transition region are both smaller than the widths of the first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) in the cell region; The widths of the first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) in the terminal region are both smaller than those of the first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) in the cell region.

4. A power semiconductor device, characterized in that: It includes a cellular region (100), a transition region (101) and a terminal region (102), The transition region (101) is located between the device cell region (100) and the terminal region (102); the device cell region (100), the transition region (101) and the terminal region (102) have a common bottom structure, the bottom structure comprising a drain metal (17), a first conductive type substrate (1) located above the drain metal (17), a first conductive type epitaxial layer (2) located above the first conductive type substrate (1), and a first conductive type buffer layer (3) located at the bottom of the first conductive type epitaxial layer (2); the direction from the first conductive type epitaxial layer (2) to the first conductive type substrate (1) is the longitudinal direction of the device, and the direction from the cell region (100) to the terminal region (102) is the lateral direction of the device; In the cell region (100), a first conductive type epitaxial layer (2) is provided with first conductive type longitudinal strip regions (4) and second conductive type longitudinal strip regions (5) that are alternately distributed in the transverse direction; a second conductive type body region (9) is provided on top of the first conductive type longitudinal strip regions (4) and the second conductive type longitudinal strip regions (5); a first conductive type heavily doped region (11) and a second conductive type body contact region (10) are provided in the second conductive type body region (9); the first conductive type heavily doped region (11) is located on the left and right sides of the second conductive type body contact region (10); the first conductive type heavily doped region (11) and the second conductive type body contact region (10) are both connected to a source metal (16); a gate oxide layer (12) is provided above the second conductive type body region (9); a gate polysilicon (13) is provided above the gate oxide layer (12); a dielectric layer (14) and a source metal (16) are provided above the gate polysilicon (13); In the transition region (101), first conductive type longitudinal strip regions (4) and second conductive type longitudinal strip regions (5) are arranged in the first conductive type epitaxial layer (2) and are alternately distributed in the transverse direction; a second conductive type isolation layer body region (6) is arranged on top of the first conductive type longitudinal strip regions (4) and the second conductive type longitudinal strip regions (5) in the transition region; the second conductive type longitudinal strip regions (5) and the first conductive type longitudinal strip regions (4) are both connected to the second conductive type isolation layer body region (6); and a dielectric layer (14) is arranged above the second conductive type isolation layer body region (6); The widths of the first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) in the transition region are both smaller than the widths of the first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) in the cell region; The terminal region (102) comprises first conductive type longitudinal strip regions (4) and second conductive type longitudinal strip regions (5) which are alternately distributed in the transverse direction, and a second conductive type transverse strip region (7) is provided on top of the first conductive type longitudinal strip regions (4) and the second conductive type longitudinal strip regions (5) in the terminal region, the lower boundary of the second conductive type transverse strip region (7) is flush with the lower boundary of the second conductive type isolation layer body region (6), and the lower boundary of the second conductive type isolation layer body region (6) is flush with the lower boundary of the second conductive type body region (9); The widths of the first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) in the terminal region are both smaller than the widths of the first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) in the cell region; The lower boundary of the second conductive type transverse strip region (7) in the terminal region is connected to a plurality of first conductive type longitudinal strip regions (4) and a second conductive type longitudinal strip region (5); a dielectric layer (14) is provided above the second conductive type transverse strip region (7); a drain polysilicon field plate (15) is provided in the dielectric layer (14) at the rightmost end of the device; a first conductive type heavily doped region (11) is provided below the drain polysilicon field plate (15) and is short-circuited with the drain polysilicon field plate (15).

5. The power semiconductor device according to claim 1, 2, 3 or 4, characterized in that: The widths of the first conductive type longitudinal strip regions (4) and the second conductive type longitudinal strip regions (5) in the transition region and the terminal region decrease progressively from the cell region to the terminal region.

6. The power semiconductor device according to claim 1, 2, 3 or 4, characterized in that: The widths of the first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) in the terminal region are smaller than those of the first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) in the transition region.

7. A power semiconductor device, characterized in that: It includes a cellular region (100), a transition region (101) and a terminal region (102), The transition region (101) is located between the device cell region (100) and the terminal region (102); the device cell region (100), the transition region (101) and the terminal region (102) have a common bottom structure, the bottom structure comprising a drain metal (17), a first conductive type substrate (1) located above the drain metal (17), a first conductive type epitaxial layer (2) located above the first conductive type substrate (1), and a first conductive type buffer layer (3) located at the bottom of the first conductive type epitaxial layer (2); the direction from the first conductive type epitaxial layer (2) to the first conductive type substrate (1) is the longitudinal direction of the device, and the direction from the cell region (100) to the terminal region (102) is the lateral direction of the device; In the cell region (100), a first conductive type epitaxial layer (2) is provided with first conductive type longitudinal strip regions (4) and second conductive type longitudinal strip regions (5) that are alternately distributed in the transverse direction; a second conductive type body region (9) is provided on top of the first conductive type longitudinal strip regions (4) and the second conductive type longitudinal strip regions (5); a first conductive type heavily doped region (11) and a second conductive type body contact region (10) are provided in the second conductive type body region (9); the first conductive type heavily doped region (11) is located on the left and right sides of the second conductive type body contact region (10); the first conductive type heavily doped region (11) and the second conductive type body contact region (10) are both connected to a source metal (16); a gate oxide layer (12) is provided above the second conductive type body region (9); a gate polysilicon (13) is provided above the gate oxide layer (12); a dielectric layer (14) and a source metal (16) are provided above the gate polysilicon (13); In the transition region (101), first conductive type longitudinal strip regions (4) and second conductive type longitudinal strip regions (5) are arranged in the first conductive type epitaxial layer (2) and are alternately distributed in the transverse direction; a second conductive type isolation layer body region (6) is arranged on top of the first conductive type longitudinal strip regions (4) and the second conductive type longitudinal strip regions (5) in the transition region; the second conductive type longitudinal strip regions (5) and the first conductive type longitudinal strip regions (4) are both connected to the second conductive type isolation layer body region (6); and a dielectric layer (14) is arranged above the second conductive type isolation layer body region (6); The terminal region (102) comprises first conductive type longitudinal strip regions (4) and second conductive type longitudinal strip regions (5) which are alternately distributed in the transverse direction; a second conductive type transverse strip region (7) is provided on top of the first conductive type longitudinal strip regions (4) and the second conductive type longitudinal strip regions (5) in the terminal region; the upper left boundary of the second conductive type transverse strip region (7) is connected to the lower right boundary of the second conductive type isolation layer body region (6) in the transition region; and the lower boundary of the second conductive type isolation layer body region (6) is not lower than the lower boundary of the second conductive type body region (9); The widths of the first conductive type longitudinal strip regions (4) and the second conductive type longitudinal strip regions (5) of the cell near the transition region in the cell region (100) are the same as those of the first conductive type longitudinal strip regions (4) and the second conductive type longitudinal strip regions (5) in the transition region (101) and the terminal region (102), and are smaller than the widths of the remaining first conductive type longitudinal strip regions (4) and the second conductive type longitudinal strip regions (5) in the cell; The lower boundary of the second conductive type transverse strip region (7) in the terminal region is connected to a plurality of first conductive type longitudinal strip regions (4) and a second conductive type longitudinal strip region (5); a first conductive type transverse strip region (8) is provided above the second conductive type transverse strip region (7); a dielectric layer (14) is provided above the first conductive type transverse strip region (8); a drain polysilicon field plate (15) is provided in the dielectric layer (14) at the rightmost end of the device; a first conductive type heavily doped region (11) is provided below the drain polysilicon field plate (15) and is short-circuited with the drain polysilicon field plate (15).

8. The power semiconductor device according to claim 1, 2, 3 or 4, characterized in that: The widths of the first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) in the terminal region decrease progressively from the cell region to the terminal region and are both smaller than the first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) in the transition region.

9. The power semiconductor device according to claim 1, 3 or 4, characterized in that: A stepped oxide layer which is thick in the middle and thin at both sides is provided above the second conductive type body region (9) in the cell region (100), and the thin oxide layers above the channel regions on both sides are gate oxide layers (12).

10. The power semiconductor device according to claim 1, 2 or 4, characterized in that: A plurality of first conductive type longitudinal strip regions (4) and second conductive type longitudinal strip regions (5) which are not connected to the second conductive type transverse strip regions (7) are provided at the lower right side of the second conductive type transverse strip region (7).

11. The power semiconductor device according to claim 1, 2, 3 or 4, characterized in that: The first conductive type longitudinal strip region (4) and the second conductive type longitudinal strip region (5) are of a trapezoidal structure.

12. The power semiconductor device according to any one of claims 1 to 11, characterized in that: The structure includes an N-type power semiconductor device and its terminal structure and a P-type power semiconductor device and its terminal structure. For the terminal structure of the N-type power semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type. For the terminal structure of the P-type semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type.

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