High-reliability silicon carbide groove type super-junction MOSFET device and preparation method thereof

Abstract

The invention provides a high-reliability silicon carbide groove type super-junction MOSFET device. The high-reliability silicon carbide groove type super-junction MOSFET device comprises a drain electrode, a first doping type substrate, a first doping type drift region, a second doping type super-junction region structure, an oxidation column structure, a second doping type well region, a gate groove, a virtual gate groove, a first doping type contact region, a second doping type source region and a source electrode. The invention has excellent high-voltage bearing capacity and low on-resistance, and can provide efficient switching performance in high-voltage and high-power applications. Through the design of the super junction structure, the conduction loss is reduced, and the working efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors, and in particular relates to a high-reliability silicon carbide trench super junction MOSFET device and a preparation method thereof. Background Art

[0002] Silicon carbide is a typical wide bandgap semiconductor material. Due to the huge advantages of silicon carbide in bandgap width, thermal conductivity, breakdown electric field, electron mobility, etc., silicon carbide power devices can be better suited for high-voltage, high-frequency, and high-power power electronics applications compared to silicon-based power devices. Compared with insulated gate field effect transistors (IGBTs), silicon carbide metal oxide semiconductor field effect transistors (MOSFETs) have faster switching speeds and have huge advantages in high-frequency application scenarios. Under the guidance of charge balance theory, silicon carbide superjunction MOSFETs have an alternating N-column / P-column structure, which can achieve lower on-resistance while maintaining a high breakdown voltage.

[0003] However, there are some reliability issues in silicon carbide superjunction MOSFETs. 1. During the reverse conduction of the device, electron-hole recombination will cause the stacking faults in silicon carbide to expand. This phenomenon is called bipolar degradation. The introduction of the superjunction structure will cause more holes to be injected into the substrate, thereby triggering bipolar degradation in the substrate. 2. The reverse recovery characteristics of silicon carbide superjunction MOSFET devices are poor, which will cause electromagnetic interference during application. 3. Compared with silicon-based IGBTs, silicon carbide MOSFETs have worse short-circuit reliability, which is mainly manifested in the shorter short-circuit withstand time of the device. Summary of the invention

[0004] In view of the above problems, the present invention proposes a high-reliability silicon carbide trench superjunction MOSFET device and a manufacturing method, which aims to solve the bipolar degradation problem, improve the reverse recovery characteristics, and enhance the short-circuit reliability while ensuring that the on-resistance and breakdown voltage of the device are not affected.

[0005] The technical solution of the present invention is as follows:

[0006] A high reliability silicon carbide trench super junction MOSFET device, comprising:

[0007] A drain, a first doping type substrate, a first doping type drift region, a second doping type super junction region structure, an oxide column structure, a second doping type well region, a gate trench, a virtual gate trench, a first doping type contact region, a second doping type source region and a source electrode;

[0008] Among them, the first doping type substrate is located on the drain; the first doping type drift region is located on the first doping type substrate; the second doping type super junction region and the oxide column region are located in the first doping type drift region; the second doping type well region is located on the first doping type drift region; the gate trench and the virtual gate trench are located in the second doping type well region; the oxide column structure runs through the gate trench; the second doping type super junction region structure runs through the virtual gate trench; the first doping type contact region and the second doping type source region are alternately arranged and located on the second doping type well region; the source is located on the first doping type contact region and the second doping type source region.

[0009] Furthermore, the oxide column structure includes: an oxide column region, a gate dielectric, a gate conductor and a gate isolation dielectric, wherein the oxide column region is located below the gate trench; the gate dielectric is located on the sidewall and bottom of the gate trench; the gate conductor is located in the gate trench and is surrounded by the gate dielectric on three sides; the gate isolation dielectric is located above the gate conductor and completely covers the gate conductor.

[0010] Furthermore, the second doping type super junction region structure includes a second doping type super junction source region, a virtual gate dielectric and a virtual gate conductor; wherein the second doping type super junction source region is located on the second doping type super junction column; the virtual gate dielectric is located on the sidewall and bottom of the virtual gate trench; the virtual gate conductor is located in the virtual gate trench and is surrounded by the virtual gate dielectric on three sides.

[0011] Further, the first doping type is N-type, and the corresponding second doping type is P-type; the first doping type is P-type, and the corresponding second doping type is N-type.

[0012] Furthermore, the gate dielectric and the virtual gate dielectric are made of silicon oxide and / or high-k dielectric materials.

[0013] The dummy gate dielectric may completely cover the bottom of the trench, or may not completely cover the bottom of the trench, so that the dummy gate conductor is connected to the super junction source region.

[0014] The present invention also provides a method for manufacturing a high-reliability silicon carbide trench super junction MOSFET device, comprising:

[0015] Step 1, forming an epitaxial layer of a first doping type on a substrate of a first doping type as a drift region;

[0016] Step 2, forming a well region of a second doping type on the upper side of the drift region;

[0017] Step 3, etching a portion of the well region and the drift region to form a super junction region of the second doping type in the etched epitaxial layer;

[0018] Step 4, etching part of the well region and the drift region to form an oxide column region in the etched epitaxial layer;

[0019] Step 5, forming a contact region of the first doping type and a source region of the second doping type on the upper side of the well region;

[0020] Step 6: Etching in the source region to form a virtual gate trench penetrating the well region;

[0021] Step 7, forming a super junction source region of a second doping type below the virtual gate trench;

[0022] Step 8, forming a virtual gate dielectric in the virtual gate trench;

[0023] Step 9, etching in the oxide column region to form a gate trench, and forming a gate dielectric and a gate conductor in the trench;

[0024] Step 10: forming an isolation dielectric on the gate conductor, forming a source electrode on the contact region, the source region, the virtual gate dielectric, and the gate isolation dielectric, and forming a drain electrode and a virtual gate conductor under the substrate;

[0025] Furthermore, a polishing process is performed after forming the second doping type super junction region and the oxidation column region.

[0026] Furthermore, the method also includes annealing the source and the drain.

[0027] Compared with the prior art, the present invention has the following advantages:

[0028] 1. In the case of reverse conduction, since the virtual gate conductor is at a high potential, an inversion layer will be formed near the virtual gate dielectric in the well region, which serves as a channel for carrier drift. This avoids the presence of excessive minority carriers in the drift region and super junction region of the super junction MOSFET, thereby avoiding the occurrence of bipolar degradation;

[0029] 2. Since the minority carrier concentration in the drift region and super junction region is low when the device is reversely conducted, the reverse recovery characteristics of the device are improved and the electromagnetic interference during the switching process is suppressed;

[0030] 3. As the number of gates per unit area is reduced, the saturation current of the device in the short-circuit condition is reduced, resulting in increased short-circuit reliability of the device. Although the channel resistance increases, the structure avoids the existence of the JFET region in the traditional structure, enhancing the short-circuit reliability while avoiding an increase in on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings generally illustrate various embodiments by way of example and not limitation, and together with the description and claims, serve to illustrate the embodiments of the invention. Where appropriate, the same reference numerals are used throughout the drawings to refer to the same or similar parts. Such embodiments are illustrative and are not intended to be exhaustive or exclusive embodiments of the present apparatus or method.

[0032] Figure 1 A schematic diagram of a cell structure of a high-reliability silicon carbide trench super junction MOSFET device in Example 1 of the present invention is shown;

[0033] Figure 2 A schematic diagram of a cell structure of a high-reliability silicon carbide trench super junction MOSFET device in Example 2 of the present invention is shown;

[0034] Figure 3 A schematic diagram of the cell structure of a high-reliability silicon carbide trench super junction MOSFET device in Example 3 of the present invention is shown. DETAILED DESCRIPTION

[0035] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0036] Example 1

[0037] like Figure 1 As shown, a high reliability silicon carbide trench super junction MOSFET device comprises:

[0038] Drain 1;

[0039] An N-type substrate 2 is located on the drain electrode 1, has a resistivity of 0.025Ω·cm and a thickness of 350μm;

[0040] The N-type drift region 3 is located on the substrate 2 and has a doping concentration of 2e16 cm -3 , thickness is 9.5μm;

[0041] The P-type super junction region 4 is located on the substrate 2 and adjacent to the drift region 3, with a doping concentration of 5.6e16 cm -3 , with a width of 0.8 μm and a distance of 0.5 μm between the bottom and the substrate 2;

[0042] The oxide column region 5 is located on the substrate 2, adjacent to the drift region 3, and alternately arranged with the super junction region 4, and is made of silicon dioxide, has a width of 0.8 μm, and a distance between the bottom and the substrate 2 of 0.5 μm;

[0043] The P-type well region 6 is located above the drift region 3, the super junction region 4, and the oxide column region 5, and has a doping concentration of 2e17 cm -3 , thickness is 0.8μm;

[0044] A gate trench is located in the well region 6 and above the oxide column region 5, with a depth of 1.5 μm and a width of 0.8 μm;

[0045] A virtual gate trench is located in the well region 6 and above the super junction region 4, with a depth of 1.5 μm and a width of 0.8 μm;

[0046] The N-type contact regions 7-1, 7-2, 7-3, and 7-4 are located on the well region 6 and on both sides of the gate trench and the virtual gate trench, and the doping concentration is 1e19 cm -3 , width 0.7μm, thickness 0.4μm;

[0047] The P-type source regions 8-1, 8-2, and 8-3 are located above the well region 6 and are adjacent to the contact regions 7-1, 7-2, 7-3, and 7-4, and have a doping concentration of 1e19 cm -3 , width 0.7μm, thickness 0.4μm;

[0048] The P-type super junction source region 9 is located on the upper side of the super junction column 4 and has a doping concentration of 1e19 cm -3 , width 0.4μm, thickness 0.1μm;

[0049] The gate dielectric 10 is located on the sidewall and bottom of the gate trench, has a thickness of 50 nm, and is made of silicon dioxide;

[0050] The gate conductor 11 is located in the gate trench, surrounded by the gate dielectric on three sides, and is made of polysilicon;

[0051] The virtual gate dielectric 12 is located on the sidewall and bottom of the virtual gate trench, has a thickness of 10 nm, and is made of silicon dioxide;

[0052] A dummy gate conductor 13, located in the dummy gate trench, surrounded by the dummy gate dielectric on three sides, and made of aluminum;

[0053] A gate isolation dielectric 14 is located on the gate conductor, completely covers the gate conductor, has a thickness of 1 μm, a width of 1.2 μm, and is made of silicon dioxide;

[0054] The source electrode 15 is located on the contact regions 7-1, 7-2, 7-3, 7-4, the source regions 8-1, 8-2, 8-3, the dummy gate conductor 13, the dummy gate dielectric 12, and the gate isolation dielectric 14, and is made of aluminum.

[0055] The present invention also provides a method for preparing a high-reliability silicon carbide trench super junction MOSFET device, comprising:

[0056] Step 1: epitaxially grow a doping concentration of 2e16cm on an N-type substrate 2 by chemical vapor deposition. -3 , an N-type doped drift region 3 having a thickness of 10.7 μm;

[0057] Step 2: forming a P-type doping with a concentration of 2e17 cm-3 and a depth of 1.2 μm in the drift region 3 through a multi-step ion implantation process to obtain a well region 6;

[0058] Step 3: After masking and photolithography, a trench with a depth of 10.2 μm and a width of 0.8 μm is etched in the drift region 3 by reactive plasma etching; a doping concentration of 5.6e16 cm is filled in the trench by epitaxial backfilling process. -3 The P-type doped super junction region 4 is formed; the semiconductor surface is flattened by chemical mechanical polishing;

[0059] Step 4: After masking and photolithography, a groove with a depth of 10.2 μm and a width of 0.8 μm is etched in the drift region 3 by reactive plasma etching; silicon dioxide is filled in the groove by plasma enhanced chemical vapor deposition to form an oxide column region 5; and the semiconductor surface is flattened by chemical mechanical polishing;

[0060] Step 5, after masking and photolithography, a P-type doping and an N-type doping with a concentration of 1e19 cm-3 and a depth of 0.4 μm are formed at different positions in the well region 6 by a multi-step ion implantation process to obtain contact regions 7-1, 7-2, 7-3, 7-4 and source regions 8-1, 8-2, 8-3;

[0061] Step 6, after masking and photolithography, a virtual gate trench with a depth of 1.5 μm and a width of 0.8 μm is etched above the super junction region 4 by reactive plasma etching;

[0062] Step 7, after masking and photolithography, a P-type doped super junction source region 9 with a doping concentration of 1e19cm-3 and a width of 0.4μm is formed under the virtual gate trench by an ion implantation process; the semiconductor is subjected to high temperature thermal annealing to activate the doping, the temperature is 1700°C, and the time is 30min;

[0063] Step 8, after masking and photolithography, 10 nm of silicon dioxide is deposited in the virtual gate trench by atomic layer deposition as the virtual gate dielectric 12;

[0064] Step 9, after masking and photolithography, a gate oxide trench with a depth of 1.5 μm and a width of 0.8 μm is etched above the oxide column area 5 by reactive plasma etching; after masking and photolithography, 50 nm of silicon dioxide is deposited in the gate oxide trench as a gate dielectric 10 by plasma enhanced chemical vapor deposition; after masking and photolithography, polysilicon is filled in the gate oxide trench by low pressure chemical vapor deposition as a gate conductor 11; the device surface is flattened by chemical mechanical polishing;

[0065] Step 10, after masking and photolithography, a silicon dioxide layer with a thickness of 1 μm and a width of 1.2 μm is formed on the gate conductor by plasma enhanced chemical vapor deposition as a gate isolation medium 14; aluminum is deposited on the contact areas 7-1, 7-2, 7-3, 7-4, source areas 8-1, 8-2, 8-3, virtual gate conductors 13, virtual gate dielectrics 12, and gate isolation dielectrics 14 by magnetron sputtering as a source; nickel is deposited under the substrate 1 by magnetron sputtering as a drain; and ohmic contact of the electrode is achieved by a rapid thermal annealing process at a temperature of 1000°C for 2 minutes.

[0066] Example 2

[0067] like Figure 2 As shown, a high reliability silicon carbide trench super junction MOSFET device of this embodiment includes:

[0068] Drain 1;

[0069] An N-type substrate 2 is located on the drain electrode 1, has a resistivity of 0.025Ω·cm and a thickness of 350μm;

[0070] The N-type drift region 3 is located on the substrate 2 and has a doping concentration of 2e16 cm -3 , thickness is 9.5μm;

[0071] The P-type super junction region 4 is located on the substrate 2 and adjacent to the drift region 3, with a doping concentration of 5.6e16 cm -3 , the width is 0.8 μm, and the distance between the bottom and the substrate 2 is 0 μm;

[0072] The oxide column region 5 is located on the substrate 2, adjacent to the drift region 3, and alternately arranged with the super junction region 4, and is made of silicon dioxide, has a width of 0.8 μm, and a distance between the bottom and the substrate 2 of 0 μm;

[0073] The P-type well region 6 is located above the drift region 3, the super junction region 4, and the oxide column region 5, and has a doping concentration of 2e17 cm -3 , thickness is 0.8μm;

[0074] A gate trench is located in the well region 6 and above the oxide column region 5, with a depth of 1.5 μm and a width of 0.8 μm;

[0075] A virtual gate trench is located in the well region 6 and above the super junction region 4, with a depth of 1.5 μm and a width of 0.8 μm;

[0076] The N-type contact regions 7-1, 7-2, 7-3, and 7-4 are located on the well region 6 and on both sides of the gate trench and the virtual gate trench, and the doping concentration is 1e19 cm -3 , width 0.7μm, thickness 0.4μm;

[0077] The P-type source regions 8-1, 8-2, and 8-3 are located above the well region 6 and are adjacent to the contact regions 7-1, 7-2, 7-3, and 7-4, and have a doping concentration of 1e19 cm -3 , width 0.7μm, thickness 0.4μm;

[0078] The P-type super junction source region 9 is located on the upper side of the super junction column 4 and has a doping concentration of 1e19 cm -3 , width 0.4μm, thickness 0.1μm;

[0079] The gate dielectric 10 is located on the sidewall and bottom of the gate trench, has a thickness of 50 nm, and is made of silicon dioxide;

[0080] The gate conductor 11 is located in the gate trench, surrounded by the gate dielectric on three sides, and is made of polysilicon;

[0081] The virtual gate dielectric 12 is located on the sidewall and bottom of the virtual gate trench, has a thickness of 50 nm, and is made of hafnium dioxide;

[0082] A dummy gate conductor 13, located in the dummy gate trench, surrounded by the dummy gate dielectric on three sides, and made of aluminum;

[0083] A gate isolation dielectric 14 is located on the gate conductor, completely covers the gate conductor, has a thickness of 1 μm, a width of 1.2 μm, and is made of silicon dioxide;

[0084] The source electrode 15 is located on the contact regions 7-1, 7-2, 7-3, 7-4, the source regions 8-1, 8-2, 8-3, the dummy gate conductor 13, the dummy gate dielectric 12, and the gate isolation dielectric 14, and is made of aluminum.

[0085] The difference from Example 1 is that the distance between the bottom of the super junction region 4 and the oxide column region 5 and the substrate 2 is 0 μm; the virtual gate dielectric 12 does not completely cover the bottom of the trench, resulting in the virtual gate conductor 13 being connected to the super junction source region 9; the virtual gate dielectric 12 is located on the sidewall and bottom of the virtual gate trench, has a thickness of 50 nm, and is composed of hafnium dioxide. The device in this example has better gate oxide reliability than Example 1.

[0086] A method for manufacturing a high-reliability silicon carbide trench super junction MOSFET device in this embodiment includes:

[0087] Step 1: epitaxially grow a doping concentration of 2e16cm on an N-type substrate 2 by chemical vapor deposition. -3 , an N-type doped drift region 3 having a thickness of 10.7 μm;

[0088] Step 2: forming a P-type doping with a concentration of 2e17 cm-3 and a depth of 1.2 μm in the drift region 3 through a multi-step ion implantation process to obtain a well region 6;

[0089] Step 3: After masking and photolithography, a trench with a depth of 10.7 μm and a width of 0.8 μm is etched in the drift region 3 by reactive plasma etching; a doping concentration of 5.6e16 cm is filled in the trench by epitaxial backfilling process. -3 The P-type doped super junction region 4 is formed; the semiconductor surface is flattened by chemical mechanical polishing;

[0090] Step 4: After masking and photolithography, a groove with a depth of 10.7 μm and a width of 0.8 μm is etched in the drift region 3 by reactive plasma etching; silicon dioxide is filled in the groove by plasma enhanced chemical vapor deposition to form an oxide column region 5; and the semiconductor surface is flattened by chemical mechanical polishing;

[0091] Step 5, after masking and photolithography, a P-type doping and an N-type doping with a concentration of 1e19 cm-3 and a depth of 0.4 μm are formed at different positions in the well region 6 by a multi-step ion implantation process to obtain contact regions 7-1, 7-2, 7-3, 7-4 and source regions 8-1, 8-2, 8-3;

[0092] Step 6, after masking and photolithography, a virtual gate trench with a depth of 1.5 μm and a width of 0.8 μm is etched above the super junction region 4 by reactive plasma etching;

[0093] Step 7, after masking and photolithography, a P-type doped super junction source region 9 with a doping concentration of 1e19cm-3 and a width of 0.4μm is formed under the virtual gate trench by an ion implantation process; the semiconductor is subjected to high temperature thermal annealing to activate the doping, the temperature is 1700°C, and the time is 30min;

[0094] Step 8, after masking and photolithography, 50 nm of hafnium dioxide is deposited in the virtual gate trench by atomic layer deposition as the virtual gate dielectric 12;

[0095] Step 9, after masking and photolithography, a gate oxide trench with a depth of 1.5 μm and a width of 0.8 μm is etched above the oxide column area 5 by reactive plasma etching; after masking and photolithography, 50 nm of silicon dioxide is deposited in the gate oxide trench as a gate dielectric 10 by plasma enhanced chemical vapor deposition; after masking and photolithography, polysilicon is filled in the gate oxide trench by low pressure chemical vapor deposition as a gate conductor 11; the device surface is flattened by chemical mechanical polishing;

[0096] Step 10, after masking and photolithography, a silicon dioxide layer with a thickness of 1 μm and a width of 1.2 μm is formed on the gate conductor by plasma enhanced chemical vapor deposition as a gate isolation dielectric 14; aluminum is deposited on the contact areas 7-1, 7-2, 7-3, 7-4, source areas 8-1, 8-2, 8-3, virtual gate conductors 13, virtual gate dielectrics 12, and gate isolation dielectrics 14 by magnetron sputtering as a source; nickel is deposited under the substrate 1 by magnetron sputtering as a drain; and ohmic contact of the electrode is achieved by a rapid thermal annealing process at a temperature of 1000° C. for 2 min;

[0097] The difference from Example 1 is:

[0098] The etching depth in steps 3 and 4 is 10.7 μm;

[0099] Step 8: After masking and photolithography, 50 nm of hafnium dioxide is deposited in the virtual gate trench by atomic layer deposition as the virtual gate dielectric 12; after masking and photolithography, a notch with a width of 0.2 μm is etched in the virtual gate dielectric 12 by wet etching.

[0100] Example 3

[0101] like Figure 3 As shown, a high reliability silicon carbide trench super junction MOSFET device of this embodiment includes:

[0102] Drain 1;

[0103] An N-type substrate 2 is located on the drain electrode 1, has a resistivity of 0.025Ω·cm and a thickness of 350μm;

[0104] The N-type drift region 3 is located on the substrate 2 and has a doping concentration of 2e16 cm -3 , thickness is 9.5μm;

[0105] The P-type super junction region 4 is located on the substrate 2 and adjacent to the drift region 3, with a doping concentration of 5.6e16 cm -3, with a width of 0.8 μm and a distance of 0.5 μm between the bottom and the substrate 2;

[0106] The oxide column region 5 is located on the substrate 2, adjacent to the drift region 3, and alternately arranged with the super junction region 4, and is made of silicon dioxide, has a width of 0.8 μm, and a distance between the bottom and the substrate 2 of 0.5 μm;

[0107] The P-type well region 6 is located above the drift region 3, the super junction region 4, and the oxide column region 5, and has a doping concentration of 2e17 cm -3 , thickness is 0.8μm;

[0108] A gate trench is located in the well region 6 and above the oxide column region 5, with a depth of 1.5 μm and a width of 0.8 μm;

[0109] A virtual gate trench is located in the well region 6 and above the super junction region 4, with a depth of 1.5 μm and a width of 0.8 μm;

[0110] The N-type contact regions 7-1, 7-2, 7-3, and 7-4 are located on the well region 6 and on both sides of the gate trench and the virtual gate trench, and the doping concentration is 1e19 cm -3 , width 0.7μm, thickness 0.4μm;

[0111] The P-type source regions 8-1, 8-2, and 8-3 are located above the well region 6 and are adjacent to the contact regions 7-1, 7-2, 7-3, and 7-4, and have a doping concentration of 1e19 cm -3 , width 0.7μm, thickness 0.4μm;

[0112] The P-type super junction source region 9 is located on the upper side of the super junction column 4 and has a doping concentration of 1e19 cm -3 , width 0.4μm, thickness 0.1μm;

[0113] There is an N-type doped source 15 with a thickness of 0.3 μm and a doping concentration of 5e16 cm-3 directly between the well region 6 and the drift region 3.

[0114] The gate dielectric 10 is located on the sidewall and bottom of the gate trench, has a thickness of 50 nm, and is made of silicon dioxide;

[0115] The gate conductor 11 is located in the gate trench, surrounded by the gate dielectric on three sides, and is made of polysilicon;

[0116] The virtual gate dielectric 12 is located on the sidewall and bottom of the virtual gate trench, has a thickness of 10 nm, and is made of silicon dioxide;

[0117] A dummy gate conductor 13, located in the dummy gate trench, surrounded by the dummy gate dielectric on three sides, and made of aluminum;

[0118] A gate isolation dielectric 14 is located on the gate conductor, completely covers the gate conductor, has a thickness of 1 μm, a width of 1.2 μm, and is made of silicon dioxide;

[0119] The source electrode 15 is located on the contact regions 7-1, 7-2, 7-3, 7-4, the source regions 8-1, 8-2, 8-3, the dummy gate conductor 13, the dummy gate dielectric 12, and the gate isolation dielectric 14, and is made of aluminum.

[0120] The difference from Example 1 is that an N-type doped current spreading layer 16 with a thickness of 0.3 μm and a doping concentration of 5e16 cm-3 exists directly in the well region 6 and the drift region 3. The device in this example has better third quadrant characteristics than Example 1.

[0121] The present invention also provides a method for preparing a high-reliability silicon carbide trench super junction MOSFET device, comprising:

[0122] Step 1: epitaxially grow a doping concentration of 2e16cm on an N-type substrate 2 by chemical vapor deposition. -3 , an N-type doped drift region 3 with a thickness of 10.7 μm, and then a multi-part ion implantation process is performed to form an N-type doping with a concentration of 5e16 cm-3 and a depth of 1.5 μm in the drift region 3 to obtain a current spreading layer 16;

[0123] Step 2: forming a P-type doping with a concentration of 2e17 cm-3 and a depth of 1.2 μm in the drift region 3 through a multi-step ion implantation process to obtain a well region 6;

[0124] Step 3: After masking and photolithography, a trench with a depth of 10.2 μm and a width of 0.8 μm is etched in the drift region 3 by reactive plasma etching; a doping concentration of 5.6e16 cm is filled in the trench by epitaxial backfilling process. -3 The P-type doped super junction region 4 is formed; the semiconductor surface is flattened by chemical mechanical polishing;

[0125] Step 4: After masking and photolithography, a groove with a depth of 10.2 μm and a width of 0.8 μm is etched in the drift region 3 by reactive plasma etching; silicon dioxide is filled in the groove by plasma enhanced chemical vapor deposition to form an oxide column region 5; and the semiconductor surface is flattened by chemical mechanical polishing;

[0126] Step 5, after masking and photolithography, a P-type doping and an N-type doping with a concentration of 1e19 cm-3 and a depth of 0.4 μm are formed at different positions in the well region 6 by a multi-step ion implantation process to obtain contact regions 7-1, 7-2, 7-3, 7-4 and source regions 8-1, 8-2, 8-3;

[0127] Step 6, after masking and photolithography, a virtual gate trench with a depth of 1.5 μm and a width of 0.8 μm is etched above the super junction region 4 by reactive plasma etching;

[0128] Step 7, after masking and photolithography, a P-type doped super junction source region 9 with a doping concentration of 1e19cm-3 and a width of 0.4μm is formed under the virtual gate trench by an ion implantation process; the semiconductor is subjected to high temperature thermal annealing to activate the doping, the temperature is 1700°C, and the time is 30min;

[0129] Step 8, after masking and photolithography, 10 nm of silicon dioxide is deposited in the virtual gate trench by atomic layer deposition as the virtual gate dielectric 12;

[0130] Step 9, after masking and photolithography, a gate oxide trench with a depth of 1.5 μm and a width of 0.8 μm is etched above the oxide column area 5 by reactive plasma etching; after masking and photolithography, 50 nm of silicon dioxide is deposited in the gate oxide trench as a gate dielectric 10 by plasma enhanced chemical vapor deposition; after masking and photolithography, polysilicon is filled in the gate oxide trench by low pressure chemical vapor deposition as a gate conductor 11; the device surface is flattened by chemical mechanical polishing;

[0131] Step 10, after masking and photolithography, a silicon dioxide layer with a thickness of 1 μm and a width of 1.2 μm is formed on the gate conductor by plasma enhanced chemical vapor deposition as a gate isolation medium 14; aluminum is deposited on the contact areas 7-1, 7-2, 7-3, 7-4, source areas 8-1, 8-2, 8-3, virtual gate conductors 13, virtual gate dielectrics 12, and gate isolation dielectrics 14 by magnetron sputtering as a source; nickel is deposited under the substrate 1 by magnetron sputtering as a drain; and ohmic contact of the electrode is achieved by a rapid thermal annealing process at a temperature of 1000°C for 2 minutes.

[0132] The method for manufacturing a high-reliability silicon carbide trench super junction MOSFET device in this embodiment is different from that in Embodiment 1 in that:

[0133] Step 1 After forming the epitaxial layer, a multi-step ion implantation process is performed to form an N-type doping with a concentration of 5e16 cm-3 and a depth of 1.5 μm in the drift region 3 to obtain a current spreading layer 16.

[0134] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A high reliability silicon carbide trench super junction MOSFET device, characterized in that: include: A drain, a first doping type substrate, a first doping type drift region, a second doping type super junction region structure, an oxide column structure, a second doping type well region, a gate trench, a virtual gate trench, a first doping type contact region, a second doping type source region and a source electrode; Wherein, the first doping type substrate is located on the drain; the first doping type drift region is located on the first doping type substrate; the second doping type super junction region and the oxide column region are located in the first doping type drift region; the second doping type well region is located on the first doping type drift region; the gate trench and the virtual gate trench are located in the second doping type well region; the oxide column structure runs through the gate trench; the second doping type super junction region structure runs through the virtual gate trench; The first doping type contact regions and the second doping type source regions are alternately arranged and located on the second doping type well region; the source electrode is located on the first doping type contact regions and the second doping type source regions.

2. The high reliability silicon carbide trench super junction MOSFET device according to claim 1, characterized in that: The oxide column structure includes: an oxide column region, a gate dielectric, a gate conductor and a gate isolation dielectric, wherein the oxide column region is located below the gate trench; the gate dielectric is located on the sidewall and bottom of the gate trench; the gate conductor is located in the gate trench and is surrounded by the gate dielectric on three sides; the gate isolation dielectric is located above the gate conductor and completely covers the gate conductor.

3. The high reliability silicon carbide trench super junction MOSFET device according to claim 1, characterized in that: The second doping type super junction region structure includes a second doping type super junction source region, a virtual gate dielectric and a virtual gate conductor; wherein the second doping type super junction source region is located on the second doping type super junction column; the virtual gate dielectric is located on the sidewall and bottom of the virtual gate trench; the virtual gate conductor is located in the virtual gate trench and is surrounded by the virtual gate dielectric on three sides.

4. The high reliability silicon carbide trench super junction MOSFET device according to claim 1, characterized in that: The first doping type is N-type, and the corresponding second doping type is P-type.

5. The high reliability silicon carbide trench super junction MOSFET device according to claim 1, characterized in that: The first doping type is P type, and the corresponding second doping type is N type.

6. A method for manufacturing a high reliability silicon carbide trench super junction MOSFET device, characterized in that: include: Step 1, forming an epitaxial layer of a first doping type on a substrate of a first doping type as a drift region; Step 2, forming a well region of a second doping type on the upper side of the drift region; Step 3, etching a portion of the well region and the drift region to form a super junction region of the second doping type in the etched epitaxial layer; Step 4, etching part of the well region and the drift region to form an oxide column region in the etched epitaxial layer; Step 5, forming a contact region of the first doping type and a source region of the second doping type on the upper side of the well region; Step 6: Etching in the source region to form a virtual gate trench penetrating the well region; Step 7, forming a super junction source region of a second doping type below the virtual gate trench; Step 8, forming a virtual gate dielectric in the virtual gate trench; Step 9, etching in the oxide column region to form a gate trench, and forming a gate dielectric and a gate conductor in the trench; Step 10: forming an isolation dielectric on the gate conductor, forming a source electrode on the contact region, the source region, the dummy gate dielectric, and the gate isolation dielectric, and forming a drain electrode and a dummy gate conductor under the substrate.

7. The method for manufacturing a high reliability silicon carbide trench super junction MOSFET device according to claim 6, characterized in that: After forming the second doping type super junction region and the oxidation column region, polishing is performed.

8. The method for manufacturing a high-reliability silicon carbide trench super junction MOSFET device according to claim 6, characterized in that: The method further includes annealing the source and the drain.

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