Distributed gate drive for DrMOS

Abstract

A transistor device includes a semiconductor substrate composition and a first gate electrode material disposed on a portion of a surface of the substrate composition. A gate insulating material is over the first gate electrode material, including two or more first gate vias through the gate insulating material in the first gate electrode contact region. A transistor device package includes a gate controller integrated circuit including a first transistor gate driver output node. A first gate conductive redistribution material connects a first gate electrode material of the first transistor device to an output node of the gate controller integrated circuit through the two or more first gate vias.

Description

Technical Field

[0001] Various aspects of the present disclosure relate to driver MOSFET (DrMOS) devices. More particularly, various aspects of the present disclosure relate to wafer level packaging and drivers in DrMOS devices. Background Art

[0002] In traditional DrMOS devices, the transistor driver is packaged with the transistor device in a multi-chip package. Popular multi-chip packages include quad flat no-lead (QFN) and flip-chip, which use bonding wires to connect the chip inside the package to the lead frame. Flip-chip packaging involves using clips to connect the back of the chip to the lead frame.

[0003] Figure 1A and Figure 1B A prior art flip chip design is schematically depicted. As shown, the flip chip package includes a gate controller integrated circuit 101, a high-side metal oxide semiconductor field effect transistor (MOSFET) 103, a low-side MOSFET 102, a lead frame 107, and a back clip 110. The gate of the low-side MOSFET 102 includes a large gate contact pad 104, which requires sufficient area to connect to the transistor driver 101. A large solder joint 111 forms a connection between the gate contact pad 104 and the lead frame 107. Metal bonding wires 106 connect the lead frame to the transistor driver, allowing the transistor to send signals to the gate contact pad 104 of the low-side MOSFET 102 through the large solder joint 111. The high-side MOSFET 103 also includes a large gate contact pad 105, and a high-side gate bonding wire 108 connects the gate contact pad 105 to the high-side gate control output node of the transistor driver 101. The large gate contact pads take up a lot of space in the low-side MOSFET 102 and the high-side MOSFET 103. Since there is no active area under the gate pads, the space under the gate contact pads is wasted. The transistor driver 101 also includes pads for other control inputs, which are connected to the lead frame 107 via bond wires 109. Figure 1B As shown, the backside clip 110 connects the source of the high-side MOSFET 103 to the drain low-side MOSFET 102, and then to the VSWH pin outside the leadframe 107. The bond wires require space within the device package because each wire must be separated by a large enough gap to ensure that there is no arcing between the leads, and the pads on each device must be large enough to allow for bonding. In addition, bond wires have a large inductance compared to thin metal leads. The leadframe and clip also have a size disadvantage because the metal clip must have sufficient strength to maintain contact with the back of the chip. Finally, the large single bond pad creates a problem because the gate impedance is uneven, resulting in uneven switching of the transistor device.

[0004] It is against this background that various aspects of the present invention are presented. Summary of the invention

[0005] The present invention discloses a transistor device, comprising: a semiconductor substrate composition; a first gate electrode material, which is arranged on a portion of the surface of the semiconductor substrate composition, wherein the first gate electrode material includes a first gate electrode contact area close to at least one edge of the substrate composition; a gate insulating material on the first gate electrode material, comprising two or more first gate through holes passing through the gate insulating material in the first gate electrode contact area, wherein the two or more first gate through holes expose the first gate electrode material.

[0006] It also includes a source region formed in the substrate composition; and a source region insulating material, which is arranged above the source region and includes two or more source through holes passing through the source insulating material, wherein the two or more source through holes expose the substrate composition in the source region.

[0007] It also includes a conductive first gate redistribution material, which is conductively coupled to the first gate metal layer, wherein the first gate metal layer at least arranges the two or more first gate through holes and conductively couples each first gate through hole to each other.

[0008] Wherein, the first gate redistribution material is connected to an output node of a gate controller.

[0009] Wherein, two or more first gate redistribution layer through holes are distributed proportionally on the first gate electrode contact region.

[0010] The method further includes a conductive source redistribution material, which is conductively coupled to the top metal of the source region, lines at least two or more source through holes, and conductively couples each source through hole.

[0011] Wherein, the conductive source redistribution material is connected to a source contact node of the transistor device.

[0012] Wherein, two or more source redistribution layer through holes are distributed proportionally on the source region.

[0013] It also includes a drain region formed on the back side of the substrate composition and a drain insulating material above the back side drain region, wherein the drain region includes two or more through holes passing through the drain insulating material for connecting to the drain metal or the drain redistribution layer.

[0014] The method further comprises a second gate electrode located on the surface of the substrate composition, and the gate insulating material further comprises two or more second gate through holes, wherein the second gate through holes expose the second gate electrode for connection.

[0015] It also includes a sensor FET source region formed in the substrate composition, wherein the source region insulating material includes at least one through-hole passing through the source region insulating material, and the through-hole is located above the source region of the sensor FET to expose the source region of the sensor FET for connection.

[0016] It also includes a sense FET source redistribution material that conductively couples the source region of the sense FET to a sense FET node of the gate controller.

[0017] Wherein, the sensing FET gate is located at the center of the source region.

[0018] The diameter of the through hole from the redistribution layer to the gate metal layer in conductive contact with the first gate electrode material is 20 microns or less.

[0019] Also included is an on-wafer capacitor formed in the substrate composition, wherein the on-wafer capacitor connects the gate electrode to the first gate electrode contact region.

[0020] Wherein, the first gate electrode material is formed in a groove of the substrate composition.

[0021] Wherein, at least a portion of the first gate electrode material is formed on a conductive shield electrode in a trench of the substrate composition.

[0022] The first gate electrode material is part of a planar gate structure on the surface of the substrate composition.

[0023] The present invention also discloses a distributed drive package, comprising: a first transistor device having two or more first gate through holes on a first top edge portion of the first transistor device, electrically connected to a first gate electrode material; a gate controller integrated circuit comprising a first gate driver output node; and a first gate conductive redistribution material, conductively coupling the first gate electrode material of the first transistor device to the first gate driver output node through two or more first gate through holes.

[0024] It also includes a second transistor device having two or more second gate through holes along the top edge of the second transistor device, exposing a second gate electrode material and a second gate conductive redistribution material, wherein the second gate conductive redistribution material conductively couples the second gate electrode material to a second gate output node of the gate controller integrated circuit.

[0025] The first transistor device is a low-side field effect transistor for a voltage regulator, and the second transistor is a high-side field effect transistor.

[0026] Wherein, the first gate redistribution material includes two or more connections between the first gate driver output node and the first gate metal layer through two or more redistribution layer vias to the first gate electrode material.

[0027] The two or more connections are distributed proportionally between two or more redistribution layer through holes.

[0028] Wherein, the two or more connections are formed between two or more first gate driver output nodes on the first gate driver integrated circuit and the first gate electrode material.

[0029] The first gate conductive redistribution material includes a metal line connected to the first gate driver output node and conductively coupled to the first gate electrode material.

[0030] Wherein the first gate conductive redistribution material includes one or more conductive traces conductively coupled to the first gate driver output node and conductively coupled to the first gate electrode material.

[0031] wherein the first transistor device comprises two or more additional first gate through holes at a second top edge portion thereof, and the first gate conductive redistribution material further conductively couples the first gate electrode material of the first transistor device to the first gate driver output node of the gate controller integrated circuit through two or more additional first gate through holes on the second top boundary portion of the substrate composition.

[0032] wherein the gate controller integrated circuit includes a second gate driver output node, and wherein the first transistor device includes two or more second gate through holes on a second top edge portion of the first crystal device, and wherein a second gate conductive redistribution layer conductively couples a third gate electrode material of the first semiconductor device to the second gate drive output node through the two or more second gate through holes on a second bottom edge portion of the substrate composition.

[0033] The two or more second gate through holes are distributed proportionally on the second gate electrode contact region.

[0034] Wherein, the first transistor device includes at least one on-wafer capacitor.

[0035] Wherein, the gate controller integrated circuit is a monolithic integrated circuit including a second transistor device.

[0036] Wherein, the first transistor device includes a sense FET and a sense FET redistribution material, wherein the sense FET redistribution material is between the sense FET and a sense FET node on the gate controller integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Other features and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the following drawings, in which:

[0038] Figure 1A A top-down schematic diagram showing a prior art flip chip design.

[0039] Figure 1B Shows a side view of a prior art flip chip design.

[0040] Figure 2 A top view of a redistribution layer (RDL) of a transistor device is shown according to various aspects of the present disclosure.

[0041] Figure 3 A top view of an RDL of a DRMOS device with a distributed gate driver having a single gate bus for the gate of each MOSFET is shown in accordance with various aspects of the present disclosure.

[0042] Figure 4 A top view of an RDL of a DRMOS device with a distributed gate driver having multiple proportionally distributed gate busses for the gate of each MOSFET is shown in accordance with various aspects of the present disclosure.

[0043] Figure 5 A top view of an RDL of a DRMOS device with a distributed gate driver having multiple evenly distributed gate bus lines for gate electrode contact areas on both top sides of each FET device is shown in accordance with various aspects of the present disclosure.

[0044] Figure 6 A top view of an RDL of a DRMOS device with a distributed gate driver having a plurality of proportionally distributed gate busses for gate electrode contact areas on both top sides of each FET device including a sense FET is shown in accordance with various aspects of the present disclosure.

[0045] Figure 7A top view of an RDL of a DRMOS device having FET devices integrated with gate control and a distributed gate driver having multiple proportionally distributed gate busses for gate electrode contact areas located at top edges of individual FET devices according to various aspects of the present disclosure is shown.

[0046] Figure 8 A top view of an RDL of a DRMOS device with an integrated trench capacitor in a semiconductor wafer is shown in accordance with various aspects of the present disclosure.

[0047] Fig. 9 FIG. 1 is a top view of a distributed gate driver DRMOS device RDL according to various aspects of the present disclosure.

[0048] Fig.10 A top view of a DRMOS device RDL including a split FET device is shown in accordance with various aspects of the present disclosure.

[0049] Fig.11A According to various aspects of the present disclosure, Fig.10 A cross-sectional side view of a shielded gate trench (SGT) MOSFET device in a DRMOS embodiment, taken along line AA.

[0050] Fig. 11B According to various aspects of the present disclosure, Fig.10 A cross-sectional side view of a shielded gate trench (SGT) MOSFET device in a DRMOS embodiment, taken along line BB.

[0051] Fig. 12A According to various aspects of the present disclosure, Fig.10 A cross-sectional side view of a planar gate MOSFET device in a DRMOS embodiment, taken along line AA.

[0052] Fig. 12B According to various aspects of the present disclosure, Fig.10 A cross-sectional side view of a planar gate MOSFET device in a DRMOS embodiment, taken along line BB. DETAILED DESCRIPTION

[0053] Although for the purpose of illustration, the following detailed description contains many specific details, it will be appreciated by those skilled in the art that many changes and modifications to the following details are within the scope of the present invention. Therefore, the exemplary embodiments of the present invention described below are proposed without losing the generality of the claimed invention and without imposing limitations thereon.

[0054] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document, and in which specific embodiments in which the present invention may be practiced are shown by way of illustration. In this regard, directional terms, such as "top", "bottom", "front", "rear", "leading edge", "trailing edge", etc., are used with reference to the direction of the described figures. Because the components of embodiments of the present invention can be positioned in a plurality of different directions, the directional terms are used for illustrative purposes and are not restrictive. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description should not be considered restrictive, and the scope of the present invention is defined by the appended claims.

[0055] The disclosure herein relates to semiconductor materials, such as silicon, doped with ions of a first conductivity type or a second conductivity type. The ions of the first conductivity type may be the opposite ions of the second conductivity type. For example, but not limited to, in some embodiments, the ions of the first conductivity type may be n-type, which contribute negative charge carriers, such as electrons, when doped into silicon. In such embodiments, the ions of the first conductivity type may include phosphorus, antimony, bismuth, lithium, and arsenic. In such embodiments, the ions of the second conductivity may be p-type, which generate holes for charge carriers when doped into silicon, and in this way are referred to as opposite to the n-type. P-type ions include boron, aluminum, gallium, and indium. Although the above description refers to the n-type as the first conductivity type and the p-type as the second conductivity type, the present disclosure is not limited thereto, and the p-type may be the first conductivity type, and the n-type may be the second conductivity type. In addition, according to various aspects of the present disclosure, semiconductor materials other than silicon, such as germanium, silicon carbide, and gallium arsenide, etc., may be used in MOSFET devices.

[0056] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and in which are shown by way of illustration specific embodiments in which the invention may be practiced. For convenience, the use of + or - after specifying a conductivity or net impurity carrier type (p or n) generally refers to the relative concentration of net impurity carriers of the specified type in the semiconductor material. In general, n+ materials have a higher concentration of n-type net dopants (e.g., electrons) than n materials, and n materials have a higher carrier concentration than n- materials. Similarly, p+ materials have a higher concentration of p-type net dopants (e.g., holes) than p materials, and p materials have a higher concentration than p- materials. It should be noted that it is the net concentration of carriers that is relevant, not necessarily the dopant concentration. For example, a material can be heavily doped with an n-type dopant, but still have a relatively low net carrier concentration if the material is also heavily counter-doped with a p-type dopant. As used herein, about 10 15 / cm 3 Dopant concentrations greater than about 1017 / cm 3 A doping concentration of 1000 Å can be considered “heavily doped”.

[0057] According to various aspects of the present disclosure, an improved DrMOS device can be created by using a wafer-level or panel-level package with distributed contact placement in a transistor device, thereby providing more uniform transistor device switching and a smaller device area. In addition, the use of distributed gate drive in a wafer-level or panel-level package can also improve the DrMOS device by splitting the fault point between multiple drivers, reducing parasitic inductance, reducing device area, and improving robustness. Finally, the use of distributed contact placement and distributed gate drive in a wafer-level or panel-level package can provide an enhanced DrMOS device with all of the aforementioned advantages.

[0058] Figure 2 1 shows a top view of a redistribution layer (RDL) of a transistor device according to various aspects of the present disclosure. As shown, the transistor device 201 includes a gate RDL or gate top metal 205. The transistor device includes a source RDL or source top metal 204. A separation region 206 insulates the source RDL or top metal from the gate RDL or top alloy 205.

[0059] As shown, the gate RDL or top metal 205 includes a plated gate via 202 that passes through the gate insulating layer to the gate electrode. The gate electrode material can be distributed in the substrate composition to form a gate contact region along the top edge of the substrate composition. It should be noted that the embodiments are not limited to the gate contact region along a single top edge, and the gate contact region can be on one or more horizontal lines at the top of the subassembly in any area, and can also extend along two top edges, such as Figure 5 and Figure 6 As shown. Two or more through holes through the gate insulating material expose a portion of the gate electrode material in the gate contact area, and the conductive material of the plated gate through hole 202 is in conductive contact with a portion of the gate electrode material on the edge of the transistor device. Two or more through holes can be distributed proportionally on the gate contact area. There may be a sufficient number of through holes of appropriate size to proportionally distribute the voltage through the gate electrode. In some embodiments, the plated gate through hole 202 can be filled with the conductive material of the gate RDL or gate metal layer. The gate RDL or gate metal layer can be made of, for example, but not limited to, copper, aluminum, iron, tungsten, lead or any alloy thereof.

[0060] Here, when discussing RDL, reference may be made to the source RDL, gate RDL, or drain RDL, which refers to the RDL material in the RDL that is conductively coupled to the aforementioned elements. For example, the gate RDL is an RDL material that is conductively coupled to the gate electrode through a via in the gate insulating layer. Similarly, the source RDL is an RDL material that is conductively coupled to the source region and the body region through a via in the source insulating layer, and a drain RDL material that is conductively coupled to the drain region through a via in the drain insulating layer. It should be understood that the source RDL and the gate RDL can be different traces on the same RDL layer or traces on different layers.

[0061] As shown, the source RDL or top metal 204 includes a plated source via 203 that passes through the source insulating layer to reach the source contact. The source insulating layer and the gate insulating layer can be formed of the same material and formed at the same time. Therefore, in some embodiments, the gate insulating layer and the source insulating layer can be the same layer on the device substrate composition. The source and gate insulating layers can be made of oxide (such as silicon dioxide) or another material (such as silicon nitride), which can be formed on the top of the gate electrode material (such as polysilicon or silicide). Two or more through holes through the source insulating material expose the source region in the substrate composition, and the conductive material of the plated source via 203 is in conductive contact with a portion of the source region. Two or more plated source vias can be distributed in proportion on the source RDL or source metal. There may be a sufficient number of through holes to distribute the voltage through the gate region in proportion. In addition, the plated source via 203 can be in conductive contact with the body region of the substrate composition of the so-called anti-parallel diode forming the MOSFET device. In some embodiments, the plated source via 203 may be filled with the conductive material of the source RDL or source metal layer. The source RDL or source metal layer may be made of, for example, but not limited to, copper, aluminum, iron, tungsten, lead, or any alloy thereof. Distributed vias may improve device switching by more evenly distributing the contact with the gate electrode compared to implementations utilizing a single gate pad.

[0062] Figure 31 shows a top view of a DRMOS device RDL with a distributed gate driver having a single gate bus for the gate of each MOSFET according to various aspects of the present disclosure. As shown, the first FET device 302 and the second FET device 303 are connected to the gate driver output node of the gate controller 301 through a single bus of each FET device. The gate controller 301 can be, for example, but not limited to, a gate controller integrated circuit. The gate controller 301 can include gate drivers proportionally distributed between gate electrodes. In the example shown, there are three gate drivers corresponding to the three gate contacts on the first FET device 302. The gate driver is connected to the RDL 306 on the gate controller 301 through a through hole 308. The RDL 306 conductively couples each distributed driver through the through hole 308. A single bus 304 in the device RDL connects the distributed driver to the first gate of the FET 302 through the gate RDL 305. The first FET device gate plated through hole 308 connects the first FET device RDL 305 to the three gate electrodes of the first FET device 302. The first FET source RDL or source metal layer 307 also includes two or more plated through holes that contact the source region of the FET device 302. As shown, there are multiple plated through holes in the first FET device RDL or source metal. Distributed drivers improve the device's ability to withstand failures because it can continue to operate even if one driver fails.

[0063] Similarly, the second FET device 303 includes two sets of gate through holes through the gate insulating layer, exposing the gate electrode of the FET device. The conductive plating of the plated through hole 310 connects the gate RDL 311 to the gate electrode. The second bus 312 formed by the RDL connects the gate electrode to the gate controller 301. The second plated through hole 313 in the gate second gate RDL 314 connects the gate driver to the second gate RDL 314 and the second bus 312. As shown, the second FET device source RDL 309 includes two or more plated through holes, which are in conductive contact with the gate region of the FET device. Here, the first FET device can be a low-side FET and the second FET can be a high-side FET, but aspects of the present disclosure are not limited to this. In some embodiments, the first FET device can be a high-side FET and the second FET device can be a low-side FET. For example, the high-side FET and the low-side FET can be part of a voltage regulator. In addition, in some embodiments, the configuration shown can be extended to multiple phases, where one controller can be connected to multiple low-voltage side and high-voltage side devices. Furthermore, while the illustrated embodiments have two or three gate drivers, aspects of the present disclosure are not so limited, and there may be any number of gate drivers sufficient to control the FET devices.

[0064] Figure 4 A top view of an RDL of a DRMOS device with a distributed gate driver having multiple proportionally distributed gate buses for the gate of each MOSFET is shown according to various aspects of the present disclosure. As shown, three buses 402 are made of RDL material. The three buses can be traces formed by the RDL layer. In an alternative embodiment, the three traces can be lines made of conductive material. The three buses are proportionally distributed between the three gate drivers of the gate controller. The plated through-holes 401 made through the gate controller insulating layer conductively couple the RDL material to the output node of each gate driver of the first FET. In the embodiment shown, each output node of the gate driver is conductively coupled to the RDL material through four plated through-holes 401. The three buses proportionally distribute the connections to three groups of gate electrode through-holes 403 in the RDL. Here, the gate electrodes are connected through three groups of five plated through-holes 403 for the first FET device. Similarly, the gate driver for the second FET device is distributed in proportion to two busses made of RDL material connected to two sets of five gate vias between gate electrodes through a gate insulating layer and to two sets of five electrode driver vias connected through a gate controller insulating layer.

[0065] Figure 5 A top view of an RDL of a DRMOS device with a distributed gate driver having a plurality of proportionally distributed gate busses for gate electrode contact regions located on both top sides of each FET device is shown in accordance with various aspects of the present disclosure. As shown, the gate contact regions are located on a first top edge 503 and a second top edge 504. Plated through holes in the RDL material are in conductive contact with the gate electrodes on the first top edge 503 and the second top edge 504. Two busses 502 made of the RDL material conductively couple the gate electrodes to the gate driver output nodes through plated through holes made of the RDL material 501. The two busses 502 are proportionally distributed to the connections of the two gate contact regions and the two gate drivers, each gate driver being conductively coupled to the busses through six plated through holes.

[0066] Figure 6A top view of an RDL of a DRMOS device with a distributed gate driver having multiple proportionally distributed gate busses for gate electrode contact areas located on both top sides of each FET device including a sense FET, in accordance with various aspects of the present disclosure. Having edge-located contact areas for gate electrodes provides new possibilities for the location of the sense FETs. Typically, the sense FETs are located at the edge of the device for ease of connection. This provides less than ideal sensing because the sense FETs are separated from the rest of the FET device area. As shown, the sense FET source region 603 is located in the middle of the source region, allowing for more precise sensing operations. Two edge contact areas leave the RDL material busses unobstructed. The sense FET source region is connected to the sense FET RDL material through conductive vias. A special sense gate bus 604 made of RDL material connects the sense FET source region to the sense FET node of the gate controller IC 601 through conductive vias 602. Although the illustrated embodiment includes two edge contact regions for the gate electrode material aspects of the present disclosure, it is not limited thereto and the sense FET located in the middle of the source region may be implemented with a single edge contact region, three or more edge contact regions.

[0067] Figure 7 701 is a top view of an RDL of a DRMOS device having a FET device integrated with a gate control and a distributed gate driver having a plurality of proportionally distributed gate buses for gate electrode contact regions located at the top edge of individual FET devices according to various aspects of the present disclosure. As shown, a gate controller 701 includes an integrated FET. The integrated FET may be, for example, but not limited to, a high-side FET. An integrated FET drain RDL 702 may include an RDL having a plated through hole 705 conductively contacting the drain region of an integrated FET 704. The plated through hole 705 may be proportionally distributed on the drain region of the integrated FET. The integrated FET drain RDL 702 may extend to the drain connection node of the DRMOS device. An integrated FET source RDL 703 may be conductively contacted with the source region of the integrated FET 704 through a plated through hole 706. The integrated FET source RDL 703 may also include a plated through hole 707 that passes through the molding material layer to reach the source connection node of the DRMOS device. Additionally, the DRMOS device may include individual FET devices and distributed drivers, similar to those seen in previous embodiments.

[0068] Figure 8A top view of an RDL of a DRMOS device having an integrated trench capacitor in a semiconductor substrate composition according to various aspects of the present disclosure is shown. As shown here, a first FET device 803 includes an on-wafer trench capacitor 802 formed in the substrate composition of the first FET device. In some alternative embodiments, the on-wafer capacitor may be a planar capacitor. The plated through hole 801 may be in conductive contact with the gate electrode material in the gate contact region at the top edge of the substrate composition. The trench capacitor may also be in conductive contact with the gate electrode of the gate of the FET device. The second FET device 804 may also include a trench capacitor 805 similarly coupled to the gate electrode material. The gate electrode material in the contact region is in conductive contact with the trench capacitor. In this way, each distributed gate driver is coupled to a separate trench capacitor through a gate RDL. Various aspects of the present disclosure are not limited to this, and may include, for example, but not limited to, a single trench capacitor structure conductively contacted with each gate driver or a plurality of trench capacitor architectures conductively connected to a single gate driver.

[0069] Fig. 9 A top view of an RDL of a DRMOS device is shown for showing distributed gate drivers in accordance with various aspects of the present disclosure. Here, a gate controller 901 includes a visible gate driver 902 for a first FET device, and a gate driver 903 for a second FET. It can also be seen that each of the gate driver 902 for the first FET device and the gate driver 903 for the second FET device are coupled to their respective FET devices via plated through holes 904. Distributed gate drivers provide redundancy in the event of driver failure, and in embodiments including multiple RDL traces connecting gate electrodes, better distribute energy to the gate electrodes.

[0070] Fig.10 A top view of an RDL of a DRMOS device including a split FET device according to various aspects of the present disclosure is shown. In the illustrated embodiment, the first FET device 1010 includes two separate gate structures of uneven size. The first gate structure 1001 of the first FET device shown here is a larger sized gate used in normal device operation. The size of the gate here refers to the device area occupied by the gate electrode. The second gate structure 1002 of the first FET device is a smaller sized gate that can be used under light load conditions. In some embodiments, the distributed driver for the first FET can be proportionally distributed between the first gate structure 1001 and the second gate structure 1002. Specifically, a larger FET may have a larger distributed driver than a smaller FET. It is shown here that the first gate driver is connected to the first gate structure RDL 1004 through a plated through hole. The second gate driver is connected to the second gate structure RDL 1005 through a plated through hole.

[0071] Similarly, the second FET device 1011 includes two individual gate structures of uneven size. The first gate structure 1006 of the second FET device is a larger sized gate used in normal device operation. The second gate structure 1007 of the first FET device is a smaller sized gate that can be used under light load conditions. The distributed driver of the first FET can also be evenly distributed between the first gate structure 1006 and the second gate structure 1007. Here, it is shown that the first gate driver is connected to the first gate structure RDL 1009 through a plated through hole. The second gate driver is connected to the second gate structure RDL 1008 through a plated through hole. As with the first FET device 1010, the distributed driver of the second FET device 1011 can be proportionally distributed between the first gate structure 1006 and the second gate structure 1007. The larger of the two FETs may have a larger distributed driver than the smaller FET.

[0072] Fig.11A and Fig. 11B A cross-sectional side view of a shielded gate trench (SGT) MOSFET device in a DRMOS implementation is shown in accordance with various aspects of the present disclosure. Fig.11A 1 shows a cross section of the device region below the source region RDL 1101, Fig. 11B The cross-sectional area of ​​the gate contact region below the gate RDL 1106 is shown. As shown, the device includes a substrate composition, which includes a substrate layer 1113 heavily doped with ions of the first conductivity type, a drift region 1118 lightly doped with ions of the first conductivity type formed on top of the substrate layer, and a body region 1112 formed in the drift region and doped with ions of the second conductivity type. The source region 1111 is formed on the upper part of the body region and is heavily doped with ions of the first conductivity type. Here, the substrate composition can be a semiconductor material, such as but not limited to gallium nitride, silicon or silicon carbide.

[0073] The substrate composition includes trenches, and a trench insulating layer 1119 is lined on the surface of each trench. In the illustrated embodiment, the shield electrode 1109 is located on the bottom surface of the trench on the trench insulating layer 1119. The trench insulating layer 1119 extends over the shield electrode 1109. The gate electrode 1105 is located above the shield electrode 1109 on the trench insulating layer 1119. The trench insulating layer 1119 also covers the gate electrode. It should be noted that each source region 1111 is also located near one side of the trench. In addition, although an SGT structure is shown, aspects of the present disclosure are not limited to this, and a trench gate structure can be manufactured by simply excluding the shield electrode. The gate electrode 1105 is connected to the gate contact area through a gate runner 1110, and the gate runner 1110 is electrically contacted to the gate RDL 1106 through a plated through hole 1124 in the molding material layer 1126 to the gate metal layer 1123 and the conductive through hole 1108 in the gate contact area insulating layer 1120, as shown. Fig. 11B The shielding electrode 1109 may be conductively coupled to the source region RDL 1101 (not shown). The RDL via may be formed by laser ablation and may have a diameter of 20 microns or less.

[0074] like Fig. 11B As shown, the gate RDL 1106 extends along the top edge of the substrate composition. The gate RDL 1106 can be formed from the same material as the source region RDL 1101, for example, by conventional metal deposition and patterning techniques.

[0075] The source insulating layer 1102 is located on top of the substrate composition below the source region top metal 1121 and above the source region 1111 and the body region 1112. A through hole 1103 is formed in the source insulating layer, exposing a portion of the source region 1111 and a portion of the body region 1112. In some embodiments, a doped region 1112a of a second conductivity type may exist between two source regions 1111 of a first conductivity type. The doped region 1112a is more heavily doped than the body region 1112. For example, if the body region or P-type and the source region are N-type, the doped region 1112a may be doped P+. Alternatively, a shallow trench P+ contact plug may be formed in the body region to short the N+ and P+ / P bodies on the vertical sides of the shallow trench contact plug.

[0076] A conductive material may plate the through-holes 1104, as shown here, and the conductive material may fill each through-hole. Here, for example but not limited to, the top metal may be aluminum, copper, tungsten, nickel, iron, or any alloy thereof. The conductive vias are in conductive contact with the source region 1111 and the body region 1112 that form an anti-parallel diode. The source top metal 1121 is in conductive contact with the source RDL layer 1101 through the plated RDL via 1122. The RDL vias in the molding material layer 1125 expose the source top metal 1121. The RDL material may plate the sides of the through-holes, and in some embodiments, for example, as shown, the entire RDL via 1122 may be filled. The conductive RDL vias 1122 may be proportionally distributed on the source region top metal and conductively coupled to the source region and body region of the substrate composition.

[0077] like Fig. 11B As shown, the gate contact region insulating layer 1120 covers the top of the substrate composition above the gate contact region. The through hole 1108 that passes through the gate contact region insulating layer 1120 and the trench insulating layer in the gate contact region exposes the gate electrode material that forms the gate runner 1110. The gate RDL 1106 is located on the top of the gate contact region insulating layer 1120. The gate RDL 1106 can plate the gate RDL through hole 1124 and fill each through hole. The conductive gate RDL through hole 1124 can be in conductive contact with the gate metal layer 1123. The gate metal layer 1121 can plate the gate contact through hole 1108 and fill each through hole. The conductive gate through hole is in conductive contact with the gate runner 1110, and the gate runner 1110 is formed in the insulating trench in a similar manner to the gate electrode 1105. A portion of the shielding electrode 1109 can also be formed in the trench together with the gate runner 1110. The RDL through hole can be distributed proportionally on the gate contact region 1110. Here, the gate electrode material and the shield electrode material may be a conductive material such as polysilicon.

[0078] In the illustrated embodiment, substrate layer 1118 acts as a back drain contact region. Drain insulating layer 1114 is formed below the bottom of the substrate composition. A through hole 1116 formed through drain insulating layer 1114 exposes substrate 1118. Drain RDL or metal layer 1115 is located below drain insulating layer 1114. As shown, drain RDL covers through hole 1117 and fills the entire through hole. Here, drain RDL, source RDL and gate RDL can be made of conductive materials, such as but not limited to copper, aluminum, nickel, tungsten, gold, silver or any alloy thereof.

[0079] It should be noted that for embodiments utilizing trench capacitors, e.g. Figure 8As shown in the trench capacitor 805, the trench capacitor can be formed in any combination using the gate electrode 1105 and the shield electrode 1109 to the source terminal or the drain terminal. For example, a trench capacitor can be formed between the top gate electrode 1105 as one end of the capacitor and the source metal as the other end of the capacitor (the shield electrode 1109 is connected to the source terminal).

[0080] Fig. 12A and Fig. 12B 1 shows a cross-sectional side view of a planar gate MOSFET device in a DRMOS embodiment according to various aspects of the present disclosure. Fig. 12A 1 shows a cross section of the device region below the source region RDL 1203, Fig. 12B 1213. The cross-sectional area of ​​the gate contact region below the gate RDL 1213 is shown. In this embodiment, a body region 1207 heavily doped with ions of the second conductivity type is formed in the body region 1208 below the source region RDL 1203. A source region 1209 heavily doped with ions of the first conductivity type is formed in the body region. In some embodiments, a doped region 1207a of the second conductivity type may exist between the two source regions 1209. The doped region 1207a is more heavily doped than the body region 1207. Alternatively, a shallow trench contact plug of the second conductivity type may be formed in the body region, short-circuiting the source region and the body region on the vertical side of the shallow trench contact plug.

[0081] The planar gate electrode 1202 is located on the substrate composition on the planar gate insulating layer 1206. In some embodiments, the planar gate insulating layer can wrap around the planar gate electrode 1202. In another embodiment, the source insulating layer 1215 can insulate the top and sides of the planar gate electrode. A portion of the planar gate electrode overlaps the source region and the body region.

[0082] like Fig. 12B As shown, the planar gate runner 1201 forms an electrical contact between the gate RDL 1213 and the gate electrode 1202. The gate RDL can be located at the top edge of the substrate composition, for example, as shown in FIG. Fig.10 As shown. The gate contact region insulating layer 1215 is located on top of the substrate composition in the planar gate contact region. The gate RDL 1213 extends on the gate contact region isolation layer 1215. The gate via 1204 passing through the gate electrode contact region insulating layer 1215 exposes the gate electrode material forming the planar gate runner 1201. The gate RDL 1213 can plate the gate RDL via 1204 and can fill the entire via to contact the gate top metal layer 1221. The gate metal layer 1221 can plate the gate via 1204 and can file the entire via in contact with the gate electrode material. The RDL vias 1220 can be distributed proportionally on the gate electrode contact area.

[0083] Improved DrMOS devices of the type described herein can be created by distributed contact placement in transistor devices, thereby providing more uniform transistor device switching and a smaller device area. In addition, the use of distributed gate drive in wafer-level or panel-level packaging can also reduce parasitic inductance, reduce device area, and improve robustness by dividing the failure point among multiple drivers. Finally, the use of distributed contact layout and distributed gate drive provides an enhanced DrMOS device with all the advantages mentioned previously.

[0084] While the above is a complete description of the preferred embodiments of the present invention, various alternatives, modifications and equivalents may be used. Therefore, the scope of the present invention should not be determined by reference to the above description, but should be determined by reference to the full scope of the appended claims and their equivalents. Any feature described herein, whether preferred or not, may be combined with any other feature described herein, whether preferred or not. In the following claims, the indefinite article "a" or "an" refers to the quantity of one or more items following the clause, unless otherwise expressly stated. The appended claims should not be interpreted as including means plus function limitations unless such limitation is expressly stated in a given claim using the phrase "meant to be".

Claims

1. A transistor device, comprising: Semiconductor substrate composition; a first gate electrode material disposed on a portion of a surface of the semiconductor substrate composition, wherein the first gate electrode material includes a first gate electrode contact region proximate at least one edge of the substrate composition; A gate insulating material on the first gate electrode material includes two or more first gate through holes passing through the gate insulating material in the first gate electrode contact region, wherein the two or more first gate through holes expose the first gate electrode material.

2. The transistor device of claim 1, further comprising a source region formed in the substrate composition; and A source region insulating material is disposed above the source region, comprising two or more source through holes passing through the source insulating material, wherein the two or more source through holes expose the substrate composition in the source region.

3. The transistor device of claim 1, further comprising a conductive first gate redistribution material conductively coupled to the first gate metal layer, wherein the first gate metal layer at least arranges the two or more first gate vias and conductively couples each first gate via to each other. The transistor device of claim 3 , wherein the first gate redistribution material is connected to an output node of a gate controller. 5 . The transistor device of claim 1 , wherein two or more first gate redistribution layer vias are proportionally distributed on the first gate electrode contact region.

6. The transistor device of claim 2, further comprising a conductive source redistribution material conductively coupled to the source region top metal, lining at least two or more source vias, and conductively coupling each source via.

7. The transistor device of claim 6, wherein the conductive source redistribution material is connected to a source contact node of the transistor device. 8 . The transistor device of claim 2 , wherein two or more source redistribution layer vias are distributed proportionally on the source region.

9. The transistor device of claim 1 further comprising a drain region formed on the back side of the substrate composition and a drain insulating material above the back side drain region, the drain region comprising two or more vias passing through the drain insulating material for connecting to a drain metal or a drain redistribution layer.

10. The transistor device of claim 1, further comprising a second gate electrode on a surface of the substrate composition, and wherein the gate insulating material further comprises two or more second gate vias exposing the second gate electrode for connection.

11. The transistor device of claim 2 further comprises a sense FET source region formed in the substrate composition, wherein the source region insulating material comprises at least one through-hole passing through the source region insulating material, the through-hole being located above the source region of the sense FET to expose the source region of the sense FET for connection.

12. The transistor device of claim 11, further comprising a sense FET source redistribution material conductively coupling a source region of the sense FET to a sense FET node of the gate controller.

13. The transistor device of claim 11, wherein the sense FET gate is located at the center of the source region.

14. The transistor device of claim 1, wherein a via diameter from the redistribution layer to the gate metal layer in conductive contact with the first gate electrode material is 20 microns or less.

15. The transistor device of claim 1, further comprising an on-wafer capacitor formed in the substrate composition, wherein the on-wafer capacitor connects the gate electrode to the first gate electrode contact region.

16. The transistor device of claim 1, wherein the first gate electrode material is formed in a trench in the substrate composition.

17. The transistor device of claim 16, wherein at least a portion of the first gate electrode material is formed on a conductive shield electrode in a trench of the substrate composition.

18. The transistor device of claim 1, wherein the first gate electrode material is part of a planar gate structure on a surface of the substrate composition.

19. A distributed driver package, comprising: a first transistor device having two or more first gate vias on a first top edge portion of the first transistor device electrically connected to a first gate electrode material; a gate controller integrated circuit comprising a first gate driver output node; and A first gate conductive redistribution material conductively couples the first gate electrode material of the first transistor device to the first gate driver output node through two or more first gate vias.

20. The distributed drive package of claim 19 further comprises a second transistor device having two or more second gate through holes along a top edge of the second transistor device, exposing a second gate electrode material and a second gate conductive redistribution material, wherein the second gate conductive redistribution material conductively couples the second gate electrode material to a second gate output node of the gate controller integrated circuit.

21. The distributed drive package of claim 20, wherein the first transistor device is a low-side field effect transistor for a voltage regulator, and the second transistor is a high-side field effect transistor.

22. The distributed drive package of claim 19, wherein the first gate redistribution material comprises two or more connections between the first gate driver output node and the first gate metal layer through two or more redistribution layer vias to the first gate electrode material.

23. The distributed drive package of claim 22, wherein the two or more connections are proportionally distributed between two or more redistribution layer vias.

24. The distributed drive package of claim 22, wherein the two or more connections are each formed between two or more first gate driver output nodes on the first gate driver integrated circuit and the first gate electrode material.

25. The distributed drive package of claim 19, wherein the first gate conductive redistribution material comprises a metal line connected to the first gate driver output node and conductively coupled to the first gate electrode material.

26. The distributed drive package of claim 19, wherein the first gate conductive redistribution material comprises one or more conductive traces conductively coupled to the first gate driver output node and conductively coupled to the first gate electrode material.

27. The distributed drive package of claim 19, wherein the first transistor device comprises two or more additional first gate through holes on a second top edge portion thereof, and the first gate conductive redistribution material also conductively couples the first gate electrode material of the first transistor device to the first gate driver output node of the gate controller integrated circuit through two or more additional first gate through holes on the second top boundary portion of the substrate composition.

28. The distributed drive package of claim 19, wherein the gate controller integrated circuit includes a second gate driver output node, and wherein the first transistor device includes two or more second gate vias on a second top edge portion of the first crystal device, and wherein a second gate conductive redistribution layer conductively couples a third gate electrode material of the first semiconductor device to the second gate drive output node through the two or more second gate vias on a second bottom edge portion of the substrate composition.

29. The distributed drive package of claim 27, wherein the two or more second gate vias are distributed proportionally on the second gate electrode contact area.

30. The distributed drive package of claim 19, wherein the first transistor device comprises at least one on-die capacitor.

31. The distributed drive package of claim 19, wherein the gate controller integrated circuit is a monolithic integrated circuit including a second transistor device.

32. The distributed drive package of claim 19, wherein the first transistor device comprises a sense FET and a sense FET redistribution material between the sense FET and a sense FET node on the gate controller integrated circuit.

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