Preparation method of diamond CMOS inverter and inverter

Abstract

The application provides a preparation method of a diamond CMOS inverter and the inverter, and relates to the technical field of super-wide band gap semiconductor field effect transistor devices. The method comprises the following steps: introducing boron elements and nitrogen elements into a microwave plasma chemical vapor deposition chamber through a gaseous source or a solid source, so as to grow an n-type diamond epitaxy on a diamond substrate layer; treating the diamond substrate after depositing a metal mask by using hydrogen plasma, so as to prepare a p-type active region on a second n-type diamond epitaxy, and the first n-type diamond epitaxy becomes an n-type active region; and preparing a source electrode, a drain electrode, an NMOS field effect tube gate dielectric layer, a PMOS field effect tube gate dielectric layer and a gate electrode on the p-type active region and the n-type active region. In this way, the hydrogen-terminated diamond preparation process and the diamond boron-nitrogen co-doping process are used to simultaneously form the p-type active region and the n-type active region on a single monocrystalline diamond surface, so that the preparation of the CMOS inverter on the single diamond is realized.

Description

Technical Field

[0001] This invention relates to the field of ultra-wide bandgap semiconductor field-effect transistor technology, and in particular to a method for fabricating a diamond complementary metal oxide semiconductor (CMOS) inverter and the inverter itself. Background Technology

[0002] Diamond is a representative of ultra-wide bandgap semiconductor materials, possessing a high breakdown electric field, high thermal conductivity, and excellent physicochemical stability, earning it the reputation of being the ultimate semiconductor material. The ideal electron mobility of diamond is 4500 cm⁻¹. 2 / Vs, ideal hole mobility is 3800cm 2 / Vs, and its saturation rate is as high as 3×10 7 The speed of cm / s indicates that diamond devices have ideal application prospects in the field of high-speed switching devices. The excellent electrical properties of diamond material determine the application potential of diamond devices, while the fabrication process of the active region of diamond determines the degree of application development of this material. In logic circuits, CMOS inverters are the most basic logic units, and fabricating CMOS inverters on a single material is one of the important research goals of ultra-wide bandgap semiconductor materials. However, for ultra-wide bandgap semiconductors like diamond, it is difficult to simultaneously achieve stable p-type and n-type conductances, which has become a major obstacle to the fabrication of CMOS devices.

[0003] Currently, traditional doping impurities are used for diamond n-type conductivity. However, since traditional doping impurities are difficult to activate effectively in diamond, it is difficult to form effective n-type conductivity at room temperature, making the feasibility of diamond n-type conductivity low. The commonly used doping elements in diamond doping processes are P and N. Since diamond doping processes are basically achieved during diamond growth, it is not possible to selectively grow specific doped diamond materials, making it difficult to integrate n-type diamond field-effect transistors and p-type diamond field-effect transistors on a single chip. Summary of the Invention

[0004] The purpose of this invention is to provide a method for fabricating a diamond CMOS inverter and the inverter itself, thereby addressing the issues of low feasibility of diamond n-type conductivity and the difficulty in monolithic integration of n-type and p-type diamond field-effect transistors.

[0005] To address the aforementioned technical problems, the embodiments of the present invention provide the following technical solutions:

[0006] The first aspect of this invention provides a method for fabricating a diamond CMOS inverter, comprising:

[0007] Select a diamond substrate;

[0008] Place the diamond substrate into a microwave plasma chemical vapor deposition system;

[0009] Boron precursor and nitrogen precursor are introduced into the microwave plasma chemical vapor deposition chamber using a gaseous source or a solid source to grow n-type diamond epitaxial layer on diamond substrate. The n-type diamond epitaxial layer includes a first n-type diamond epitaxial layer and a second n-type diamond epitaxial layer, which are adjacent to each other and located on the same horizontal plane.

[0010] Deposit a metal mask on the first n-type diamond epitaxy;

[0011] A diamond substrate after depositing a metal mask is treated with hydrogen plasma to prepare a diamond hydrogen terminal on a second n-type diamond epitaxy, and the diamond hydrogen terminal is used as a p-type active region. The first n-type diamond epitaxy is prepared as a nitrogen-boron co-doped diamond epitaxial layer, and the nitrogen-boron co-doped diamond epitaxial layer is used as an n-type active region.

[0012] Source electrode, drain electrode, NMOS field-effect transistor gate dielectric layer, PMOS field-effect transistor gate dielectric layer and gate electrode are sequentially fabricated on the p-type active region and n-type active region.

[0013] In some embodiments, the method further includes, prior to placing the diamond substrate into the microwave plasma chemical vapor deposition system:

[0014] The diamond substrate was sequentially cleaned in a strong acid mixture at 200°C, acetone, ethanol, and deionized water.

[0015] In some embodiments, a source electrode, a drain electrode, an NMOS field-effect transistor gate dielectric layer, a PMOS field-effect transistor gate dielectric layer, and a gate electrode are sequentially fabricated on a p-type active region and an n-type active region, including:

[0016] Source and drain electrodes arranged at intervals are fabricated on the upper surfaces of the p-type and n-type active regions.

[0017] An NMOS field-effect transistor gate dielectric layer is fabricated on the upper surface of the p-type active region and between the source and drain electrodes.

[0018] A PMOS field-effect transistor gate dielectric layer is fabricated on the upper surface of the n-type active region and between the drain electrode and the source electrode.

[0019] Gate electrodes are fabricated on the upper surface of the gate dielectric layer of the NMOS field-effect transistor and the upper surface of the gate dielectric layer of the PMOS field-effect transistor, respectively.

[0020] In some embodiments, the source electrode and the drain electrode are made of one or more of Ti, Au, and Pt.

[0021] In some embodiments, the gate dielectric layer of the NMOS field-effect transistor and the gate dielectric layer of the PMOS field-effect transistor are made of one or more of SiO2, Al2O3, MoO3, HfO2, HfAlO2, BaF2, and MgF2.

[0022] In some embodiments, the gate electrode is made of one or more of Al and Au.

[0023] In some embodiments, the thickness of the nitrogen-boron co-doped diamond epitaxial layer is 50-80 nm.

[0024] In some embodiments, the thickness of the source electrode, drain electrode, and gate electrode is 100-200 nm.

[0025] In some embodiments, the thickness of the gate dielectric layer of the NMOS field-effect transistor and the gate dielectric layer of the PMOS field-effect transistor are both 20-50 nm.

[0026] A second aspect of the present invention provides a diamond CMOS inverter, comprising:

[0027] Diamond substrate;

[0028] A nitrogen-boron co-doped diamond epitaxial layer is formed on one edge region of a diamond substrate;

[0029] A diamond hydrogen-terminated layer is formed on the edge region of the diamond substrate layer, and the diamond hydrogen-terminated layer and the nitrogen-boron co-doped diamond epitaxial layer are arranged alternately.

[0030] The source electrodes are formed on the edge region of the nitrogen-boron co-doped diamond epitaxial layer away from the diamond hydrogen terminal layer, and on the edge region of the diamond hydrogen terminal layer away from the nitrogen-boron co-doped diamond epitaxial layer, respectively. The source electrode on the edge region of the nitrogen-boron co-doped diamond epitaxial layer is connected to GND, and the source electrode on the edge region of the diamond hydrogen terminal layer is connected to VDD.

[0031] Drain electrodes are formed on the edge region of the nitrogen-boron co-doped diamond epitaxial layer near the diamond hydrogen terminal layer and on the edge region of the diamond hydrogen terminal layer near the nitrogen-boron co-doped diamond epitaxial layer, respectively. The two drain electrodes are connected and serve as the output terminals of the diamond CMOS inverter.

[0032] The gate dielectric layer of the NMOS field-effect transistor is formed on the upper surface of the nitrogen-boron co-doped diamond epitaxial layer and is located between the drain electrode and the source electrode.

[0033] The gate dielectric layer of the PMOS field-effect transistor is formed on the upper surface of the diamond hydrogen terminal layer and is located between the source electrode and the drain electrode.

[0034] Gate electrodes are formed on the upper surfaces of the gate dielectric layer of the NMOS field-effect transistor and the gate dielectric layer of the PMOS field-effect transistor, respectively. The two gate electrodes are connected and serve as the input terminals of the diamond CMOS inverter.

[0035] Compared to existing technologies, this invention provides a method for fabricating a diamond CMOS inverter and the inverter itself. The method involves selecting a diamond substrate; placing the diamond substrate in a microwave plasma chemical vapor deposition (PCCVD) system; introducing boron and nitrogen precursors into the PCCVD chamber using a gaseous or solid-state source to grow an n-type diamond epitaxial layer on the diamond substrate; depositing a metal mask on the first n-type diamond epitaxial layer; treating the diamond substrate after metal mask deposition with hydrogen plasma to prepare a diamond hydrogen terminal on the second n-type diamond epitaxial layer, using the diamond hydrogen terminal as the p-type active region; fabricating the first n-type diamond epitaxial layer as a nitrogen-boron co-doped diamond epitaxial layer, using the nitrogen-boron co-doped diamond epitaxial layer as the n-type active region; and sequentially fabricating a source electrode, a drain electrode, an NMOS field-effect transistor gate dielectric layer, a PMOS field-effect transistor gate dielectric layer, and a gate electrode on the p-type and n-type active regions. In this way, the n-type conductivity of diamond is achieved by using boron-nitrogen co-doping, and p-type and n-type active regions are simultaneously formed on the surface of a single crystal diamond through hydrogen-terminated diamond preparation process and diamond boron-nitrogen co-doping process, thus realizing the fabrication of diamond CMOS inverter. Attached Figure Description

[0036] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the invention are illustrated by way of example and not limitation, with the same or corresponding reference numerals denoteing the same or corresponding parts, wherein:

[0037] Figure 1 A schematic flowchart illustrating the fabrication method of a diamond CMOS inverter is shown.

[0038] Figure 2 A schematic diagram illustrating the fabrication process of a diamond CMOS inverter is shown.

[0039] Figure 3 A schematic diagram of the structure of a diamond CMOS inverter is shown.

[0040] Figure 4 A schematic top view of a diamond CMOS inverter is shown.

[0041] Figure 5 Hall effect test results for the n-type conductivity region of a diamond CMOS inverter are schematically shown.

[0042] Figure 6 The Hall effect test results for the p-type conductivity region of a diamond CMOS inverter are schematically shown.

[0043] Explanation of reference numerals in the attached figures:

[0044] 1. Diamond substrate; 2. Nitrogen-boron co-doped diamond epitaxial layer; 3. Diamond hydrogen termination layer; 4. Source electrode; 5. Drain electrode; 6. NMOS field-effect transistor gate dielectric layer; 7. PMOS field-effect transistor gate dielectric layer; 8. Gate electrode. Detailed Implementation

[0045] The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to illustrate the principles of the present invention by way of example, but should not be used to limit the scope of the present invention. The present invention can be implemented in many different forms and is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

[0046] The following is a detailed description of a method for fabricating a diamond CMOS inverter according to an embodiment of the present invention.

[0047] See Figure 1 As shown, Figure 1 A flowchart illustrating a method for fabricating a diamond CMOS inverter is shown. This invention provides a method for fabricating a diamond CMOS inverter, comprising:

[0048] S101. Select diamond substrate layer 1.

[0049] The selected diamond substrate layer 1 is an intrinsic diamond substrate epitaxially generated by chemical vapor deposition (CVD).

[0050] The material of the diamond substrate 1 includes, but is not limited to, single-crystal diamond, with a thickness of 100-1000 μm.

[0051] S102. Place the diamond substrate 1 into a microwave plasma chemical vapor deposition system.

[0052] Before placing the diamond substrate 1 into the microwave plasma chemical vapor deposition system, the method further includes:

[0053] The diamond substrate 1 was sequentially cleaned at 200°C in a strong acid mixture, acetone, ethanol, and deionized water.

[0054] A strong acid mixture solution can be H2SO4:HNO3.

[0055] Figure 2A schematic diagram illustrating the fabrication process of a diamond CMOS inverter is shown, wherein... Figure 2 (a) is a schematic diagram of the diamond substrate 1 after cleaning and drying. See [reference needed] Figure 2 As shown in (a), after cleaning the diamond substrate 1, the cleaned diamond substrate 1 is dried with a nitrogen gun for later use.

[0056] The diamond substrate 1 was placed in a microwave plasma chemical vapor deposition system for pretreatment with hydrogen plasma etching.

[0057] S103. Boron precursor and nitrogen precursor are introduced into the microwave plasma chemical vapor deposition chamber through a gaseous source or a solid source to grow n-type diamond epitaxy on the diamond substrate 1.

[0058] The n-type diamond epitaxial layer includes a first n-type diamond epitaxial layer and a second n-type diamond epitaxial layer, which are adjacent to each other and located on the same horizontal plane.

[0059] The first n-type diamond epitaxial layer is the n-type diamond epitaxial layer on the left, and the second n-type diamond epitaxial layer is the n-type diamond epitaxial layer on the right.

[0060] Specifically, Figure 2 (b) is a schematic diagram of the growth of n-type diamond epitaxy, see [reference]. Figure 2 As shown in (b), boron and nitrogen precursors are simultaneously introduced into the microwave plasma chemical vapor deposition (MPCVD) chamber through a gaseous or solid source to provide the boron and nitrogen sources required for the growth of nitrogen-boron co-doped diamond epitaxy. At the same time, the growth temperature, microwave power and growth pressure are controlled to achieve the growth of n-type diamond epitaxy.

[0061] S104. Deposit a metal mask on the first n-type diamond epitaxy.

[0062] Specifically, Figure 2 (c) is a schematic diagram of the deposition of a metal mask. A metal mask is deposited on the first n-type diamond epitaxial layer. The metal mask protects the first n-type diamond epitaxial layer while exposing the diamond region requiring hydrogenation treatment, i.e., the second n-type diamond epitaxial layer. The metal mask can be Mo, W, etc.; in this embodiment, W is used as the metal mask.

[0063] S105. The diamond substrate after the metal mask is deposited is treated with hydrogen plasma to prepare a diamond hydrogen terminal on the second n-type diamond epitaxy and the diamond hydrogen terminal is used as a p-type active region. The first n-type diamond epitaxy is prepared as a nitrogen-boron co-doped diamond epitaxial layer 2 and the nitrogen-boron co-doped diamond epitaxial layer 2 is used as an n-type active region.

[0064] Specifically, Figure 2 (d) Schematic diagram of the formation of p-type and n-type active regions. A diamond substrate with a deposited metal mask is placed in an MPCVD system. Hydrogen plasma is used to treat the diamond substrate after the metal mask deposition to prepare diamond hydrogen terminals on the second n-type diamond epitaxial layer (the region without metal mask protection). These diamond hydrogen terminals serve as the p-type active region. The n-type diamond epitaxial layer under the first n-type diamond epitaxial layer (the region protected by the metal mask 2) becomes nitrogen-boron co-doped diamond epitaxial layer 2, which serves as the n-type active region. Thus, both p-type and n-type active regions are simultaneously realized on a single diamond wafer.

[0065] Figure 2 (e) is a schematic diagram of washing away the metal mask. After step S105, the metal mask is washed away to obtain a diamond substrate that has both n-type and p-type active regions.

[0066] The thickness of the nitrogen-boron co-doped diamond epitaxial layer 2 is 50-80 nm.

[0067] S106. Source electrode 4, drain electrode 5, NMOS field-effect transistor gate dielectric layer 6, PMOS field-effect transistor gate dielectric layer 7 and gate electrode 8 are sequentially fabricated on the p-type active region and n-type active region.

[0068] Specifically, source electrode 4, drain electrode 5, NMOS field-effect transistor gate dielectric layer 6, PMOS field-effect transistor gate dielectric layer 7, and gate electrode 8 are sequentially fabricated on the p-type active region and n-type active region, including:

[0069] Step A1: On the upper surfaces of the p-type active region and the n-type active region, source electrodes 4 and drain electrodes 5 are arranged at intervals.

[0070] Specifically, Figure 2 (f) is a schematic diagram of the fabrication of source electrode 4 and drain electrode 5. Source electrode 4 is fabricated on the edge region of the p-type active region away from the n-type active region, source electrode 4 is fabricated on the edge region of the n-type active region away from the p-type active region, and drain electrode 5 is fabricated in the adjacent region of the p-type active region and the n-type active region.

[0071] The source electrode 4 and drain electrode 5 are made of one or more of Ti, Au, and Pt. The thickness of the source electrode 4, drain electrode 5, and gate electrode 8 is 100-200 nm.

[0072] Step A2: Fabricate the NMOS field-effect transistor gate dielectric layer 6 on the upper surface of the p-type active region and between the source electrode 4 and the drain electrode 5.

[0073] Step A3: Fabricate the PMOS field-effect transistor gate dielectric layer 7 on the upper surface of the n-type active region and between the drain electrode 5 and the source electrode 4.

[0074] Figure 2 (g) is a schematic diagram of the fabrication of NMOS field-effect transistor gate dielectric layer 6 and PMOS field-effect transistor gate dielectric layer 7. NMOS field-effect transistor gate dielectric layer 6 is fabricated on the upper surface of the p-type active region between the source electrode 4 and the drain electrode 5, and PMOS field-effect transistor gate dielectric layer 7 is fabricated on the upper surface of the n-type active region between the drain electrode 5 and the source electrode 4.

[0075] The gate dielectric layer 6 of the NMOS field-effect transistor and the gate dielectric layer 7 of the PMOS field-effect transistor are both made of one or more of the following materials: SiO2, Al2O3, MoO3, HfO2, HfAlO2, BaF2, and MgF2. The thickness of both the gate dielectric layer 6 of the NMOS field-effect transistor and the gate dielectric layer 7 of the PMOS field-effect transistor is 20-50 nm.

[0076] Step A4: Prepare gate electrodes 8 on the upper surface of the gate dielectric layer 6 of the NMOS field-effect transistor and the upper surface of the gate dielectric layer 7 of the PMOS field-effect transistor, respectively.

[0077] Figure 2 (h) is a schematic diagram of the fabrication of the gate electrode 8. The gate electrode 8 is fabricated on the upper surface of the gate dielectric layer 6 of the NMOS field-effect transistor and on the upper surface of the gate dielectric layer 7 of the PMOS field-effect transistor.

[0078] The gate electrode 8 is made of one or more of Al and Au.

[0079] Based on the above Figure 1As can be seen from the implementation method, the embodiment of the present invention selects a diamond substrate layer 1; places the diamond substrate layer 1 into a microwave plasma chemical vapor deposition system; introduces boron and nitrogen precursors into the microwave plasma chemical vapor deposition chamber through a gaseous or solid source to grow an n-type diamond epitaxial layer on the diamond substrate layer 1; deposits a metal mask on the first n-type diamond epitaxial layer; treats the diamond substrate after depositing the metal mask with hydrogen plasma to prepare a diamond hydrogen terminal on the second n-type diamond epitaxial layer, and uses the diamond hydrogen terminal as a p-type active region; the first n-type diamond epitaxial layer is prepared as a nitrogen-boron co-doped diamond epitaxial layer 2, and the nitrogen-boron co-doped diamond epitaxial layer 2 is used as an n-type active region; and sequentially prepares a source electrode 4, a drain electrode 5, an NMOS field-effect transistor gate dielectric layer 6, a PMOS field-effect transistor gate dielectric layer 7, and a gate electrode 8 on the p-type active region and the n-type active region. In this way, the n-type conductivity of diamond is achieved by using boron-nitrogen co-doping, and p-type and n-type active regions are simultaneously formed on the surface of a single crystal diamond through hydrogen-terminated diamond preparation process and diamond boron-nitrogen co-doping process, thus realizing the fabrication of diamond CMOS inverter.

[0080] Based on the same inventive concept, as an implementation of the above-mentioned method for fabricating a diamond CMOS inverter, this embodiment of the invention also provides a diamond CMOS inverter. Figure 3 This is a schematic diagram of the diamond CMOS inverter in an embodiment of the present invention. Figure 4 A schematic top view of a diamond CMOS inverter is shown; see [link / reference]. Figure 3 and Figure 4 As shown, the diamond CMOS inverter may include:

[0081] Diamond substrate 1;

[0082] A nitrogen-boron co-doped diamond epitaxial layer 2 is formed on one side edge region of the diamond substrate layer 1;

[0083] A diamond hydrogen terminal layer 3 is formed on the edge region of the diamond substrate layer 1 on the other side, and the diamond hydrogen terminal layer 3 and the nitrogen-boron co-doped diamond epitaxial layer 2 are arranged alternately.

[0084] Source electrodes 4 are formed on the edge region of the nitrogen-boron co-doped diamond epitaxial layer 2 away from the diamond hydrogen terminal layer 3, and on the edge region of the diamond hydrogen terminal layer 3 away from the nitrogen-boron co-doped diamond epitaxial layer 2, respectively. The source electrode 4 on the edge region of the nitrogen-boron co-doped diamond epitaxial layer 2 is connected to GND, and the source electrode 4 on the edge region of the diamond hydrogen terminal layer 3 is connected to VDD.

[0085] Drain electrodes 5 are formed on the edge region of the nitrogen-boron co-doped diamond epitaxial layer 2 near the diamond hydrogen terminal layer 3 and on the edge region of the diamond hydrogen terminal layer 3 near the nitrogen-boron co-doped diamond epitaxial layer 2, respectively. The two drain electrodes 5 are connected and serve as the output terminals of the diamond CMOS inverter.

[0086] The gate dielectric layer 6 of the NMOS field-effect transistor is formed on the upper surface of the nitrogen-boron co-doped diamond epitaxial layer 2 and is located between the drain electrode 5 and the source electrode 4.

[0087] The gate dielectric layer 7 of the PMOS field-effect transistor is formed on the upper surface of the diamond hydrogen terminal layer 3 and is located between the source electrode 4 and the drain electrode 5.

[0088] Gate electrodes 8 are formed on the upper surfaces of the gate dielectric layer 6 of the NMOS field-effect transistor and the gate dielectric layer 7 of the PMOS field-effect transistor, respectively. The two gate electrodes 8 are connected and serve as the input terminals of the diamond CMOS inverter.

[0089] Specifically, the diamond substrate 1 is made of materials including, but not limited to, single-crystal diamond, with a thickness of 100-1000 μm. The nitrogen-boron co-doped diamond epitaxial layer 2 has a thickness of 50-80 nm, and the diamond hydrogen termination layer 3 is on the diamond surface with negligible thickness. The source electrode 4 and drain electrode 5 are made of one or more of Ti, Au, and Pt, with a thickness of 100-200 nm. For example, the source electrode 4 and drain electrode 5 are made of Ti / Au, with a thickness of 20 / 100 nm. The NMOS field-effect transistor gate dielectric layer 6 and the PMOS field-effect transistor gate dielectric layer 7 are made of one or more of SiO2, Al2O3, MoO3, HfO2, HfAlO2, BaF2, and MgF2, with a thickness of 20-50 nm. For example, the NMOS field-effect transistor gate dielectric layer 6 is 20 nm thick Al2O3, and the PMOS field-effect transistor gate dielectric layer 7 is 20 nm thick BaF2. The gate electrode 8 is made of one or more of Al and Au, and has a thickness of 100-200 nm.

[0090] Figure 5 The Hall effect test results for the n-type conductivity region of a diamond CMOS inverter are schematically shown. Figure 5 The test results show that the majority carriers in the n-type diamond region are electrons (Ns: -7.861e+14), and the sheet resistance of the material is 3490 ohm / sq. Figure 6 The Hall effect test results of the p-type conductivity region of the diamond CMOS inverter are schematically shown. The test results show that the majority carriers in the n-type diamond region are holes (Ns: +1.266e+13), and the sheet resistance of the material is 8063 ohm / sq. Figure 5 and Figure 6The test results show that the method for fabricating the diamond CMOS inverter of the present invention can realize the fabrication of n-type active regions and p-type active regions with low sheet resistance on diamond substrates.

[0091] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0092] 1. Effectively improves the feasibility of achieving n-type conductivity in diamond. The method for fabricating a diamond CMOS inverter provided by this invention uses boron and nitrogen co-doping to epitaxially grow a diamond layer with n-type conductivity on the surface of a diamond substrate layer 1. Compared with traditional doping methods for achieving n-type conductivity in diamond, this method is more feasible, has lower temperature requirements for sample operation, and can form diamond materials with n-type conductivity at room temperature.

[0093] 2. Effectively reduces process difficulty. The method for fabricating diamond CMOS inverters provided by this invention can simultaneously fabricate p-type and n-type active regions on a single diamond substrate without using ion implantation. This effectively avoids the difficulty of selectively doping diamond materials like silicon semiconductors, thereby advancing the research of diamond CMOS devices;

[0094] 3. This invention achieves n-type bulk conductivity in diamond through boron-nitrogen co-doping, and based on this, combines hydrogen-terminated diamond fabrication processes to fabricate diamond CMOS devices. This invention simultaneously solves two key challenges: the fabrication of n-type conductivity in diamond and the integration of n-type and p-type field-effect transistors on a monolithic diamond substrate, thus significantly advancing the application of diamond CMOS devices.

[0095] While specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and are not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of the invention. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any manner.

[0096] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method of fabricating a diamond CMOS inverter, comprising: The method comprises the following steps: selecting a diamond substrate layer; putting the diamond substrate layer into a microwave plasma chemical vapor deposition system; introducing a boron element precursor and a nitrogen element precursor into the microwave plasma chemical vapor deposition chamber through a gaseous source or a solid source to grow an n-type diamond epitaxial layer on the diamond substrate layer, the n-type diamond epitaxial layer comprising a first n-type diamond epitaxial layer and a second n-type diamond epitaxial layer, the first n-type diamond epitaxial layer and the second n-type diamond epitaxial layer being adjacent and located on the same horizontal plane; depositing a metal mask on the first n-type diamond epitaxial layer; processing the diamond substrate after the deposition of the metal mask by using a hydrogen plasma to prepare a diamond hydrogen termination on the second n-type diamond epitaxial layer, and taking the diamond hydrogen termination as a p-type active region, the first n-type diamond epitaxial layer being prepared as a nitrogen-boron co-doped diamond epitaxial layer and taking the nitrogen-boron co-doped diamond epitaxial layer as an n-type active region; sequentially preparing a source electrode, a drain electrode, an NMOS field effect transistor gate dielectric layer, a PMOS field effect transistor gate dielectric layer and a gate electrode on the p-type active region and the n-type active region.

2. The method of claim 1, wherein the diamond CMOS inverter is prepared by the steps of: Before putting the diamond substrate layer into the microwave plasma chemical vapor deposition system, the method further comprises the following steps: cleaning the diamond substrate layer in a strong acid mixed solution, acetone, ethanol and deionized water at 200℃ in sequence.

3. The method of claim 1, wherein the diamond CMOS inverter is prepared by the steps of: The step of sequentially preparing a source electrode, a drain electrode, an NMOS field effect transistor gate dielectric layer, a PMOS field effect transistor gate dielectric layer and a gate electrode on the p-type active region and the n-type active region comprises the following steps: preparing the source electrode and the drain electrode arranged at intervals on the upper surface of the p-type active region and the n-type active region; preparing the NMOS field effect transistor gate dielectric layer on the upper surface of the p-type active region and between the source electrode and the drain electrode; preparing the PMOS field effect transistor gate dielectric layer on the upper surface of the n-type active region and between the drain electrode and the source electrode; preparing the gate electrode on the upper surface of the NMOS field effect transistor gate dielectric layer and the upper surface of the PMOS field effect transistor gate dielectric layer, respectively.

4. The method of claim 1, wherein the diamond CMOS inverter is prepared by the steps of: The material of the source electrode and the drain electrode is one or more of Ti, Au and Pt.

5. The method of claim 1, wherein the diamond CMOS inverter is prepared by the steps of: The material of the NMOS field effect transistor gate dielectric layer and the PMOS field effect transistor gate dielectric layer is one or more of SiO2, Al2O3, MoO3, HfO2, HfAlO2, BaF2 and MgF2.

6. The method of claim 1, wherein the diamond CMOS inverter is prepared by the steps of: The material of the gate electrode is one or more of Al and Au.

7. The method of claim 1, wherein the diamond CMOS inverter is prepared by the steps of: The thickness of the nitrogen-boron co-doped diamond epitaxial layer is 50-80 nm.

8. The method of claim 1, wherein the diamond CMOS inverter is prepared by the steps of: The thickness of the source electrode, the drain electrode and the gate electrode is 100-200 nm.

9. The method of claim 1, wherein, The thickness of the NMOS field effect transistor gate dielectric layer and the PMOS field effect transistor gate dielectric layer is 20-50 nm.

10. A diamond CMOS inverter, characterized by, The preparation method of the diamond CMOS inverter of any one of claims 1-9 comprises the following steps: a diamond substrate layer; a nitrogen-boron co-doped diamond epitaxial layer formed on one side edge region of the diamond substrate layer; a diamond hydrogen-terminated layer formed on another side edge region of the diamond substrate layer, and the diamond hydrogen-terminated layer and the nitrogen-boron co-doped diamond epitaxial layer are arranged at intervals; a source electrode formed on a side edge region of the nitrogen-boron co-doped diamond epitaxial layer away from the diamond hydrogen-terminated layer and a side edge region of the diamond hydrogen-terminated layer away from the nitrogen-boron co-doped diamond epitaxial layer, respectively, the source electrode on the side edge region of the nitrogen-boron co-doped diamond epitaxial layer is connected to GND, and the source electrode on the side edge region of the diamond hydrogen-terminated layer is connected to VDD; a drain electrode formed on another side edge region of the nitrogen-boron co-doped diamond epitaxial layer close to the diamond hydrogen-terminated layer and another side edge region of the diamond hydrogen-terminated layer close to the nitrogen-boron co-doped diamond epitaxial layer, respectively, wherein the two drain electrodes are connected, and the connected two drain electrodes serve as an output terminal of the diamond CMOS inverter; an NMOS field effect tube gate dielectric layer formed on an upper surface of the nitrogen-boron co-doped diamond epitaxial layer and located between the drain electrode and the source electrode; a PMOS field effect tube gate dielectric layer formed on an upper surface of the diamond hydrogen-terminated layer and located between the source electrode and the drain electrode; a gate electrode formed on an upper surface of the NMOS field effect tube gate dielectric layer and the PMOS field effect tube gate dielectric layer, respectively, wherein the two gate electrodes are connected, and the connected two gate electrodes serve as an input terminal of the diamond CMOS inverter.

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