Method and structure for integrating CMOS and self-aligned silicon germanium HBT

Abstract

The present invention discloses a method and structure for integrating CMOS and self-aligned silicon-germanium (SGe) HBTs. The method comprises: forming multiple shallow trench isolation regions on a silicon substrate; forming polysilicon gates, gate silicon oxide, and lightly doped regions in the CMOS active region; opening a base window in the HBT region and forming a selective ion implantation region; forming a SiGe base region; forming a sacrificial emitter region; etching to expose the surface of the outer region of the SiGe base region and forming an extrinsic base region; forming an emitter window and exposing the SiGe surface of the underlying SiGe base region; forming a silicon emitter region in the emitter window, and photolithographically patterning the emitter region and the extrinsic base region. The present invention utilizes a novel sacrificial emitter process, combined with a method for self-aligning the raised extrinsic base region and the emitter region, effectively reducing process complexity and making the device process compatible with standard CMOS and other passive device processes.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuits, and in particular relates to a method and structure for integrating CMOS and self-aligned silicon germanium HBT. Background Art

[0002] SiGe HBT (silicon-germanium HBT) devices are widely used in wireless communications due to their high frequency, low noise, and large gain-early voltage product. The SiGe BiCMOS process, formed by integrating HBT devices with standard CMOS processes, plays a significant role in analog RF applications. The SiGe BiCMOS process integrates HBT devices, MOSFETs, and other passive components simultaneously, sharing a common thermal budget across all devices. Therefore, the ability to form diverse devices and integrate a wider variety of devices with diverse structures is a key indicator of the process's completeness and scalability. Summary of the Invention

[0003] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a method and structure for integrating CMOS and self-aligned silicon germanium HBT.

[0004] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0005] A method for integrating CMOS and self-aligned silicon germanium HBT, comprising the following steps:

[0006] S1. Etching a plurality of shallow trenches on a silicon substrate by photolithography, and filling each shallow trench with oxide to form a plurality of shallow trench isolation regions, wherein the plurality of shallow trench isolation regions separate the upper portion of the silicon substrate into a CMOS region and an HBT region, and further separate the CMOS region into a CMOS active region and a substrate contact region, and separate the HBT region into a collector active region and a collector contact region;

[0007] S2. forming a polysilicon gate above the CMOS active area, and forming gate silicon oxide by oxidation on the surface of the polysilicon gate, and forming lightly doped regions by implantation in the CMOS active area on both sides of the polysilicon gate;

[0008] S3, sequentially depositing a first silicon oxide layer and a first silicon nitride layer on a silicon substrate, etching the first silicon nitride layer and the first silicon oxide layer by photolithography to open a base window in the HBT region, then stripping off the remaining first silicon nitride layer, and implanting an N+ type selective ion implantation region into the base window;

[0009] S4. Forming an epitaxial SiGe layer on the silicon substrate in a non-selective manner, wherein the epitaxial SiGe layer formed on the surface of the single crystal silicon is a single crystal SiGe region, the single crystal SiGe region forms a SiGe base region, and the epitaxial SiGe layer formed on the surface of the first silicon oxide layer is a polycrystalline SiGe region;

[0010] S5, sequentially depositing a second silicon oxide layer and a polysilicon sacrificial layer on the silicon substrate, and etching the polysilicon sacrificial layer to form a sacrificial emitter region above the selective ion implantation region;

[0011] S6, depositing a second silicon nitride layer to cover the sacrificial emitter region, photolithographically etching the second silicon nitride layer and the second silicon oxide layer to expose the SiGe surface in the outer region of the SiGe base region, and forming a P+-type doped extrinsic base region on the SiGe surface exposed in the SiGe base region by selective epitaxial SiGe;

[0012] S7, depositing a third silicon oxide layer on the silicon substrate, and performing chemical mechanical polishing on the third silicon oxide layer, using the second silicon nitride layer as a barrier layer;

[0013] S8, sequentially etching the second silicon nitride layer above the sacrificial emitter region, the sacrificial emitter region, and the second silicon oxide layer below the sacrificial emitter region to form an emitter region window, exposing the SiGe surface of the SiGe base region below the emitter region window;

[0014] S9, forming an N+-type doped silicon emitter region in the emitter region window, and patterning the emitter region and the extrinsic base region by photolithography;

[0015] S10, completing the subsequent SiGe Bi CMOS process.

[0016] Furthermore, the width of the shallow trench is 0.2 μm to 1 μm, the depth of the shallow trench is 0.2 μm to 0.8 μm, the width of the collector active area is 0.2 μm to 2 μm, and the width of the collector contact area is 0.1 μm to 2 μm.

[0017] Furthermore, the injection energy for forming the selective ion injection region is 50KeV to 300KeV, and the injection dose is 2e13cm -3 ~2e14cm -3 , the implanted impurities are arsenic or phosphorus.

[0018] Furthermore, the thickness of the epitaxial SiGe layer formed in a non-selective manner is 300Å to 1000Å, and the impurity in situ doped with boron forms a trapezoidal distribution with a peak concentration of 5e19cm -3 ~2e20cm -3 ;

[0019] Furthermore, the thickness of the second silicon oxide layer is 200A to 1000A, and the thickness of the polysilicon sacrificial layer is 2000A to 4000A.

[0020] Furthermore, the width of the sacrificial emitter region is 1 / 2 to 1 / 5 of the width of the collector active region.

[0021] Furthermore, the thickness of the second silicon nitride layer is 300Å to 1500Å; the in-situ impurity of the external base region is boron, and the doping concentration is 1e19cm -3 ~5e19cm -3 .

[0022] Furthermore, the thickness of the third silicon oxide layer is 1000 Å to 3000 Å; and after chemical mechanical polishing, the residual thickness of the third silicon oxide layer in the CMOS region is 200 Å to 1500 Å.

[0023] Furthermore, the impurities in the silicon emitter region are phosphorus or arsenic, and the doping concentration is 5e19cm -3 ~1.5e20cm -3 .

[0024] A structure integrating CMOS and self-aligned silicon-germanium HBT is manufactured by adopting a method of integrating CMOS and self-aligned silicon-germanium HBT.

[0025] This invention provides a self-aligned SiGe HBT structure and manufacturing method compatible with standard CMOS processes. These structures offer excellent compatibility with existing process conditions, expanding the overall process adaptability and model library. Compared to existing self-aligned HBT processes using other technical approaches, this method first deposits a sacrificial emitter region, then opens the emitter window after epitaxial growth and elevation of the extrinsic base region. This effectively reduces process complexity and improves process robustness. By adjusting the selective implantation conditions, HBT devices with a variety of breakdown voltages can be manufactured. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0027] Figure 1 FIG. 1 is a flow chart of an embodiment of a method for integrating CMOS and self-aligned silicon germanium HBT according to the present invention. Figure 2 It is a schematic diagram of the structure after a shallow trench isolation region is formed on a silicon substrate.

[0028] Figure 3 This is a schematic diagram of the structure after the polysilicon gate, gate silicon oxide, and lightly doped region are formed.

[0029] Figure 4 Schematic diagram of the structure after depositing the first silicon oxide layer and the first silicon nitride layer.

[0030] Figure 5 This is a schematic diagram of the structure after the base window is opened and implanted to form a selective ion implantation area.

[0031] Figure 6 Schematic diagram of the structure after forming the epitaxial Si Ge layer.

[0032] Figure 7 This is a schematic diagram of the structure after forming the second silicon oxide layer and the polysilicon sacrificial layer.

[0033] Figure 8 Schematic diagram of the structure after forming a sacrificial emitter region and depositing a second silicon nitride layer.

[0034] Figure 9 This is a schematic diagram of the structure after the Si Ge surface in the outer area of ​​the Si Ge base region is exposed by photolithography.

[0035] Figure 10 Schematic diagram of the structure after forming an external base region, depositing a third silicon oxide layer and performing chemical mechanical polishing.

[0036] Figure 11 Schematic diagram of the structure after the emission area window is formed.

[0037] Figure 12 This is a schematic diagram of the structure after the silicon emitter region and the external base region are patterned by photolithography.

[0038] Figure 13 This is a schematic diagram of the structure after silicon nitride sidewalls and silicon oxide sidewalls are simultaneously formed in the CMOS area and the HBT area.

[0039] The accompanying drawings in this specification are numeraled as follows:

[0040] Silicon substrate 101; shallow trench isolation region 102; first silicon oxide layer 110; first silicon nitride layer 120; epitaxial SiGe layer 130; second silicon oxide layer 140; polysilicon sacrificial layer 150; second silicon nitride layer 160; third silicon oxide layer 170;

[0041] Polysilicon gate 201; gate silicon oxide 202; lightly doped region 203; silicon nitride sidewalls 208, 308; silicon oxide sidewalls 209, 309; CMOS active region 210; substrate contact region 220;

[0042] Selective ion implantation region 301; base region window 302; Si Ge base region 303; sacrificial emitter region 304; external base region 305; emitter region window 306; silicon emitter region 307; emitter region single crystal silicon 3071; emitter region polycrystalline silicon 3072; collector region active region 310; collector region contact region 320. DETAILED DESCRIPTION

[0043] The following describes the implementation of the present invention through specific examples. The illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention. The following embodiments and features in the embodiments may be combined with each other unless there is any conflict.

[0044] See also Figure 1 , Figure 1 This is a flow chart of an embodiment of a method for integrating CMOS and self-aligned silicon-germanium HBT according to the present invention. The method for integrating CMOS and self-aligned silicon-germanium HBT according to this embodiment includes the following steps:

[0045] S1. Please refer to Figure 2 , multiple shallow trenches are etched on the silicon substrate 101 by photolithography, and oxide is filled in each shallow trench to form multiple shallow trench isolation regions 102. The width of the shallow trench is 0.2μm to 1μm, and the depth of the shallow trench is 0.2μm to 0.8μm. After the oxide is filled in each shallow trench, the oxide surface can be planarized by chemical mechanical polishing. Among the multiple shallow trench isolation regions 102, the middle shallow trench isolation region 102 separates the upper part of the silicon substrate 101 into a CMOS region on the right and an HBT region on the left. The two shallow trench isolation regions 102 on the right further separate the CMOS region into a CMOS active region 210 and a substrate contact region 220. The two shallow trench isolation regions 102 on the left further separate the HBT region into a collector active region 310 and a collector contact region 320. The width of the collector active region 310 is 0.2 μm to 2 μm, and the width of the collector contact region 320 is 0.1 μm to 2 μm.

[0046] S2, please refer to Figure 3 First, a polysilicon gate 201 is formed above the CMOS active area 210. The polysilicon gate 201 can be obtained by depositing a polysilicon layer and then performing patterning etching. A gate oxide 202 is then formed on the surface of the polysilicon gate 201 through rapid thermal oxidation. Finally, lightly doped regions 203 are formed by implantation in the CMOS active area 210 on both sides of the polysilicon gate 201. These two lightly doped regions 203 serve as source / drain extension regions.

[0047] S3, please refer to Figure 4 First, a first silicon oxide layer 110 and a first silicon nitride layer 120 are sequentially deposited on a silicon substrate 101 as protective layers. Figure 5 Then, the first silicon nitride layer 120 and the first silicon oxide layer 110 are etched by photolithography to open a base window 302 in the HBT region. The remaining first silicon nitride layer 120 is then stripped off, and an N+ type selective ion implantation region 301 is implanted in the base window 302. The selective ion implantation region 301 is formed by implanting N-type impurities with medium energy and high dose, with an implantation energy of generally 50KeV to 300KeV and an implantation dose of generally 2e13cm -3 ~2e14cm -3 , the implanted impurities can be arsenic or phosphorus.

[0048] S4. Please refer to Figure 6 An epitaxial SiGe layer 130 is formed on the silicon substrate 101 in a non-selective manner. The epitaxial SiGe layer 130 formed on the surface of the single-crystalline silicon is a single-crystalline SiGe region, which forms the SiGe base region 303 (i.e., the intrinsic base region). The epitaxial SiGe layer 130 formed on the surface of the first silicon oxide layer 110 is a polycrystalline SiGe region (the epitaxial SiGe layer 130 outside the SiGe base region 303 is the polycrystalline SiGe region). The thickness of the epitaxial SiGe layer 130 formed in a non-selective manner is 300 Å to 1000 Å. The in-situ doping of the epitaxial SiGe layer 130 is boron, forming a trapezoidal distribution with a peak concentration of 5e19 cm -3 ~2e20cm -3 .

[0049] S5, please refer to Figure 7 First, a high-quality oxide layer is deposited on the silicon substrate 101 as the second silicon oxide layer 140. The thickness of the second silicon oxide layer 140 is 200A to 1000A. Then, a layer of polysilicon is deposited to form a polysilicon sacrificial layer 150. The thickness of the polysilicon sacrificial layer 150 is 2000A to 4000A. Figure 8 Afterwards, the polysilicon sacrificial layer 150 is etched and patterned, and the remaining polysilicon sacrificial layer 150 forms a sacrificial emitter region 304 above the selective ion implantation region 301 . The width of the sacrificial emitter region 304 is 1 / 2 to 1 / 5 of the width of the collector active region 310 .

[0050] S6. Please continue reading Figure 8 First, a second silicon nitride layer 160 is deposited to cover the sacrificial emitter region 304. The thickness of the second silicon nitride layer 160 is 300Å to 1500Å. Figure 9 Then, the second silicon nitride layer 160 and the second silicon oxide layer 140 are photolithographically etched to expose the SiGe surface outside the SiGe base region 303. Figure 10Then, a P+-type doped extrinsic base region 305 is formed on the SiGe surface exposed by the SiGe base region 303 by selective epitaxy. The in-situ impurity of the extrinsic base region 305 is boron with a doping concentration of 1e19 cm -3 ~5e19cm -3 By using the above method, an elevated extrinsic base region 305 can be formed outside the intrinsic base region, so that the elevated extrinsic base region 305 is self-aligned with the emitter region.

[0051] S7, please continue to refer to Figure 10 A third silicon oxide layer 170 is deposited on the silicon substrate 101. The third silicon oxide layer 170 has a thickness of 1000 Å to 3000 Å. The third silicon oxide layer 170 is chemically mechanically polished, using the second silicon nitride layer 160 as a stop layer for the chemical mechanical polishing. After the chemical mechanical polishing, the remaining thickness of the third silicon oxide layer 170 in the CMOS region is 200 Å to 1500 Å.

[0052] S8, please refer to Figure 11 The second silicon nitride layer 160 above the sacrificial emitter region 304 , the sacrificial emitter region 304 and the second silicon oxide layer 140 below the sacrificial emitter region 304 are sequentially etched to form an emitter region window 306 , exposing the SiGe surface of the SiGe base region 303 below the emitter region window 306 .

[0053] S9, please refer to Figure 12 , an N+-type doped silicon emitter region 307 is formed in the emitter region window 306 by non-selective epitaxial silicon layer and patterned etching; the impurity of the silicon emitter region 307 is phosphorus or arsenic, and the doping concentration is 5e19cm -3 ~1.5e20cm -3 Due to the non-selective growth method, when the epitaxial silicon layer is grown, single crystal silicon is epitaxially grown on the single crystal SiGe surface, and polycrystalline silicon is formed on the silicon nitride surface. That is, the silicon emitter region 307 includes emitter region single crystal silicon 3071 and emitter region polycrystalline silicon 3072. Afterwards, the emitter region and the extrinsic base region 305 are patterned by photolithography. The third silicon oxide layer 170 outside the emitter region and the extrinsic base region 305 is first photolithographically removed. Then, the second silicon nitride layer 160, the second silicon oxide layer 140, and the epitaxial SiGe layer 130 not covering the third silicon oxide layer 170 are etched away.

[0054] S10, complete the subsequent Si Ge Bi CMOS process. Figure 13First, a gate spacer process is used to simultaneously form silicon nitride and silicon oxide sidewalls in the CMOS and HBT regions. Silicon nitride and silicon oxide sidewalls 208 and 209 are sequentially formed on the sides of the gate silicon oxide 202 in the CMOS region, and silicon nitride and silicon oxide sidewalls 308 and 309 are sequentially formed on the sides of the extrinsic base region 305 in the HBT region. Next, high-doping implantation, rapid thermal annealing, and metallization are performed in the source / drain contact regions of the CMOS region, completing the entire Si Ge Bi CMOS process. These processes are conventional and will not be described in detail here.

[0055] The self-aligned SiGe HBT manufacturing method of this embodiment is highly compatible with the process conditions of existing standard CMOS processes, expanding the overall process adaptability and model library. Compared to other existing self-aligned HBT processes, this embodiment first deposits the sacrificial emitter region 304 and then opens the emitter window 306 after epitaxial growth of the elevated extrinsic base region 305, effectively reducing process complexity and improving process robustness. The process of this embodiment is compatible with existing Bi CMOS processes and is scalable. By adjusting the selective implantation conditions, HBT devices with various breakdown voltages can be manufactured.

[0056] The present invention also discloses a structure integrating CMOS and self-aligned SiGe HBT. The structure integrating CMOS and self-aligned SiGe HBT of the present invention can be manufactured by the method of integrating CMOS and self-aligned SiGe HBT of any of the above embodiments.

[0057] The above embodiments merely represent preferred embodiments of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A method for integrating CMOS and self-aligned silicon germanium HBT, characterized in that: The following steps are involved: S1. Etching a plurality of shallow trenches on a silicon substrate by photolithography, and filling each shallow trench with oxide to form a plurality of shallow trench isolation regions, wherein the plurality of shallow trench isolation regions separate the upper portion of the silicon substrate into a CMOS region and an HBT region, and further separate the CMOS region into a CMOS active region and a substrate contact region, and separate the HBT region into a collector active region and a collector contact region; S2. forming a polysilicon gate above the CMOS active area, and forming gate silicon oxide by oxidation on the surface of the polysilicon gate, and forming lightly doped regions by implantation in the CMOS active area on both sides of the polysilicon gate; S3, sequentially depositing a first silicon oxide layer and a first silicon nitride layer on a silicon substrate, etching the first silicon nitride layer and the first silicon oxide layer by photolithography to open a base window in the HBT region, then stripping off the remaining first silicon nitride layer, and implanting an N+ type selective ion implantation region into the base window; S4. Forming an epitaxial SiGe layer on the silicon substrate in a non-selective manner, wherein the epitaxial SiGe layer formed on the surface of the single crystal silicon is a single crystal SiGe region, the single crystal SiGe region forms a SiGe base region, and the epitaxial SiGe layer formed on the surface of the first silicon oxide layer is a polycrystalline SiGe region; S5, sequentially depositing a second silicon oxide layer and a polysilicon sacrificial layer on the silicon substrate, and etching the polysilicon sacrificial layer to form a sacrificial emitter region above the selective ion implantation region; S6, depositing a second silicon nitride layer to cover the sacrificial emitter region, photolithographically etching the second silicon nitride layer and the second silicon oxide layer to expose the SiGe surface in the outer region of the SiGe base region, and forming a P+-type doped extrinsic base region on the SiGe surface exposed in the SiGe base region by selective epitaxial SiGe; S7, depositing a third silicon oxide layer on the silicon substrate, and performing chemical mechanical polishing on the third silicon oxide layer, using the second silicon nitride layer as a barrier layer; S8, sequentially etching the second silicon nitride layer above the sacrificial emitter region, the sacrificial emitter region, and the second silicon oxide layer below the sacrificial emitter region to form an emitter region window, exposing the SiGe surface of the SiGe base region below the emitter region window; S9, forming an N+-type doped silicon emitter region in the emitter region window, and patterning the emitter region and the extrinsic base region by photolithography; S10, completing the subsequent SiGe BiCMOS process.

2. The method for integrating CMOS and self-aligned silicon germanium HBT according to claim 1, wherein: The width of the shallow trench is 0.2 μm to 1 μm, the depth of the shallow trench is 0.2 μm to 0.8 μm, the width of the collector active area is 0.2 μm to 2 μm, and the width of the collector contact area is 0.1 μm to 2 μm.

3. The method for integrating CMOS and self-aligned silicon germanium HBT according to claim 1, wherein: The injection energy for forming the selective ion injection region is 50KeV to 300KeV, and the injection dose is 2e13cm -3 ~2e14cm -3 , the implanted impurities are arsenic or phosphorus.

4. The method for integrating CMOS and self-aligned silicon germanium HBT according to claim 1, wherein: The thickness of the epitaxial SiGe layer formed in a non-selective manner is 300A to 1000A. The impurity in situ doped with boron forms a trapezoidal distribution with a peak concentration of 5e19cm -3 ~2e20cm -3 .

5. The method for integrating CMOS and self-aligned silicon germanium HBT according to claim 1, wherein: The thickness of the second silicon oxide layer is 200A to 1000A, and the thickness of the polysilicon sacrificial layer is 2000A to 4000A.

6. The method for integrating CMOS and self-aligned silicon germanium HBT according to claim 1, wherein: The width of the sacrificial emitter region is 1 / 2 to 1 / 5 of the width of the collector active region.

7. The method for integrating CMOS and self-aligned silicon germanium HBT according to claim 1, wherein: The thickness of the second silicon nitride layer is 300Å to 1500Å; the in-situ impurity of the external base region is boron with a doping concentration of 1e19cm -3 ~5e19cm -3 .

8. The method for integrating CMOS and self-aligned silicon germanium HBT according to claim 1, wherein: The thickness of the third silicon oxide layer is 1000 Å to 3000 Å; after chemical mechanical polishing, the residual thickness of the third silicon oxide layer in the CMOS region is 200 Å to 1500 Å.

9. The method for integrating CMOS and self-aligned silicon germanium HBT according to claim 1, wherein: The impurities in the silicon emitter region are phosphorus or arsenic, with a doping concentration of 5e19cm -3 ~1.5e20cm -3 .

10. A structure integrating CMOS and self-aligned silicon germanium HBT, characterized in that: The method for integrating CMOS and self-aligned silicon germanium HBT is used to manufacture the device.

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