Semiconductor device

Abstract

The invention provides a semiconductor device with high reliability. The semiconductor device includes: an oxide semiconductor layer including an impurity region containing an impurity element and having a polycrystalline structure; a gate electrode provided on the oxide semiconductor layer; an insulating layer provided between the oxide semiconductor layer and the gate electrode; a first contact hole penetrating the insulating layer and exposing the impurity region; a second contact hole penetrating at least the insulating layer and having a depth greater than that of the first contact hole; and a connection wiring that electrically connects the impurity region and the layer exposed through the second contact hole via the first contact hole and the second contact hole. Wherein the connection wiring includes a first conductive layer and a second conductive layer on the first conductive layer, and a portion of the first conductive layer exposed from the second conductive layer contains an impurity element.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device using an oxide semiconductor having a polycrystalline structure. Background Art

[0002] In recent years, instead of using silicon semiconductor films such as amorphous silicon, low-temperature polycrystalline silicon and single crystal silicon, the development of semiconductor devices including oxide semiconductor films is progressing (for example, refer to Patent Documents 1 to 6). Semiconductor devices including oxide semiconductor films have a simple structure like semiconductor devices including amorphous silicon films and can be formed using a low-temperature process. In addition, it is known that semiconductor devices including oxide semiconductor films have higher field effect mobility than semiconductor devices including amorphous silicon films.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-141338

[0006] Patent Document 2: Japanese Patent Application Publication No. 2014-099601

[0007] Patent Document 3: Japanese Patent Application Publication No. 2021-153196

[0008] Patent Document 4: Japanese Patent Application Publication No. 2018-006730

[0009] Patent Document 5: Japanese Patent Application Publication No. 2016-184771

[0010] Patent Document 6: Japanese Patent Application Publication No. 2021-108405 Summary of the invention

[0011] Problems to be solved by the invention

[0012] A semiconductor device is required to have not only high field effect mobility but also high reliability. One object of one embodiment of the present invention is to provide a semiconductor device having high reliability.

[0013] Means for solving problems

[0014] A semiconductor device according to one embodiment of the present invention includes: an oxide semiconductor layer including an impurity region containing an impurity element and having a polycrystalline structure; a gate electrode provided on the oxide semiconductor layer; an insulating layer provided between the oxide semiconductor layer and the gate electrode; a first contact hole penetrating the insulating layer and exposing the impurity region; a second contact hole penetrating at least the insulating layer and having a depth greater than that of the first contact hole; and a connecting wiring electrically connecting the impurity region and a layer exposed through the second contact hole via the first contact hole and the second contact hole; the connecting wiring includes a first conductive layer and a second conductive layer on the first conductive layer, and a portion of the first conductive layer exposed from the second conductive layer contains the impurity element. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0016] Figure 2 It is a schematic enlarged cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0017] Figure 3 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0018] Figure 4 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0019] Figure 5 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0020] Figure 6 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0021] Figure 7 Graph 1 is a simulation result showing the concentration distribution of boron implanted into the oxide semiconductor layer.

[0022] Figure 8 It is a schematic cross-sectional view showing the structure of a semiconductor device according to a modified example of one embodiment of the present invention.

[0023] Fig. 9 It is a schematic cross-sectional view showing the structure of a semiconductor device according to a modified example of one embodiment of the present invention.

[0024] Fig.10 It is a schematic cross-sectional view showing the structure of a semiconductor device according to a modified example of one embodiment of the present invention.

[0025] Fig.11 It is a schematic cross-sectional view showing the structure of a semiconductor device according to a modified example of one embodiment of the present invention.

[0026] Fig.12 It is a schematic cross-sectional view showing the structure of a semiconductor device according to one embodiment of the present invention.

[0027] Explanation of symbols

[0028] 1, 1A, 1B, 1C, 1D, 2: semiconductor device; 10: substrate; 11, 12, 13, 14: insulating layer; CH1: first contact hole; CH2: second contact hole; CN: connecting wiring; EX: extension portion; GE1, GE2: gate electrodes; L1: first conductive layer; L2: second conductive layer; L3: third conductive layer; L4: fourth conductive layer; LS: light shielding layer; MO: metal oxide layer; OS: oxide semiconductor layer, OS_1: channel region; OS_2: impurity region; SS: silicon semiconductor layer; TR1: first transistor; TR2: second transistor. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is always just an example. While maintaining the gist of the invention, those skilled in the art will naturally also be included in the scope of the present invention by making appropriate changes to the configuration of the embodiment and easily conceivable configurations. In order to make the description clearer, the accompanying drawings sometimes schematically illustrate the width, film thickness, shape, etc. of the constituent elements compared to the actual form. However, the illustrated shape is always an example and does not limit the interpretation of the present invention. In this specification and the accompanying drawings, the same symbol is sometimes used for the constituent elements that are the same as the constituent elements described in the illustrated figures, and the detailed description is appropriately omitted.

[0030] In this specification, etc., the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above". On the contrary, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below". In this way, for the convenience of explanation, the terms "up" or "down" are used for explanation, but the up-and-down relationship between the substrate and the oxide semiconductor layer can also be configured in the opposite direction to the diagram. In addition, the expression "oxide semiconductor layer on the substrate" is only used to illustrate the up-and-down relationship between the substrate and the oxide semiconductor layer, and other components can also be configured between the substrate and the oxide semiconductor layer. Above or below refers to the stacking order in a structure in which multiple layers are stacked. When expressed as "a pixel electrode above the semiconductor device", it can also be a positional relationship in which the semiconductor device and the pixel electrode do not overlap in a top view. On the other hand, when expressed as "a pixel electrode vertically above the semiconductor device", it refers to a positional relationship in which the semiconductor device and the pixel electrode overlap in a top view. In addition, the so-called top view refers to looking from a direction perpendicular to the surface of the substrate.

[0031] In this specification, etc., expressions such as “α includes A, B or C”, “α includes any one of A, B and C”, and “α includes one selected from A, B and C” do not exclude the case where α includes a plurality of combinations of A to C unless otherwise specified. In addition, these expressions do not exclude the case where α includes other constituent elements.

[0032] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are included in one form of a semiconductor device. The semiconductor device of the embodiment shown below may also be a transistor used in an integrated circuit (IC) such as a display device, a microprocessor (MPU), or a memory circuit.

[0033] In this specification, the so-called "display device" refers to a structure that uses an electro-optical layer to display an image. For example, the term "display device" sometimes refers to a display panel including an electro-optical layer, or sometimes refers to a structure in which other optical components (such as a polarizing component, a backlight, a touch panel, etc.) are installed relative to the display unit. In the "electro-optical layer", as long as there is no technical contradiction, it can include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer.

[0034] In this specification and the like, the term "film" and the term "layer" can be used interchangeably according to circumstances.

[0035] In addition, the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0036] <First Embodiment>

[0037] Reference Figure 1 to Figure 7 , a semiconductor device 1 according to an embodiment of the present invention will be described.

[0038] [1. Configuration of Semiconductor Device 1]

[0039] Figure 1 It is a schematic cross-sectional view showing the structure of a semiconductor device 1 according to one embodiment of the present invention.

[0040] like Figure 1 As shown, the semiconductor device 1 includes a first transistor TR1 and a second transistor TR2 on a substrate 10. In addition, the semiconductor device 1 includes insulating layers 11 to 14 that are provided in common in the first transistor TR1 and the second transistor TR2.

[0041] The first transistor TR1 includes an insulating layer 11, an insulating layer 12, a light shielding layer LS, an insulating layer 13, an oxide semiconductor layer OS, an insulating layer 14, and a gate electrode GE1. The insulating layer 11 is provided on the substrate 10. The insulating layer 12 is provided on the insulating layer 11. The light shielding layer LS is provided on the insulating layer 12. The insulating layer 13 covers the upper surface and the end surface of the light shielding layer LS and is provided on the insulating layer 12. The oxide semiconductor layer OS is provided on the insulating layer 13. The insulating layer 14 covers the upper surface and the end surface of the oxide semiconductor layer OS and is provided on the insulating layer 13. The gate electrode GE1 overlaps with the oxide semiconductor layer OS and is provided on the insulating layer 14. In the first transistor TR1, the insulating layer 11 and the insulating layer 12 function as substrate insulating layers, the insulating layer 13 functions as an interlayer insulating layer, and the insulating layer 14 functions as a gate insulating layer. The gate electrode GE1 is an electrode electrically connected to a gate line. The detailed structure of the oxide semiconductor layer OS will be described later.

[0042] The second transistor TR2 includes an insulating layer 11, a silicon semiconductor layer SS, an insulating layer 12, a gate electrode GE2, an insulating layer 13, and an insulating layer 14. The insulating layer 11 is provided on the substrate 10. The silicon semiconductor layer SS is provided on the insulating layer 11. The insulating layer 12 covers the upper surface and end surface of the silicon semiconductor layer SS and is provided on the insulating layer 11. The gate electrode GE2 overlaps with the silicon semiconductor layer SS and is provided on the insulating layer 12. The insulating layer 13 covers the upper surface and end surface of the gate electrode GE2 and is provided on the insulating layer 12. The insulating layer 14 is provided on the insulating layer 13. In the second transistor TR2, the insulating layer 11 functions as a substrate insulating layer, the insulating layer 12 functions as a gate insulating layer, and the insulating layers 13 and 14 function as interlayer insulating layers. The gate electrode GE2 is an electrode electrically connected to the gate line. As the silicon semiconductor layer SS, for example, a polycrystalline silicon semiconductor can be used, but the material of the silicon semiconductor layer SS is not limited thereto. As the silicon semiconductor layer SS, other silicon-based semiconductors can also be used.

[0043] The first transistor TR1 and the second transistor TR2 are electrically connected via the connection wiring CN. Specifically, the connection wiring CN directly electrically connects the oxide semiconductor layer OS of the first transistor TR1 and the second transistor TR2. The connection wiring CN functions as one of the source electrode and the drain electrode of the first transistor TR1. In addition, the connection wiring CN also functions as one of the source electrode and the drain electrode of the second transistor TR2. Figure 1 In FIG. 1 , the other of the source electrode and the drain electrode of the second transistor TR2 is omitted from illustration.

[0044] The substrate 10 can support each layer constituting the semiconductor device 1. For example, as the substrate 10, a glass substrate, a quartz substrate, a sapphire substrate or other light-transmitting rigid substrate can be used. In addition, as the substrate 10, a silicon substrate or other non-light-transmitting rigid substrate can also be used. In addition, as the substrate 10, a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate or a fluororesin substrate or other light-transmitting flexible substrate can be used. In order to improve the heat resistance of the substrate 10, impurities can also be introduced into the flexible substrate.

[0045] The light-shielding layer LS can reflect or absorb light incident from the substrate 10 side. In other words, the light-shielding layer LS can shield light incident on the oxide semiconductor layer OS. The light-shielding layer LS is formed of the same layer as the gate electrode GE2. In other words, the light-shielding layer LS is formed of the same material as the gate electrode GE2. For example, as the light-shielding layer LS and the gate electrode GE2, metals such as aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo) or tungsten (W), or alloys of these metals or compounds of these metals can be used. The light-shielding layer LS may have a single-layer structure or a stacked structure.

[0046] As the insulating layers 11 to 14, for example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ) or aluminum oxynitride (AlO x N y ) or silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum nitride (AlN x ) or aluminum oxynitride (AlN x O y Each of the insulating layers 11 to 14 may have a single layer structure or a stacked layer structure.

[0047] Among them, silicon oxynitride (SiO x N y ) and aluminum oxynitride (AlO x N y ) are oxides containing nitrogen (N) at a lower ratio (x>y) than oxygen (O). x O y ) and aluminum oxynitride (AlN x O y ) is a nitride containing oxygen at a lower ratio (x>y) than nitrogen. x ) and silicon oxynitride (SiO x N y ) is referred to as "silicon oxide", and silicon nitride (SiN x ) and silicon oxynitride (SiN x O y ) is referred to as "silicon nitride". Similarly, aluminum oxide (AlO x ) and aluminum oxynitride (AlO x N y ) is referred to as "aluminum oxide", aluminum nitride (AlN x ) and aluminum oxynitride (AlN x O y ) is referred to as "aluminum nitride".

[0048] The insulating layer 13 and the insulating layer 14 in contact with the oxide semiconductor layer OS preferably contain oxide. If the oxide semiconductor layer OS is in contact with the oxide, oxygen can be supplied from the oxide to the oxide semiconductor layer OS by heat treatment. For example, the insulating layer 13 may also have a stacked structure containing silicon nitride and silicon oxide on the silicon nitride. In addition, the insulating layer 14 may also have a single-layer structure of silicon oxide.

[0049] The gate electrode GE1 is formed of the same layer as the connection wiring CN. That is, the gate electrode GE1 is formed of the same material as the connection wiring CN. The gate electrode GE1 and the connection wiring CN each have a stacked structure. Specifically, the gate electrode GE1 has a stacked structure including a first conductive layer L1 and a second conductive layer L2 on the first conductive layer L1. In addition, the connection wiring CN has a stacked structure including a third conductive layer L3 and a fourth conductive layer LS4 on the third conductive layer L3. The first conductive layer L1 is formed of the same layer as the third conductive layer L3, and the second conductive layer L2 is formed of the same layer as the fourth conductive layer L4.

[0050] In the channel length direction of the first transistor TR1 (the direction from the source electrode to the drain electrode of the first transistor TR1 or the direction from the drain electrode to the source electrode), the width of the first conductive layer L1 is greater than the width of the second conductive layer L2. Therefore, when viewed from above, the first conductive layer L1 includes a portion exposed from the second conductive layer L2. In addition, the film thickness t1 of the first conductive layer L1 is less than the film thickness t2 of the second conductive layer L2 (t1<t2). The film thickness t2 of the second conductive layer L2 is more than three times the film thickness t1 of the first conductive layer L1. For example, the film thickness t1 is about 30 nm, and the film thickness t2 is about 100 nm.

[0051] The first conductive layer L1 is formed of a material different from that of the second conductive layer L2. When selecting the materials of the first conductive layer L1 and the second conductive layer L2, the density of the material forming the first conductive layer L1 is preferably less than the density of the material forming the second conductive layer L2. As the first conductive layer L1 and the second conductive layer L2, the same material as the gate electrode GE2 can be used. For example, the first conductive layer L1 contains at least one of titanium (Ti) and aluminum (Al), and the second conductive layer L2 contains at least one of molybdenum (Mo) and tungsten (W). However, since the first conductive layer L1 is in contact with the oxide semiconductor layer OS, it is preferred that the first conductive layer L1 contains a material that is difficult to oxidize. For example, the first conductive layer L1 preferably has a single-layer structure of titanium, or a stacked structure including titanium and aluminum on titanium.

[0052] In the first transistor TR1, a first contact hole CH1 is provided to expose a portion of the oxide semiconductor layer OS so as to penetrate the insulating layer 14. In addition, in the second transistor TR2, a second contact hole CH2 is provided to expose a portion of the silicon semiconductor layer SS so as to penetrate the insulating layers 12 to 14. The depth of the second contact hole CH2 is greater than the depth of the first contact hole CH1. The connection wiring CN electrically connects the oxide semiconductor layer OS and the silicon semiconductor layer SS via the first contact hole CH1 and the second contact hole CH2.

[0053] As described above, the connection wiring CN includes the third conductive layer L3 formed of the same layer as the first conductive layer L1 and the fourth conductive layer LS4 formed of the same layer as the second conductive layer L2. Therefore, the film thickness t3 of the third conductive layer L3 is smaller than the film thickness t4 of the fourth conductive layer L4 (t3<t4). The film thickness t4 of the fourth conductive layer L4 is more than three times the film thickness t3 of the third conductive layer L3. For example, the film thickness t3 is about 30nm, and the film thickness t4 is about 100nm.

[0054] The third conductive layer L3 extends from the first contact hole CH1 to the second contact hole CH2 so as to cover the first contact hole CH1 and the second contact hole CH2. The third conductive layer L3 contacts the oxide semiconductor layer OS through the first contact hole CH1 and contacts the silicon semiconductor layer SS through the second contact hole CH2.

[0055] The fourth conductive layer L4 overlaps with the second contact hole CH2, but does not overlap with the first contact hole CH1. That is, in the connection wiring CN, a portion of the third conductive layer L3 is exposed from the fourth conductive layer L4. The portion of the third conductive layer exposed from the fourth conductive layer L4 contacts the oxide semiconductor layer OS via the first contact hole CH1.

[0056] Below, refer to Figure 2 , the electrical connection between the connection wiring CN and the oxide semiconductor layer is described.

[0057] Figure 2 1 is a schematic enlarged cross-sectional view showing the structure of a semiconductor device 1 according to an embodiment of the present invention. Specifically, Figure 2 yes Figure 1 An enlarged cross-sectional view of area A in FIG.

[0058] The oxide semiconductor layer OS includes a channel region OS_1 and an impurity region OS_2 adjacent to the channel region. The channel region OS_1 has semiconductor properties. Therefore, if a voltage is applied to the gate electrode GE1, a channel that serves as a current path is formed in the channel region OS_1. The impurity region OS_2 contains impurity elements and has conductor properties. Therefore, the carrier concentration of the impurity region OS_2 is greater than the carrier concentration of the channel region OS_1. In other words, the channel region OS_1 has a higher resistivity (or lower conductivity) than the impurity region OS_2. For example, the surface resistance of the impurity region OS_2 is less than 1000Ω / sq., preferably less than 500Ω / sq., and more preferably less than 250Ω / sq. In addition, the impurity region OS_2 is sometimes referred to as a source region or a drain region.

[0059] The impurity element contained in the impurity region OS_2 is, for example, boron (B) or phosphorus (P), but is not limited thereto. The details will be described later, but by injecting the impurity element into the oxide semiconductor layer OS, an impurity region OS_2 containing the impurity element can be formed. In the impurity region OS_2 of the oxide semiconductor layer OS, more impurity elements can be contained. This means that more oxygen defects can be generated in the impurity region OS_2, so that the impurity region OS_2 has a sufficiently large carrier concentration. Therefore, the resistance of the impurity region OS_2 is very low.

[0060] The boundary between the channel region OS_1 and the impurity region OS_2 substantially coincides with the end of the second conductive layer L2. That is, the end of the impurity region OS_2 overlaps with the portion of the first conductive layer L1 exposed from the second conductive layer L2.

[0061] The third conductive layer L3 is in contact with the impurity region OS_2 via the first contact hole CH1. The resistance of the impurity region OS_2 is sufficiently low, so that the electrical connection between the third conductive layer L3 and the impurity region OS_2 is made into an ohmic contact.

[0062] [2. Configuration of Oxide Semiconductor Layer OS]

[0063] [2-1. Composition of Oxide Semiconductor Layer OS]

[0064] As the oxide semiconductor layer OS, an oxide semiconductor containing two or more metal elements including indium (In) can be used. As metal elements other than indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr) and lanthanide elements can be used.

[0065] The oxide semiconductor layer OS is light-transmissive and has a polycrystalline structure including a plurality of crystal grains. In order to make the oxide semiconductor layer OS have a polycrystalline structure, it is preferred to use an oxide semiconductor in which the ratio of indium to all metal elements is 50% or more in atomic ratio. If the ratio of indium increases, the oxide semiconductor layer OS becomes easy to crystallize. In addition, as a metal element other than indium, gallium is preferably contained. Gallium, like indium, belongs to the 13th group element. Therefore, the crystallinity of the oxide semiconductor layer OS is hardly hindered by gallium.

[0066] The oxide semiconductor layer OS includes a channel region OS_1 and an impurity region OS_2. Not only the channel region OS_1 but also the impurity region OS_2 may have a polycrystalline structure. In this case, the crystal structure of the channel region OS_1 is the same as the crystal structure of the impurity region OS_2.

[0067] The details will be described later, but the oxide semiconductor layer OS has different properties from the conventional oxide semiconductor having a polycrystalline structure. Therefore, in order to distinguish the oxide semiconductor contained in the oxide semiconductor layer OS from the conventional oxide semiconductor having a polycrystalline structure, the oxide semiconductor contained in the oxide semiconductor layer OS is referred to as Poly-OS (Poly-crystalline Oxide Semiconductor: polycrystalline oxide semiconductor) for explanation below.

[0068] The Poly-OS included in the oxide semiconductor layer OS can be formed by sputtering and heat treatment. Hereinafter, a method for forming the oxide semiconductor layer OS will be described.

[0069] First, an oxide semiconductor film is formed by sputtering. The formed oxide semiconductor film has an amorphous structure. The so-called amorphous structure refers to a structure in which there is no long-range ordered structure and no periodic lattice arrangement is found. For example, if an oxide semiconductor film with an amorphous structure is observed by X-ray diffraction (XRD), no specific peak based on the crystal structure is obtained in the diffraction pattern. Furthermore, an oxide semiconductor film with an amorphous structure sometimes has a short-range ordered structure in a tiny area. However, since such an oxide semiconductor film does not show the characteristics of Poly-OS, it can be classified as an oxide semiconductor film with an amorphous structure.

[0070] An oxide semiconductor film having an amorphous structure can be formed at a low temperature. For example, the temperature of the substrate on which the oxide semiconductor film is formed is below 150°C, preferably below 100°C, and more preferably below 50°C. If the temperature of the substrate is high, microcrystals are easily generated in the formed oxide semiconductor. In addition, the oxygen partial pressure in the chamber during film formation is above 1% and below 10%, preferably above 1% and below 5%, and more preferably above 2% and below 4%. If the oxygen partial pressure is high, microcrystals are generated in the oxide semiconductor film due to the excess oxygen contained in the oxide semiconductor. On the other hand, if the oxygen partial pressure is lower than 1%, the oxygen composition in the oxide semiconductor film becomes uneven, thereby forming an oxide semiconductor film containing many microcrystals, or forming an oxide semiconductor film that does not crystallize even after heat treatment.

[0071] Next, the oxide semiconductor film formed by sputtering is heat treated. The heat treatment is performed in the atmosphere, but the atmosphere of the heat treatment is not limited thereto. The temperature of the heat treatment is greater than 300°C and less than 500°C, preferably greater than 350°C and less than 450°C. In addition, the heat treatment time is greater than 15 minutes and less than 120 minutes, preferably greater than 30 minutes and less than 60 minutes. By performing the heat treatment, the oxide semiconductor film having an amorphous structure can be crystallized to form an oxide semiconductor layer OS containing Poly-OS.

[0072] The composition of the oxide semiconductor layer OS is roughly consistent with the composition of the sputtering target. Therefore, the composition of the metal elements of the oxide semiconductor layer OS can be specified based on the composition of the metal elements of the sputtering target. In addition, the composition of the oxide semiconductor layer OS can also be specified by the XRD method. Specifically, the composition of the metal elements of the oxide semiconductor layer OS can be specified based on the crystal structure and lattice constant of the oxide semiconductor layer OS obtained from the XRD method. In addition, the composition of the metal elements of the oxide semiconductor layer OS can also be specified by fluorescent X-ray analysis or electron probe microanalysis (Electron Probe MicroAnalyzer: EPMA) analysis. Furthermore, since the oxygen contained in the oxide semiconductor layer OS changes with the process conditions of the sputtering method, etc., it is not limited to this.

[0073] [2-2. Characteristics of Oxide Semiconductor Layer OS]

[0074] Next, the characteristics of the oxide semiconductor layer OS including Poly-OS will be described.

[0075] The oxide semiconductor layer OS has excellent etching resistance. Specifically, the etching rate of the oxide semiconductor layer OS is very low when etching is performed using an etching solution for wet etching. This means that the oxide semiconductor layer OS is hardly etched by the etching solution. When etching the oxide semiconductor layer OS at 40°C using an etching solution containing phosphoric acid as the main component (hereinafter referred to as a "mixed acid etching solution"), the etching rate is less than 3nm / min, less than 2nm / min, or less than 1nm / min. The ratio of phosphoric acid in the mixed acid etching solution is greater than 50%, greater than 60%, or greater than 70%. In addition to phosphoric acid, acetic acid and nitric acid may also be contained in the mixed acid etching solution. Furthermore, in an oxide semiconductor film that does not contain Poly-OS, for example, an oxide semiconductor film having an amorphous structure before heat treatment, the etching rate when etching the oxide semiconductor film using a mixed acid etching solution at 40°C is greater than 100nm / min. In addition, the etching rate when etching the oxide semiconductor layer OS using a 0.5% hydrofluoric acid solution at room temperature is less than 5nm / min, less than 4nm / min, or less than 3nm / min. In an oxide semiconductor film that does not contain Poly-OS, the etching rate when etching the oxide semiconductor film using a 0.5% hydrofluoric acid solution at room temperature is greater than 15 nm / min. Here, the so-called "40°C" refers to 40±5°C, which can also be the temperature of the etching solution or the set temperature of the etching solution. In addition, the so-called "room temperature" refers to 25±5°C.

[0076] An embodiment of the oxide semiconductor layer OS is shown in Table 1. Table 1 shows the etching rates of the prepared samples relative to the mixed acid etching solution ("Mixed Acid AT-2F" manufactured by LASA Industries, Ltd. in which the ratio of phosphoric acid in the mixed acid etching solution is 65%) and the 0.5% hydrofluoric acid solution. In addition, when etching each sample, the temperature of the mixed acid etching solution is 40°C, and the temperature of the 0.5% hydrofluoric acid solution is room temperature (22°C). In Table 1, Sample 1 is an oxide semiconductor layer OS containing Poly-OS, Sample 2 is an oxide semiconductor film having an amorphous structure before heat treatment, and Sample 3 is an oxide semiconductor film of indium gallium zinc oxide (IGZO) containing an indium ratio of less than 50%.

[0077] Table 1

[0078] Mixed acid etching solution 0.5% hydrofluoric acid solution Sample 1 <0.1nm / min <2nm / min Sample 2 111nm / min >18nm / min Sample 3 162nm / min -

[0079] As shown in Table 1, sample 1 (oxide semiconductor layer OS containing Poly-OS) is hardly etched by the mixed acid etching solution, and is etched at a rate of 2 nm / min at best even by a 0.5% hydrofluoric acid solution. In the etching using the mixed acid etching solution, the etching rate of sample 1 is less than 1 / 100 of the etching rate of sample 2 (oxide semiconductor film with an amorphous structure before heat treatment). In the etching using a 0.5% hydrofluoric acid solution, the etching rate of sample 1 is less than about 1 / 10 of the etching rate of sample 2. In addition, in the etching using the mixed acid etching solution, the etching rate of sample 1 is less than 1 / 100 of the etching rate of sample 3 (oxide semiconductor film of IGZO containing an indium ratio of less than 50%). In other words, sample 1 has significantly better etching resistance than samples 2 and 3.

[0080] Such excellent etching resistance of the oxide semiconductor layer OS containing Poly-OS is a property not obtained in the conventional oxide semiconductor having a polycrystalline structure produced by a process below 500° C. The detailed mechanism of the excellent etching resistance of the oxide semiconductor layer OS containing Poly-OS is not clear, but it is believed that it is because Poly-OS has a polycrystalline structure different from the conventional one.

[0081] As described above, the etching rate of the oxide semiconductor layer OS containing Poly-OS relative to the etching solution is very low. Therefore, the pattern processing of the oxide semiconductor layer OS is very difficult. Therefore, in the case of forming an island-shaped oxide semiconductor layer OS, the oxide semiconductor film having an amorphous structure before heat treatment is patterned in an island shape, and then crystallized by heat treatment. Thus, an island-shaped oxide semiconductor layer OS containing Poly-OS can be formed.

[0082] [3. Method for Manufacturing Semiconductor Device 1]

[0083] Reference Figure 3 to Figure 6 , a method for manufacturing the semiconductor device 1 is described.

[0084] Figure 3 to Figure 6 Each of them is a schematic cross-sectional view showing a method for manufacturing the semiconductor device 1 according to an embodiment of the present invention.

[0085] First, if Figure 3 As shown, an insulating layer 11 , a silicon semiconductor layer SS, an insulating layer 12 , a gate electrode GE2 , a light shielding layer LS, an insulating layer 13 , an oxide semiconductor layer OS, and an insulating layer 14 are sequentially formed on a substrate 10 .

[0086] In the formation of the silicon semiconductor layer SS, an impurity element is implanted into the silicon semiconductor layer SS using the gate electrode GE1 as a mask. At this time, the implanted impurity element is phosphorus (P) in the case of an n-channel type and boron (B) in the case of a p-channel type. In the formation of the oxide semiconductor layer OS, after the pattern of the oxide semiconductor film formed by sputtering is formed, a heat treatment (hereinafter referred to as "OS annealing") is performed. By performing OS annealing, an oxide semiconductor layer OS containing Poly-OS is formed.

[0087] After forming the insulating layer 14, a first contact hole CH1 penetrating the insulating layer 14 and a second contact hole CH2 penetrating the insulating layers 12 to 14 are formed. The first contact hole CH1 partially exposes the oxide semiconductor layer OS, and the second contact hole CH2 partially exposes the silicon semiconductor layer SS.

[0088] Then, if Figure 4 As shown, a metal film is formed on the insulating layer 14, and then the first conductive layer L1 of the gate electrode GE2 and the third conductive layer L3 of the connection wiring CN are formed by patterning the metal film. The third conductive layer L3 contacts the oxide semiconductor layer OS via the first contact hole CH1, and contacts the silicon semiconductor layer SS via the second contact hole CH2. The first conductive layer L1 overlaps with the oxide semiconductor layer OS and is separated from the third conductive layer L3.

[0089] Then, if Figure 5 As shown in the figure, a metal film is formed on the first conductive layer L1 and the third conductive layer, and then the second conductive layer L2 of the gate electrode GE1 and the fourth conductive layer L4 of the connection wiring CN are formed by patterning the metal film. The fourth conductive layer L4 overlaps with the second contact hole CH2, but does not overlap with the first contact hole CH1. The second conductive layer L2 overlaps with the oxide semiconductor layer OS and is separated from the fourth conductive layer L4.

[0090] Then, if Figure 6 As shown, an impurity element is implanted into the oxide semiconductor layer OS using the gate electrode GE1 as a mask. For example, boron (B) is implanted into the oxide semiconductor layer OS as an impurity element by ion implantation. Furthermore, other impurity elements such as phosphorus (P) may be implanted into the oxide semiconductor layer OS instead of boron.

[0091] When ion implantation is performed, the second conductive layer L2 and the fourth conductive layer L4, which have a relatively high density and a relatively thick film thickness, have a high ability to prevent the implantation of impurity elements. Therefore, impurity elements are hardly implanted into the region overlapping with the second conductive layer L2 and the fourth conductive layer L4. On the other hand, the first conductive layer L1 and the third conductive layer L3 have a relatively low density and a relatively thin film thickness. Therefore, impurity elements easily pass through the portion of the first conductive layer L1 that does not overlap with the second conductive layer L2 and the portion of the third conductive layer that does not overlap with the fourth conductive layer L4. Therefore, impurity elements can be implanted into the region that does not overlap with the second conductive layer L2 and the fourth conductive layer L4. Thus, impurity elements can be implanted into the region of the oxide semiconductor layer OS that does not overlap with the second conductive layer L2, thereby forming a low-resistance impurity region OS_2. In addition, impurity elements are not implanted into the region of the oxide semiconductor layer OS that overlaps with the second conductive layer L2, thereby forming a channel region OS_1. As described above, in the portion of the first conductive layer L1 exposed from the second conductive layer L2, although the impurity element passes through, the impurity element may be contained in the portion. Similarly, in the portion of the third conductive layer L3 exposed from the fourth conductive layer L4, although the impurity element passes through, the impurity element may be contained in the portion.

[0092] As described above, in the case where the second transistor TR2 is an n-channel transistor, the impurity element injected into the silicon semiconductor layer SS is phosphorus. That is, the impurity element (phosphorus) contained in the silicon semiconductor layer SS is different from the impurity element (boron) injected into the oxide semiconductor layer OS. In this case, protection is required to prevent the impurity element (boron) injected into the oxide semiconductor layer OS from being injected into the silicon semiconductor layer SS. Therefore, it is necessary to prevent the fourth conductive layer L4 from being formed on the third conductive layer L3 in the second contact hole CH2, and to prevent the impurity element (boron) injected into the oxide semiconductor layer OS from being injected into the silicon semiconductor layer SS.

[0093] In addition, when the second transistor TR2 is a p-channel transistor, the impurity element injected into the silicon semiconductor layer SS is boron. When the impurity element injected into the oxide semiconductor layer OS is phosphorus, the impurity element (boron) contained in the silicon semiconductor layer SS is different from the impurity element (phosphorus) injected into the oxide semiconductor layer OS. In this case as well, it is necessary to prevent the fourth conductive layer L4 from being formed on the third conductive layer L3 in the second contact hole CH2, and to prevent the impurity element (phosphorus) injected into the oxide semiconductor layer OS from being injected into the silicon semiconductor layer SS.

[0094] Figure 7 3 is a simulation result showing the concentration distribution of boron injected into the oxide semiconductor layer OS. Figure 7 The horizontal axis and vertical axis of the graph represent the distance from the surface and the concentration of boron, respectively. Figure 7 The figure shows not only the concentration distribution of Poly-OS contained in the oxide semiconductor layer OS ( Figure 7 The solid line in FIG. 1 is a solid line in FIG. 2 ), and the concentration distribution of indium gallium zinc oxide (IGZO) is also shown as a conventional example ( Figure 7 ).

[0095] The simulation was performed using the "VICTORY PROCESS" manufactured by SILVACO at an acceleration voltage of 30 keV and a dose of 1 × 10 13 cm -2 As mentioned above, Poly-OS contains more indium and has a higher density. Therefore, in the simulation, the 3 and 6.1g / cm 3 Calculate the density of Poly-OS and IGZO.

[0096] like Figure 7 As shown in FIG. 1 , the distance of the injected boron in Poly-OS is smaller than that in IGZO. That is, compared with IGZO, Poly-OS does not inject boron to a position far from the surface. This means that the injected boron is easy to stay in Poly-OS. In other words, Poly-OS has a high blocking ability for the injected impurity elements. Therefore, the impurity elements will not pass through the oxide semiconductor layer OS containing Poly-OS, and the oxide semiconductor layer OS can contain more impurity elements. As a result, more oxygen defects are generated in the impurity region OS_2, which can make the impurity region OS_2 sufficiently low in resistance.

[0097] In the semiconductor device 1, since the impurity elements are injected into the oxide semiconductor layer OS via the first conductive layer L1 and the third conductive layer L3, the acceleration voltage in the ion injection is sometimes increased. In this case, the blocking ability of the impurity elements is significantly shown. Specifically, even under the condition that the impurity elements pass through the conventional oxide semiconductor layer containing IGZO, the impurity elements can stay in the oxide semiconductor layer OS containing Poly-OS. Therefore, in the semiconductor device 1, the impurity region OS_2 overlapping with the first conductive layer L1 and the third conductive layer L3 is sufficiently low in resistance.

[0098] As described above, in the semiconductor device 1, the connection wiring CN that directly electrically connects the oxide semiconductor layer OS and the silicon semiconductor layer SS has a stacked structure including the third conductive layer L3 having a thin film thickness and the fourth conductive layer L4 having a thick film thickness. However, the fourth conductive layer L4 may be formed in a manner that does not overlap the third conductive layer L3 and the first contact hole CH1 that contacts the oxide semiconductor layer OS.

[0099] Unlike the present embodiment, when a thick connection wiring is formed overlapping with the first contact hole CH1, if the implantation of the impurity element is performed by ion implantation, the impurity element is implanted only from the gap between the gate electrode and the connection wiring. In this case, the impurity region containing the impurity element does not overlap with the first contact hole CH1. Therefore, the electrical connection between the connection wiring and the oxide semiconductor layer does not become an ohmic contact, and the second transistor TR2 does not have the desired performance. In addition, the reliability of the second transistor TR2 is reduced because the electrical connection between the connection wiring and the oxide semiconductor layer is unstable.

[0100] On the other hand, according to the present embodiment, by injecting an impurity element into the oxide semiconductor layer OS through the third conductive layer L3, an impurity region OS_2 can be formed overlapping with the first contact hole CH1. Therefore, the electrical connection between the connection wiring CN and the oxide semiconductor layer becomes an ohmic contact, and the second transistor TR2 has a desired performance. In addition, since the electrical connection between the connection wiring CN and the oxide semiconductor layer OS is stable, the second transistor TR2 has high reliability.

[0101] In addition, according to the present embodiment, a fourth conductive layer L4 is formed in the first contact hole CH1 in which the third conductive layer L3 and the silicon semiconductor layer SS are in contact. Therefore, even if the impurities contained in the silicon semiconductor layer SS and the impurities injected into the oxide semiconductor layer OS are different, it is possible to prevent the impurity elements injected into the oxide semiconductor layer OS from being injected into the silicon semiconductor layer SS. Thus, an increase in the contact resistance between the silicon semiconductor layer SS and the connection wiring CN can be suppressed. Therefore, a decrease in the driving capability of the second transistor TR2 can also be suppressed. In addition, there is no need for a separate process to suppress the injection of undesired impurity elements into the silicon semiconductor layer SS, and an increase in manufacturing costs can be suppressed.

[0102] In this embodiment, the impurity region OS_2 of the oxide semiconductor layer OS is electrically connected to the silicon semiconductor layer SS. However, the impurity region OS_2 of the oxide semiconductor layer OS may be electrically connected to a metal layer such as a wiring.

[0103] <Modification 1>

[0104] Reference Figure 8 , a modification of the present embodiment will be described. In addition, in the following, the description of the same configuration as the above configuration may be omitted.

[0105] Figure 8 It is a schematic cross-sectional view showing the structure of a semiconductor device 1A according to a modified example of one embodiment of the present invention.

[0106] Figure 8The semiconductor device 1A shown has a different structure of the fourth conductive layer L4 than the semiconductor device 1. The third conductive layer L3 to which the fourth conductive layer L4 contacts has the same structure as described above. That is, the third conductive layer L3 contacts the silicon semiconductor layer SS via the second contact hole CH2 and contacts the oxide semiconductor layer OS via the first contact hole CH1. In addition, the third conductive layer L3 includes an extension EX extending from a position in the first contact hole CH1 that contacts the oxide semiconductor layer OS toward the gate electrode GE1.

[0107] The fourth conductive layer L4 is formed between the first contact hole CH1 and the second contact hole CH2. The fourth conductive layer L4 not only contacts the second contact hole CH2, but also contacts the third conductive layer L3 in the first contact hole CH1. However, the fourth conductive layer L4 is not formed on the extension EX. That is, the end surface of the fourth conductive layer L4 on the first transistor TR1 side overlaps with the first contact hole CH1.

[0108] In the semiconductor device 1A, the injection of impurity elements into the region overlapping the first contact hole CH1 in the oxide semiconductor layer OS can be suppressed. However, when the third conductive layer L3 is a material that easily absorbs oxygen, by making the third conductive layer L3 contact in this region, oxygen in this region is absorbed, and oxygen defects are generated. Thus, a source region or a drain region with sufficiently low resistance is formed adjacent to the channel region OS_1.

[0109] In the semiconductor device 1A as well, since the fourth conductive layer L4 is not formed in the extended portion EX, the same effects as those of the semiconductor device 1 can be obtained.

[0110] <Modification 2>

[0111] Reference Fig. 9 , another modification of the present embodiment will be described. In addition, in the following, the description of the same configuration as the above configuration may be omitted.

[0112] Fig. 9 It is a schematic cross-sectional view showing the structure of a semiconductor device 1B according to another modified example of one embodiment of the present invention.

[0113] Fig. 9 The semiconductor device 1B shown has a different structure of the gate electrode GE1 compared to the semiconductor device 1. In the gate electrode GE1 of the semiconductor device 1B, the second conductive layer L2 is formed in a manner covering the upper surface and end surface of the first conductive layer L1. In the channel direction, the width of the second conductive layer L2 is greater than the width of the first conductive layer L1. In addition, the second conductive layer L2 and the fourth conductive layer L4 are formed in a manner not to overlap with the first contact hole CH1.

[0114] In the semiconductor device 1B, it is also possible to implant impurity elements into the oxide semiconductor layer OS while the connection wiring CN is in contact with the oxide semiconductor layer OS via the first contact hole CH1. As a result, an impurity region OS_2 having a sufficiently low resistance can be formed by overlapping with the first contact hole CH1 and being adjacent to the channel region OS_1. Therefore, the same effect as that of the semiconductor device 1 can be obtained in the semiconductor device 1B as well.

[0115] <Variation 3>

[0116] Reference Fig.10 , other modified examples of this embodiment are described. In addition, in the following, the description of the same structure as the above-mentioned structure is sometimes omitted.

[0117] Fig.10 It is a schematic cross-sectional view showing the structure of a semiconductor device 1C according to a modified example of one embodiment of the present invention.

[0118] Fig.10 The semiconductor device 1C shown in FIG. 1 is different in the structure of the gate electrode GE1 from that of the semiconductor device 1. In the gate electrode GE1 of the semiconductor device 1C, the second conductive layer L2 is formed, but the first conductive layer L1 is not formed. That is, the second conductive layer L2 is in contact with the insulating layer 14. In addition, the second conductive layer L2 and the fourth conductive layer L4 are formed so as not to overlap with the first contact hole CH1.

[0119] In the semiconductor device 1C, it is also possible to implant impurity elements into the oxide semiconductor layer OS while the connection wiring CN is in contact with the oxide semiconductor layer OS via the first contact hole CH1. As a result, an impurity region OS_2 with a sufficiently low resistance can be formed by overlapping with the first contact hole CH1 and adjacent to the channel region OS_1. Therefore, in the semiconductor device 1C, the same effect as that of the semiconductor device 1 can be obtained.

[0120] <Variation 4>

[0121] Reference Fig.11 , other modified examples of this embodiment are described. In addition, in the following, the description of the same structure as the above-mentioned structure is sometimes omitted.

[0122] Fig.11 It is a schematic cross-sectional view showing the structure of a semiconductor device 1D according to a modified example of one embodiment of the present invention.

[0123] Fig.11The semiconductor device 1D shown includes a metal oxide layer MO compared to the semiconductor device 1. That is, in the semiconductor device 1D, a metal oxide layer MO is provided under the oxide semiconductor layer OS and in contact with the oxide semiconductor layer OS. The end surface of the metal oxide layer MO is substantially consistent with the end surface of the oxide semiconductor layer OS. The insulating layer 14 covers the end surface of the metal oxide layer MO and the upper surface and end surface of the oxide semiconductor layer OS, and is provided on the insulating layer 13.

[0124] The metal oxide layer MO can function as a buffer layer that improves the crystallinity of the oxide semiconductor layer OS. In the first transistor TR1 including the oxide semiconductor layer OS having improved crystallinity, the field effect mobility is further improved.

[0125] As the metal oxide layer MO, a metal oxide containing aluminum as a main component can be used. The ratio of aluminum contained in the metal oxide layer MO can also be 5% to 70%, 10% to 60%, or 30% to 50% of the entire metal oxide layer MO. The above ratio can be a mass ratio or a weight ratio.

[0126] The thickness of the metal oxide layer MO is 1 nm or more and 10 nm or less, preferably 1 nm or more and 5 nm or less. As the metal oxide layer MO, aluminum oxide is preferably used. Aluminum oxide has high barrier properties against gases such as oxygen or hydrogen. Here, the so-called barrier property refers to the function of inhibiting the permeation of gases such as oxygen or hydrogen.

[0127] Furthermore, a metal oxide containing a metal other than aluminum as a main component may be used as the metal oxide layer MO. For example, indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or the like may be used as the metal oxide layer MO.

[0128] The metal oxide layer MO can be formed by sputtering or atomic layer deposition (ALD). In addition, the metal oxide layer MO can be patterned using the oxide semiconductor layer OS as a mask. As described above, the oxide semiconductor layer 140 containing Poly-OS has excellent etching resistance. Therefore, in the pattern formation of the metal oxide layer MO, even when the metal oxide layer MO is etched, the oxide semiconductor layer 140 used as a mask will not be etched. In the semiconductor device 1D, in the formation of the metal oxide layer MO, since the oxide semiconductor layer OS can be used as a mask, the photolithography process can be omitted.

[0129] In the semiconductor device 1D, it is also possible to inject impurity elements into the oxide semiconductor layer OS while the connection wiring CN is in contact with the oxide semiconductor layer OS via the first contact hole CH1. As a result, an impurity region OS_2 with a sufficiently low resistance can be formed by overlapping with the first contact hole CH1 and adjacent to the channel region OS_1. Therefore, in the semiconductor device 1D, the same effect as that of the semiconductor device 1 can be obtained. In addition, in the semiconductor device 1D, since the metal oxide layer MO is used as a buffer layer to form the Poly-OS, the crystallinity of the oxide semiconductor layer OS containing the Poly-OS is improved. As a result, the first transistor TR1 has a higher field effect mobility.

[0130] <Second Embodiment>

[0131] Reference Fig.12 Hereinafter, a semiconductor device 2 according to an embodiment of the present invention will be described. In the following, description of the same configuration as that of the first embodiment may be omitted.

[0132] Fig.12 It is a schematic cross-sectional view showing the structure of a semiconductor device 2 according to one embodiment of the present invention.

[0133] Fig.12 The semiconductor device 2 shown has a different structure of the connection wiring CN compared to the semiconductor device 1. In the connection wiring CN of the semiconductor device 2, the fourth conductive layer L4 is formed on the third conductive layer L3 between the first contact hole CH1 and the second contact hole CH2, and is not formed in the first contact hole CH1 and the second contact hole CH2. In other words, the end surface of the fourth conductive layer L4 does not overlap with the first contact hole CH1 and the second contact hole CH2. In this case, if ion implantation is performed, impurity elements are implanted not only into the oxide semiconductor layer OS but also into the silicon semiconductor layer SS. However, in the semiconductor device 2, the impurity elements contained in the silicon semiconductor layer SS are the same as the impurity elements implanted into the oxide semiconductor layer OS. Specifically, the impurity elements contained in the silicon semiconductor layer SS and the impurity elements implanted into the oxide semiconductor layer OS are both phosphorus, or the impurity elements contained in the silicon semiconductor layer SS and the impurity elements implanted into the oxide semiconductor layer OS are both boron. Therefore, even if the impurity element is implanted into the oxide semiconductor layer OS after the impurity is implanted into the silicon semiconductor layer SS, the performance of the first transistor TR1 is not degraded.

[0134] Furthermore, the second conductive layer L2 and the fourth conductive layer L4 are formed so as not to overlap with the first contact hole CH1.

[0135] In the semiconductor device 2, it is also possible to implant impurity elements into the oxide semiconductor layer OS while the connection wiring CN is in contact with the oxide semiconductor layer OS via the first contact hole CH1. As a result, an impurity region OS_2 having a sufficiently low resistance can be formed by overlapping with the first contact hole CH1 and being adjacent to the channel region OS_1. Therefore, in the semiconductor device 2, the same effect as that of the semiconductor device 1 can be obtained.

[0136] As the embodiments of the present invention, the above-mentioned embodiments and variations can be implemented by appropriate combination as long as they are not contradictory. In addition, based on the embodiments and variations, those skilled in the art appropriately add, delete or change the design of the constituent elements, or add, omit or change the conditions of the processes, as long as they have the gist of the present invention, are included in the scope of the present invention.

[0137] Even if there are other effects that are different from the effects brought about by the forms of the above-mentioned embodiments, as long as they can be understood from the description of this specification or can be easily predicted by those skilled in the art, they should of course be understood as the effects brought about by the present invention.

Claims

1. A semiconductor device comprising: an oxide semiconductor layer including an impurity region containing an impurity element and having a polycrystalline structure; a gate electrode disposed on the oxide semiconductor layer; an insulating layer disposed between the oxide semiconductor layer and the gate electrode; a first contact hole penetrating the insulating layer and exposing the impurity region; a second contact hole that at least penetrates the insulating layer and has a depth greater than that of the first contact hole; and a connection wiring that electrically connects the impurity region and the layer exposed by the second contact hole through the first contact hole and the second contact hole; The connection wiring includes a first conductive layer and a second conductive layer on the first conductive layer. A portion of the first conductive layer exposed from the second conductive layer contains the impurity element.

2. The semiconductor device according to claim 1, wherein The oxide semiconductor layer further includes a channel region adjacent to the impurity region and having a higher resistivity than the impurity region, The gate electrode includes a third conductive layer formed of the same layer as the second conductive layer, A boundary between the channel region and the impurity region substantially coincides with an end portion of the third conductive layer.

3. The semiconductor device according to claim 2, wherein: The gate electrode further includes a fourth conductive layer formed of the same layer as the first conductive layer.

4. The semiconductor device according to claim 3, wherein: The fourth conductive layer includes a portion exposed from the third conductive layer.

5. The semiconductor device according to claim 3, wherein: The end surface of the fourth conductive layer is covered with the third conductive layer.

6. The semiconductor device according to claim 3, wherein: The impurity region has the same crystal structure as that of the channel region.

7. The semiconductor device according to claim 1, wherein The second conductive layer overlaps with the first contact hole.

8. The semiconductor device according to claim 1, wherein The second conductive layer overlaps with the second contact hole.

9. The semiconductor device according to claim 1, wherein: The layer exposed through the second contact hole is a silicon semiconductor layer.

10. The semiconductor device according to claim 1, wherein The layer exposed through the second contact hole is a metal layer.

11. The semiconductor device according to claim 1, wherein When the oxide semiconductor layer is etched at 40° C. using an etching solution containing phosphoric acid as a main component, the etching rate of the oxide semiconductor layer is lower than 3 nm / min.

12. The semiconductor device according to claim 11, wherein The etching solution contains nitric acid and acetic acid.

13. The semiconductor device according to claim 11, wherein The oxide semiconductor layer is formed by heat treating an oxide semiconductor film having an amorphous structure, When the oxide semiconductor film is etched using the etching solution at 40° C., an etching rate of the oxide semiconductor film is 100 nm / min or more.

14. The semiconductor device according to claim 1, wherein When the oxide semiconductor layer is etched using a 0.5% hydrofluoric acid solution at room temperature, an etching rate of the oxide semiconductor layer is lower than 5 nm / min.

15. The semiconductor device according to claim 1, wherein The oxide semiconductor layer contains a plurality of metal elements. One of the plurality of metal elements is indium, The atomic ratio of the indium to the plurality of metal elements is 50% or more.

16. The semiconductor device according to claim 1, wherein The impurity region has a surface resistance of 1000 Ω / sq. or less.

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