A 940nm LED chip and its manufacturing method

Abstract

The present invention relates to the field of semiconductor technology, and in particular to a 940nm LED chip and a method for manufacturing the same. The 940nm LED chip comprises a back electrode, a GaAs substrate, an N‑AlGaAs extension layer, an N‑AlGaAs restriction layer, a multi-quantum well active layer, a P‑AlGaAs restriction layer, a P‑AlGaAs extension layer, a GaAs ohmic contact layer, an ITO layer and a front electrode arranged in sequence from bottom to top; the GaAs ohmic contact layer adopts a patterned structure, the GaAs ohmic contact layer comprises a GaAs vacant portion and a GaAs remaining portion, the lower surface of the ITO layer is adapted to the structure of the GaAs ohmic contact layer, so that the ITO material fills the GaAs vacant portion, and the GaAs remaining portion is embedded in the ITO layer; the GaAs remaining portion comprises a GaAs central island, a GaAs contact lattice and a GaAs annular periphery arranged in sequence from the inside to the outside. This structure can effectively improve the long-term reliability, stability and antistatic ability of the chip, while taking into account a higher luminous efficiency.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a 940nm LED chip and a manufacturing method thereof. Background Art

[0002] 940nm LED chips are mainly used in pulse working state and have important application value in security monitoring, biosensing, remote control, optical coupling and other fields. As the application scenarios extend to high-density integration, high humidity, strong electromagnetic interference and complex working conditions, higher requirements are put forward for the reliability, stability and anti-static ability of the chip, while taking into account high luminous efficiency. Summary of the invention

[0003] The object of the present invention is to provide a 940nm LED chip and a manufacturing method thereof, which can effectively improve the reliability, stability and antistatic ability of the chip while taking into account higher luminous efficiency.

[0004] In order to solve the above problems, the technical solution provided by the present invention is:

[0005] The present invention provides a 940nm LED chip, comprising a back electrode, a GaAs substrate, an N-AlGaAs extension layer, an N-AlGaAs restriction layer, a multi-quantum well active layer, a P-AlGaAs restriction layer, a P-AlGaAs extension layer, a GaAs ohmic contact layer, an ITO layer and a front electrode, which are sequentially arranged from bottom to top;

[0006] The GaAs ohmic contact layer adopts a patterned structure, the GaAs ohmic contact layer includes a GaAs vacant portion and a GaAs remaining portion, the lower surface of the ITO layer is adapted to the structure of the GaAs ohmic contact layer, so that the ITO material fills the GaAs vacant portion, and the GaAs remaining portion is embedded in the ITO layer;

[0007] The GaAs remaining part includes a GaAs central island, a GaAs contact lattice and a GaAs annular periphery arranged in sequence from the inside to the outside;

[0008] The GaAs central island is arranged directly below the front electrode, the GaAs annular periphery is arranged around the outside of the GaAs central island, and the GaAs annular periphery is arranged at the outer edge of the chip, and the GaAs contact point matrix includes a plurality of GaAs contact block points, and the plurality of GaAs contact block points are distributed between the GaAs central island and the GaAs annular periphery.

[0009] Furthermore, the thickness of the front electrode is 3 μm to 4 μm, and the preparation material of the front electrode is Cr, Ti and PtAu evaporated in sequence;

[0010] The front electrode covers a partial area of ​​the upper surface of the chip, the shape of the front electrode is circular, and the front electrode is arranged at the center of the upper surface of the chip.

[0011] Furthermore, the shape of the GaAs central island is the same as that of the front electrode, the front electrode occupies 10% to 35% of the upper surface area of ​​the chip, and the diameter of the GaAs central island is 1 to 1.1 times the diameter of the front electrode.

[0012] Furthermore, the sidewalls of the chip are provided with cutting paths, and the cutting paths are etched from the upper surface of the chip to between the upper surface and the lower surface of the N-AlGaAs extension layer;

[0013] The cutting paths and other areas of the upper surface of the chip except the front electrode are covered with a passivation layer;

[0014] The four corners of the side wall of the cutting path are all rounded, wherein the rounded corners are 1 / 6 to 1 / 4 rounded.

[0015] Furthermore, the sidewalls of the chip have roughened surfaces;

[0016] The roughened surface covers the entire side wall of the chip, or the roughened surface covers the area of ​​the side wall of the chip except the dicing street.

[0017] Furthermore, the number of GaAs contact block points in the GaAs contact point matrix is ​​4 to 20.

[0018] Furthermore, the Al element accounts for 10% to 20% in the N-AlGaAs extension layer and the P-AlGaAs extension layer, and the Al element accounts for 25% to 35% in the N-AlGaAs confinement layer and the P-AlGaAs confinement layer.

[0019] Furthermore, the surface of the P-AlGaAs extension layer directly below the GaAs vacancy has a roughened structure.

[0020] The present invention also provides a method for manufacturing the above-mentioned 940nm LED chip, the manufacturing method comprising:

[0021] S1, providing a GaAs substrate as an epitaxial structure growth substrate;

[0022] S2. Set the program on the MOCVD machine, and sequentially grow an N-AlGaAs extension layer, an N-AlGaAs confinement layer, a multi-quantum well active layer, a P-AlGaAs confinement layer, a P-AlGaAs extension layer, and a GaAs ohmic contact layer on the GaAs substrate;

[0023] S3, cleaning the epitaxial wafer with an organic solution, and using positive resist to make a photolithography pattern on the surface of the GaAs ohmic contact layer of the epitaxial wafer, first etching away the GaAs material in the GaAs vacant part, and then further roughening the exposed P-AlGaAs extension layer to remove the photoresist;

[0024] S4, cleaning the wafer with an organic solution, and directly depositing an ITO layer by electron beam evaporation;

[0025] S5, using negative resist etching and electron beam evaporation to make a patterned front electrode, and peeling it off through a lift-off process to obtain a front electrode;

[0026] S6, using positive resist to make cutting road patterns, etching the cutting road patterns by ICP etching, monitoring the etching process by OES, etching to a depth between the upper surface and the lower surface of the N-AlGaAs extension layer, and removing the surface photoresist by a stripping solution;

[0027] S7, cleaning the wafer organically, depositing SiN material by PECVD, making a passivation layer pattern by positive photoresist, and completing the passivation layer pattern making by wet etching to expose the front electrode wire bonding area;

[0028] S8, grinding and thinning the GaAs substrate, making a back electrode, and performing high temperature annealing;

[0029] S9, applying glue to the front and back of the wafer for protection at the same time, using a blade to cut along the formed cutting path, cutting through the chip at a fixed interval to form LED core particles;

[0030] S10, immersing the core grain fixed on the crystal expansion ring in a mixture of nitric acid and water at a temperature of 10°C to 15°C to roughen the side wall, and then performing a post-resist removal treatment to obtain the final 940nm LED grain.

[0031] Furthermore, the manufacturing method of S6 is to use positive photoresist to make a cutting road pattern, and to etch the cutting road pattern through ICP etching. The etching process is monitored by OES, and the etching depth is between the upper surface and the lower surface of the N-AlGaAs extension layer. Then, the side wall and bottom of the etched wafer cutting road are roughened, and the surface photoresist is removed using a degumming solution.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] 1. In this application, the GaAs ohmic contact layer adopts a patterned structure, and the gallium arsenide material in the GaAs annular periphery adopts a surrounding manner, which can extend the current to the epitaxy around the chip as much as possible, improve the uniformity of the current expansion, and the GaAs annular periphery set on the outer edge can effectively improve the antistatic ability and reliable stability of the chip. By setting the GaAs center island, the load-bearing capacity of the front electrode bonding wire can be improved, and the product manufacturing yield can be improved. The GaAs contact lattice can evenly expand the current in the light-emitting area, and finally obtain a uniform current expansion effect in the light-emitting area. The patterned structure of the GaAs ohmic contact layer is compatible with the upper ITO material. When the area of ​​the GaAs ohmic contact material is constant, the contact interface area between the two is increased, and the current expansion effect is effectively improved. The embedded structure between the GaAs ohmic contact layer and the ITO layer can improve the overall reliability and stability of the material, thereby obtaining a better light-emitting effect, reliability and antistatic effect, and the overall performance is excellent.

[0034] 2. The cutting path and other areas of the upper surface of the chip described in the present application except the front electrode are covered with a passivation layer. After being covered with the passivation layer, the front and side walls of the chip can be effectively protected to prevent the formation of leakage channels; further, the passivation layer material is SiN material, which has high transparency and good passivation effect, can protect the chip and does not affect the emission of light. Rounding the four corners of the side wall of the cutting path can further reduce the accumulation of static electricity at the corners, thereby improving the antistatic effect of the chip. By roughening the side walls around the chip, the reflection of light by the side walls can be reduced, thereby improving the light emission effect of the side walls. The surface of the P-AlGaAs extension layer directly below the GaAs vacancy adopts a roughened structure, which can improve the light emission effect on the front and improve the bonding force between the P-AlGaAs extension layer and the ITO layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0036] Figure 1 This is a schematic diagram of the epitaxial structure of a 940nm LED chip shown in some embodiments of the present application;

[0037] Figure 2 This is a schematic diagram of the structure of a 940nm LED chip after the epitaxial sidewall is roughened as shown in some embodiments of the present application;

[0038] Figure 3 This is a schematic structural diagram of another viewing angle of a 940nm LED chip after the epitaxial sidewall is roughened as shown in some embodiments of the present application;

[0039] Figure 4 This is a schematic diagram of the structure of a 940nm LED chip shown in some embodiments of the present application;

[0040] Figure 5 This is a schematic diagram of the structure of a 940nm LED chip after the epitaxial sidewall is roughened as shown in some other embodiments of the present application;

[0041] Figure 6 This is a schematic structural diagram of another viewing angle of a 940nm LED chip after the epitaxial sidewall is roughened as shown in some other embodiments of the present application;

[0042] Figure 7 This is a schematic diagram of the structure of a 940nm LED chip shown in some other embodiments of the present application;

[0043] Description of the drawings: 1. GaAs substrate; 2. N-AlGaAs extension layer; 3. N-AlGaAs confinement layer; 4. Multi-quantum well active layer; 5. P-AlGaAs confinement layer; 6. P-AlGaAs extension layer; 7. GaAs ohmic contact layer; 71. GaAs vacant portion; 72. GaAs remaining portion; 721. GaAs central island; 722. GaAs annular periphery; 723. GaAs contact lattice; 8. ITO layer; 9. front electrode; 10. passivation layer; 11. back electrode. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present application and its application or use. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0045] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant field may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so that once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0046] In the description of the present application, it should be understood that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present application.

[0047] In the description of the present application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present application; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0048] The present application is further described in detail below with reference to specific embodiments:

[0049] Example 1

[0050] This embodiment provides a 940nm LED chip, please combine Figure 4Specifically, the 940nm LED chip includes a back electrode 11, a GaAs substrate 1, an N-AlGaAs extension layer 2, an N-AlGaAs restriction layer 3, a multi-quantum well active layer 4, a P-AlGaAs restriction layer 5, a P-AlGaAs extension layer 6, a GaAs ohmic contact layer 7, an ITO layer 8 and a front electrode 9, which are arranged in sequence from bottom to top; the GaAs ohmic contact layer 7 adopts a patterned structure, and the GaAs ohmic contact layer 7 includes a GaAs vacant portion 71 and a GaAs remaining portion 72, and the lower surface of the ITO layer 8 is adapted to the structure of the GaAs ohmic contact layer 7, so that the ITO material fills the GaAs vacant portion 71, and the GaAs remaining portion 72 is embedded in the ITO layer 8; the GaAs remaining portion 72 includes a GaAs central island 721, a GaAs contact lattice 723 and a GaAs annular periphery 722, which are arranged in sequence from the inside to the outside;

[0051] The GaAs central island 721 is arranged directly below the front electrode 9, the GaAs annular periphery 722 is arranged around the outside of the GaAs central island 721, and the GaAs annular periphery 722 is arranged at the outer edge of the chip, and the GaAs contact point matrix 723 includes a plurality of GaAs contact block points, and the plurality of GaAs contact block points are distributed between the GaAs central island 721 and the GaAs annular periphery 722.

[0052] In the present application, the GaAs ohmic contact layer 7 adopts a patterned structure, and the gallium arsenide material in the GaAs annular periphery 722 adopts a surrounding manner, which can extend the current to the epitaxy around the chip as much as possible, improve the uniformity of the current expansion, and the GaAs annular periphery 722 set on the outer edge can effectively improve the antistatic ability and reliable stability of the chip. The epitaxial structure of the 940nm LED chip is relatively brittle. By setting the GaAs central island 721 under the front electrode 9, the load-bearing capacity of the front electrode 9 bonding wire can be improved, and the product manufacturing yield can be improved. The GaAs contact dot matrix 723 can evenly expand the current in the luminous area, and finally obtain a uniform current expansion effect in the luminous area. The GaAs ohmic contact layer 7 patterned structure is adapted to the upper ITO material. When the area of ​​the GaAs ohmic contact material is constant, the contact interface area between the two is increased, and the current expansion effect is effectively improved. The embedded structure between the GaAs ohmic contact layer 7 and the ITO layer 8 can improve the reliability and stability of the material as a whole, thereby obtaining a better luminous effect, reliability and antistatic effect, and the overall performance is excellent.

[0053] According to a preferred embodiment, the thickness of the front electrode 9 is 3μm to 4μm, and the preparation material of the front electrode 9 is Cr, Ti and PtAu evaporated in sequence; the front electrode 9 covers a partial area of ​​the upper surface of the chip, the shape of the front electrode 9 is circular, and the front electrode 9 is arranged at the center of the upper surface of the chip.

[0054] According to a preferred embodiment, the shape of the GaAs central island 721 is the same as that of the front electrode 9, the front electrode 9 occupies 10% to 35% of the upper surface area of ​​the chip, and the diameter of the GaAs central island 721 is 1 to 1.1 times the diameter of the front electrode 9, which can further improve the load-bearing effect of the epitaxial electrode bonding wire.

[0055] Please combine Figure 3 The shape of the GaAs annular periphery 722 is consistent with the shape of the chip cutting road, and the outer edge of the GaAs annular periphery 722 coincides with the cutting road pattern.

[0056] According to a preferred embodiment, the side walls around the chip have cutting paths, and the cutting paths are etched from the upper surface of the chip to between the upper surface and the lower surface of the N-AlGaAs extension layer 2; the cutting paths and other areas of the upper surface of the chip except the front electrode 9 are covered with a passivation layer 10, and the passivation layer 10 can effectively protect the front and side walls of the chip after covering, and prevent the formation of leakage channels; further, the passivation layer 10 is made of SiN material, which has high transparency and good passivation effect, and can protect the chip without affecting the emission of light (the 940nm LED chip of this application adopts a through-body light-emitting structure).

[0057] According to a preferred embodiment, the four corners of the side wall of the cutting path are all rounded, wherein the rounded corners are 1 / 6 to 1 / 4 rounded. In the process of making the cutting path, the four corners of the side wall of the cutting path are rounded to further reduce the accumulation of static electricity at the corners, thereby improving the antistatic effect of the chip.

[0058] According to a preferred embodiment, the sidewalls of the chip have a roughened surface; in some embodiments, please combine Figure 7 , the roughened surface covers the entire side wall of the chip; in other embodiments, please combine Figure 4 The roughened surface covers the chip sidewall except the cutting path (or the passivation layer 10 covers the area). By roughening the sidewalls around the chip, the reflection of the sidewalls on light can be reduced, thereby improving the light emitting effect of the sidewalls.

[0059] According to a preferred embodiment, the number of GaAs contact blocks in the GaAs contact point matrix 723 is 4 to 20. Further, the number of GaAs contact blocks is 12. The distribution of the GaAs contact point matrix 723 is combined with Figure 3 and Figure 6 In the GaAs contact matrix 723, several GaAs contact blocks are radially distributed between the GaAs central island 721 and the GaAs annular periphery 722, so as to achieve a more uniform current spreading effect.

[0060] According to a preferred embodiment, the Al element accounts for 10% to 20% in the N-AlGaAs extension layer 2 and the P-AlGaAs extension layer 6 , and the Al element accounts for 25% to 35% in the N-AlGaAs confinement layer 3 and the P-AlGaAs confinement layer 5 .

[0061] According to a preferred embodiment, the surface of the P-AlGaAs extension layer 6 directly below the GaAs vacancy 71 adopts a roughened structure, which can improve the light emission effect at the front side and enhance the bonding force between the P-AlGaAs extension layer 6 and the ITO layer 8 .

[0062] From the above, it can be seen that the 940nm LED chip provided in the embodiment of the present application has the following advantages:

[0063] 1. In this application, the GaAs ohmic contact layer adopts a patterned structure, and the gallium arsenide material in the GaAs annular periphery adopts a surrounding manner, which can extend the current to the epitaxy around the chip as much as possible, improve the uniformity of the current expansion, and the GaAs annular periphery set on the outer edge can effectively improve the antistatic ability and reliable stability of the chip. By setting the GaAs center island, the load-bearing capacity of the front electrode bonding wire can be improved, and the product manufacturing yield can be improved. The GaAs contact lattice can evenly expand the current in the light-emitting area, and finally obtain a uniform current expansion effect in the light-emitting area. The patterned structure of the GaAs ohmic contact layer is compatible with the upper ITO material. When the area of ​​the GaAs ohmic contact material is constant, the contact interface area between the two is increased, and the current expansion effect is effectively improved. The embedded structure between the GaAs ohmic contact layer and the ITO layer can improve the overall reliability and stability of the material, thereby obtaining a better light-emitting effect, reliability and antistatic effect, and the overall performance is excellent.

[0064] 2. The cutting path and other areas of the upper surface of the chip described in the present application except the front electrode are covered with a passivation layer. After being covered with the passivation layer, the front and side walls of the chip can be effectively protected to prevent the formation of leakage channels; further, the passivation layer material is SiN material, which has high transparency and good passivation effect, can protect the chip and does not affect the emission of light. Rounding the four corners of the side wall of the cutting path can further reduce the accumulation of static electricity at the corners, thereby improving the antistatic effect of the chip. By roughening the side walls around the chip, the reflection of light by the side walls can be reduced, thereby improving the light emission effect of the side walls. The surface of the P-AlGaAs extension layer directly below the GaAs vacancy adopts a roughened structure, which can improve the light emission effect on the front and improve the bonding force between the P-AlGaAs extension layer and the ITO layer.

[0065] Example 2

[0066] Please combine Figure 1 to Figure 4 This embodiment provides a method for manufacturing a 940nm LED chip, the manufacturing method comprising:

[0067] Step 1: Provide a GaAs substrate 1 as an epitaxial growth substrate. Figure 1 , setting the program on the MOCVD machine, and sequentially growing the N-AlGaAs extension layer 2, the N-AlGaAs confinement layer 3, the multi-quantum well active layer 4, the P-AlGaAs confinement layer 5, the P-AlGaAs extension layer 6 and the GaAs ohmic contact layer 7 on the GaAs substrate 1;

[0068] Among them, Al accounts for 15% in the N-AlGaAs extension layer 2 and the P-AlGaAs extension layer 6, and Al accounts for 30% in the N-AlGaAs confinement layer 3 and the P-AlGaAs confinement layer 5; the material of the GaAs ohmic contact layer 7 is GaAs, and the thickness is 20nm to 50nm;

[0069] Step 2: Clean the epitaxial wafer with an organic solution, and use positive resist to make a photolithography pattern on the surface of the GaAs ohmic contact layer 7 of the epitaxial wafer, first etch away the GaAs material in the GaAs vacant part 71, and then further roughen the exposed P-AlGaAs extension layer 6 to remove the photoresist;

[0070] The area ratio of the GaAs vacant portion 71 and the GaAs remaining portion 72 in the GaAs ohmic contact layer 7 is set to 8:2, the diameter of the GaAs central island 721 is 80 μm to 100 μm, and the width of the GaAs annular periphery 722 is 7 μm to 10 μm. The roughening solution of the P-AlGaAs extension layer 6 can be a mixed solution of nitric acid and water for roughening, and the roughening depth is 0.8 μm to 1.2 μm; the organic solvent for cleaning the epitaxial wafer can be acetone or isopropyl alcohol; the etching solution of the GaAs ohmic contact layer 7 material can be a mixed solution of phosphoric acid, hydrogen peroxide and water;

[0071] Step 3: Clean the wafer with an organic solution, and directly deposit an ITO layer 8 by electron beam evaporation; wherein the evaporation thickness of the ITO layer 8 is 0.3 μm to 0.5 μm, and the parameters of the electron beam evaporation used for the evaporation of the ITO layer 8 are as follows: the ITO source evaporation rate is 10 angstroms / second, the oxygen flow rate is 10 sccm to 15 sccm, and the temperature is 280° C. to 320° C.; the organic solution for cleaning the wafer can be acetone or isopropanol, etc.;

[0072] Step 4: a patterned front electrode 9 is prepared by negative resist etching and electron beam evaporation, and the front electrode 9 is obtained by lift-off process. The thickness of the front electrode 9 is 3 μm to 4 μm, and the preparation material of the front electrode 9 is Cr, Ti and PtAu which are evaporated in sequence.

[0073] Step 5: Use positive resist to make cutting path pattern, and etch the cutting path pattern by ICP etching. The four corners of the cutting path sidewall are all rounded, with a radius of 15μm to 30μm, and a rounded corner of 1 / 6 to 1 / 4. The etching process is monitored by OES, and the etching depth is 0.5μm to the N-AlGaAs extension layer 2. The surface photoresist is removed by a stripping solution. The schematic diagram of the obtained wafer structure is shown in FIG. Figure 2 and Figure 3 ; Among them, the width of the cutting road is 40μm, the power of ICP etching is 350W, the pressure is 30mTOrr, the BCl3 flow rate is 30sccm, the Cl2 flow rate is 15sccm and the N2 flow rate is 20sccm;

[0074] Step 6: Clean the wafer organically, deposit SiN material by PECVD, use positive photoresist to make the passivation layer 10 pattern, and complete the passivation layer 10 pattern making by wet etching to expose the front electrode 9 wire bonding area;

[0075] Step 7: Grind and thin the GaAs substrate 1 to make a back electrode 11, and perform high temperature annealing; wherein the material of the back electrode 11 includes AuGe and Au deposited in sequence, the deposition thickness of the back electrode 11 is 2000 angstroms, and the temperature used for high temperature annealing is 380° C. to 430° C.;

[0076] Step 8: Glue the front and back of the wafer for protection at the same time, use a blade to cut along the formed cutting path, cut through the chip at a fixed interval to form LED core particles;

[0077] Step 9: The core grain fixed on the crystal expansion ring is immersed in a mixture of nitric acid and water at a temperature of 10°C to 15°C to roughen the side wall to a depth of 1μm to 2μm. After the debonding treatment is completed, the final 940nm LED grain (structure as shown in FIG. Figure 4 as shown).

[0078] Example 3

[0079] This embodiment provides a method for manufacturing a 940nm LED chip. The manufacturing steps of the embodiment 2 are different in that step 5 also includes roughening the sidewalls and bottom of the cutting path. The schematic diagram of the obtained chip structure is shown in FIG. Figure 5 and Figure 6 ; The final prepared 940nm LED grain (structure as Figure 7 As shown), the roughening method is to immerse the wafer in a mixture of nitric acid and water at a temperature of 10°C to 15°C for roughening treatment, and the roughening depth of the sidewall and bottom of the cutting path is 0.8μm to 1.2μm.

[0080] As can be seen from the above, the method for manufacturing the 940nm LED chip provided in the embodiment of the present application has the following advantages: the 940nm LED chip manufactured by the above method has the advantages of simple processing and low cost. Since the method for manufacturing the 940nm LED chip provided in embodiments 2 to 3 of the present application obtains the 940nm LED chip in the above embodiment 1, it also has the advantages of the 940nm LED chip in the above embodiment 1, which will not be described in detail here.

[0081] For content not described in this embodiment, please refer to the relevant description in the rest of this application.

[0082] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present application and not to limit it. Although the present application has been described in detail with reference to the preferred embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present application can still be modified or some technical features can be replaced by equivalents, which should all be included in the scope of the technical solution requested for protection in this application.

Claims

1. A 940nm LED chip, characterized in that: The invention comprises a back electrode, a GaAs substrate, an N-AlGaAs extension layer, an N-AlGaAs restriction layer, a multi-quantum well active layer, a P-AlGaAs restriction layer, a P-AlGaAs extension layer, a GaAs ohmic contact layer, an ITO layer and a front electrode which are arranged in sequence from bottom to top; The GaAs ohmic contact layer adopts a patterned structure, the GaAs ohmic contact layer includes a GaAs vacant portion and a GaAs remaining portion, the lower surface of the ITO layer is adapted to the structure of the GaAs ohmic contact layer, so that the ITO material fills the GaAs vacant portion, and the GaAs remaining portion is embedded in the ITO layer; The GaAs remaining part includes a GaAs central island, a GaAs contact lattice and a GaAs annular periphery arranged in sequence from the inside to the outside; The GaAs central island is arranged directly below the front electrode, the GaAs annular periphery is arranged around the outside of the GaAs central island, and the GaAs annular periphery is arranged at the outer edge of the chip, and the GaAs contact point matrix includes a plurality of GaAs contact block points, and the plurality of GaAs contact block points are distributed between the GaAs central island and the GaAs annular periphery.

2. The 940nm LED chip according to claim 1, characterized in that: The thickness of the front electrode is 3 μm to 4 μm, and the preparation material of the front electrode is Cr, Ti and PtAu which are evaporated in sequence; The front electrode covers a partial area of ​​the upper surface of the chip, the shape of the front electrode is circular, and the front electrode is arranged at the center of the upper surface of the chip.

3. The 940nm LED chip according to claim 2, characterized in that: The shape of the GaAs central island is the same as that of the front electrode. The front electrode occupies 10% to 35% of the upper surface area of ​​the chip. The diameter of the GaAs central island is 1 to 1.1 times the diameter of the front electrode.

4. The 940nm LED chip according to claim 1, characterized in that: The sidewalls of the chip are provided with cutting paths, and the cutting paths are etched from the upper surface of the chip to between the upper surface and the lower surface of the N-AlGaAs extension layer; The cutting paths and other areas of the upper surface of the chip except the front electrode are covered with a passivation layer; The four corners of the side wall of the cutting path are all rounded, wherein the rounded corners are 1 / 6 to 1 / 4 rounded.

5. The 940nm LED chip according to claim 1, characterized in that: The side walls of the chip have roughened surfaces; The roughened surface covers the entire side wall of the chip, or the roughened surface covers the area of ​​the side wall of the chip except the dicing street.

6. The 940nm LED chip according to claim 1, characterized in that: The number of GaAs contact block points in the GaAs contact point matrix is ​​4 to 20.

7. The 940nm LED chip according to claim 1, characterized in that: The Al element accounts for 10% to 20% in the N-AlGaAs extension layer and the P-AlGaAs extension layer, and the Al element accounts for 25% to 35% in the N-AlGaAs confinement layer and the P-AlGaAs confinement layer.

8. The 940nm LED chip according to claim 1, characterized in that: The surface of the P-AlGaAs extension layer directly below the GaAs vacancy has a roughened structure.

9. A method for manufacturing a 940nm LED chip as claimed in any one of claims 1 to 8, characterized in that: The production method comprises: S1, providing a GaAs substrate as an epitaxial structure growth substrate; S2. Set the program on the MOCVD machine, and sequentially grow an N-AlGaAs extension layer, an N-AlGaAs confinement layer, a multi-quantum well active layer, a P-AlGaAs confinement layer, a P-AlGaAs extension layer, and a GaAs ohmic contact layer on the GaAs substrate; S3, cleaning the epitaxial wafer with an organic solution, and using positive resist to make a photolithography pattern on the surface of the GaAs ohmic contact layer of the epitaxial wafer, first etching away the GaAs material in the GaAs vacant part, and then further roughening the exposed P-AlGaAs extension layer to remove the photoresist; S4, cleaning the wafer with an organic solution, and directly depositing an ITO layer by electron beam evaporation; S5, using negative resist etching and electron beam evaporation to make a patterned front electrode, and peeling it off through a lift-off process to obtain a front electrode; S6, using positive resist to make cutting road patterns, etching the cutting road patterns by ICP etching, monitoring the etching process by OES, etching to a depth between the upper surface and the lower surface of the N-AlGaAs extension layer, and removing the surface photoresist by a stripping solution; S7, cleaning the wafer organically, depositing SiN material by PECVD, making a passivation layer pattern by positive photoresist, and completing the passivation layer pattern making by wet etching to expose the front electrode wire bonding area; S8, grinding and thinning the GaAs substrate, making a back electrode, and performing high temperature annealing; S9, applying glue to the front and back of the wafer for protection at the same time, using a blade to cut along the formed cutting path, cutting through the chip at a fixed interval to form LED core particles; S10, immersing the core grain fixed on the crystal expansion ring in a mixture of nitric acid and water at a temperature of 10°C to 15°C to roughen the side wall, and then performing a post-resist removal treatment to obtain the final 940nm LED grain.

10. The method for manufacturing a 940nm LED chip according to claim 9, characterized in that: The manufacturing method of S6 is to use positive photoresist to make a cutting path pattern, and to etch the cutting path pattern through ICP etching. The etching process is monitored by OES, and the etching depth is between the upper surface and the lower surface of the N-AlGaAs extension layer. Then, the side wall and bottom of the etched wafer cutting path are roughened, and the surface photoresist is removed by a degumming solution.

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