Display panel and display device

Abstract

The present application discloses a display panel and a display device, which relate to the display field, and include: an array substrate, a circuit board located on the second surface of the array substrate, and a buffer layer located between the second surface of the array substrate and the circuit board, wherein the connecting wire is located between the buffer layer and the circuit board, and in a direction perpendicular to the plane where the array substrate is located, the buffer layer covers the binding area of ​​the circuit board and the connecting wire, so that when binding the circuit board and the connecting wire, the mechanical strength of the buffer layer can be used to buffer the binding pressure of the circuit board and the connecting wire during the binding process, thereby improving the force uniformity of the second surface of the array substrate, reducing the pressure degree on the display surface of the display panel, reducing the probability of deformation of the film layer on the display side of the display panel due to high pressure, alleviating the indentation phenomenon on the display surface of the display panel, and improving the display quality of the display surface of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device including the display panel. Background Art

[0002] Micro-LED display screens have a simple structure, usually consisting of three major parts: TFT driver, LED chip, and packaging structure. Compared with LCD, Micro-LED has advantages such as high brightness, high contrast, wide color gamut, and fast response. Compared with OLED, Micro-LED has technical advantages such as better reliability and longer life. However, when Micro-LED display panels are currently used in borderless display or negative border display scenarios, there are indentations on the display surface, which affects the display effect. Summary of the invention

[0003] In view of the above problems, the present application provides a display panel and a display device including the display panel to achieve the purpose of alleviating the phenomenon of indentation on the display surface of the Micro-LED display panel and improving the display quality. The specific solution is as follows:

[0004] A display panel, comprising:

[0005] An array substrate, the array substrate comprising a first surface and a second surface opposite to each other;

[0006] A plurality of light emitting units located on the first surface of the array substrate;

[0007] a buffer layer located on the second surface of the array substrate;

[0008] A circuit board located on a side of the buffer layer away from the array substrate;

[0009] A connecting wire, one end of which is bound to a side of the circuit board facing the buffer layer, and the other end of which extends from a side surface of the array substrate to the first surface of the array substrate and is electrically connected to a pad on the first surface of the array substrate;

[0010] In a first direction, the buffer layer covers the connection wiring and the binding area of ​​the circuit board, and the first direction is perpendicular to the plane where the display panel is located.

[0011] A display device comprises at least one display panel, wherein the display panel is the above-mentioned display panel.

[0012] In the display panel and the display device provided in the embodiments of the present application, a buffer layer is arranged between the second surface of the array substrate and the circuit board, the connecting wire is located between the buffer layer and the circuit board, and in the direction perpendicular to the plane where the array substrate is located, the buffer layer covers the binding area of ​​the circuit board and the connecting wire, so that when binding the circuit board and the connecting wire, the mechanical strength of the buffer layer can be used to buffer the binding pressure of the circuit board and the connecting wire during the binding process, thereby improving the force uniformity of the second surface of the array substrate, reducing the pressure degree on the display surface of the display panel, reducing the probability of deformation of the film layer on the display side of the display panel due to high pressure, alleviating the indentation phenomenon on the display surface of the display panel, and improving the display quality of the display surface of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0014] Figure 1 A schematic diagram of the structure of a current display panel;

[0015] Figure 2 for Figure 1 Schematic diagram of the display effect of area A in the display panel;

[0016] Figure 3 A schematic diagram of the structure of a display panel provided in this application;

[0017] Figure 4 A schematic diagram of the structure of another display panel provided in this application;

[0018] Figure 5 A schematic diagram of the structure of another display panel provided in the present application;

[0019] Figure 6 A schematic structural diagram of a second surface of an array substrate in another display panel provided by the present application;

[0020] Figure 7 A schematic structural diagram of a second surface of an array substrate in another display panel provided by the present application;

[0021] Figure 8 A schematic structural diagram of a second surface of an array substrate in another display panel provided by the present application;

[0022] Fig. 9 A schematic diagram of the relative positions of an array substrate and a supporting layer in another display panel provided by the present application;

[0023] Fig.10 A schematic diagram of the relative positions of an array substrate and a supporting layer in another display panel provided by the present application;

[0024] Fig.11 A schematic structural diagram of a second surface of an array substrate in another display panel provided by the present application;

[0025] Fig.12 A schematic diagram of the structure of another display panel provided in the present application;

[0026] Fig.13 A schematic diagram of the structure of a display device provided in this application;

[0027] Fig.14 This is a schematic structural diagram of another display device provided in the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0029] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0030] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0031] As described in the background technology section, when the current Micro-LED display panel is used in borderless display or negative border display scenarios, there are indentations on its display surface, which affects the display effect.

[0032] This is because the current way of achieving borderless or negative border display of Micro-LED display panels is to guide the circuits on the front of the display panel to the back of the display panel through side wiring, and then bind the circuit board electrically connected to the side wiring on the back of the display panel. Figure 1As shown, the hot pressing head B needs to be used to continuously act on the binding position of the circuit board and the back of the display panel for several seconds, and the temperature can reach 185°C and the pressure can reach 5Gpa during the process. However, at least part of the film layer on the display side of the display panel is prone to deformation or physical property changes under high temperature and high pressure environment, making the local reflectivity of the display surface of the display panel different from that of other areas, such as Figure 2 As shown, Figure 2 for Figure 1 The schematic diagram of the display effect in area A in the middle causes an indentation on the display surface of the display panel. This indentation will be more obvious under strong ambient light, thus affecting the display effect.

[0033] In view of this, an embodiment of the present application provides a display panel, such as Figure 3 As shown, the display panel includes:

[0034] An array substrate 10, wherein the array substrate 10 comprises a first surface and a second surface opposite to each other;

[0035] A plurality of light emitting units 20 located on the first surface of the array substrate 10;

[0036] A buffer layer 30 located on the second surface of the array substrate 10;

[0037] A circuit board 40 located on a side of the buffer layer 30 away from the array substrate 10, the circuit board 40 may be a driving backplane of the display panel, and optionally, the circuit board 40 is a flexible circuit board, and the integrated circuit of the display panel is fixed on the flexible circuit board by means of COF, wherein COF (Chip On Flex, or Chip On Film), commonly known as chip on film, is a grain soft film assembly technology for fixing an integrated circuit (IC) on a flexible circuit board;

[0038] A connecting wire 50, one end of which is bound to the side of the circuit board 40 facing the buffer layer 30, and the other end of which extends from the side of the array substrate 10 to the first surface of the array substrate 10 and is electrically connected to the pad on the first surface of the array substrate 10;

[0039] In the first direction X, the buffer layer 30 covers the binding area of ​​the connecting wire 50 and the circuit board 40, that is, in the first direction X, the buffer layer 30 covers the binding area C, and the binding area C is the binding area of ​​the connecting wire 50 and the circuit board 30. The first direction X is perpendicular to the plane where the display panel is located.

[0040] In the display panel provided in the embodiment of the present application, a buffer layer is arranged between the second surface of the array substrate and the circuit board, the connecting wire is located between the buffer layer and the circuit board, and in the direction perpendicular to the plane where the array substrate is located, the buffer layer covers the binding area of ​​the circuit board and the connecting wire, so that when binding the circuit board and the connecting wire, the mechanical strength of the buffer layer can be used to buffer the binding pressure of the circuit board and the connecting wire during the binding process, thereby improving the force uniformity of the second surface of the array substrate, reducing the pressure degree on the display surface of the display panel, reducing the probability of deformation of the film layer on the display side of the display panel due to high pressure, alleviating the indentation phenomenon on the display surface of the display panel, and improving the display quality of the display surface of the display panel.

[0041] Optionally, in one embodiment of the present application, the buffer layer is a thermally conductive buffer layer, so that when binding the circuit board and the connecting wires, the thermal conductivity of the buffer layer can be used to dissipate the heat in the binding process of the circuit board and the connecting wires, thereby improving the heating uniformity of the second surface of the array substrate, reducing the temperature height to which the display surface of the display panel is subjected, reducing the probability of deformation of the film layer on the display side of the display panel due to high temperature, alleviating the indentation phenomenon on the display surface of the display panel, and improving the display quality of the display surface of the display panel.

[0042] Optionally, in one embodiment of the present application, continue as Figure 1 As shown, the display panel further includes: a shading layer 21 located between adjacent light-emitting units 20, and the shading layer 21 can be a black shading layer, such as a black ink layer, to reduce the amount of light reflected from the display surface of the display panel and improve the display quality of the display panel.

[0043] Continue as Figure 1 As shown, in one embodiment of the present application, the display panel further includes: an encapsulation layer 22 covering the plurality of light-emitting units 20. Optionally, the encapsulation layer 22 is a transparent encapsulation layer so as to encapsulate and protect the plurality of light-emitting units 20 without affecting the light emission of the light-emitting units.

[0044] Continue as Figure 1 As shown, in one embodiment of the present application, the display panel further includes: a protective layer 51 covering the exposed portion of the connecting wire 50, wherein the protective layer 51 is used to protect the connecting wire 50 and reduce the probability of the connecting wire 50 being oxidized by water oxygen in the environment.

[0045] Optionally, in one embodiment of the present application, Figure 4As shown, the display panel includes a functional film 60 located on the side of the light-emitting unit 20 away from the array substrate 10, and the functional layer 60 has at least one of anti-glare, anti-reflection and anti-fingerprint functions. Specifically, the material of the functional layer 60 can be a polymer material such as TAC (cellulose triacetate film) or PET (polyethylene terephthalate), which is not limited in this application and depends on the specific situation.

[0046] Based on the above embodiments, in one embodiment of the present application, the functional layer 60 is fixed to the side of the encapsulation layer 22 away from the light-emitting unit 20 by a photosensitive adhesive 61, but the present application is not limited to this. In other embodiments of the present application, the functional layer 60 can also be fixed to the side of the encapsulation layer 22 away from the light-emitting unit by other means, depending on the specific circumstances.

[0047] It should be noted that the functional layer and the photosensitive adhesive between the functional layer and the encapsulation layer are prone to deformation or changes in physical properties under high temperature and high pressure, which makes the local reflectivity inconsistent with other areas. Especially under the anti-reflection effect of the anti-reflection film, this inconsistency will become more obvious. In this embodiment, the buffer layer is located between the connecting wire and the second surface of the array substrate. When binding the circuit board and the connecting wire, the buffer layer can be used to even out the pressure and temperature of the binding position of the circuit board and the connecting wire, reduce the pressure and temperature of the functional film during the binding process of the connecting wire and the circuit board, alleviate the indentation phenomenon of the display surface of the display panel, and improve the display quality of the display surface of the display panel.

[0048] Optionally, in one embodiment of the present application, continue as Figure 4 As shown, in the direction parallel to the plane where the display panel is located, the area of ​​the functional film 60 is larger than the area of ​​the array substrate 10. In this embodiment, the display panel also includes: a frame sealing glue 63 located on the side of the functional film 60, and the sealing glue 63 also extends to cover the side of the array substrate to protect the side of the functional film 60 and the array substrate 10. Specifically, the sealing glue 63 can be a low-resistance glue, but the present application does not limit this, and it depends on the specific situation.

[0049] It should be noted that, in the above embodiment, in the direction parallel to the plane where the display panel is located, there is a certain gap between the packaging glue 63 and the side of the array substrate 10. Optionally, based on the above embodiment, in an embodiment of the present application, the display panel also includes: a filling glue filling the gap between the packaging glue 63 and the side of the array substrate 10 to prevent the functional film 60 from collapsing in the gap between the packaging glue 63 and the array substrate 10.

[0050] Based on any of the above embodiments, in one embodiment of the present application, the buffer layer is a metal buffer layer, so that the buffer layer has both high mechanical strength and good thermal conductivity. It should be noted that since metal has electrical conductivity, in this embodiment, Figure 4 As shown, the display panel further includes: an insulating layer 70 located between the connecting wire 50 and the buffer layer 30, so as to utilize the insulating layer 70 to realize electrical insulation between the connecting wire 50 and the buffer layer 30, and avoid the short circuit between the buffer layer 30 and the connecting wire 50. However, the present application does not limit this, and in other embodiments of the present application, the buffer layer may also be other material layers having both high mechanical strength and good thermal conductivity, depending on the specific situation.

[0051] Optionally, in one embodiment of the present application, the metal buffer layer may be an aluminum plate, a steel plate, or other metal buffer layers, and the present application does not limit this, and it depends on the specific circumstances.

[0052] On the basis of any of the above embodiments, in an embodiment of the present application, in a plane within the plane where the display panel is located, the contact area between the connecting wire and the circuit board is a first area, and the buffer layer has a second area, and the second area is not less than twice the first area, so that during the binding process of the connecting wire and the circuit board, the buffer layer can have a better conductive effect on the heat and pressure generated during the binding process of the connecting wire and the buffer layer, thereby improving the force uniformity and heat uniformity of the second side of the array substrate, reducing the probability and degree of deformation of at least part of the film layer on the display side of the display panel due to high temperature and high pressure, alleviating the indentation phenomenon on the display surface of the display panel, and improving the display quality of the display surface of the display panel.

[0053] Optionally, in one embodiment of the present application, in a plane within the plane where the display panel is located, the contact area between the connecting trace and the circuit board is a first area, and the buffer layer has a second area, and the second area is larger than twice the first area, so as to improve the heat dissipation capacity of the buffer layer, reduce the probability and degree of deformation of at least part of the film layer on the display side of the display panel due to high temperature, and improve the display quality of the display surface of the display panel.

[0054] It should be noted that, since the connecting wiring is only located in a partial area of ​​the buffer layer, therefore, based on any of the above embodiments, in an embodiment of the present application, continue as follows Figure 4As shown, the buffer layer 30 includes a first side surface 31, the connecting trace 50 includes a first portion located on the first side surface 31, and in a second direction Y, the first side surface 31 covers the first portion, and the second direction Y is parallel to the plane where the display panel is located. Figure 4 As shown, the angle α between the first side surface 31 and the surface of the buffer layer 30 facing the array substrate 10 is less than 80°, that is, the angle α between the side surface of the buffer layer 30 on which the connecting wire 50 is arranged and the surface of the buffer layer 30 facing the array substrate 10 is less than 80°, so that when the connecting wire 50 climbs from the second surface of the array substrate 10 to the side surface of the buffer layer 30, the probability of the connecting wire 50 being broken is reduced. It should be noted that the present application does not limit the angle between the other side surfaces of the buffer layer on which the connecting wires are not arranged and the surface of the buffer layer facing the array substrate, which depends on the specific situation.

[0055] Optionally, in one embodiment of the present application, the angle between the first side surface and the surface of the buffer layer facing the array substrate is less than 60°, that is, the angle between the side surface of the buffer layer where the connection trace is provided and the surface of the buffer layer facing the array substrate is less than 60°, so that when the connection trace climbs from the second surface of the array substrate to the side surface of the buffer layer, the probability of the connection trace being broken is further reduced. It should be noted that the present application does not limit the angle between the other side surfaces of the buffer layer where the connection trace is not provided and the surface of the buffer layer facing the array substrate, which depends on the specific situation.

[0056] Optionally, in one embodiment of the present application, the connecting trace is a copper trace or a gold trace, so that the connecting trace has good flexibility and low resistivity, thereby reducing the signal attenuation of the connecting trace when transmitting signals, and at the same time, further reducing the probability of the connecting trace breaking when climbing from the second surface of the array substrate to the side of the buffer layer.

[0057] Specifically, based on the above embodiment, in one embodiment of the present application, continue as follows Figure 4 As shown, the first side surface 31 may be a plane to reduce the process difficulty when the connecting trace 50 is formed on the first side surface 31; in another embodiment of the present application, as shown Figure 5As shown, the first side surface 31 is an arc-shaped surface, so as to further reduce the probability of the connection line 50 being broken when the connection line 50 climbs from the second surface of the array substrate 10 to the first side surface 31 of the buffer layer 30. In other embodiments of the present application, the first side surface 31 can also be in other forms, depending on the specific situation.

[0058] Based on any of the above embodiments, in one embodiment of the present application, continue as follows Figure 4 As shown, the buffer layer 30 includes a first surface 32 away from the array substrate 10 and a second surface 33 close to the array substrate 10 in the first direction X. Optionally, in a plane parallel to the plane where the display panel is located, the area of ​​the first surface 32 of the buffer layer 30 is smaller than the area of ​​the second surface 33 of the buffer layer 30. For example, in the first direction X, the cross-sectional view of the buffer layer is an inverted trapezoid, but the present application is not limited to this. In other embodiments of the present application, in the first direction X, the cross-sectional view of the buffer layer can also be other shapes, depending on the specific circumstances.

[0059] Based on any of the above embodiments, in one embodiment of the present application, Figure 6 As shown, the circuit board 40 includes a first sub-circuit board 41 and a second sub-circuit board 42, and the buffer layer 30 includes a first buffer part 34 and a second buffer part 35. The first sub-circuit board 41 is bound to the side of the first buffer part 34 away from the array substrate 10, so that the high temperature and high pressure generated in the binding process of the first sub-circuit board 41 and the connecting wiring 50 are buffered by the first buffer part 34, thereby reducing the probability and degree of deformation of at least part of the film layer on the display side of the display panel due to high temperature and high pressure, alleviating the indentation phenomenon of the display surface of the display panel, and improving the display quality of the display surface of the display panel; similarly, the second sub-circuit board 42 is bound to the side of the second buffer part 35 away from the array substrate 10, so that the high temperature and high pressure generated in the binding process of the second sub-circuit board 42 and the connecting wiring 50 are buffered by the second buffer part 35, thereby reducing the probability and degree of deformation of at least part of the film layer on the display side of the display panel due to high temperature and high pressure, alleviating the indentation phenomenon of the display surface of the display panel, and improving the display quality of the display surface of the display panel.

[0060] Optionally, based on the above embodiment, in one embodiment of the present application, continue as follows Figure 6As shown, the connecting wire 50 includes a first wire 51 and a second wire 52, the first sub-circuit board 41 is electrically connected to the first wire 51, the second sub-circuit board 42 is electrically connected to the second wire 52, and the first wire 51 and the second wire 52 transmit different signals, so that the first wire 51 and the second wire 52 that transmit different signals in the display panel are transmitted through different first sub-circuit boards 41 and second sub-circuit boards 42, and then the display panel can be driven by two first sub-circuit boards 41 and second sub-circuit boards 42 with smaller driving capabilities, avoiding the phenomenon that the driving capability of the circuit board is insufficient when the display panel is driven by one circuit board. However, the present application does not limit this, and it depends on the specific situation.

[0061] Specifically, in one embodiment of the present application, the first wiring is used to transmit a power signal, and the second wiring is used to transmit a communication signal, but the present application does not limit this, and it depends on the specific situation.

[0062] Optionally, in one embodiment of the present application, continue as Figure 6 As shown, the first sub-circuit board 41 is electrically connected to the first trace 51 through the first conductive structure 43, and the second sub-circuit board 42 is electrically connected to the second trace 52 through the second conductive structure 44, wherein the first conductive structure and the second conductive structure can be conductive photosensitive adhesives, such as ACF (Anisotropic Conductive Film) photosensitive adhesives, i.e., anisotropic conductive films, which is not limited in the present application and depends on the specific circumstances.

[0063] Based on any of the above embodiments, in one embodiment of the present application, Figure 6 and Figure 7 As shown, the first sub-circuit board 41 is located on the second surface of the array substrate 10 and close to the first side of the array substrate 10; the second sub-circuit board 42 is located on the second surface of the array substrate 10 and close to the second side of the array substrate 10. Optionally, in an embodiment of the present application, continue as Figure 6 As shown in FIG. 1 , the first side edge of the array substrate 10 and the second side edge of the array substrate 10 are the same side edge, so that the first sub-circuit board 41 and the second sub-circuit board 42 are arranged on the same side of the second surface of the array substrate 10, thereby facilitating the layout of the first buffer portion 34 and the second buffer portion 35; in another embodiment of the present application, as Figure 7As shown, the first side of the array substrate 10 and the second side of the array substrate 10 are different sides of the array substrate 10, so that the first sub-circuit board 41 and the second sub-circuit board 42 are located near different sides of the second surface of the array substrate 10, thereby facilitating the layout of the first sub-circuit board 41 and the second sub-circuit board 42, but the present application does not limit this and it depends on the specific situation.

[0064] Optionally, in one embodiment of the present application, continue as Figure 6 and Figure 7 As shown, the first buffer portion 34 and the second buffer portion 35 are two independent buffer portions, so that the probability and degree of deformation of at least part of the film layer on the display side of the display panel due to high temperature and high pressure are reduced by utilizing the first buffer portion 34 and the second buffer portion 35, the indentation phenomenon of the display surface of the display panel is alleviated, and the display quality of the display surface of the display panel is improved, while the overall area of ​​the buffer layer is reduced as much as possible.

[0065] In another embodiment of the present application, Figure 8 As shown, the first buffer portion 34 and the second buffer portion 35 are different areas in the same buffer portion, so that different areas in the same buffer portion are utilized to reduce the probability and degree of deformation of at least part of the film layer on the display side of the display panel due to high temperature and high pressure during the binding process of the first sub-circuit board 41 and the second sub-circuit board 42, thereby simplifying the process flow of forming the buffer layer while alleviating the indentation phenomenon of the display surface of the display panel and improving the display quality of the display surface of the display panel.

[0066] Optionally, in an embodiment of the present application, when the first buffer portion and the second buffer portion are different regions in the same buffer portion, in a plane parallel to the array substrate, the area of ​​the buffer layer may be equal to the sum of the area of ​​the first buffer portion and the area of ​​the second buffer portion, wherein the area of ​​the first buffer portion is not less than the sum of the binding area of ​​the first sub-circuit board and the contact area of ​​the first trace and the buffer layer; the area of ​​the second buffer portion is not less than the sum of the binding area of ​​the second sub-circuit board and the contact area of ​​the second trace and the buffer layer. Specifically, in this embodiment, the area of ​​the buffer layer is S0, the area of ​​the first buffer portion is S1, the area of ​​the second buffer portion is S2, the binding area of ​​the first sub-circuit board is S11, the contact area of ​​the first trace and the first buffer portion is S12, the binding area of ​​the second sub-circuit board is S21, and the contact area of ​​the second trace and the second buffer portion is S22, wherein S1≥S11+S12, S2≥S21+S22, and S0=S1+S2.

[0067] In another embodiment of the present application, when the first buffer portion and the second buffer portion are different regions in the same buffer portion, in a plane parallel to the array substrate, the area of ​​the buffer layer may also be greater than the sum of the areas of the first buffer portion and the second buffer portion, wherein the area of ​​the first buffer portion is not less than the sum of the binding area of ​​the first sub-circuit board and the contact area of ​​the first trace with the buffer layer; the area of ​​the second buffer portion is not less than the sum of the binding area of ​​the second sub-circuit board and the contact area of ​​the second trace with the buffer layer. Specifically, in this embodiment, the area of ​​the buffer layer is S0, the area of ​​the first buffer portion is S1, the area of ​​the second buffer portion is S2, the binding area of ​​the first sub-circuit board is S11, the contact area of ​​the first trace and the first buffer portion is S12, the binding area of ​​the second sub-circuit board is S21, and the contact area of ​​the second trace and the second buffer portion is S22, wherein S1≥S11+S12, S2≥S21+S22, S0>S1+S2.

[0068] Optionally, in one embodiment of the present application, in a plane parallel to the array substrate, the area of ​​the buffer layer and the area of ​​the second surface of the array substrate meet the same condition, that is, the area of ​​the buffer layer and the area of ​​the second surface of the array substrate are the same, such as Fig. 9 as shown, or substantially the same as Fig.10 It should be noted that, in the specific production process, due to certain process errors, therefore, in an optional embodiment of the present application, continue as Figure 8 As shown, in the first direction X, the array substrate 10 covers the buffer layer 30, and the distance D between the boundary of the buffer layer 30 and the boundary of the array substrate 10 is not greater than 5 mm, so as to ensure that the boundary of the buffer layer 30 does not exceed the boundary of the second surface of the array substrate 10 under the premise that the area of ​​the buffer layer 30 and the area of ​​the second surface of the array substrate 10 meet the same conditions. However, this application does not limit this, and it depends on the specific situation.

[0069] Based on any of the above embodiments, in one embodiment of the present application, Fig.11As shown, if the area of ​​the buffer layer 30 is much smaller than the area of ​​the second surface of the array substrate 10, the display panel also includes: a heat dissipation layer 80 located on the second surface of the array substrate 10, and the heat dissipation layer 80 and the buffer layer 30 are located in different areas of the second surface of the array substrate 10, so as to utilize the buffer layer 30 to reduce the probability and degree of deformation of at least part of the film layer on the display side of the display panel due to high temperature and high pressure, alleviate the indentation phenomenon of the display surface of the display panel, improve the display quality of the display surface of the display panel, and utilize the heat dissipation layer 80 to dissipate the heat generated in the array substrate 10 to avoid the temperature of the array substrate 10 being too high and affecting the display of the display panel.

[0070] In another embodiment of the present application, continue as Figure 8 As shown, if the area of ​​the buffer layer 30 and the area of ​​the second surface of the array substrate 10 meet the same conditions, the buffer layer 30 is a thermally conductive buffer layer, that is, the buffer layer 30 is also a heat dissipation layer. Therefore, the buffer layer 30 is used to reduce the probability and degree of deformation of at least part of the film layer on the display side of the display panel due to high temperature and high pressure, alleviate the indentation phenomenon of the display surface of the display panel, and improve the display quality of the display surface of the display panel. In addition, the buffer layer 30 is used to dissipate the heat generated in the array substrate 10 to avoid the temperature of the array substrate being too high, which affects the display of the display panel.

[0071] It should be noted that when the buffer layer is a metal buffer layer, the supporting strength of the metal buffer layer can reduce the probability and degree of deformation of at least part of the film layer on the display side of the display panel due to high temperature and high pressure, alleviate the indentation phenomenon on the display surface of the display panel, and improve the display quality of the display surface of the display panel. The thermal conductivity of the metal buffer layer can dissipate the heat generated in the array substrate to avoid the temperature of the array substrate being too high and affecting the display of the display panel.

[0072] Optionally, in one embodiment of the present application, the insulating layer between the metal buffer layer and the connecting trace is a high temperature resistant insulating layer, so as to achieve electrical insulation between the metal buffer layer and the connecting trace without being deformed by the high temperature during the circuit board binding process.

[0073] It should be noted that, in this embodiment, the material of the insulating layer can be an organic material or an inorganic material. Since it is difficult to make a very thin inorganic layer by the process of making an organic layer, therefore, in an optional embodiment of the present application, when the insulating layer is an organic material, the thickness of the insulating layer ranges from 3μm to 20μm, so as to ensure the electrical insulation performance and support strength of the insulating layer, while reducing the process difficulty of the insulating layer; and since the inorganic layer has good high temperature resistance and the process can achieve the production of a thinner film layer, therefore, in an optional embodiment of the present application, when the insulating layer is an inorganic material, the thickness of the insulating layer does not exceed 5μm, so as to reduce the thickness of the insulating layer on the basis of ensuring the electrical insulation performance and support strength of the insulating layer, so that the display panel is suitable for the development trend of thinness, but the present application does not limit this, it depends on the specific situation.

[0074] Specifically, in one embodiment of the present application, the material of the insulating layer may be acrylic to achieve electrical insulation between the metal buffer layer and the connecting traces, and will not be deformed by the high temperature during the circuit board binding process, but the present application is not limited to this. In other embodiments of the present application, the material of the insulating layer may also be polyester or other insulating materials that can withstand high temperatures (such as 185°C), depending on the specific circumstances.

[0075] Based on any of the above embodiments, in one embodiment of the present application, Fig.12 As shown, when an insulating layer 70 is provided between the buffer layer 30 and the connecting wire 50 , the insulating layer 70 is at least located in the overlapping area of ​​the buffer layer 30 and the connecting wire 50 to achieve insulation between the buffer layer 30 and the connecting wire 50 .

[0076] Optionally, in one embodiment of the present application, continue as Fig.12 As shown, the insulating layer 70 is located in the overlapping area of ​​the buffer layer 30 and the connecting wire 50 , so that the insulating layer 70 can reduce the area of ​​the insulating layer 70 while electrically insulating the buffer layer 30 and the connecting wire 50 .

[0077] In another embodiment of the present application, continue as Figure 4 As shown, the insulating layer 70 may also cover all exposed surfaces of the buffer layer 30, that is, the insulating layer 70 covers the buffer layer 30, to facilitate the production of the insulating layer, but the present application does not limit this, which depends on the specific circumstances.

[0078] Based on any of the above embodiments, in one embodiment of the present application, the thickness of the buffer layer is in the range of 0.1 mm to 0.6 mm, so as to ensure the supporting strength of the buffer layer while avoiding excessive increase in the overall thickness and cost of the display panel due to the excessive thickness of the buffer layer. However, the present application does not impose any limitation on this, and it depends on the specific situation.

[0079] In addition, the present application also provides a display device, such as Fig.13 As shown, the display device 200 includes at least one display panel 100, which can be the display panel provided by any of the above embodiments. Since the display panel 300 has been described in detail in the above embodiments, it will not be repeated here.

[0080] Optionally, in this embodiment, the display device can be a mobile phone, a tablet computer, a wearable device, a vehicle-mounted device, an augmented reality (AR) / virtual reality (VR) device, a laptop computer, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (PDA), etc., and the embodiments of the present application do not impose any restrictions on this.

[0081] Since in the aforementioned display panel, the connection traces extend from the first surface of the array substrate along the side surface of the array substrate to the second surface of the array substrate, and the circuit board is bound to the connection traces from the back surface of the array substrate to achieve electrical connection with the connection traces, the display panel provided in the embodiment of the present application can achieve borderless display or negative border display. Therefore, in one embodiment of the present application, if Fig.14 As shown, the display device 200 may include at least two display panels 100, and the at least two display panels 100 are spliced ​​for display, so that the display device is a spliced ​​display device, which can be applied to some large display scenes, such as exhibition displays, billboards, conference rooms or TV walls, etc., but the present application does not limit this, and it depends on the specific situation.

[0082] In summary, in the display panel and the display device provided in the embodiments of the present application, a buffer layer is arranged between the second surface of the array substrate and the circuit board, the connecting wire is located between the buffer layer and the circuit board, and in the direction perpendicular to the plane where the array substrate is located, the buffer layer covers the binding area of ​​the circuit board and the connecting wire, so that when binding the circuit board and the connecting wire, the mechanical strength of the buffer layer can be used to buffer the binding pressure of the circuit board and the connecting wire during the binding process, thereby improving the force uniformity of the second surface of the array substrate, reducing the degree of pressure on the display surface of the display panel, reducing the probability of deformation of the film layer on the display side of the display panel due to high pressure, alleviating the indentation phenomenon on the display surface of the display panel, and improving the display quality of the display surface of the display panel.

[0083] In this specification, each embodiment is described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0084] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same reference numerals throughout the embodiments of the specification mark the same structure. In addition, for the purpose of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "includes", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that the article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such articles or equipment. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the articles or equipment including the above elements.

[0085] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: An array substrate, the array substrate comprising a first surface and a second surface opposite to each other; A plurality of light emitting units located on the first surface of the array substrate; a buffer layer located on the second surface of the array substrate; A circuit board located on a side of the buffer layer away from the array substrate; A connecting wire, one end of which is bound to a side of the circuit board facing the buffer layer, and the other end of which extends from a side surface of the array substrate to the first surface of the array substrate and is electrically connected to a pad on the first surface of the array substrate; In a first direction, the buffer layer covers the connection wiring and the binding area of ​​the circuit board, and the first direction is perpendicular to the plane where the display panel is located.

2. The display panel according to claim 1, characterized in that: The buffer layer is a metal buffer layer; the display panel further comprises: an insulating layer located between the connecting wiring and the buffer layer.

3. The display panel according to claim 1, characterized in that: In a plane parallel to the display panel, the contact area between the connecting wire and the circuit board is a first area, and the buffer layer has a second area, which is not less than twice the first area.

4. The display panel according to claim 1, characterized in that: The buffer layer includes a first side surface, the connecting trace includes a first portion located on the first side surface, and in a second direction, the first side surface covers the first portion, and the second direction is parallel to the plane where the display panel is located; An angle between the first side surface and a surface of the buffer layer facing the array substrate is less than 80°.

5. The display panel according to claim 4, characterized in that: The first side surface is a plane or an arc-shaped surface.

6. The display panel according to claim 1, characterized in that: The circuit board includes a first sub-circuit board and a second sub-circuit board; the buffer layer includes a first buffer part and a second buffer part, the first sub-circuit board is bound to a side of the first buffer part away from the array substrate, and the second sub-circuit board is bound to a side of the second buffer part away from the array substrate.

7. The display panel according to claim 6, characterized in that: The connecting line includes a first line and a second line. The first sub-circuit board is electrically connected to the first line, and the second sub-circuit board is electrically connected to the second line. The signals transmitted in the first line and the second line are different.

8. The display panel according to claim 6, characterized in that: The first sub-circuit board is located on the second surface of the array substrate and is close to the first side of the array substrate; the second sub-circuit board is located on the second surface of the array substrate and is close to the second side of the array substrate; The first side edge of the array substrate and the second side edge of the array substrate are the same side edge; or, the first side edge of the array substrate and the second side edge of the array substrate are different sides.

9. The display panel according to claim 6, characterized in that: The first buffer portion and the second buffer portion are two buffer portions independent of each other.

10. The display panel according to claim 6, characterized in that: The first buffer portion and the second buffer portion are different areas in the same buffer portion.

11. The display panel according to claim 1, characterized in that: In the first direction, the array substrate covers the buffer layer, and a distance between a boundary of the buffer layer and a boundary of the array substrate is no greater than 5 mm.

12. The display panel according to claim 11, characterized in that: The buffer layer is a heat dissipation layer.

13. The display panel according to claim 1, characterized in that: It also includes a heat dissipation layer located on the second surface of the array substrate, and the heat dissipation layer and the buffer layer correspond to different areas of the second surface of the array substrate.

14. The display panel according to claim 2, characterized in that: The insulating layer is an organic layer, and the thickness of the organic layer ranges from 3 μm to 20 μm.

15. The display panel according to claim 2, characterized in that: The insulating layer is made of acrylic acid.

16. The display panel according to claim 2, characterized in that: The insulating layer is at least located in an overlapping area between the buffer layer and the connecting wiring.

17. The display panel according to claim 16, characterized in that: The insulating layer covers the buffer layer.

18. The display panel according to claim 1, characterized in that: The thickness of the buffer layer ranges from 0.1 mm to 0.6 mm.

19. A display device, characterized in that: It comprises at least one display panel, and the display panel is the display panel according to any one of claims 1 to 18.

20. The display device according to claim 19, characterized in that It comprises at least two display panels, and at least two display panels are spliced ​​for display.

Images