An artificial synaptic device based on molybdenum disulfide ink, its array, and its fabrication method.

Abstract

This invention belongs to the field of semiconductor materials technology, specifically relating to an artificial synapse device based on molybdenum disulfide ink, its array, and fabrication method. The device mainly includes a substrate, a channel, source / drain electrodes, a P(VDF-TrFE) ferroelectric thin-film gate dielectric layer, and a gate electrode; wherein the channel material is a MoS2 ink thin film; the device is a top-gate structure, i.e., the P(VDF-TrFE) ferroelectric thin-film gate dielectric layer is located on the upper surface of the channel, the gate electrode is located on the upper surface of the P(VDF-TrFE) ferroelectric thin-film gate dielectric layer, and the source and drain electrodes are located on opposite sides of the channel and in contact with it. The artificial synapse device of this invention features a large storage window, high on / off ratio, and fast response. It possesses advantages such as non-volatile storage characteristics, continuously adjustable weight updates, high-density integration, low-power operation, fast response time, and high durability, enabling the simulation of biological synaptic behavior.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor materials technology, specifically relating to an artificial synapse device based on molybdenum disulfide ink, its array, and its fabrication method. Background Technology

[0002] Compared to traditional von Neumann-based computing architectures, artificial synaptic devices based on neuromorphic computing can achieve in-memory computing functionality, potentially significantly reducing the energy and time consumption of data-intensive computations. Among various artificial synaptic devices, two-dimensional material devices are increasingly widely used, and the arraying of these devices is becoming increasingly important.

[0003] Although various MoS2-based artificial synaptic transistors have been reported in the past few years, the controllable fabrication of large-area artificial synaptic transistor arrays to simulate biological synaptic behavior remains a major challenge due to the low yield and quality of MoS2 thin films. Existing technologies typically employ mechanical exfoliation, chemical vapor deposition (CVD), and ultrasonic-based liquid-phase exfoliation to prepare MoS2: (1) Mechanical exfoliation of MoS2 suffers from low yield and difficulty in controlling thickness, size, and shape. (2) Chemical vapor deposition (CVD) growth is considered the most promising method for synthesizing large-area MoS2 thin films, but the stringent growth conditions and poor reproducibility increase integration complexity, hindering its implementation in large-scale circuit applications. (3) Traditional ultrasonic-based liquid-phase exfoliation produces nanosheets with a wide thickness distribution and short lateral length, resulting in unsatisfactory film electrical properties, making them unsuitable as semiconductor channels. Compared to traditional mechanical exfoliation and the widely explored chemical vapor deposition techniques, electrochemical exfoliation of MoS2 based on electrochemically assisted molecular intercalation has been reported as an emerging solution-based processing method.

[0004] Despite the rapid development of solution-processable two-dimensional semiconductor channel devices (2D semiconductor channel devices), research on gate dielectric materials compatible with solution-processable channel materials remains limited. Mechanically exfoliated 2D ferroelectric gate dielectrics cannot be arrayed, while CVD growth of large-area gate dielectric materials requires high temperatures and complex process conditions, making it difficult to meet the demands of large-scale applications. For TMDCs that can also be prepared by liquid-phase exfoliation, such as hafnium disulfide (HfS2), its oxide phase can be used as a gate dielectric, but post-oxidation processing at temperatures above 500 °C is still required. MoS2 ink, a stable dispersion composed of molybdenum disulfide 2D material and solvent, is commonly used in inkjet printing or 3D printing technologies. Current research on MoS2 ink largely focuses on the fundamental characteristic analysis of two- or three-terminal devices. One study used MoS2 ink to fabricate memristors (Chinese patent application CN 118076218 A), using MoS2 ink as the intermediate layer of a two-terminal memristor. This device holds promise for neural network computing. However, memristors rely on internal material physical variations, which may introduce additional noise sources during high-density integration. Furthermore, the limited number of ports makes wiring and interconnection complex when constructing complex neural networks. Three-terminal structures offer greater flexibility in circuit design and allow for easier integration of logic operations and memory functions on the same device. To construct artificial synaptic device arrays that mimic biological synaptic behavior using MoS2 ink, it is necessary to find functional layers compatible with semiconductor processes and capable of arraying. This presents challenges related to device fabrication complexity and arraying process compatibility. Substantial progress in constructing three-terminal artificial synaptic devices using MoS2 ink is currently scarce. Our investigation indicates that research on artificial synaptic device arrays based on MoS2 ink and ferroelectric gate dielectrics has not yet been reported. Summary of the Invention

[0005] To address the shortcomings and deficiencies of existing technologies, the primary objective of this invention is to provide an artificial synapse device based on molybdenum disulfide ink. This artificial synapse device features a large storage window, high on / off ratio, fast response, excellent stability, and the ability to simulate biological synaptic behavior.

[0006] Another objective of this invention is to provide a method for fabricating the aforementioned artificial synaptic device based on molybdenum disulfide ink. The method proposed in this invention uses molybdenum disulfide (MoS2) ink as the semiconductor channel and the ferroelectric copolymer polyvinylidene fluoride-trifluoroethylene (P(VDF-TrFE)) as the gate dielectric, wherein both the semiconductor channel and the ferroelectric gate dielectric are prepared by spin coating. The low-temperature fabrication of high-performance thin-film transistors using all-solution processing of this invention provides a cost-effective and scalable method for heterogeneous thin-film electronics.

[0007] Another object of the present invention is to provide applications of the above-described artificial synaptic device.

[0008] The present invention also provides an artificial synaptic device array based on the above-mentioned artificial synaptic device.

[0009] The objective of this invention is achieved through the following technical solution:

[0010] An artificial synaptic device based on molybdenum disulfide ink is disclosed. The device mainly includes a substrate, a channel, a source / drain, a P(VDF-TrFE) ferroelectric thin film gate dielectric, and a gate; wherein the channel material is a MoS2 ink thin film.

[0011] The device is a top-gate structure, that is, the P(VDF-TrFE) ferroelectric thin film gate dielectric is located on the upper surface of the MoS2 ink channel, the gate is located on the upper surface of the P(VDF-TrFE) ferroelectric thin film gate dielectric, the source and drain are located on both sides of the MoS2 ink channel and in contact with it, and the lower surface of the channel is in contact with the substrate.

[0012] Preferably, the source / drain electrode is a Cr / Au source / drain electrode.

[0013] More preferably, in the Cr / Au source / drain electrode, the Cr thickness is 10~15nm and the Au thickness is 30~35nm.

[0014] Preferably, the thickness of the P(VDF-TrFE) ferroelectric thin film gate dielectric is 200~300 nm; and the thickness of the MoS2 ink channel layer is 10~15 nm.

[0015] Preferably, the gate electrode is a pure Au gate electrode.

[0016] More preferably, the thickness of the gate is 20~30 nm.

[0017] Preferably, the substrate is a SiO2 substrate with a thickness of 285 nm.

[0018] This invention proposes a method for fabricating an artificial synaptic device based on molybdenum disulfide ink, comprising the following steps:

[0019] (1) Preparation of colloidal solution: MoS2 nanosheet ink was prepared by electrochemical molecular intercalation exfoliation method; polyvinylidene fluoride-trifluoroethylene (P(VDF-TrFE)) was dissolved in solvent to obtain P(VDF-TrFE) gate dielectric solution;

[0020] (2) Substrate pretreatment: The substrate is cleaned and then treated with oxygen plasma to improve the substrate's hydrophilicity;

[0021] (3) Semiconductor channel thin film deposition and post-processing: MoS2 nanosheet ink is spin-coated several times on a pretreated substrate to obtain a continuous and uniform nanosheet interconnect film; then, the entire film is acid-washed and thermally annealed; finally, semiconductor channels are obtained by mask etching, which facilitates the fabrication of subsequent devices.

[0022] (4) Fabrication of source / drain electrodes: Source / drain electrodes are fabricated to both ends of the channel by spin coating photoresist, ultraviolet lithography, development, vacuum metal evaporation and stripping processes in sequence;

[0023] (5) Deposition and post-processing of ferroelectric gate dielectric film: On the channel with source / drain electrodes built, the gate dielectric layer is prepared by spin coating. The P(VDF-TrFE) gate dielectric solution is spin coated on the channel as the P(VDF-TrFE) ferroelectric thin film gate dielectric layer, and then dried and vacuum thermally annealed to achieve close contact between the channel and the gate dielectric layer.

[0024] (6) Gate fabrication: The gate is fabricated using electrode transfer technology to complete the fabrication of the artificial synaptic device.

[0025] Preferably, the concentration of the P(VDF-TrFE) gate dielectric solution in step (1) is 4~6 wt%, more preferably 6 wt%, and its solvent is N,N-dimethylformamide (DMF); the peak absorbance of the MoS2 nanosheet ink at 450 nm is 0.70, and its solvent is isopropanol.

[0026] Preferably, the specific preparation steps of the MoS2 nanosheet ink in step (1) include: in an electrolyte solution, using blocky molybdenum disulfide crystals and graphite sheets as the cathode and anode, respectively; applying a voltage of 8~10V to the anode for 1 hour using an electrochemical workstation; ultrasonically dispersing the expanded MoS2 in a PVP / DMF solution; centrifuging the resulting dispersion to remove large pieces and unpeeled pieces; further centrifuging the remaining supernatant; washing the resulting deposit with isopropanol; and finally dispersing the deposit in isopropanol to obtain the MoS2 nanosheet ink.

[0027] Preferably, the cleaning in step (2) refers to ultrasonically cleaning the substrate with acetone, isopropanol and water for 10-15 minutes each, and then drying the substrate with nitrogen; then treating it with oxygen plasma for 10-15 minutes to improve the hydrophilicity of the substrate.

[0028] Preferably, the rotational speed of the spin coating in step (3) is 2000 r / min, and the coating time is 60s each time; the acid washing refers to immersing the entire membrane in a 1,2-dichloroethane solution of 10 mg / mL bis(trifluoromethane)sulfonylimide (TFSI) and keeping it at 70~80 ℃ for 1 h; the thermal annealing is carried out under inert gas protection for 1 hour at a temperature of 250~300 ℃.

[0029] Preferably, the number of spin coating operations in step (3) is about 3 times, and the thickness of the MoS2 ink channel is 10~15nm.

[0030] Preferably, in step (5), the spin coating is carried out at a speed of 500 r / min for 10 seconds, and then at a speed of 3000 r / min for 60 seconds; the drying is carried out at 70~80 ℃ for 5~10 min, and the heat annealing is carried out at 145 ℃ for 1~2 h.

[0031] Preferably, the specific steps of step (6) are as follows: first, pure Au electrode is deposited onto SiO2 substrate, and then Au electrode is transferred as top metal electrode through polyvinyl butyral (PVB) film.

[0032] The artificial synaptic device described in this invention has a wide range of applications and prospects, especially in neuromorphic computing, low-power electronic devices, and intelligent systems. This artificial synaptic device can construct a hardware platform that simulates the structure of a biological nervous system, enabling efficient and energy-saving information processing, and can perform excellently in image recognition, natural language processing, and other cognitive tasks.

[0033] This invention also proposes an artificial synaptic device array using molybdenum disulfide (MoS2) ink as the semiconductor channel and ferroelectric copolymer polyvinylidene fluoride-trifluoroethylene (P(VDF-TrFE)) as the gate dielectric, wherein both the semiconductor channel and the ferroelectric gate dielectric are prepared by spin coating.

[0034] In this embodiment of the invention, a 3×3 artificial synapse array was constructed based on the aforementioned artificial synapse device, demonstrating the scalability potential of the invention.

[0035] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0036] (1) The artificial synaptic device described in this invention has the characteristics of large storage window, high on / off ratio and fast response. It has advantages such as non-volatile storage characteristics, continuously adjustable weight update, high-density integration, low power consumption operation, fast response time and strong durability, and can realize the simulation of biological synaptic behavior.

[0037] (2) The three-terminal structure of the artificial synaptic device described in this invention provides greater flexibility for circuit design and can be used to construct a hardware platform that simulates the structure of a biological nervous system, thereby achieving efficient and energy-saving information processing. The artificial synaptic device described in this invention can mimic the behavior of biological synapses, including non-volatile weighted storage, synaptic plasticity, and excitatory postsynaptic currents (EPSC), thus supporting complex neural network operations. Its application fields and prospects are very broad.

[0038] (3) The channel material of the artificial synaptic device of the present invention is prepared by a stable phase pure 2H-MoS2 ink solution through an electrochemical molecular intercalation-based exfoliation method. This method is low in cost, high in efficiency, simple in process, and can be mass-produced. The resulting two-dimensional MoS2 nanosheets with high quality and excellent morphology can be successfully used to form thin film transistor networks on a large area. In this method, due to the effect of the electric field, ions or molecules can more easily enter the interlayer of the host material, improving the efficiency of the intercalation process, and can be carried out at a lower temperature. During the preparation of MoS2 nanosheets, the intercalation process can be monitored in real time by measuring parameters such as current and voltage online using an electrochemical workstation, which facilitates timely adjustment of experimental conditions to optimize the results.

[0039] (4) The ferroelectric gate medium used in the artificial synaptic device of the present invention is copolymer P(VDF-TrFE), which has significant advantages such as high spontaneous polarization, good polarization stability, fast polarization reversal time, low leakage current, low-temperature processing capability, and compatibility with semiconductor technology. As a solution-processable ferroelectric gate medium, copolymer P(VDF-TrFE) can be combined with semiconductor channels made of MoS2 ink to realize the arraying of devices. In addition, the use of the functional layer of ferroelectric copolymer P(VDF-TrFE) introduces logic operation and storage functions into the device, which can be used to construct artificial synaptic devices that simulate biological synaptic behavior and support neuromorphic computing.

[0040] (5) The gate dielectric and semiconductor channel of the artificial synaptic device described in this invention are assembled by layer-by-layer spin coating. The low-temperature layer-by-layer spin coating process is conducive to the formation of a good van der Waals interface between the semiconductor and the ferroelectric copolymer, which significantly improves the gate control efficiency of the transistor. Moreover, the processing cost is relatively low and the scalability is strong. While ensuring that the overall device can serve as a high-performance artificial synaptic device, large-area, batch thin film preparation can be achieved, which is suitable for industrial-scale production and solves the complexity of two-dimensional material device array preparation and the compatibility problem of arraying process. This invention demonstrates for the first time a high-performance artificial synaptic transistor array based on molybdenum disulfide nanosheet ink, indicating that MoS2 ink prepared by electrochemical exfoliation has broad application prospects in the manufacturing of high-performance artificial synaptic arrays. Our low-temperature manufacturing process for high-performance thin film transistors provides an economical, efficient and scalable method for heterogeneous integrated thin film electronic devices.

[0041] (6) After obtaining the channel made of molybdenum disulfide ink, the artificial synaptic device of the present invention is subjected to additional acid washing and thermal annealing processes to passivate the sulfur vacancies of molybdenum disulfide, thereby obtaining a high-quality 2Dn type semiconductor thin film. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the structure of the artificial synaptic device prepared in Embodiment 1 of the present invention;

[0043] Wherein, 1 is Si; 2 is SiO2 substrate; 3 is channel prepared by MoS2 ink thin film; 4 is Cr / Au source / drain electrode; 5 is P(VDF-TrFE) ferroelectric thin film gate dielectric layer; and 6 is Au top gate electrode.

[0044] Figure 2 The image shows the Raman characterization of the MoS2 nanosheets prepared in Example 1 of this invention.

[0045] Figure 3 This invention compares the electrical performance of transistors fabricated with SiO2 as the gate dielectric before and after acid treatment and thermal annealing of the MoS2 ink film prepared in Example 1 of the present invention.

[0046] Figure 4 The electrical properties of the transistor fabricated using SiO2 as the gate dielectric based on the MoS2 ink thin film prepared in Example 1 of this invention are shown.

[0047] Figure 5 The ferromagnetic hysteresis loops of P(VDF-TrFE) ferroelectric thin films prepared in Example 1 of the present invention and P(VDF-TrFE) gate dielectric solutions of different concentrations were obtained in an Au-P(VDF-TrFE)-Au capacitor at a test frequency of 10 kHz.

[0048] Figure 6 An optical photograph of a 3×3 artificial synaptic device array constructed using the artificial synaptic device prepared in Example 1 of this invention.

[0049] Figure 7 The electrical properties of the artificial synaptic device prepared in Example 1 of this invention are shown.

[0050] Figure 8 The current response of the artificial synaptic device prepared in Embodiment 1 of the present invention when different gate voltages are applied.

[0051] Figure 9 The current response of the artificial synaptic device prepared in Embodiment 1 of the present invention when applied with electrical pulses of different widths. Detailed Implementation

[0052] The present invention will be further described in detail below with reference to embodiments and accompanying drawings, but the embodiments of the present invention are not limited thereto. All raw materials involved in the present invention can be purchased directly from the market. For process parameters not specifically specified, conventional techniques can be referred to.

[0053] Example 1

[0054] A method for fabricating an artificial synaptic device based on molybdenum disulfide ink includes the following steps:

[0055] (1) Preparation of colloidal solutions

[0056] MoS2 nanosheet ink was prepared by electrochemical exfoliation: ink containing tetraheptylammonium bromide (THA) was prepared. + Br − In an electrolyte solution of molybdenum disulfide (TMS) and acetonitrile (10 mg / mL), bulk molybdenum disulfide crystals and graphite sheets were used as the cathode and anode, respectively. An electrochemical workstation was used to apply a voltage of 8–10 V to the anode for 1 hour. During this process, THA… + The interlayer of bulk molybdenum disulfide was embedded, extending its layered structure. The swollen MoS2 was sonicated in a 22 mg / mL PVP / DMF solution (PVP molecular weight 40,000) for 10 min. The resulting dispersion was centrifuged at 3000 rpm for 10 min to remove bulk and unpeeled fragments. The remaining supernatant was then further centrifuged at 10000 rpm for 20 min. The resulting precipitate was washed three times with isopropanol (IPA) to remove excess PVP. Finally, it was dispersed in IPA to form a homogeneous and pure 2H-phase MoS2 nanosheet ink. The optical absorbance of the ink solution was measured using a UV-Vis spectrophotometer to determine the concentration of the MoS2 dispersion. As a standard, the peak absorbance of the ink solution at 450 nm was adjusted to 0.70. Figure 2 Raman spectroscopy confirmed that the present invention yielded phase-pure, semiconductor 2H-MoS2 nanosheets with narrow thickness distribution.

[0057] Preparation of P(VDF-TrFE) gate dielectric solution: The solvent for the P(VDF-TrFE) (PVDF:TrFE molar ratio of 70%:30%) ferroelectric thin film gate dielectric solution is N,N-dimethylformamide, and the mass concentration of P(VDF-TrFE) in the P(VDF-TrFE) gate dielectric solution is 6%.

[0058] (2) Substrate pretreatment: The selected substrate is a 285 nm thick SiO2 substrate. First, the substrate is ultrasonically cleaned with acetone, isopropanol and water for 10 min each, and then dried with nitrogen. In order to make the substrate surface hydrophilic to obtain a better spin coating effect, oxygen plasma is used for treatment at 200 W for 10 min.

[0059] (3) Semiconductor channel film deposition and post-treatment: MoS2 nanosheet ink was spin-coated three times on a pretreated substrate to obtain a continuous and uniform nanosheet interconnect film. The spin-coating speed was 2000 r / min, and each spin lasted for 60 s. Then, the entire film was immersed in a 10 mg / mL solution of bis(trifluoromethane)sulfonylimide (TFSI) in 1,2-dichloroethane and heated in a water bath at 80 °C for 1 h. TFSI molecules can passivate the sulfur vacancies of MoS2 nanosheets. Then, it was thermally annealed at 250 °C for 1 hour in an inert gas tube furnace. The further annealing process further improved the contact between MoS2 nanosheets and removed residual solvent. Finally, the semiconductor channel was obtained by mask etching, which facilitates the subsequent fabrication of devices.

[0060] (4) Fabrication of source / drain electrodes: Cr / Au (10 nm / 30 nm) electrodes were fabricated to both ends of the channel by spin-coating photoresist, ultraviolet lithography, development, vacuum metal evaporation and stripping processes.

[0061] (5) Deposition and post-processing of ferroelectric gate dielectric film: On the channel with the source / drain electrodes constructed, a P(VDF-TrFE) ferroelectric thin film gate dielectric layer (thickness ≈ 300 nm) was prepared by spin coating using a 6% P(VDF-TrFE) gate dielectric solution prepared in step (1) as the raw material. The detailed parameters of the spin coating were: 500 r / min for 10 seconds and 3000 r / min for 60 seconds. Finally, the entire structure was heated on an 80 ℃ heating plate for 5 min and then annealed in a vacuum drying oven at 145 ℃ for 2 h. The spin coating and drying steps were carried out in a glove box, and the thermal annealing was carried out in a vacuum drying oven.

[0062] (6) Gate fabrication: First, pure Au electrode is deposited onto a 285 nm SiO2 substrate (electrode thickness 20 nm), and then Au electrode is transferred as the top metal electrode through a polyvinyl butyral (PVB) film. Then the entire device is immersed in an ethanol solution at 45 °C for half an hour to dissolve the PVB film. This process does not damage the P(VDF-TrFE) copolymer and the overall device structure.

[0063] (1) Electrical properties and comparison of the artificial synaptic device prepared in Example 1:

[0064] The electrical performance of transistors fabricated using SiO2 as the gate dielectric on the MoS2 ink film prepared in step (3) before and after acid treatment and thermal annealing was tested, and the results are as follows: Figure 3 As shown, transistors fabricated from MoS2 ink films through acid treatment and thermal annealing exhibit typical n-type behavior and over 10 when SiO2 is used as the gate dielectric. 3 The switching ratio is high; while the transistors prepared from MoS2 ink films that have not undergone acid treatment and thermal annealing exhibit negligible current modulation due to the large presence of sulfur vacancies.

[0065] The artificial synapse device of this invention is a typical ferroelectric transistor architecture, which relies on the polarization state of the ferroelectric layer to modulate the conductivity of the channel. It spontaneously polarizes under the influence of an external electric field, and this polarization state can switch between two directions; even after the external electric field is removed, the polarization state can still be maintained, which is called remanent polarization or coercivity. In transistors using SiO2 as the gate dielectric, this manifests as a small clockwise window after bidirectional scanning, such as... Figure 4 As shown, this is due to unavoidable interface charge trapping effects and the adsorption of water and oxygen in the air. For the ferroelectric transistor architecture of this invention, when a gate voltage V higher than the coercivity voltage is applied... gs When the dipoles in the P(VDF-TrFE) layer are aligned (polarization flipped), a typical counterclockwise memory window is generated, demonstrating the effective control of the ferroelectric grid dielectric of the present invention.

[0066] Referring to step (1) of Example 1 above, P(VDF-TrFE) gate dielectric solutions with concentrations of 2wt%, 4wt%, 6wt%, 8wt%, and 10wt% were prepared. Ferroelectric gate dielectric films were prepared using Example 1 and the above-mentioned P(VDF-TrFE) gate dielectric solutions of different concentrations, and their performance was tested. The ferroelectric hysteresis loops obtained in Au-P(VDF-TrFE)-Au capacitors at a test frequency of 10 kHz are shown below. Figure 5 As shown, the remanent polarization intensity of the P(VDF-TrFE) ferroelectric gate dielectric layer shows a slight increase followed by a decrease with varying concentrations, reaching its highest value at a mass concentration of 6% (Example 1). This is because, during device fabrication, a lower concentration of P(VDF-TrFE) results in a thinner gate dielectric layer after spin-coating, typically 50-100 nm, which is prone to leakage or even breakdown when a large gate voltage is applied. Conversely, a high concentration of gate dielectric, due to its lower remanent polarization intensity and greater thickness, cannot effectively control the semiconductor layer.

[0067] Based on the artificial synapse device prepared in Example 1, we constructed a 3×3 artificial synapse array (e.g., Figure 6 As shown in the figure, the transfer curves of each ferroelectric transistor in the 3×3 artificial synapse array were tested. The results are as follows. Figure 7 As shown, the artificial synaptic device prepared in Example 1 has a source-drain voltage V ds At 0.1V, it exhibits typical n-type behavior and a very clear memory hysteresis window exceeding 10V over a scan range higher than the coercivity voltage (±20 V) of the P(VDF-TrFE) ferroelectric polymer, with an on / off ratio >10. 3 This allows for low leakage current (~10). −10 A) operates at low power consumption. The electrical performance of each transistor exhibits good uniformity with no significant deviation between them.

[0068] (2) Simulation of the biological synaptic behavior of the artificial synaptic device prepared in Example 1:

[0069] Biological synapses transmit various electrical or chemical signals from the presynaptic to the postsynaptic terminal by regulating neurotransmitter levels. In a three-terminal ferroelectric device, the gate terminal transmits signals at the synaptic front end, while the channel layer transmits signals at the synaptic rear end. When the gate receives a "presynaptic" signal (i.e., an input pulse), it triggers a change in the internal polarization state (polarization reversal), causing a momentary increase in channel conductivity and generating a transient current similar to that of an EPSC (Electro-Electro-Polymer Capacitor).

[0070] like Figure 8 and 9 As shown, under a 10 ms pulse width, the artificial synaptic device prepared in Example 1 exhibits an excitatory postsynaptic current (EPSC) response triggered by a gate voltage with an amplitude ranging from 10 V to 25 V. Increasing the pulse amplitude leads to higher EPSC. Different gate voltages represent different neurotransmitter release amounts representing synaptic connection strength. After voltage pulse stimulation, EPSCs do not return to their initial values, and higher voltage amplitudes result in significant residual current. This observation indicates that voltage amplitude modulation can shift from short-term to long-term enhancement. With a gate voltage pulse intensity of 15 V, EPSC gradually increases with increasing pulse width, while longer pulse widths result in slower EPSC decay. The pulse amplitude has also been shown to effectively modulate the conductivity of ion channels; therefore, larger pulse amplitudes and longer pulse widths favor ferroelectric polarization, confirming the correlation between the non-volatility of ferroelectric modulation and synaptic weight update behavior in the artificial synaptic device prepared in this invention, consistent with biological synaptic behavior.

[0071] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A method for fabricating an artificial synaptic device based on molybdenum disulfide ink, characterized in that, Includes the following steps: (1) MoS2 nanosheet ink was prepared by electrochemical molecular intercalation exfoliation method; polyvinylidene fluoride-trifluoroethylene (P(VDF-TrFE)) was dissolved in a solvent to obtain a P(VDF-TrFE) gate dielectric solution; the peak absorbance of the MoS2 nanosheet ink at 450 nm was 0.70, and its solvent was isopropanol; (2) The substrate is cleaned and then treated with oxygen plasma; (3) Spin-coating MoS2 nanosheet ink several times on the substrate treated in step (2) to obtain a continuous and uniform nanosheet interconnect film; then, acid washing and thermal annealing of the entire film; finally, semiconductor channels are obtained by mask etching; the spin coating speed in step (3) is 2000 r / min, and the coating time is 60s each time; the acid washing refers to immersing the entire film in a 10 mg / mL bis(trifluoromethane)sulfonylimide 1,2-dichloroethane solution and keeping it at 80 ℃ for 1 h; the thermal annealing is carried out under inert gas protection for 1 hour at a temperature of 250~300 ℃; (4) Source / drain electrodes are fabricated to both ends of the channel by spin coating photoresist, ultraviolet lithography, development, vacuum metal evaporation and stripping in sequence; (5) Spin-coating the P(VDF-TrFE) gate dielectric solution onto the upper surface of the channel as the P(VDF-TrFE) ferroelectric thin film gate dielectric layer, and then drying and vacuum heat annealing. (6) Fabrication of the gate: The gate is fabricated using electrode transfer technology to complete the fabrication of the artificial synaptic device; The MoS2 nanosheet ink in step (1) is prepared by the following steps: In an electrolyte solution, a blocky molybdenum disulfide crystal and a graphite sheet are used as the cathode and anode, respectively; an electrochemical workstation is used to apply a voltage of 8-10V to the anode for 1 hour; the expanded MoS2 is ultrasonically dispersed in a PVP / DMF solution, and the resulting dispersion is centrifuged to remove large pieces and unpeeled pieces. The remaining supernatant is further centrifuged, and the resulting deposit is washed with isopropanol. Finally, the deposit is dispersed in isopropanol to obtain the MoS2 nanosheet ink.

2. The preparation method according to claim 1, characterized in that, The concentration of the P(VDF-TrFE) gate dielectric solution in step (1) is 4~6 wt%, and its solvent is N,N-dimethylformamide.

3. The preparation method according to claim 1, characterized in that, The cleaning described in step (2) refers to ultrasonically cleaning the substrate with acetone, isopropanol, and water for 10-15 minutes, and then drying the substrate with nitrogen; then treating it with oxygen plasma for 10-15 minutes to improve the hydrophilicity of the substrate. The specific steps of step (6) are as follows: first, pure Au electrode is deposited onto SiO2 substrate, and then Au electrode is transferred as top metal electrode through polyvinyl butyral film.

4. The preparation method according to claim 1, characterized in that, The spin coating in step (5) is performed at a speed of 500 r / min for 10 seconds, and then at a speed of 3000 r / min for 60 seconds. The drying process involves heating at 80 °C for 5-10 min, and the heat annealing process involves annealing at 145 °C for 2 h.

5. An artificial synaptic device based on molybdenum disulfide ink, characterized in that, It is prepared by the preparation method according to any one of claims 1 to 4, and the device includes a substrate, a channel, a source / drain, a P(VDF-TrFE) ferroelectric thin film gate dielectric and a gate; wherein the material of the channel is a MoS2 ink thin film; The device is a top-gate structure, meaning that the P(VDF-TrFE) ferroelectric thin film gate dielectric is located on the upper surface of the channel, the gate is located on the upper surface of the P(VDF-TrFE) ferroelectric thin film gate dielectric, the source and drain are located on both sides of the channel and in contact with it, and the lower surface of the channel is in contact with the substrate.

6. The artificial synaptic device based on molybdenum disulfide ink according to claim 5, characterized in that, The source / drain electrodes are Cr / Au source / drain electrodes, the gate electrode is a pure Au gate electrode, and the substrate is a SiO2 substrate.

7. An artificial synaptic device based on molybdenum disulfide ink according to claim 6, characterized in that, In the Cr / Au source / drain electrode, the Cr thickness is 10~15nm and the Au thickness is 30~35nm; The thickness of the P(VDF-TrFE) ferroelectric thin film gate dielectric is 200~300 nm; The thickness of the channel layer is 10~15nm; The thickness of the gate is 20~30 nm.

8. The application of the artificial synaptic device according to any one of claims 5 to 7, characterized in that, This device is used in neuromorphic computing, low-power electronic devices, and intelligent systems.

9. An array of artificial synaptic devices, characterized in that, It is made using the artificial synaptic device as described in any one of claims 5 to 7.

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