Display device

Abstract

A novel display device is provided. The display device includes first to fifth p-channel type transistors and n-channel type transistors, respectively connecting a gate of the fifth p-channel type transistor and a gate of the n-channel type transistor, which operate at the same timing, to different nodes. The gate of the first p-channel transistor is directly connected to the gate of the n-channel transistor. The gate of the fifth p-channel transistor is electrically connected to the gate of the first p-channel transistor through the source and drain of the third p-channel transistor.

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of one embodiment of the invention disclosed in this specification, etc. relates to an object, a method, a driving method or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a product or a composition of matter. Specifically, as an example of the technical field of one embodiment of the present invention disclosed in this specification, etc., there can be cited semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, camera devices, lighting devices, computing devices, control devices, storage devices, input devices, output devices, input-output devices, signal processing devices, computing processing devices, electronic computers, electronic devices, their driving methods or their manufacturing methods. Background Art

[0003] As a result of recent technological innovations, display devices have been generally commercialized, and in order to gain competitiveness under such circumstances, products with higher added value are being demanded.

[0004] For example, a display device using a transistor having an oxide semiconductor (Oxide Semiconductor) in a semiconductor layer having a channel formation region (also referred to as an OS transistor) and a transistor having a low-temperature polysilicon (LTPS: Low Temperature Poly Silicon) in a semiconductor layer having a channel formation region (also referred to as an LTPS transistor) is known (see Patent Document 1). A display device using an OS transistor and an LTPS transistor can be a display device with high added value such as high definition, low power consumption, high switching speed, and / or narrow frame of a panel.

[0005] [Patent Document 1] International Patent Application Publication No. 2021 / 053707

[0006] Patent document 1 discloses a structure using the above-mentioned OS transistor and LTPS transistor in a gate line driving circuit. In a part of the gate line driving circuit, a so-called complementary circuit structure is adopted in which the OS transistor is used as an n-channel transistor and the LTPS transistor is used as a p-channel transistor. In the complementary circuit structure, for example, when an L-level signal is supplied to the gate, the n-channel transistor is turned off and the p-channel transistor is turned on. A driving circuit having a complementary circuit structure is effective for reducing power consumption.

[0007] However, in a complementary circuit structure, for example, when a signal that is not sufficiently lowered to an L level is supplied to the gate, there is a concern that the p-channel transistor becomes turned on and the n-channel transistor cannot become turned off. As a result, there is a possibility of causing malfunctions in the driving circuit having a complementary circuit structure, increased power consumption, and / or degradation of the transistor. Summary of the invention

[0008] One of the purposes of one embodiment of the present invention is to provide a display device capable of suppressing an increase in power consumption. Another purpose of one embodiment of the present invention is to provide a display device capable of reducing manufacturing costs. Another purpose of one embodiment of the present invention is to provide a display device with high reliability. Another purpose of one embodiment of the present invention is to provide a novel display device.

[0009] Note that the above-listed objectives do not prevent the existence of other objectives. One embodiment of the present invention does not need to achieve all of the above-listed objectives. Other objectives other than the above-listed objectives can be extracted from the description of this specification, drawings, claims, etc.

[0010] One embodiment of the present invention is a display device including a gate line driving circuit, wherein a unit circuit included in the gate line driving circuit includes first to fifth p-channel transistors and an n-channel transistor, one of a source and a drain of the first p-channel transistor is electrically connected to a first clock signal line, one of a source and a drain of the second p-channel transistor is electrically connected to a first power supply line, the other of the source and the drain of the first p-channel transistor is electrically connected to the other of the source and the drain of the second p-channel transistor, the gate of the first p-channel transistor is electrically connected to one of the source and the drain of a third p-channel transistor, the gate of the first p-channel transistor is directly connected to the gate of the n-channel transistor, and the gate of the third p-channel transistor is electrically connected to the second power supply line. The first p-channel transistor and the second p-channel transistor are electrically connected to the source line, the other of the source and the drain of the third p-channel transistor is electrically connected to one of the source and the drain of the fourth p-channel transistor, the other of the source and the drain of the third p-channel transistor is electrically connected to the gate of the fifth p-channel transistor, the gate of the fourth p-channel transistor is electrically connected to the second clock signal line, one of the source and the drain of the fifth p-channel transistor is electrically connected to the first power line, the other of the source and the drain of the fifth p-channel transistor is electrically connected to the gate of the second p-channel transistor, the other of the source and the drain of the fifth p-channel transistor is electrically connected to one of the source and the drain of the n-channel transistor, and the other of the source and the drain of the n-channel transistor is electrically connected to the second power line.

[0011] In the display device according to one embodiment of the present invention, preferably, the n-channel transistor includes a first semiconductor layer, and the first semiconductor layer includes an oxide semiconductor.

[0012] In the display device of one embodiment of the present invention, preferably, each of the first to fifth p-channel transistors includes a second semiconductor layer, and the second semiconductor layer includes silicon.

[0013] One embodiment of the present invention is a display device including a gate line driving circuit, wherein a unit circuit included in the gate line driving circuit includes first to seventh p-channel transistors and an n-channel transistor, one of a source and a drain of the first p-channel transistor is electrically connected to a first clock signal line, one of a source and a drain of the second p-channel transistor is electrically connected to a first power supply line, the other of the source and the drain of the first p-channel transistor is electrically connected to the other of the source and the drain of the second p-channel transistor, the gate of the first p-channel transistor is electrically connected to one of the source and the drain of a third p-channel transistor, the gate of the first p-channel transistor is directly connected to the gate of the n-channel transistor, the gate of the third p-channel transistor is electrically connected to the second power supply line, the other of the source and the drain of the third p-channel transistor is electrically connected to one of the source and the drain of a fourth p-channel transistor, the other of the source and the drain of the third p-channel transistor is electrically connected to one of the source and the drain of a sixth p-channel transistor The gate of the fourth p-channel transistor is electrically connected to the second clock signal line, one of the source and the drain of the fifth p-channel transistor is electrically connected to the first power supply line, the other of the source and the drain of the fifth p-channel transistor is electrically connected to the gate of the second p-channel transistor, the other of the source and the drain of the fifth p-channel transistor is electrically connected to the gate of the seventh p-channel transistor, the other of the source and the drain of the fifth p-channel transistor is electrically connected to one of the source and the drain of the n-channel transistor, the other of the source and the drain of the n-channel transistor is electrically connected to the second power supply line, the gate of the sixth p-channel transistor is electrically connected to the first clock signal line, the other of the source and the drain of the sixth p-channel transistor is electrically connected to one of the source and the drain of the seventh p-channel transistor, and the other of the source and the drain of the seventh p-channel transistor is electrically connected to the first power supply line.

[0014] In the display device according to one embodiment of the present invention, preferably, the n-channel transistor includes a first semiconductor layer, and the first semiconductor layer includes an oxide semiconductor.

[0015] In the display device according to one embodiment of the present invention, preferably, each of the first to seventh p-channel transistors includes a second semiconductor layer, and the second semiconductor layer includes silicon.

[0016] Note that other aspects of the present invention are described in the following embodiments and drawings.

[0017] According to one embodiment of the present invention, a display device capable of suppressing an increase in power consumption can be provided. In addition, according to one embodiment of the present invention, a display device capable of reducing manufacturing costs can be provided. In addition, according to one embodiment of the present invention, a display device with high reliability can be provided. In addition, according to one embodiment of the present invention, a novel display device can be provided.

[0018] Note that the effects listed above do not prevent the existence of other effects. One embodiment of the present invention does not necessarily have all the effects listed above. Other effects other than the effects listed above can be extracted from the description of this specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1A and Figure 1B is a block diagram and circuit diagram illustrating a display device; Figure 2A and Figure 2B is a circuit diagram illustrating a display device; Figure 3 is a timing diagram illustrating a display device; Figure 4A and Figure 4B is a circuit diagram illustrating a display device; Figure 5A and Figure 5B is a circuit diagram illustrating a display device; Fig. 6A and Figure 6B is a circuit diagram illustrating a display device; Fig. 7A and Figure 7B is a circuit diagram and timing diagram illustrating the operation of the display device; Fig. 8A and Figure 8B is a circuit diagram illustrating a display device; Fig. 9A and Fig. 9B is a circuit diagram illustrating a display device; Fig. 10A and Fig. 10B is a circuit diagram illustrating a display device; Fig.11A and Fig. 11B is a circuit diagram illustrating a display device; Fig. 12A and Fig. 12B is a circuit diagram illustrating a display device; FIG. 13A to FIG. 13C is a circuit diagram illustrating a display device; FIG. 14A to FIG. 14C is a circuit diagram illustrating a display device; FIG. 15A to FIG. 15C is a circuit diagram illustrating a display device; Fig.16A and Fig. 16B is a circuit diagram illustrating a display device; FIG. 17A to FIG. 17C is a circuit diagram illustrating a display device; 18A to 18C is a circuit diagram illustrating a display device; FIG. 19A to FIG. 19C is a circuit diagram illustrating a display device; FIG. 20A to FIG. 20C is a circuit diagram illustrating a display device; Fig.21 is a timing diagram illustrating a display device; Fig.22A and Fig. 22B is a circuit diagram illustrating a display device; Fig.23A and Fig. 23B is a circuit diagram illustrating a display device; Fig.24A and Fig. 24B is a circuit diagram illustrating a display device; Fig.25A and Fig.25B is a circuit diagram illustrating a display device; Fig.26 is a circuit diagram illustrating a display device; Fig.27A and Fig.27B is a circuit diagram illustrating a display device; Fig.28 is a perspective view showing a structural example of a display device; FIG. 29A to FIG. 29C is a cross-sectional view showing a structural example of a display device; Fig. 30A and Fig. 30B is a cross-sectional view showing a structural example of a display device; Fig.31 is a plan view showing a structural example of a display device; Fig.32A and Fig.32B is a cross-sectional view showing a structural example of a display device; Fig.33 is a plan view showing a structural example of a display device; Fig.34 is a plan view showing a structural example of a display device; Fig.35 is a plan view showing a structural example of a display device; Fig.36 is a plan view showing a structural example of a display device; FIG. 37A to FIG. 37D is a circuit diagram showing a structural example of a display device; FIG. 38A to FIG. 38C is a circuit diagram showing a structural example of a display device; Fig.39A and Fig.39B is a diagram showing an example of an electronic device; FIG. 40A to FIG. 40D is a diagram showing an example of an electronic device; FIG. 41A to FIG. 41G is a diagram showing an example of an electronic device; FIG. 42A1 to FIG. 42A7 and Figures 42B1 to 42B6 This is a diagram showing the “connection” in this specification. DETAILED DESCRIPTION

[0020] Hereinafter, the embodiments are described with reference to the accompanying drawings. Note that the embodiments can be implemented in a plurality of different forms. Thus, a person skilled in the art can easily understand that the embodiments and details can be transformed into various forms without departing from the purpose and scope thereof. Therefore, one embodiment of the present invention should not be interpreted as being limited to the contents described in the embodiments.

[0021] In addition, in this specification, the structure shown in each embodiment can be appropriately combined with the structure shown in other embodiments to constitute one mode of the present invention. In addition, when multiple structures are shown in one embodiment, these structures can be appropriately combined and regarded as one mode of the present invention.

[0022] Note that, with respect to the drawings illustrating the embodiments, in the structure of the invention, the same symbol is sometimes used in common in different drawings to represent the same part or part having the same function, thereby omitting repeated description. In addition, in the drawings, when representing parts having the same function, for example, the same hatching is sometimes used without adding a special symbol. For example, in a stereogram, a plan view, etc., for the sake of clarity, the illustration of some constituent elements is sometimes omitted. For example, the description of some hidden lines in the drawings is sometimes omitted. In addition, for example, the description of hatching, etc. in the drawings is sometimes omitted.

[0023] In the drawings, the size, thickness of the layer or the area are sometimes exaggerated for the sake of clarity. Therefore, the drawings are not limited to the size or aspect ratio in the drawings, for example. In addition, in the drawings, ideal examples are schematically shown, so the present invention is not limited to the shapes or values ​​shown in the drawings, for example. For example, in the actual manufacturing process, layers or resist masks are sometimes unintentionally thinned due to etching and other processes, but for the sake of ease of understanding, this is sometimes not reflected in the drawings. In addition, for example, in actual circuit operation, voltage or current is sometimes uneven due to noise or timing deviation, but for the sake of ease of understanding, they are sometimes not reflected in the drawings.

[0024] In this specification and the drawings, the components of the present invention are classified according to their functions and are represented as components that are independent of each other. However, it is difficult to classify the components according to their functions, and sometimes one circuit involves multiple functions or multiple circuits involve one function. Therefore, the components shown in this specification and the drawings are not limited to the description thereof, and the words and phrases may be appropriately changed.

[0025] In this specification and the drawings, when the same symbol is used for a plurality of components and it is necessary to distinguish them, an identification symbol such as "A", "b", "_1", "[n]", or "[m, n]" may be added to the symbol. In addition, when the common content between a plurality of components to which identification symbols are added is described or it is not necessary to distinguish them, they may be described without adding identification symbols.

[0026] Implementation Method 1 A display device according to one embodiment of the present invention will be described with reference to the drawings. The display device described in this embodiment includes a gate line driver circuit that outputs an output signal for selecting pixels on a row basis.

[0027] <Configuration Example of Display Device> Figure 1A is an example of a block diagram of a display device according to one embodiment of the present invention. Figure 1B Yes Description Figure 1A An example of a circuit diagram of a shift register included in a gate line driving circuit included in a display device.

[0028] Figure 1AThe display device 300 shown includes a display unit 362 and a gate line driving circuit 364. The display unit 362 is provided with a pixel unit 345 including pixels 370 arranged in m rows and n columns (m and n are both integers greater than 2). The gate line driving circuit 364 includes a shift register 350, which outputs output signals OUT_1 to OUT_m for selecting pixels 370 of each row arranged in the pixel unit 345. The shift register 350 includes a plurality of unit circuits 100 that output output signals by being supplied with a clock signal and a start pulse signal. Note that a unit circuit refers to a circuit that outputs an output signal (also referred to as a pulse signal or a selection signal) of a row in a shift register included in the gate line driving circuit. The unit circuit is sometimes referred to as a pulse signal output circuit or a selection signal output circuit.

[0029] The display unit 362 and the gate line driving circuit 364 include an OS transistor and an LTPS transistor. The OS transistor and the LTPS transistor may be a thin film transistor (TFT). Since the thin film transistor can be formed on a light-transmitting substrate such as a glass substrate, the display device 300 can be made larger and less expensive. In addition, since the gate line driving circuit 364 can be manufactured together with the display unit 362 on the substrate, a narrow frame and / or a reduction in the number of components such as an external driving circuit can be achieved.

[0030] The display unit 362 and the gate line driving circuit 364 may have a circuit structure in which the OS transistor is an n-channel transistor and the LTPS transistor is a p-channel transistor. That is, the display unit 362 and the gate line driving circuit 364 may have a complementary circuit structure. As a complementary circuit structure, for example, in an inverter circuit, by supplying the same logic level potential to the gates of the two transistors, one of them can be turned on and the other can be turned off. In this case, by providing an n-channel transistor and a p-channel transistor between the power lines, the current flowing between the power lines can be reduced, thereby achieving low power consumption. Sometimes the structure combining the LTPS transistor and the OS transistor is called LTPO.

[0031] Figure 1B The shift register 350 shown includes unit circuits 100_1 to 100_m (m is an integer greater than or equal to 2) as a plurality of unit circuits 100. The unit circuits 100_1 to 100_m are connected to the wiring 101, the wiring 102, the power supply line 103, the power supply line 104, the wiring 105, and the wiring 106, respectively.

[0032] Wiring 101 is a wiring for transmitting a clock signal CK1 to unit circuits 100_1 to 100_m arranged in each row. Wiring 102 is a wiring for transmitting a clock signal CK2 to unit circuits 100_1 to 100_m arranged in each row. Wiring 101 and 102 are sometimes referred to as clock signal lines. Figure 1B In the illustrated unit circuits 100_1 to 100 — m, terminals connected to the wirings 101 and 102 are represented by CK1 and CK2.

[0033] The power supply line 103 is a power supply line for transmitting a power supply potential such as a potential VDD to the unit circuits 100_1 to 100_m arranged in each row. The power supply line 104 is a power supply line for transmitting a power supply potential such as a potential VSS to the unit circuits 100_1 to 100_m arranged in each row. Figure 1B In the illustrated unit circuits 100_1 to 100 — m, a terminal connected to the power supply line 103 is represented as VDD, and a terminal connected to the power supply line 104 is represented as VSS.

[0034] The wiring 105 is a wiring for transmitting a control signal, such as a start pulse signal SP, to the unit circuit 100_1 arranged in the first row. The wiring 105 is sometimes referred to as a signal line. Figure 1B In the unit circuit 100_1 shown in FIG. 1 , the terminal connected to the wiring 105 is represented by SP. Figure 1B In the unit circuits 100_2 to 100_m arranged in the second and subsequent rows, the output signal output by the unit circuit 100 in the previous row is used as a control signal. Therefore, the terminal connected to the wiring 106 in the previous row is represented as SP.

[0035] The wiring 106 is a wiring for transmitting output signals OUT_1 to OUT_m output by the unit circuits 100_1 to 100_m arranged in each row. The wiring 106 is sometimes referred to as an output signal line. Figure 1B In the unit circuits 100_1 to 100_m shown in FIG. 1 , the terminal connected to the wiring 106 is represented as OUT. Figure 1B In the illustrated unit circuits 100_1 to 100_m-1, the output signals OUT_1 to OUT_m-1 are also control signals for the next row. That is, the wiring 106 that outputs the output signals OUT_1 to OUT_m-1 is also used as a signal line for transmitting a control signal.

[0036] <Configuration Example of Unit Circuit 100> Figure 2A It is available for Figure 1B The unit circuits 100_1 to 100_m are an example of a circuit diagram of the unit circuit 100. In addition, Figure 2B Yes means Figure 2AThe circuit symbol of the circuit diagram of the unit circuit 100 is shown. Figure 1B The circuit diagram shown is composed of Figure 2B Circuit symbol representation.

[0037] The unit circuit 100 includes transistors Tp1 to Tp5, a transistor Tn1, and a capacitor Cp. Figure 1B The wiring 101, the wiring 102, the power supply line 103, the power supply line 104, the wiring 105, and the wiring 106 are connected.

[0038] One of the source and drain of the transistor Tp1 is connected to the wiring 101. One of the source and drain of the transistor Tp2 is connected to the power supply line 103. The other of the source and drain of the transistor Tp1 is connected to the other of the source and drain of the transistor Tp2. The other of the source and drain of the transistor Tp1 is connected to the wiring 106. The gate of the transistor Tp1 is connected to one of the source and drain of the transistor Tp3. The gate of the transistor Tp1 is connected to the gate of the transistor Tn1. One electrode of the capacitor Cp is connected to the other of the source and drain of the transistor Tp1. The other electrode of the capacitor Cp is connected to the gate of the transistor Tp1. The gate of the transistor Tp3 is connected to the power supply line 104. The other of the source and drain of the transistor Tp3 is connected to one of the source and drain of the transistor Tp4. The other of the source and drain of the transistor Tp3 is connected to the gate of the transistor Tp5. The other of the source and drain of the transistor Tp4 is connected to the wiring 105. The gate of the transistor Tp4 is connected to the wiring 102. One of the source and drain of the transistor Tp5 is connected to the power supply line 103. The other of the source and drain of the transistor Tp5 is connected to the gate of the transistor Tp2. The other of the source and drain of the transistor Tp5 is connected to one of the source and drain of the transistor Tn1. The other of the source and drain of the transistor Tn1 is connected to the power supply line 104.

[0039] Note that Figure 2A In the circuit diagram shown, symbols are given to each node for easy understanding. Figure 2A In FIG. 1 , the node connected to the gate of transistor Tn1 is represented as node N1. Figure 2A In FIG. 1 , the node connected to the gate of transistor Tp5 is represented as node N2. Figure 2A In FIG. 1 , the node connected to the gate of transistor Tp2 is represented as node N3. Note that a node refers to an element (e.g., wiring, etc.) that realizes the connection between elements constituting a circuit. Therefore, a "node connected to A" refers to a wiring that is connected to A and can be regarded as having the same potential as A.

[0040] Transistors Tp1 to Tp5 are p-channel transistors. The semiconductor layer having a channel formation region included in transistors Tp1 to Tp5 includes silicon. As silicon used for the semiconductor layer included in transistors Tp1 to Tp5, single crystal silicon, polycrystalline silicon, amorphous silicon, etc. can be cited. In particular, LTPS transistors containing low-temperature polycrystalline silicon in the semiconductor layer are preferred. By using LTPS transistors as transistors Tp1 to Tp5, transistors with high field effect mobility and good frequency characteristics can be realized. Transistors Tp1 to Tp5 are sometimes referred to as first to fifth p-channel transistors.

[0041] The transistor Tp1 connected to the wiring 106 for outputting an output signal is sometimes called a pull-up transistor, and the transistor Tp2 is sometimes called a pull-down transistor. In addition, the transistor Tp3 having the function of differentially setting the potential or voltage of the node N1 and the node N2 is sometimes called a potential adjustment transistor or a voltage adjustment transistor.

[0042] The transistor Tn1 is an n-channel transistor. As the n-channel transistor, it is preferable to use an OS transistor in which an oxide semiconductor is included in a semiconductor layer having a channel formation region.

[0043] Since the band gap of the oxide semiconductor forming the channel is 2 eV or more, the OS transistor has the characteristic of extremely low off-state current. The off-state current value of the OS transistor with a channel width of 1 μm at room temperature can be 1×10 -12 A or less, 1aA (1×10 -18 A) or less, 1zA(1×10 -21 A) or less or 1yA(1×10 -24 Therefore, by providing the transistor Tn1 between the power supply lines 103 and 104 and turning it off, the current flowing between the power supply lines can be made extremely small. Therefore, the power consumption of the display device can be reduced.

[0044] In addition, even in a high temperature environment, the off-state current of the OS transistor hardly increases. Specifically, even in an environment above room temperature and below 200°C, the off-state current hardly increases. In addition, even in a high temperature environment, the on-state current of the OS transistor is not easy to drop. In addition, even in an environment above 125°C and below 150°C, the ratio of the on-state current to the off-state current of the OS transistor is large, so good switching operation can be performed. Therefore, the semiconductor device using the OS transistor operates stably and has high reliability even in a high temperature environment. That is, by using the OS transistor as a transistor included in the gate line driver circuit 364, the reliability of the display device can be improved.

[0045] In addition, the withstand voltage between the source and the drain of the OS transistor (also referred to as the drain withstand voltage) is high. Therefore, the OS transistor works stably even when driven in a manner of applying a high voltage. For example, in the unit circuit 100, an OS transistor can be used as a transistor connected to a node to which a high voltage is applied. Therefore, a gate line drive circuit including an OS transistor can help improve reliability.

[0046] In addition, the OS transistor can be provided in a layer different from the LTPS transistor, for example. In this case, a layer including the LTPS transistor and a layer including the OS transistor can be stacked. By having such a structure, the area occupied by the gate line driver circuit 364 can be reduced. In particular, in a display device using an organic EL element, a variety of gate line driver circuits are formed. Therefore, in the case where the gate line driver circuit 364 is used in a display device using an organic EL element, the area in which the gate line driver circuit 364 can be configured is smaller. In this case, it is particularly preferred that the OS transistor is provided in a layer different from the LTPS transistor to reduce the area occupied by the gate line driver circuit 364.

[0047] The OS transistor may have a gate, or may have a gate and a back gate. In particular, the OS transistor preferably has a back gate. When the OS transistor has a back gate, the threshold voltage of the OS transistor may be increased or decreased by applying a predetermined potential to the back gate of the OS transistor. Alternatively, the on-state current of the OS transistor may be increased by connecting the back gate of the OS transistor to the gate.

[0048] In addition, as OS transistors and LTPS transistors, transistors having various structures can be used. For example, transistors having various structures such as planar type, staggered type, FIN type, TRI-GATE type, top gate type, bottom gate type, or double gate type (a structure in which gates are arranged on both sides (for example, top and bottom) of a channel forming region) can be used.

[0049] As transistor Tn1, a transistor other than an OS transistor may be used. Any n-channel transistor having a higher withstand voltage than an LTPS transistor used as a p-channel transistor may be used for transistor Tn1. For example, in an n-channel LTPS transistor, the withstand voltage is increased by increasing the channel length or the thickness of the gate insulating film, and the transistor may be used as an n-channel transistor having a higher withstand voltage than an LTPS transistor used as a p-channel transistor for transistor Tn1.

[0050] <Operation Example of Unit Circuit 100> Figure 3 It is explained by Figure 2A The circuit diagram shown is a timing diagram of the operation of the unit circuit 100 .

[0051] Figure 3 CK1 shown is a clock signal supplied to the wiring 101 . Figure 3 CK2 shown is a clock signal supplied to the wiring 102. Figure 3 SP shown is a control signal supplied to the wiring 105 . Figure 3 N1 to N3 shown indicate potential changes of nodes N1 to N3. Figure 3 OUT shown is an output signal output to the wiring 106. Figure 3 In order to illustrate the operation, time t1 to t7 are added.

[0052] 4A to 6B It is schematically shown Figure 3 The circuit diagram shows the operation from time t1 to t7. 4A to 6B In the circuit symbol of the transistor that is turned off, a cross is added. 4A to 6B In FIG. 1 , the thick arrow indicates the current flowing when the transistor is turned on.

[0053] In the following description, the power line 103 is set to the potential VDD (hereinafter referred to as VDD), and the power line 104 is set to the potential VSS (hereinafter referred to as VSS) for description. In addition, the p-channel transistor becomes an on state when the logic level of the signal applied to the gate is L level (low level) and becomes an off state when the logic level is H level (high level). The n-channel transistor becomes an on state when the logic level of the signal applied to the gate is H level and becomes an off state when the logic level is L level. Therefore, sometimes the logic level at which the transistor becomes an on state is called an on level, and the logic level at which the transistor becomes an off state is called an off level. The H level refers to the potential of the high potential side level or VDD based on the control signal or the clock signal. In addition, the L level refers to the potential of the low potential side level or VSS based on the control signal or the clock signal.

[0054] Figure 4A Yes Description Figure 3 The diagram shows the operation during the time period t1-t2. According to CK1, CK2, SP, VDD and VSS, transistors Tp1, Tp3 to Tp5 are turned on, and transistors Tp2 and Tn1 are turned off. OUT becomes the potential of the H level of CK1. N1 and N2 become the L level of SP. N3 becomes VDD, that is, the H level.

[0055] Figure 4B Yes Description Figure 3FIG. 1 is a diagram showing the operation during the time period t2-t3 shown in FIG. According to CK1, CK2, SP, VDD and VSS, transistors Tp1, Tp3 and Tp5 are turned on, and transistors Tp2, Tp4 and transistor Tn1 are turned off. OUT becomes the potential of the H level of CK1. Since transistor Tp4 is turned off, N1 and N2 are electrically floating (floating). Therefore, N1 and N2 maintain the L level of SP. N3 continues to be VDD, that is, the H level.

[0056] Figure 5A Yes Description Figure 3 The diagram shows the operation during the time period t3-t4. According to CK1, CK2, SP, VDD and VSS, transistors Tp1 and Tp5 are turned on, and transistors Tp2 to Tp4 and transistor Tn1 are turned off.

[0057] During the time period t3-t4, transistor Tp4 becomes closed, so N1 and N2 are in a floating state. Capacitor Cp maintains the potential difference between the electrodes at both ends, so the potential of N1 changes as the potential of OUT changes. Specifically, as CK1 changes from H level to L level, the potential of OUT decreases, and the potential of N1 also decreases. As the potential of N1 decreases, transistor Tp3 becomes closed because the gate-source voltage (Vgs) becomes above the threshold voltage (Vth<0). N2 becomes VSS-Vth, which is VSS minus the threshold voltage (Vth) of transistor Tp3, and N1 becomes a potential smaller than VSS-Vth. With the help of transistor Tp3 as a potential adjustment transistor, the potential of the same logic level, such as an L-level signal, can also be set differently between N1 and N2.

[0058] Since N1 has a potential lower than VSS-Vth, OUT can drop to VSS. N3 continues to be VDD, that is, H level.

[0059] In one embodiment of the present invention, in order to control the on state of transistor Tn1 and the off state of transistor Tp5 operating at the same logic level with different potentials, the gate of transistor Tn1 is connected to node N1 and the gate of transistor Tp5 is connected to node N2.

[0060] The potential of the node N1 is lower than the potential of the node N2. By using the potential of the node N1 as a signal of the off level of the n-channel transistor Tn1, the transistor Tn1 can be more reliably turned off. Since the potential of the node N1 is lower than VSS, it is possible to cause degradation and insulation breakdown of the transistor, but since the transistor Tn1 is an OS transistor, such degradation and insulation breakdown can be prevented.

[0061] In addition, VSS-Vth of the node N2 is higher than the potential of the node N1. By using the potential of the node N2 as a signal of the turn-on level of the p-channel transistor Tp5, the transistor Tp5 can be turned on without causing degradation and insulation breakdown of the transistor. Since the potential of the node N2 is lower than that of the node N1, degradation and / or insulation breakdown of the transistors Tp3 and Tp4, which are other transistors connected to the node N2, can be prevented.

[0062] Figure 5B Yes Description Figure 3 FIG. 1 is a diagram showing the operation during the time period t4-t5 shown in FIG. According to CK1, CK2, SP, VDD and VSS, transistors Tp1, Tp3 and Tp5 are turned on, and transistors Tp2, Tp4 and transistor Tn1 are turned off. OUT becomes the potential of the H level of CK1. Since transistor Tp4 is turned off, N1 and N2 become floating. Therefore, N1 and N2 maintain the L level of SP. N3 continues to be VDD, that is, the H level.

[0063] Fig. 6A Yes Description Figure 3 The diagram shows the operation during the time period t5-t6. According to CK1, CK2, SP, VDD and VSS, transistors Tp2 to Tp4 and transistor Tn1 are turned on, and transistors Tp1 and Tp5 are turned off. OUT becomes VDD. N1 and N2 become the potential of SP at the H level. N3 becomes VSS, that is, at the L level.

[0064] Figure 6B Yes Description Figure 3 FIG. 1 is a diagram showing the operation during the time period t6-t7 shown in FIG. According to CK1, CK2, SP, VDD and VSS, transistors Tp2, Tp3 and transistor Tn1 are turned on, and transistors Tp1, Tp4 and Tp5 are turned off. OUT continues to be VDD. Since transistor Tp4 is turned off, N1 and N2 are in a floating state. Therefore, N1 and N2 maintain the H level of SP. N3 continues to be VSS, that is, the L level.

[0065] <Configuration Example of Unit Circuit 100A> Fig. 7A Is with Figure 2A The circuit diagram of the unit circuit 100A is a circuit diagram of a unit circuit 100 having a different structure. Fig. 7A In the description of Figure 2A The above description is used for structures that have repeated descriptions, and the description may be omitted.

[0066] The unit circuit 100A includes transistors Tp1 to Tp7, a transistor Tn1, and a capacitor Cp. The unit circuit 100A can be used for Figure 1B The shift register 350 shown includes unit circuits 100_1 to 100_m. The unit circuit 100A is connected to the wiring 101, the wiring 102, the power supply line 103, the power supply line 104, the wiring 105, and the wiring 106.

[0067] One of the source and drain of the transistor Tp1 is connected to the wiring 101. One of the source and drain of the transistor Tp2 is connected to the power supply line 103. The other of the source and drain of the transistor Tp1 is connected to the other of the source and drain of the transistor Tp2. The other of the source and drain of the transistor Tp1 is connected to the wiring 106. The gate of the transistor Tp1 is connected to one of the source and drain of the transistor Tp3. The gate of the transistor Tp1 is connected to the gate of the transistor Tn1. One electrode of the capacitor Cp is connected to the other of the source and drain of the transistor Tp1. The other electrode of the capacitor Cp is connected to the gate of the transistor Tp1. The gate of the transistor Tp3 is connected to the power supply line 104. The other of the source and drain of the transistor Tp3 is connected to one of the source and drain of the transistor Tp4. The other of the source and drain of the transistor Tp3 is connected to one of the source and drain of the transistor Tp6. The other of the source and drain of transistor Tp3 is connected to the gate of transistor Tp5. The other of the source and drain of transistor Tp4 is connected to wiring 105. The gate of transistor Tp4 is connected to wiring 102. One of the source and drain of transistor Tp5 is connected to power supply line 103. The other of the source and drain of transistor Tp5 is connected to the gate of transistor Tp2. The other of the source and drain of transistor Tp5 is connected to the gate of transistor Tp7. The other of the source and drain of transistor Tp5 is connected to one of the source and drain of transistor Tn1. The other of the source and drain of transistor Tn1 is connected to power supply line 104. The gate of transistor Tp6 is connected to wiring 101. The other of the source and drain of transistor Tp6 is connected to one of the source and drain of transistor Tp7. The other of the source and drain of transistor Tp7 is connected to power supply line 103.

[0068] Transistors Tp1 to Tp7 are p-channel transistors. The semiconductor layer having a channel formation region included in transistors Tp1 to Tp7 includes silicon. As silicon used for the semiconductor layer included in transistors Tp1 to Tp7, single crystal silicon, polycrystalline silicon, amorphous silicon, etc. can be cited. In particular, LTPS transistors containing low-temperature polycrystalline silicon in the semiconductor layer are preferred. By using LTPS transistors as transistors Tp1 to Tp7, transistors with high field effect mobility and good frequency characteristics can be realized. Transistors Tp1 to Tp7 are sometimes referred to as first to seventh p-channel transistors.

[0069] The transistor Tn1 is an n-channel transistor. As the n-channel transistor, it is preferable to use an OS transistor in which an oxide semiconductor is included in a semiconductor layer having a channel formation region.

[0070] <Operation Example of Unit Circuit 100A> Figure 7B It is explained by Fig. 7A The circuit diagram shown is a timing chart showing the operation of the unit circuit 100A. FIG. 8A to FIG. 11B It is schematically shown Figure 7B The circuit diagram shows the operation from time t1 to t9. Figure 7B In order to illustrate the operation, time t1 to t9 are added. Figure 7B and FIG. 8A to FIG. 11B In the description of Figure 3 and 4A to 6B The above description is used for structures that have repeated descriptions, and the description may be omitted.

[0071] Fig. 8A Yes Description Figure 7B The diagram of the operation during the time period t1-t2 shown in FIG. According to CK1, CK2, SP, VDD and VSS, transistors Tp1, Tp3 to Tp5 are turned on, and transistors Tp2, Tp6, Tp7 and transistor Tn1 are turned off. OUT becomes the potential of the H level of CK1. N1 and N2 become the L level of SP. N3 becomes VDD, that is, the H level.

[0072] Figure 8B Yes Description Figure 7B FIG. 1 is a diagram showing the operation during the time period t2-t3 shown in FIG. According to CK1, CK2, SP, VDD and VSS, transistors Tp1, Tp3 and Tp5 are turned on, and transistors Tp2, Tp4, Tp6, Tp7 and transistor Tn1 are turned off. OUT becomes the potential of the H level of CK1. Since transistors Tp4, Tp6 and Tp7 are turned off, N1 and N2 become floating. Therefore, N1 and N2 maintain the L level of SP. N3 continues to be VDD, that is, the H level.

[0073] Fig. 9A Yes Description Figure 7B The diagram shows the operation during the time period t3-t4. According to CK1, CK2, SP, VDD and VSS, transistors Tp1, Tp5 and Tp6 are turned on, and transistors Tp2 to Tp4, Tp7 and transistor Tn1 are turned off.

[0074] During the time period t3-t4, transistors Tp4 and Tp7 are turned off, so N1 and N2 are in a floating state. Capacitor Cp maintains the potential difference between the electrodes at both ends, so the potential of N1 changes with the change of OUT. Specifically, as CK1 changes from the H level to the L level, the potential of N1 also decreases. As the potential of N1 decreases, transistor Tp3 becomes turned off because the gate-source voltage (Vgs) becomes above the threshold voltage (Vth<0). N2 becomes VSS-Vth, which is VSS minus the threshold voltage (Vth) of transistor Tp3, and N1 becomes a potential smaller than VSS-Vth. With the help of transistor Tp3 as a potential adjustment transistor, the potential of the same logic level, such as the L level signal, can also be set differently between N1 and N2.

[0075] Since N1 has a potential lower than VSS-Vth, OUT can drop to VSS. N3 continues to be VDD, that is, H level.

[0076] In one embodiment of the present invention, in order to control the on state of transistor Tn1 and the off state of transistor Tp5 operating at the same logic level with different potentials, the gate of transistor Tn1 is connected to node N1 and the gate of transistor Tp5 is connected to node N2.

[0077] The potential of the node N1 is lower than the potential of the node N2. By using the potential of the node N1 as a signal of the off level of the n-channel transistor Tn1, the transistor Tn1 can be more reliably turned off. Since the potential of the node N1 is lower than VSS, it is possible to cause degradation and insulation breakdown of the transistor, but since the transistor Tn1 is an OS transistor, such degradation and insulation breakdown can be prevented.

[0078] In addition, VSS-Vth of the node N2 is higher than the potential of the node N1. By using the potential of the node N2 as a signal of the turn-on level of the p-channel transistor Tp5, the transistor Tp5 can be turned on without causing degradation and insulation breakdown of the transistor. Since the potential of the node N2 is lower than that of the node N1, degradation and / or insulation breakdown of the transistors Tp3 and Tp4, which are other transistors connected to the node N2, can be prevented.

[0079] Fig. 9B Yes Description Figure 7BFIG. 1 is a diagram showing the operation during the time period t4-t5 shown in FIG. According to CK1, CK2, SP, VDD and VSS, transistors Tp1, Tp3 and Tp5 are turned on, and transistors Tp2, Tp4, Tp6, Tp7 and transistor Tn1 are turned off. OUT becomes the potential of the H level of CK1. Since transistors Tp4, Tp6 and Tp7 are turned off, N1 and N2 become floating. Therefore, N1 and N2 maintain the L level of SP. N3 continues to be VDD, that is, the H level.

[0080] Fig. 10A Yes Description Figure 7B The diagram of the operation during the time period t5-t6 shown in FIG. According to CK1, CK2, SP, VDD and VSS, transistors Tp2 to Tp4, Tp7 and transistor Tn1 are turned on, and transistors Tp1, Tp5 and Tp6 are turned off. OUT becomes VDD. N1 and N2 become the potential of the H level of SP. N3 becomes VSS, that is, the L level.

[0081] Fig. 10B Yes Description Figure 7B FIG. 1 is a diagram showing the operation during the time period t6-t7 shown in FIG. According to CK1, CK2, SP, VDD and VSS, transistors Tp2, Tp3, Tp7 and transistor Tn1 are turned on, and transistors Tp1, Tp4, Tp5 and Tp6 are turned off. OUT continues to be VDD. Since transistors Tp4 and Tp6 are turned off, N1 and N2 are in a floating state. Therefore, N1 and N2 maintain the H level of SP. N3 continues to be VSS, that is, the L level.

[0082] Fig.11A Yes Description Figure 7B FIG. 1 is a diagram showing the operation during the time period t7-t8 shown in FIG. According to CK1, CK2, SP, VDD and VSS, transistors Tp2, Tp3, Tp6, Tp7 and transistor Tn1 are turned on, and transistors Tp1, Tp4 and Tp5 are turned off. OUT continues to be VDD. Since transistors Tp6 and Tp7 are turned on, N1 and N2 become VDD, that is, H level. By adopting this structure, N1 and N2 are regularly supplied with H level, so that transistor Tp1 as a pull-up transistor can continue to be in the off state. N3 continues to be VSS, that is, L level.

[0083] Fig. 11B Yes Description Figure 7BFIG. 1 is a diagram showing the operation during the time period t8-t9 shown in FIG. According to CK1, CK2, SP, VDD and VSS, transistors Tp2, Tp3, Tp7 and transistor Tn1 are turned on, and transistors Tp1, Tp4, Tp5 and Tp6 are turned off. OUT continues to be VDD. Since transistors Tp4 and Tp6 are turned off, N1 and N2 are in a floating state. Therefore, N1 and N2 maintain VDD, that is, H level. N3 continues to be VSS, that is, L level.

[0084] <Modification Example 1 of Unit Circuit 100A> The following is a modified example of the above-mentioned unit circuit 100A. Fig. 7A The above description is used for the structure that is repeated in the description of the unit circuit 100A, and the description may be omitted.

[0085] The wiring or transistor connected to the transistor Tp5 in the unit circuit 100A may have FIG. 12A to FIG. 14C The structure shown.

[0086] Fig. 12A The unit circuit 100B1 shown has the following structure: in the structure of the unit circuit 100A, one of the source and drain of the transistor Tp5 is connected to the wiring 102. By adopting this structure, the number of transistors connected to the power line 103 can be reduced, thereby reducing the load of the power line 103. In addition, since the potential of one of the source and drain of the transistor Tp5 can be changed, the degradation of the transistor Tp5 can be suppressed. In addition, during the time t1-t2, the node N3 can be made L level, so that the transistors Tp2 and Tp7 are turned on. By making the transistor Tp2 turn on, VDD can be output to OUT. Therefore, it is easy to set OUT to the potential of the H level.

[0087] Fig. 12B The unit circuit 100B2 shown has the following structure: in the structure of the unit circuit 100A, one of the source and drain of the transistor Tp5 is connected to the wiring 105. By adopting this structure, the number of transistors connected to the power line 103 can be reduced, thereby reducing the load of the power line 103. In addition, since the potential of one of the source and drain of the transistor Tp5 can be changed, the degradation of the transistor Tp5 can be suppressed. In addition, during the time t1-t2, the node N3 can be made L level, so that the transistors Tp2 and Tp7 are turned on. By making the transistor Tp2 turn on, VDD can be output to OUT. Therefore, it is easy to set OUT to the potential of the H level.

[0088] Fig.13AThe unit circuit 100B3 shown has a structure in which, in the structure of the unit circuit 100A, the gate of the transistor Tp5 is connected to the wiring 101. With this structure, the number of transistors connected to the node N2 can be reduced, thereby reducing the parasitic capacitance of the node N2.

[0089] Fig. 13B The unit circuit 100B4 shown has the following structure: in the structure of the unit circuit 100A, the gate of the transistor Tp5 is connected to the wiring 101, and one of the source and the drain of the transistor Tp5 is connected to the wiring 102. This structure is equivalent to the structure of the modified example shown in the combined unit circuit 100B1 and the unit circuit 100B3. In this way, in one embodiment of the present invention, a structure combining the above-mentioned modified examples can also be adopted. By adopting this structure, the load of the power supply line 103 can be reduced, and the parasitic capacitance of the node N2 can be reduced.

[0090] Fig. 13C The unit circuit 100B5 shown has the following structure: in the structure of the unit circuit 100A, the gate of the transistor Tp5 is connected to the wiring 101, and one of the source and the drain of the transistor Tp5 is connected to the wiring 105. This structure is equivalent to the structure of the modified example shown in the combined unit circuit 100B2 and the unit circuit 100B3. In this way, in one embodiment of the present invention, a structure combining the above-mentioned modified examples can also be adopted. By adopting this structure, the load of the power supply line 103 can be reduced, and the parasitic capacitance of the node N2 can be reduced. In addition, since the potential of one of the source and the drain of the transistor Tp5 can be changed, the degradation of the transistor Tp5 can be suppressed.

[0091] Fig.14A The unit circuit 100B6 shown has a structure in which, in the structure of the unit circuit 100A, the gate of the transistor Tp5 is connected to the wiring 102. With this structure, the number of transistors connected to the node N2 can be reduced, thereby reducing the parasitic capacitance of the node N2.

[0092] Fig. 14B The unit circuit 100B7 shown has the following structure: in the structure of the unit circuit 100A, the gate of the transistor Tp5 is connected to the wiring 102, and one of the source and the drain of the transistor Tp5 is connected to the wiring 101. This structure is equivalent to the structure of the modified example shown in the combined unit circuit 100B1 and the unit circuit 100B6. In this way, in one embodiment of the present invention, a structure combining the above-mentioned modified examples can also be adopted. By adopting this structure, the load of the power supply line 103 can be reduced, and the parasitic capacitance of the node N2 can be reduced.

[0093] Fig. 14CThe unit circuit 100B8 shown has the following structure: in the structure of the unit circuit 100A, the gate of the transistor Tp5 is connected to the wiring 102, and one of the source and the drain of the transistor Tp5 is connected to the wiring 106. This structure is equivalent to the structure of the modified example shown in the combined unit circuit 100B2 and the unit circuit 100B6. In this way, in one embodiment of the present invention, a structure combining the above-mentioned modified examples can also be adopted. By adopting this structure, the load of the power supply line 103 can be reduced, and the parasitic capacitance of the node N2 can be reduced.

[0094] <Modification Example 2 of Unit Circuit 100A> The wiring or transistor connected to the transistor Tn1 in the unit circuit 100A may have FIG. 15A to FIG. 15C The structure shown.

[0095] Fig.15A The unit circuit 100C1 shown has a structure in which the other of the source and the drain of the transistor Tn1 is connected to the wiring 101 in the structure of the unit circuit 100A. By adopting this structure, the number of transistors connected to the power supply line 104 can be reduced, so that the load on the power supply line 104 can be reduced. In addition, since the potential of the other of the source and the drain of the transistor Tn1 can be changed, the degradation of the transistor Tn1 can be suppressed.

[0096] Fig. 15B The unit circuit 100C2 shown has the following structure: in the structure of the unit circuit 100A, the other of the source and drain of the transistor Tn1 is connected to the wiring 102. By adopting this structure, the number of transistors connected to the power line 104 can be reduced, so that the load of the power line 104 can be reduced. In addition, since the potential of the other of the source and drain of the transistor Tn1 can be changed, the degradation of the transistor Tn1 can be suppressed. In addition, during the time t3-t4, the other of the source and drain of the transistor Tn1 can be set to the H level, thereby making it easy to turn off the transistor Tn1. At this time, a large voltage is applied to the transistor Tn1, but by adopting the OS transistor as the transistor Tn1, the degradation and insulation breakdown of the transistor Tn1 can be prevented.

[0097] Fig. 15C The unit circuit 100C3 shown has a structure in which the other of the source and the drain of the transistor Tn1 is connected to the wiring 105 in the structure of the unit circuit 100A. By adopting this structure, the number of transistors connected to the power supply line 104 can be reduced, so that the load on the power supply line 104 can be reduced. In addition, since the potential of the other of the source and the drain of the transistor Tn1 can be changed, the degradation of the transistor Tn1 can be suppressed.

[0098] The modified examples shown in the unit circuits 100C1 to 100C3 can be combined with the modified examples of the unit circuits 100B1 to 100B8 described above. By adopting this structure, the load on the power supply line 103 and / or the parasitic capacitance of the node N2 can be reduced.

[0099] <Variation Example 3 of Unit Circuit 100A> The wiring or transistor connected to the transistors Tp6 and Tp7 in the unit circuit 100A may have FIG. 16A to FIG. 18C The structure shown.

[0100] Fig.16A The unit circuit 100D1 shown has a structure in which the other of the source and the drain of the transistor Tp7 is connected to the wiring 102 in the structure of the unit circuit 100A. By adopting this structure, the number of transistors connected to the power supply line 103 can be reduced, so that the load of the power supply line 103 can be reduced. In addition, since the potential of the other of the source and the drain of the transistor Tp7 can be changed, the degradation of the transistor Tp7 can be suppressed.

[0101] Fig. 16B The unit circuit 100D2 shown has a structure in which the other of the source and the drain of the transistor Tp7 is connected to the wiring 106 in the structure of the unit circuit 100A. By adopting this structure, the number of transistors connected to the power supply line 103 can be reduced, so that the load of the power supply line 103 can be reduced. In addition, since the potential of the other of the source and the drain of the transistor Tp7 can be changed, the degradation of the transistor Tp7 can be suppressed.

[0102] Fig.17A The unit circuit 100D3 shown has the following structure: in the structure of the unit circuit 100A, the other of the source and the drain of the transistor Tp7 is connected to the node N2, and one of the source and the drain of the transistor Tp6 is connected to the power supply line 103. By adopting this structure, the transistor Tp6 can be connected to the node N2 through the transistor Tp7, so the influence of the noise brought to the node N2 by the clock signal CK1 supplied to the gate of the transistor Tp6 can be reduced. In addition, since the potential of one of the source and the drain of the transistor Tp6 can be changed, the degradation of the transistor Tp6 can be suppressed.

[0103] Fig. 17BThe unit circuit 100D4 shown has the following structure: in the structure of the unit circuit 100A, the other of the source and the drain of the transistor Tp7 is connected to the node N2, and one of the source and the drain of the transistor Tp6 is connected to the wiring 102. By adopting this structure, the transistor Tp6 can be connected to the node N2 through the transistor Tp7, so the influence of the noise brought to the node N2 by the clock signal CK1 supplied to the gate of the transistor Tp6 can be reduced. In addition, since the potential of one of the source and the drain of the transistor Tp6 can be changed, the degradation of the transistor Tp6 can be suppressed.

[0104] Fig. 17C The unit circuit 100D5 shown has the following structure: in the structure of the unit circuit 100A, the other of the source and the drain of the transistor Tp7 is connected to the node N2, and one of the source and the drain of the transistor Tp6 is connected to the wiring 106. By adopting this structure, the transistor Tp6 can be connected to the node N2 through the transistor Tp7, so the influence of the noise of the clock signal CK1 supplied to the gate of the transistor Tp6 on the node N2 can be reduced.

[0105] exist Fig.18A In the unit circuit 100D6 shown, the transistor Tp6 in the structure of the unit circuit 100A is omitted. By adopting this structure, the number of transistors included in the unit circuit can be reduced. In addition, the influence of noise on the node N2 caused by the clock signal CK1 supplied to the gate of the transistor Tp6 can be reduced.

[0106] exist Fig.18B In the unit circuit 100D7 shown in the figure, the transistor Tp6 in the structure of the unit circuit 100A is omitted, and the other of the source and the drain of the transistor Tp7 is connected to the wiring 102. This structure is equivalent to the structure of the modified example shown in the combined unit circuit 100D1 and the unit circuit 100D6. In this way, in one embodiment of the present invention, a structure combining the above-mentioned modified examples can also be adopted. By adopting this structure, the number of transistors included in the unit circuit can be reduced, and the load on the power supply line 103 can be reduced.

[0107] exist Fig.18C In the unit circuit 100D8 shown, the transistor Tp6 in the unit circuit 100A is omitted and the other of the source and the drain of the transistor Tp7 is connected to the wiring 101. With this structure, the number of transistors included in the unit circuit can be reduced, and the load on the power supply line 103 can be reduced.

[0108] The modified examples shown in unit circuits 100D1 to 100D8 can be combined with the modified examples of unit circuits 100B1 to 100B8 and unit circuits 100C1 to 100C3. By adopting this structure, the load of power supply line 103, parasitic capacitance of node N2 and / or the number of transistors can be reduced.

[0109] <Variation Example 4 of Unit Circuit 100A> The wiring or transistor connected to the transistor Tp4 in the unit circuit 100A may have FIG. 19A to FIG. 20C The structure shown. FIG. 19A to FIG. 20C The unit circuits 100E1 to 100E6 shown in the figure have a structure in which a transistor Tp8 is added. The transistor Tp8 is a p-channel transistor similarly to the transistors Tp1 to Tp7.

[0110] Fig.19A The unit circuit 100E1 shown has the following structure: in the structure of the unit circuit 100A, the gate of the transistor Tp4 is connected to the wiring 105, and the other of the source and the drain of the transistor Tp4 is connected to the wiring 102. In addition, in the unit circuit 100E1, the gate of the transistor Tp8 is connected to the wiring 107, one of the source and the drain is connected to the node N2, and the other of the source and the drain is connected to the power supply line 103. By adopting this structure, the H level can be regularly supplied to N1 and N2 regardless of the state of the transistor Tp4, so that the transistor Tp1 as a pull-up transistor can be kept in the off state.

[0111] The wiring 107 is used as a reset line to which a reset signal is supplied. The reset signal is a signal for regularly supplying an H-level potential to the node N2.

[0112] Fig.19B The unit circuit 100E2 shown has the following structure: in the structure of the unit circuit 100A, the gate of the transistor Tp4 is connected to the wiring 105, and the other of the source and the drain of the transistor Tp4 is connected to the power supply line 104. In addition, in the unit circuit 100E2, the gate of the transistor Tp8 is connected to the wiring 107, one of the source and the drain is connected to the node N2, and the other of the source and the drain is connected to the power supply line 103. By adopting this structure, the H level can be regularly supplied to N1 and N2 regardless of the state of the transistor Tp4, so that the transistor Tp1 as a pull-up transistor can be kept in the off state.

[0113] Fig.19CThe unit circuit 100E3 shown has the following structure: in the structure of the unit circuit 100A, the gate of the transistor Tp4 and the other of the source and the drain of the transistor Tp4 are connected to the wiring 105. In addition, in the unit circuit 100E3, the gate of the transistor Tp8 is connected to the wiring 107, one of the source and the drain is connected to the node N2, and the other of the source and the drain is connected to the power supply line 103. By adopting this structure, the H level can be regularly supplied to N1 and N2 regardless of the state of the transistor Tp4, so that the transistor Tp1 as the pull-up transistor can continue to be in the off state. In addition, the wiring 102 can be omitted.

[0114] Fig. 20A The unit circuit 100E4 shown has the following structure: in the structure of the unit circuit 100A, the gate of the transistor Tp4 is connected to the wiring 105, and the other of the source and the drain of the transistor Tp4 is connected to the wiring 102. In addition, in the unit circuit 100E4, the gate of the transistor Tp8 is connected to the wiring 107, one of the source and the drain is connected to the node N2, and the other of the source and the drain is connected to the wiring 101. By adopting this structure, the H level can be regularly supplied to N1 and N2 regardless of the state of the transistor Tp4, so that the transistor Tp1 as the pull-up transistor can continue to be in the off state. In addition, even if the transistor Tp8 is added, the number of transistors connected to the power line 103 does not increase, so the increase in the load of the power line 103 can be suppressed.

[0115] Fig. 20B The unit circuit 100E5 shown has the following structure: in the structure of the unit circuit 100A, the gate of the transistor Tp4 is connected to the wiring 105, and the other of the source and the drain of the transistor Tp4 is connected to the power supply line 104. In addition, in the unit circuit 100E5, the gate of the transistor Tp8 is connected to the wiring 107, one of the source and the drain is connected to the node N2, and the other of the source and the drain is connected to the wiring 101. By adopting this structure, the H level can be regularly supplied to N1 and N2 regardless of the state of the transistor Tp4, so the transistor Tp1 as the pull-up transistor can continue to be in the off state. In addition, even if the transistor Tp8 is added, the number of transistors connected to the power supply line 103 does not increase, so the increase in the load of the power supply line 103 can be suppressed. In addition, the wiring 102 can be omitted.

[0116] Fig. 20CThe unit circuit 100E6 shown has the following structure: in the structure of the unit circuit 100A, the gate of the transistor Tp4 and the other of the source and the drain of the transistor Tp4 are connected to the wiring 105. In addition, in the unit circuit 100E6, the gate of the transistor Tp8 is connected to the wiring 107, one of the source and the drain is connected to the node N2, and the other of the source and the drain is connected to the wiring 101. By adopting this structure, the H level can be regularly supplied to N1 and N2 regardless of the state of the transistor Tp4, so the transistor Tp1 as the pull-up transistor can continue to be in the off state. In addition, even if the transistor Tp8 is added, the number of transistors connected to the power line 103 does not increase, so the increase in the load of the power line 103 can be suppressed. In addition, the wiring 102 can be omitted.

[0117] The modified examples shown in unit circuits 100E1 to 100E6 can be combined with the modified examples of unit circuits 100B1 to 100B8, unit circuits 100C1 to 100C3, and unit circuits 100D1 to 100D8. By adopting this structure, the load of power supply line 103, parasitic capacitance of node N2, and / or the number of transistors can be reduced.

[0118] To illustrate FIG. 19A to FIG. 20C An example of the working of the circuit diagram shown is Fig.21 Show Fig.19C The timing diagram of the unit circuit 100E3 shown in FIG. FIG. 22A to FIG. 25B It is schematically shown Fig.21 The circuit diagram shows the operation from time t1 to t9. Note that Fig.21 and FIG. 22A to FIG. 25B In the description of Figure 7B and FIG. 8A to FIG. 11B The above description is used for repeated structures, and the description may be omitted.

[0119] Fig.21 RE shown is a reset signal supplied to the wiring 107. In addition, CK1, CK2, SP, N1, N2, N3 and OUT are Figure 7B The same description applies.

[0120] Fig.22A Yes Description Fig.21 The diagram of the operation during the time t1-t2 shown in FIG. According to CK1, CK2, SP, RE, VDD and VSS, transistors Tp1, Tp3 to Tp5 are turned on, and transistors Tp2, Tp6, Tp7, Tp8 and transistor Tn1 are turned off. OUT becomes the potential of the H level of CK1. N1 and N2 become the L level of SP. N3 becomes VDD, that is, the H level.

[0121] Fig. 22BYes Description Fig.21 FIG. 1 is a diagram showing the operation during the time period t2-t3 shown in FIG. According to CK1, CK2, SP, RE, VDD and VSS, transistors Tp1, Tp3 and Tp5 are turned on, and transistors Tp2, Tp4, Tp6, Tp7, Tp8 and transistor Tn1 are turned off. OUT becomes the potential of the H level of CK1. Since transistors Tp4, Tp6, Tp7 and Tp8 are turned off, N1 and N2 become floating. Therefore, N1 and N2 maintain the L level of SP. N3 continues to be VDD, that is, the H level.

[0122] Fig.23A Yes Description Fig.21 The diagram shows the operation during the time period t3-t4. According to CK1, CK2, SP, RE, VDD and VSS, transistors Tp1, Tp5 and Tp6 are turned on, and transistors Tp2 to Tp4, Tp7, Tp8 and transistor Tn1 are turned off.

[0123] During the time period t3-t4, transistors Tp4, Tp7 and Tp8 are turned off, so N1 and N2 are in a floating state. Capacitor Cp maintains the potential difference between the electrodes at both ends, so the potential of N1 changes with the change of OUT. Specifically, as CK1 changes from the H level to the L level, the potential of N1 also decreases. As the potential of N1 decreases, transistor Tp3 becomes turned off because the gate-source voltage (Vgs) becomes above the threshold voltage (Vth<0). N2 becomes VSS-Vth, which is VSS minus the threshold voltage (Vth) of transistor Tp3, and N1 becomes a potential smaller than VSS-Vth. With the help of transistor Tp3 as a potential adjustment transistor, the potential of the same logic level, such as the L level signal, can also be set differently between N1 and N2.

[0124] Since N1 has a potential lower than VSS-Vth, OUT can drop to VSS. N3 continues to be VDD, that is, H level.

[0125] In one embodiment of the present invention, in order to control the on state of transistor Tn1 and the off state of transistor Tp5 operating at the same logic level (L level) with different potentials, the gate of transistor Tn1 is connected to node N1 and the gate of transistor Tp5 is connected to node N2.

[0126] The potential of the node N1 is lower than the potential of the node N2. By using the potential of the node N1 as a signal of the off level of the n-channel transistor Tn1, the transistor Tn1 can be more reliably turned off. Since the potential of the node N1 is lower than VSS, it is possible to cause degradation and insulation breakdown of the transistor, but since the transistor Tn1 is an OS transistor, such degradation and insulation breakdown can be prevented.

[0127] In addition, VSS-Vth of the node N2 is higher than the potential of the node N1. By using the potential of the node N2 as a signal of the turn-on level of the p-channel transistor Tp5, the transistor Tp5 can be turned on without causing degradation and insulation breakdown of the transistor. Since the potential of the node N2 is lower than that of the node N1, degradation and / or insulation breakdown of the transistors Tp3, Tp4, and Tp8, which are other transistors connected to the node N2, can be prevented.

[0128] Fig. 23B Yes Description Fig.21 FIG. 1 is a diagram showing the operation during the time period t4-t5 shown in FIG. According to CK1, CK2, SP, RE, VDD and VSS, transistors Tp1, Tp3 and Tp5 are turned on, and transistors Tp2, Tp4, Tp6, Tp7, Tp8 and transistor Tn1 are turned off. OUT becomes the potential of the H level of CK1. Since transistors Tp4, Tp6, Tp7 and Tp8 are turned off, N1 and N2 become floating. Therefore, N1 and N2 maintain the L level of SP. N3 continues to be VDD, that is, the H level.

[0129] Fig.24A Yes Description Fig.21 FIG. 1 is a diagram showing the operation during the time period t5-t6 shown in FIG. According to CK1, CK2, SP, RE, VDD and VSS, transistors Tp2, Tp3, Tp7, Tp8 and transistor Tn1 are turned on, and transistors Tp1, Tp4, Tp5 and Tp6 are turned off. OUT becomes VDD. Since transistor Tp8 becomes turned on, N1 and N2 become H level. By adopting this structure, N1 and N2 are regularly supplied with H level, so that transistor Tp1 as a pull-up transistor can continue to be in the off state. N3 becomes VSS, that is, L level.

[0130] Fig. 24B Yes Description Fig.21FIG. 1 is a diagram showing the operation during the time period t6-t7 shown in FIG. According to CK1, CK2, SP, RE, VDD and VSS, transistors Tp2, Tp3, Tp7 and transistor Tn1 are turned on, and transistors Tp1, Tp4, Tp5, Tp6 and Tp8 are turned off. OUT continues to be VDD. Since transistors Tp4, Tp6 and Tp8 are turned off, N1 and N2 are in a floating state. Therefore, N1 and N2 maintain VDD, that is, H level. N3 continues to be VSS, that is, L level.

[0131] Fig.25A Yes Description Fig.21 FIG. 1 is a diagram showing the operation during the time period t7-t8 shown in FIG. According to CK1, CK2, SP, RE, VDD and VSS, transistors Tp2, Tp3, Tp6, Tp7 and transistor Tn1 are turned on, and transistors Tp1, Tp4, Tp5 and Tp8 are turned off. OUT continues to be VDD. Since transistors Tp6 and Tp7 are turned on, N1 and N2 become H level. By adopting this structure, N1 and N2 are regularly supplied with H level, so that transistor Tp1 as a pull-up transistor can continue to be in the off state. N3 continues to be VSS, that is, L level.

[0132] Fig.25B Yes Description Fig.21 FIG. 1 is a diagram showing the operation during the time period t8-t9 shown in FIG. According to CK1, CK2, SP, RE, VDD and VSS, transistors Tp2, Tp3, Tp7 and transistor Tn1 are turned on, and transistors Tp1, Tp4, Tp5, Tp6 and Tp8 are turned off. OUT continues to be the potential of VDD of power supply line 103. Since transistors Tp4, Tp6 and Tp8 are turned off, N1 and N2 are in a floating state. Therefore, N1 and N2 maintain VDD, that is, H level. N3 continues to be VSS, that is, L level.

[0133] <Variation Example 5 of Unit Circuit 100A> The node N1 connected to the transistor Tp3 in the unit circuit 100A may have Fig.26 The structure shown. Fig.26 The unit circuit 100F shown has a structure in which transistors Tp3_A and Tp3_B are provided as transistors used as the transistor Tp3. The transistors Tp3_A and Tp3_B are p-channel transistors similarly to the transistors Tp1 to Tp7.

[0134] By adopting Fig.26In the structure of FIG. 1 , a potential adjustment transistor can be provided between the node N1 and the transistor Tp6. Since the potential of the node N1 is lower than VSS, it may cause the degradation and insulation breakdown of the transistor. However, by providing the transistor Tp3_B, the potential of the node between the transistor Tp6 and the transistor Tp3_B is set to a potential substantially the same as the potential of the node N2. As a result, the degradation and / or insulation breakdown of the transistor Tp6 can be prevented.

[0135] In addition, by providing transistor Tp3_A, VSS-Vth of node N2 can be made higher than the potential of node N1. By using the potential of node N2 as a signal of the turn-on level of p-channel transistor Tp5, transistor Tp5 can be turned on without causing degradation and insulation breakdown of the transistor. Since the potential of node N2 is lower than that of node N1, degradation and / or insulation breakdown of transistors Tp4 and Tp5, which are other transistors connected to node N2, can be prevented.

[0136] The modification example shown in the unit circuit 100F can be combined with the modification examples of the unit circuits 100B1 to 100B8, the unit circuits 100C1 to 100C3, the unit circuits 100D1 to 100D8, and the unit circuits 100E1 to 100E6. By adopting this structure, the load of the power supply line 103, the parasitic capacitance of the node N2, and / or the number of transistors can be reduced.

[0137] <Variation Example 6 of Unit Circuit 100A> The number of output signals OUT in the unit circuit 100A may be plural. Fig.27A The unit circuit 100G shown includes wirings 106P and 106N for outputting output signals. The wiring 106P outputs an output signal OUTP equivalent to the output signal OUT output by the unit circuit 100A. The wiring 106N outputs an output signal OUTN corresponding to the potential change of the node N3. Fig.27B Shown including Fig.27A The circuit diagram of the shift register 350 of the unit circuit 100G is shown in FIG. As the unit circuits 100G_1 to 100G_m arranged in each row, Fig.27A The unit circuit 100G is shown.

[0138] like Fig.27B As shown, the output signal OUTP is suitable for being used as a selection signal for turning on a p-channel transistor. In addition, the output signal OUTN is suitable for being used as a selection signal for turning on an n-channel transistor. Therefore, the structure of the unit circuit 100G can be suitable for a pixel circuit having an LTPO structure.

[0139] The modification example shown in the unit circuit 100G can be combined with the modification examples of the above-mentioned unit circuits 100B1 to 100B8, unit circuits 100C1 to 100C3, unit circuits 100D1 to 100D8, unit circuits 100E1 to 100E6, and unit circuit 100F. By adopting this structure, the load of the power supply line 103, the parasitic capacitance of the node N2, and / or the number of transistors can be reduced.

[0140] In addition, in the unit circuit 100, the unit circuit 100A, the unit circuit 100B1 to 100B8, the unit circuit 100C1 to 100C3, the unit circuit 100D1 to 100D8, the unit circuit 100E1 to 100E6, the unit circuit 100F and the unit circuit 100G and the unit circuits combining them, the gate of the transistor Tn1 can also be connected to the node N2. By connecting the gate of the transistor Tn1 to the node N2, the degradation and / or insulation breakdown of the transistor Tn1 can be prevented. Therefore, it is easy to use an LTPS transistor as the transistor Tn1. Of course, even if the gate of the transistor Tn1 is connected to the node N2, an OS transistor can be used as the transistor Tn1.

[0141] In the unit circuit described in the present embodiment, the driving load of transistor Tp1 is greater than the driving loads of transistors Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. Therefore, W (channel width) / L (channel length) of transistor Tp1 is preferably greater than W / L of transistor Tp3. W / L of transistor Tp1 is preferably greater than W / L of transistor Tp4. W / L of transistor Tp1 is preferably greater than W / L of transistor Tp5. W / L of transistor Tp1 is preferably greater than W / L of transistor Tp6. W / L of transistor Tp1 is preferably greater than W / L of transistor Tp7. W / L of transistor Tp1 is preferably greater than W / L of transistor Tp8. In addition, the driving load of transistor Tp1 is greater than the sum of the driving loads of transistors Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. Therefore, the W / L of transistor Tp1 is preferably greater than the sum of the W / Ls of transistors Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. Of course, the W / L of transistor Tp1 is preferably greater than the sum of the W / Ls of at least two of transistors Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. For example, it is preferred that the W / L of transistor Tp1 is greater than the sum of the W / Ls of transistors Tp3, Tp4, Tp5, Tp6, and Tp7, and greater than the sum of the W / Ls of transistors Tp3, Tp4, and Tp5.

[0142] In the unit circuit described in the present embodiment, the driving load of transistor Tp2 is greater than the driving load of transistors Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. Therefore, W (channel width) / L (channel length) of transistor Tp2 is preferably greater than W / L of transistor Tp3. W / L of transistor Tp2 is preferably greater than W / L of transistor Tp4. W / L of transistor Tp2 is preferably greater than W / L of transistor Tp5. W / L of transistor Tp2 is preferably greater than W / L of transistor Tp6. W / L of transistor Tp2 is preferably greater than W / L of transistor Tp7. W / L of transistor Tp2 is preferably greater than W / L of transistor Tp8. In addition, the driving load of transistor Tp2 is greater than the sum of the driving loads of transistors Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. Therefore, the W / L of transistor Tp2 is preferably greater than the sum of the W / Ls of transistors Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. Of course, the W / L of transistor Tp2 is preferably greater than the sum of the W / Ls of at least two of transistors Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. For example, the W / L of transistor Tp2 is preferably greater than the sum of the W / Ls of transistors Tp3, Tp4, Tp5, Tp6, and Tp7, and greater than the sum of the W / Ls of transistors Tp3, Tp4, and Tp5.

[0143] In the unit circuit described in the present embodiment, transistor Tp1 changes the potential of OUT, and transistor Tp2 maintains the potential of OUT. The load of transistor Tp1 is very large. Therefore, the W / L of transistor Tp1 is preferably greater than the W / L of transistor Tp2. In addition, the driving load of transistor Tp1 is greater than the sum of the driving loads of transistors Tp2, Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. Therefore, the W / L of transistor Tp1 is preferably greater than the sum of the W / L of transistors Tp2, Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. Of course, the W / L of transistor Tp1 is preferably greater than the sum of the W / L of at least two of transistors Tp2, Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8.

[0144] In the unit circuit described in the present embodiment, when an OS transistor is used as the transistor Tn1 and an LTPS transistor is used as the transistors Tp1, Tp2, Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8, the mobility of the transistor Tn1 is smaller than the mobility of the transistors Tp1, Tp2, Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. Therefore, the W / L of the transistor Tn1 is preferably greater than the W / L of the transistor Tp1. The W / L of the transistor Tn1 is preferably greater than the W / L of the transistor Tp2. The W / L of the transistor Tn1 is preferably greater than the W / L of the transistor Tp3. The W / L of the transistor Tn1 is preferably greater than the W / L of the transistor Tp4. The W / L of the transistor Tn1 is preferably greater than the W / L of the transistor Tp5. The W / L of the transistor Tn1 is preferably greater than the W / L of the transistor Tp6. The W / L of the transistor Tn1 is preferably greater than the W / L of the transistor Tp7. The W / L of the transistor Tn1 is preferably larger than the W / L of the transistor Tp8. Note that since the transistor Tp1 charges and discharges a large load, the W / L of the transistor Tp1 may also be larger than the W / L of the transistor Tn1.

[0145] The signal from SP is transmitted to the gate of transistor Tp1 through transistors Tp4 and Tp3. Therefore, by improving the driving capabilities of transistors Tp4 and Tp3, the operating speed can be improved. Therefore, the W / L of transistor Tp3 is preferably greater than the W / L of transistor Tp5. The W / L of transistor Tp3 is preferably greater than the W / L of transistor Tp6. The W / L of transistor Tp3 is preferably greater than the W / L of transistor Tp7. The W / L of transistor Tp3 is preferably greater than the W / L of transistor Tp8. The W / L of transistor Tp4 is preferably greater than the W / L of transistor Tp5. The W / L of transistor Tp4 is preferably greater than the W / L of transistor Tp6. The W / L of transistor Tp4 is preferably greater than the W / L of transistor Tp7. The W / L of transistor Tp4 is preferably greater than the W / L of transistor Tp8.

[0146] This embodiment mode can be combined with other embodiment modes as appropriate.

[0147] Implementation Method 2 In this embodiment, refer to Figures 28 to 38C A display device according to one embodiment of the present invention will be described.

[0148] <Perspective view and cross-sectional view of display device> Fig.28 A perspective view showing a display device 300A is shown. Fig.29A A cross-sectional view of the display device 300A is shown. Fig.29B and Fig.29C Yes Description Fig.29A FIG. 1 is a diagram showing a structural example of a transistor in a cross-sectional view.

[0149] The display device 300A has a structure in which a substrate 352 and a substrate 351 are bonded together. Fig.28 In FIG. 3 , the substrate 352 is indicated by a dotted line.

[0150] The display device 300A includes a display portion 362 , a connection portion 340 , a gate line driving circuit 364 , wiring 365 , and the like. Fig.28 FIG. 3 shows an example in which IC 373 and FPC 372 are mounted in a display device 300A. Fig.28 The structure shown is called a display module including a display device 300A, an IC (integrated circuit), and an FPC.

[0151] The connection portion 340 is disposed outside the display portion 362. The connection portion 340 may be disposed along one side or multiple sides of the display portion 362. The number of the connection portion 340 may also be one or more. Fig.28 The example in which the connection part 340 is provided so as to surround the four sides of the display part is shown. In the connection part 340, by connecting the common electrode of the light-emitting device to the conductive layer, a potential can be supplied to the common electrode.

[0152] As the gate line driving circuit 364 , for example, a gate line driving circuit 364 including the unit circuit 100 or the unit circuit 100A described in the above-mentioned first embodiment can be used.

[0153] The wiring 365 has a function of supplying signals and power to the display portion 362 and the gate line driver circuit 364. The signals and power are input to the wiring 365 from the outside through the FPC 372 or from the IC 373.

[0154] Fig.28 An example of providing IC 373 on substrate 351 by COG (Chip On Glass) method or COF (Chip On Film) method is shown. As IC 373, for example, an IC including a signal line driver circuit can be used. Note that the display device 300A and the display module do not necessarily have to be provided with an IC. In addition, the IC can also be mounted on an FPC by COF method or the like.

[0155] Fig.29A An example of a cross section of a portion of the region including the FPC 372 , a portion of the gate line driver circuit 364 , a portion of the display portion 362 , a portion of the connection portion 340 , and a portion of the region including the end portion of the display device 300A is shown.

[0156] Fig.29AThe display device 300A shown includes not only a layer 301 including a transistor 201 and a transistor 202 but also a light emitting device 330 and the like between a substrate 351 and a substrate 352 .

[0157] The light-emitting device 330 includes a conductive layer 311, a conductive layer 312 on the conductive layer 311, and a conductive layer 326 on the conductive layer 312. The conductive layer 311, the conductive layer 312, and the conductive layer 326 may all be referred to as pixel electrodes, or a portion of the conductive layer 311, the conductive layer 312, and the conductive layer 326 may be referred to as pixel electrodes. As the light-emitting device 330, for example, self-luminous light-emitting devices such as LEDs (Light Emitting Diodes), organic EL (Electro Luminescence) elements (also called OLEDs (Organic LEDs)), inorganic EL elements, and semiconductor lasers may be used. As LEDs, for example, mini LEDs or micro LEDs may be cited. In the following description, the case of using organic EL elements is described.

[0158] The conductive layer 311 is connected to the transistor 202 provided in the display portion 362 through an opening provided in the insulating layer 324. For example, a conductive layer that functions as a reflective electrode can be used for the conductive layer 311 and the conductive layer 312. For example, a conductive layer that functions as a transparent electrode can be used for the conductive layer 326.

[0159] A recess is formed in the conductive layer 311 so as to cover the opening provided in the insulating layer 324. The recess is filled with a layer 328. The layer 328 has a function of flattening the recess of the conductive layer 311. A conductive layer 312 is provided on the conductive layer 311 and the layer 328. The region overlapping the recess of the conductive layer 311 can also be used as a light emitting region, thereby increasing the aperture ratio of the pixel.

[0160] The layer 328 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be appropriately used for the layer 328. In particular, the layer 328 is preferably formed using an insulating material.

[0161] An insulating layer containing an organic material can be used as the layer 328 as appropriate. For example, acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimide amide resin, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors of the above resins can be used as the layer 328. In addition, a photosensitive resin can be used as the layer 328. The photosensitive resin can use a positive material or a negative material.

[0162] By using a photosensitive resin, the layer 328 can be manufactured only by the steps of exposure and development, and the influence of dry etching or wet etching on the surface of the conductive layer 311 can be reduced. In addition, by forming the layer 328 using a negative photosensitive resin, the layer 328 can be formed using the same photomask (exposure mask) as the photomask used to form the opening of the insulating layer 324.

[0163] The top and side surfaces of the conductive layer 312 and the conductive layer 326 are covered by the layer 313. Therefore, the entire region provided with the conductive layer 312 can be used as the light emitting region of the light emitting device 330, thereby increasing the aperture ratio of the pixel.

[0164] The side of the layer 313 is covered by the insulating layer 325 and the insulating layer 327. The sacrificial layer 318 is located between the layer 313 and the insulating layer 325. The layer 314 is disposed on the layer 313, the insulating layer 325, and the insulating layer 327. The common electrode 315 is disposed on the layer 314. The layer 314 and the common electrode 315 are continuous films commonly disposed in the plurality of light emitting devices 330. In addition, a protective layer 331 is disposed on the light emitting device 330.

[0165] The protective layer 331 and the substrate 352 are bonded by the adhesive layer 342. The light emitting device 330 may be sealed by a solid sealing structure or a hollow sealing structure. Fig.29A In the embodiment, the space between the substrate 352 and the substrate 351 is filled with the adhesive layer 342, that is, a solid sealing structure is adopted. Alternatively, a hollow sealing structure in which the space is filled with an inert gas (nitrogen or argon, etc.) can also be adopted. In this case, the adhesive layer 342 can also be arranged in a manner not to overlap with the light-emitting device. In addition, a resin different from the adhesive layer 342 arranged in a frame shape can also be used to fill the space.

[0166] In the connection part 340, a conductive layer 323 is provided on an insulating layer 324. The following example is shown: the conductive layer 323 has a stacked structure of a conductive film obtained by processing the same conductive film as the conductive layer 311, a conductive film obtained by processing the same conductive film as the conductive layer 312, and a conductive film obtained by processing the same conductive film as the conductive layer 326. The end of the conductive layer 323 is covered by a sacrificial layer 318, an insulating layer 325, and an insulating layer 327. In addition, a layer 314 is provided on the conductive layer 323, and a common electrode 315 is provided on the layer 314. The conductive layer 323 and the common electrode 315 are connected through the layer 314. In addition, the connection part 340 may not be formed with the layer 314. In this case, the conductive layer 323 and the common electrode 315 are directly in contact and connected.

[0167] The display device 300A is, for example, a top emission type. The light emitting device emits light L to the substrate 352 side. The substrate 352 is preferably made of a material with high transmittance to visible light. The pixel electrode includes a material that reflects visible light, and the counter electrode (common electrode 315) includes a material that allows visible light to pass through. In addition, the display device may also be a bottom emission type.

[0168] The insulating layer 220 is provided in a manner covering the transistor. The insulating layer 324 is provided in a manner covering the transistor and is used as a planarization layer. In addition, there is no particular limitation on the number of insulating layers covering the transistor, and it can be one or more than two.

[0169] Preferably, a material that is not easy to diffuse impurities such as water and hydrogen is used for at least one of the insulating layers covering the transistor. Thus, the insulating layer can be used as a blocking insulating layer. By adopting this structure, it is possible to effectively suppress the diffusion of impurities from the outside into the transistor, thereby improving the reliability of the display device.

[0170] As the insulating layer 220, for example, a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, etc. can be used. In addition, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, a neodymium oxide film, etc. can also be used. In addition, two or more of the above insulating films can also be stacked.

[0171] An organic insulating film may be used as the insulating layer 324 used as a planarizing layer. Examples of materials that can be used for the organic insulating film include acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimideamide resins, siloxane resins, benzocyclobutene resins, phenolic resins, and precursors of these resins.

[0172] The connection portion 204 is provided in a region of the substrate 351 that does not overlap with the substrate 352. In the connection portion 204, the wiring 365 is connected to the FPC 372 through the conductive layer 366 and the connection layer 203. The following example is shown: the conductive layer 366 has a laminated structure of a conductive film obtained by processing the same conductive film as the conductive layer 311, a conductive film obtained by processing the same conductive film as the conductive layer 312, and a conductive film obtained by processing the same conductive film as the conductive layer 326. The conductive layer 366 is exposed on the top surface of the connection portion 204. Therefore, the connection portion 204 can be connected to the FPC 372 through the connection layer 203.

[0173] It is preferred to provide a light shielding layer 317 on the surface of the substrate 352 on the side of the substrate 351. The light shielding layer 317 can be provided between adjacent light emitting devices 330, in the connecting portion 340 and the gate line driving circuit 364, etc. In addition, various optical components can be configured on the outside of the substrate 352. As optical components, polarizers, phase difference plates, light diffusion layers (diffusion films, etc.), anti-reflection layers, and condensing films can be used. In addition, an antistatic film that suppresses the adhesion of dust, a water-repellent film that is not easily soiled, a hard coating that suppresses damage during use, an impact absorption layer, etc. can also be configured on the outside of the substrate 352.

[0174] By forming the protective layer 331 covering the light emitting device 330 , it is possible to suppress impurities such as water from entering the light emitting device 330 , thereby improving the reliability of the light emitting device.

[0175] Glass, quartz, ceramic, sapphire, resin, metal, alloy, semiconductor, etc. can be used for the substrate 351 and the substrate 352. A material that allows light to pass through is used as the substrate on the side that extracts light from the light-emitting device. By using a flexible material for the substrate 351 and the substrate 352, the flexibility of the display device can be improved. A polarizing plate can also be used as the substrate 351 or the substrate 352.

[0176] As substrate 351 and substrate 352, the following materials can be used: polyester resins such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resins, acrylic resins, polyimide resins, polymethyl methacrylate resins, polycarbonate (PC) resins, polyether sulfone (PES) resins, polyamide resins (nylon, aromatic polyamide, etc.), polysiloxane resins, cycloolefin resins, polystyrene resins, polyamide-imide resins, polyurethane resins, polyvinyl chloride resins, polyvinylidene chloride resins, polypropylene resins, polytetrafluoroethylene (PTFE) resins, ABS resins, and cellulose nanofibers, etc. In addition, glass having a thickness that allows flexibility can be used as one or both of substrate 351 and substrate 352.

[0177] When a circular polarizing plate is superimposed on a display device, it is preferable to use a substrate having high optical isotropy as a substrate included in the display device. A substrate having high optical isotropy has low birefringence (it can also be said that the amount of birefringence is small).

[0178] Adhesive layer 342 can use various curing adhesives such as light curing adhesives such as ultraviolet curing adhesives, reaction curing adhesives, heat curing adhesives, anaerobic adhesives, etc. As these adhesives, epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, EVA (ethylene-vinyl acetate) resins, etc. can be cited. In particular, it is preferred to use materials with low moisture permeability such as epoxy resins. In addition, two-liquid mixed resins can also be used. In addition, adhesive sheets, etc. can also be used.

[0179] The connection layer 203 may be made of anisotropic conductive film (ACF: Anisotropic Conductive Film), anisotropic conductive paste (ACP: Anisotropic Conductive Paste), or the like.

[0180] A layer 301 including transistors is provided between the substrate 351 and the insulating layer 220. The layer 301 includes a transistor 201 and a transistor 202. The transistor 201 is, for example, the OS transistor described in the above embodiment 1. The transistor 202 is the LTPS transistor described in the above embodiment 1. The transistor 201 and the transistor 202 are provided over the substrate 351. The transistor 201 and the transistor 202 can be formed using the same material and the same process.

[0181] Fig.29B is an enlarged view of a cross section including the transistor 201 . Fig.29C It is an enlarged view of a cross section including the transistor 202. As described in Embodiment 1, in one embodiment of the present invention, as transistors included in the gate line driver circuit 364, an OS transistor which is an n-channel transistor and an LTPS transistor which is a p-channel transistor are used. Fig.29B The transistor 201 shown may be an n-channel transistor. Fig.29C The transistor 202 shown may be a p-channel transistor.

[0182] The transistor 201 includes an insulating layer 211, a conductive layer 212A, an insulating layer 213, an insulating layer 214, a semiconductor layer 215, an insulating layer 216, a conductive layer 217, an insulating layer 218, and conductive layers 219a and 219b stacked in this order over a substrate 351. Parts of the insulating layer 213, the insulating layer 214, and the insulating layer 218 are used as gate insulating layers of the transistor 201. The conductive layer 212A is used as a bottom gate electrode of the transistor 201. The conductive layer 217 is used as a top gate electrode of the transistor 201. The conductive layers 219a and 219b are used as source electrodes or drain electrodes.

[0183] The semiconductor layer 215 includes a metal oxide such as In-Ga-Zn oxide. The conductive layer 219a and the conductive layer 219b are connected to the low resistance region 215n included in the semiconductor layer 215 through openings provided in the insulating layer 216 and the insulating layer 218, respectively. In addition, the low resistance region 215n can also be said to be a region with lower resistance than the channel formation region of the transistor 201, a region with higher carrier concentration, a region with higher oxygen vacancy density, a region with higher impurity concentration, or a region presenting n-type. For example, the low resistance region 215n is a region containing impurity elements. As the impurity elements, for example, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum and rare gases can be cited. As typical examples of rare gases, helium, neon, argon, krypton and xenon can be cited. The low resistance region 215n particularly preferably contains boron or phosphorus. In addition, the low resistance region 215n can also contain two or more of the above elements.

[0184] The transistor 202 includes a semiconductor layer 210, an insulating layer 211, a conductive layer 212B, an insulating layer 213, an insulating layer 214, an insulating layer 216, an insulating layer 218, and conductive layers 219c and 219d stacked in this order over a substrate 351. A portion of the insulating layer 211 is used as a gate insulating layer of the transistor 202. The conductive layer 212B is used as a top gate electrode of the transistor 202. The conductive layers 219c and 219d are used as source electrodes or drain electrodes.

[0185] The semiconductor layer 210 includes silicon such as low-temperature polysilicon. The conductive layer 219c and the conductive layer 219d are connected to the low resistance region 210p included in the semiconductor layer 210 through openings provided in the insulating layer 211, the insulating layer 213, the insulating layer 214, the insulating layer 216, and the insulating layer 218, respectively. The low resistance region 210p can also be said to be a region with lower resistance than the channel formation region of the transistor 202, a region with higher impurity concentration, or a region presenting p-type. For example, the low resistance region 210p is a region containing impurity elements used to form a p-channel transistor. In the case where the transistor 202 is a p-channel transistor, boron and / or aluminum, etc. can be added to the low resistance region 210p. In addition, in order to control the threshold voltage of the transistor 202, the above-mentioned impurities can also be added to the channel formation region of the transistor 202.

[0186] Components other than the semiconductor layer of the transistor 201 and the transistor 202 can be formed in the same process. Thus, even when two types of transistors are mixed and mounted, an increase in the number of steps can be suppressed.

[0187] As materials that can be used for the gate electrode, source electrode and drain electrode of the transistor and various wirings and electrodes constituting the display device, there can be mentioned metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum or tungsten, or alloys containing the above metals as main components, etc. A single layer or a stack of films containing these materials can be used.

[0188] As a conductive material with light transmittance, conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, zinc oxide containing gallium, or graphene can be used. Alternatively, metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium or titanium, or alloy materials containing the metal materials can be used. Alternatively, nitrides of the metal materials (for example, titanium nitride) can also be used. In addition, when a metal material or alloy material (or their nitrides) is used, it is formed thin enough to be light transmittance. In addition, a laminated film of the above-mentioned materials can be used as a conductive layer. For example, by using a laminated film of an alloy of silver and magnesium and indium tin oxide, the conductivity can be improved. The above-mentioned materials can also be used for the conductive layers of various wirings and electrodes constituting the display device and the conductive layers included in the light-emitting device (the conductive layers used as pixel electrodes or common electrodes).

[0189] Examples of insulating materials that can be used for each insulating layer include resins such as acrylic resins and epoxy resins, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide.

[0190] In addition, you can omit Fig.29B The conductive layer 217 used as the top gate electrode. For example, Fig. 30A FIG. 2 is a schematic cross-sectional view of a display device 300A_1 including a transistor 201A in which the conductive layer 217 serving as a top gate electrode is omitted. Fig. 30B Shown including Fig. 30A FIG. 2 is an enlarged view of a cross section of the transistor 201A shown in FIG. 2 . In the detailed description of the display device 300A_1 and the transistor 201A, Fig.29A and Fig.29B The display device 300A shown in the figure has many parts in common with the transistor 201, and therefore repeated description will be omitted.

[0191] Fig.31 Yes Fig.29C , Fig. 30A and Fig. 30B The transistor 201A and the transistor 202 shown are used in a unit circuit included in the gate line driver circuit 364 , for example, a plan view of the unit circuit 100G described in Embodiment 1. Fig.31 This is an example of a plan view of the unit circuit 100G and is not limited to this.

[0192] Fig.311 shows a unit circuit 100G that outputs to a gate line in a k-th row (k is an integer greater than or equal to 1 and less than or equal to m). In the unit circuit 100G, the transistor Tn1 as an n-channel OS transistor can be referred to as Fig. 30B The transistor 201A shown in FIG. 1 is provided, and the transistors Tp1 to Tp7 as p-channel LTPS transistors can be referred to. Fig.29C The transistor 202 is shown as being provided.

[0193] Fig.31 As an example, a power line 103 for transmitting VDD, a power line 104 for transmitting VSS, a wiring 101 for transmitting a clock signal CK1, a wiring 102 for transmitting a clock signal CK2, a wiring 106P for transmitting an output signal OUTP, a wiring 106N for transmitting an output signal OUTN, a wiring 105_k-1 for transmitting a signal equivalent to the output signal OUTP_k-1 of a previous stage, and a wiring 105_k for transmitting a signal equivalent to the output signal OUTP_k to a subsequent stage are shown.

[0194] In addition, Fig.31 4, a conductive layer 401, a conductive layer 402, a semiconductor layer 403, a semiconductor layer 404, a contact hole 405, and a contact hole 406 for forming wiring, a transistor, and a capacitor are shown as an example. The conductive layer 401 is provided at Fig.29C and Fig. 30B The conductive layer 402 is disposed in the same layer as the conductive layers 212A and 212B shown in FIG. Fig.29C and Fig. 30B The semiconductor layer 403 is provided in the same layer as the conductive layers 219a to 219d shown. Fig. 30B The semiconductor layer 404 is disposed in the same layer as the semiconductor layer 215 shown. Fig.29C The contact hole 405 is an opening for connecting the conductive layer 401 and the conductive layer 402. The contact hole 406 is an opening for connecting the conductive layer 402 and the semiconductor layer 215 (or the semiconductor layer 210).

[0195] exist Fig.31 In the plan view shown in FIG. 1 , the transistor 201A in which the conductive layer 217 serving as the top gate electrode is omitted is used for the transistor Tn1. Therefore, the step of providing the conductive layer 217 can be omitted, so that improvement in yield can be expected.

[0196] exist Fig.31In the embodiment, the capacitor Cp can be formed by overlapping the conductive layer 401 and the conductive layer 402 via the insulating layer. In addition, in the region other than the region where the capacitor Cp is provided, the cross capacitance of the wiring is sometimes increased due to the overlap of the conductive layer 401 and the conductive layer 402. Therefore, it is preferable to reduce the cross capacitance of the wiring by providing a notch portion in the conductive layer. By adopting this structure, noise, signal delay or waveform distortion caused to the transmitted signal can be reduced.

[0197] exist Fig.31 In the embodiment, the power supply lines 103 and 104 for transmitting VDD and VSS are preferably arranged outside the wirings 101 and 102 for transmitting the clock signals CK1 and CK2 (the side away from the transistors Tn1, Tp1 to Tp8). By adopting this structure, the cross capacitance between the wirings 101 and 102 for transmitting the clock signals CK1 and CK2 and the power supply lines 103 and 104 for transmitting VDD and VSS can be reduced. Therefore, by adopting this structure, the noise, signal delay or waveform distortion caused to the transmitted signal can be reduced.

[0198] In addition, Fig.31 In the embodiment, the transistors Tp1 and Tp2 preferably have a structure in which the area of ​​the conductive layer 401 overlapping the semiconductor layer 215 (or the semiconductor layer 210) is larger than that of the transistors Tn1, Tp3 to Tp7. By adopting this structure, the channel width of the transistor can be increased, and the amount of current flowing through the transistor can be increased. As a result, the wiring for transmitting the output signal OUTP with a large load can be charged and discharged at a high speed.

[0199] As described in the first embodiment, in the unit circuit, the driving load of transistors Tp1 and Tp2 is greater than the driving load of transistors Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. Fig.31 As shown, W (channel width) / L (channel length) of transistors Tp1 and Tp2 is preferably greater than W (channel width) / L (channel length) of transistors Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. Fig.31 As shown in FIG. 4 , W (channel width) / L (channel length) can be calculated using the area of ​​the region where the semiconductor layer 404 and the conductive layer 401 overlap.

[0200] In addition, you can omit Fig.29B The conductive layer 212A used as the bottom gate electrode. For example, Fig.32A FIG. 2 is a schematic cross-sectional view of a display device 300A_2 including a transistor 201B in which a conductive layer 212A serving as a bottom gate electrode is omitted. Fig.32B Shown including Fig.32A FIG. 2 is an enlarged view of a cross section of the transistor 201B shown in FIG. 2 . In the detailed description of the display device 300A_2 and the transistor 201B, Fig.29A and Fig.29B The display device 300A shown in the figure has many parts in common with the transistor 201, and therefore repeated description will be omitted.

[0201] Fig.33 Yes Fig.29C , Fig.32A and Fig.32B The transistor 201B and the transistor 202 shown are used in a unit circuit included in the gate line driving circuit 364 , for example, a plan view of the unit circuit 100G described in Embodiment 1. Fig.33 FIG. 1 is an example of a plan view of the unit circuit 100G and is not limited thereto. Fig.33 In the description of the plan view shown, the Fig.32A and Fig.32B In the detailed description of the display device 300A_2 and the transistor 201B, the same components as those in the plan view are described repeatedly. Fig.29A and Fig.29B The display device 300A shown in the figure has many parts in common with the transistor 201, and therefore repeated description will be omitted.

[0202] Fig.33 The unit circuit 100G_2 outputs to the gate line of the kth row. In the unit circuit 100G_2, the transistor Tn1 which is an n-channel OS transistor can be referred to as Fig.32B The transistor 201B shown in FIG. 1 is provided, and the transistors Tp1 to Tp7 as p-channel LTPS transistors can be referred to as Fig.29C The transistor 202 is shown as being provided.

[0203] In addition, Fig.33 4, a conductive layer 401, a conductive layer 402, a semiconductor layer 403, a semiconductor layer 404, a contact hole 405, a contact hole 406, a conductive layer 407, and a contact hole 408 are shown as an example for forming wiring, transistors, and capacitors. The conductive layer 401 is provided at Fig.29C The conductive layer 402 is disposed in the same layer as the conductive layer 212B shown. Fig.29C and Fig.32B The semiconductor layer 403 is provided in the same layer as the conductive layers 219a to 219d shown. Fig.32B The semiconductor layer 404 is disposed in the same layer as the semiconductor layer 215 shown. Fig.29C The contact hole 405 is an opening for connecting the conductive layer 401 and the conductive layer 402. The contact hole 406 is an opening for connecting the conductive layer 402 and the semiconductor layer 215 (or the semiconductor layer 210). The conductive layer 407 is provided at the same Fig.32BThe contact hole 408 is an opening for connecting the conductive layer 402 and the conductive layer 407.

[0204] exist Fig.33 In the plan view of the unit circuit 100G_A shown in FIG. 1 , the transistor 201B in which the conductive layer 212A used as the bottom gate electrode is omitted is used for the transistor Tn1. Therefore, the conductive layer 407 can be used to connect wiring and set elements such as capacitors. For example, in Fig.33 In the capacitor Cp shown in the figure, an insulating layer (equivalent to Fig.32B The insulating layer 216 shown in the figure is provided with a conductive layer 402 and a conductive layer 407. The insulating layer of the capacitor Cp is an insulating layer equivalent to the gate insulating film of the transistor 201B. Therefore, a capacitor can be provided using a thin insulating layer. As a result, the area occupied by the capacitor Cp, the noise caused to the transmitted signal, the signal delay or the waveform distortion can be reduced.

[0205] As described in the first embodiment, in the unit circuit, the driving load of the transistor Tp1 is greater than the driving load of the transistor Tp2. Therefore, the W / L of the transistor Tp1 is preferably greater than the W / L of the transistor Tp2. Fig.34 As shown in the plan view of the unit circuit 100G_B, W (channel width) / L (channel length) of the transistor Tp1 is preferably greater than W (channel width) / L (channel length) of the transistor Tp2. Fig.34 As shown in FIG. 4 , W (channel width) / L (channel length) can be calculated using the area of ​​the region where the semiconductor layer 404 and the conductive layer 401 overlap.

[0206] As described in the first embodiment, in the unit circuit, the mobility of the transistor Tn1 is smaller than the mobility of the transistors Tp1 to Tp7. Therefore, the W / L of the transistor Tn1 is preferably larger than the W / L of the transistors Tp1 to Tp7. Fig.35 As shown in the plan view of the unit circuit 100G_C, W (channel width) / L (channel length) of the transistor Tn1 is preferably larger than W (channel width) / L (channel length) of the transistors Tp3 to Tp7. Fig.35 As shown in FIG. 4 , W (channel width) / L (channel length) can be calculated using the area of ​​the region where the semiconductor layer 403 and the conductive layer 401 overlap.

[0207] As described in the above-mentioned Embodiment 1, in the unit circuit, the SP supplied to the wiring 105_k-1 is transmitted to the gate of the transistor Tp1 through the transistors Tp3 and Tp4. Therefore, by improving the driving capability of the transistors Tp3 and Tp4, the operating speed can be improved. Therefore, the W / L of the transistors Tp3 and Tp4 is preferably greater than the W / L of the transistors Tp5 to Tp7. For example, Fig.36As shown in the plan view of the unit circuit 100G_D, W (channel width) / L (channel length) of transistors Tp3 and Tp4 is preferably greater than W (channel width) / L (channel length) of transistors Tp5 to Tp7. Fig.36 As shown in FIG. 4 , W (channel width) / L (channel length) can be calculated using the area of ​​the region where the semiconductor layer 404 and the conductive layer 401 overlap.

[0208] Note that although Fig.29A , Fig. 30A and Fig.32A 2 shows a structure in which transistors 201 and transistor 202 are provided in both the gate line driving circuit 364 and the display unit 362, but only transistor 201 or transistor 202 may be used as a transistor provided in the display unit 362, that is, transistors having the same structure may be used as transistors included in the display unit 362.

[0209] For example, LTPS transistors such as the transistor 202 are preferably used as all transistors included in the pixel circuit of the display portion 362 that drives the light-emitting device. As silicon used for the semiconductor layer included in the LTPS transistor, in addition to low-temperature polycrystalline silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, etc. can be used. LTPS transistors are preferred because they have high field effect mobility and good frequency characteristics.

[0210] In addition, it is preferred that an OS transistor such as the transistor 201 is used as at least one of the transistors included in the pixel circuit of the display portion 362 that drives the light-emitting device. Compared with a transistor using amorphous silicon, the field effect mobility of the OS transistor is very high. In addition, the off-state current of the OS transistor is extremely small, and the charge stored in the capacitor connected in series with the transistor can be maintained for a long period of time. In addition, by using the OS transistor, the power consumption of the display device can be reduced.

[0211] By using LTPS transistors for some transistors included in the pixel circuit and OS transistors for other transistors, a display device with low power consumption and high driving capability can be realized. As a more preferred example, it is preferred that OS transistors are used as transistors used as switches for controlling conduction and non-conduction between wirings and LTPS transistors are used as transistors for controlling current.

[0212] For example, one of the transistors provided in the pixel circuit is used as a transistor for controlling the current flowing through the light emitting device, and may also be referred to as a driving transistor. One of the source and drain of the driving transistor is connected to the pixel electrode of the light emitting device. An LTPS transistor is preferably used as the driving transistor. Therefore, the current flowing through the light emitting device in the pixel circuit can be increased.

[0213] On the other hand, another of the transistors provided in the pixel circuit is used as a switch for controlling the selection and non-selection of the pixel, and may also be referred to as a selection transistor. The gate of the selection transistor is connected to the gate line, and one of the source and drain is connected to the source line (signal line). The selection transistor preferably uses an OS transistor. Therefore, even if the frame rate is significantly reduced (for example, below 1fps), the grayscale of the pixel can be maintained, thereby reducing power consumption by stopping the driver when displaying a static image.

[0214] <Block Diagram of Display Device> Fig.37A 300A is a block diagram of a display device 300A. The display device 300A includes a display portion 362, a gate line driving circuit 364, an IC 373, and the like.

[0215] The display unit 362 includes a plurality of pixels 363 arranged in a matrix. The pixel 363 includes a sub-pixel 370R, a sub-pixel 370G, and a sub-pixel 370B. The sub-pixel 370R, the sub-pixel 370G, and the sub-pixel 370B each include a light-emitting device used as a display device.

[0216] The pixel 363 is connected to the wiring GL, the wiring SLR, the wiring SLG, and the wiring SLB. The wiring SLR, the wiring SLG, and the wiring SLB are each connected to the IC373. The wiring GL is connected to the gate line driving circuit 364. The wiring GL is a wiring for outputting the output signal OUT described in the first embodiment. The IC373 is used as a source line driving circuit (also called a source driver), and the gate line driving circuit 364 is used as a gate line driving circuit (also called a gate driver). The wiring GL is used as a gate line, and the wiring SLR, the wiring SLG, and the wiring SLB are each used as a source line.

[0217] Sub-pixel 370R includes a light-emitting device that emits red light. Sub-pixel 370G includes a light-emitting device that emits green light. Sub-pixel 370B includes a light-emitting device that emits blue light. Therefore, display device 300A is capable of full-color display. Note that pixel 363 may also include sub-pixels having light-emitting devices that emit other colors. For example, pixel 363 may also include, in addition to the above three sub-pixels, a sub-pixel having a light-emitting device that emits white light or a sub-pixel having a light-emitting device that emits yellow light.

[0218] The wiring GL is connected to the sub-pixel 370R, the sub-pixel 370G, and the sub-pixel 370B arranged in the row direction (the direction in which the wiring GL extends). The wiring SLR, the wiring SLG, and the wiring SLB are respectively connected to the sub-pixel 370R, the sub-pixel 370G, or the sub-pixel 370B (not shown) arranged in the column direction (the direction in which the wiring SLR, etc. extends).

[0219] Fig.37BAn example of a circuit diagram of a pixel 370 that can be used for the above-mentioned sub-pixel 370R, sub-pixel 370G, and sub-pixel 370B is shown. The pixel 370 includes a transistor M1, a transistor M2, a transistor M3, a capacitor C1, and a light-emitting device EL. In addition, a wiring GL and a wiring SL are connected to the pixel 370. The wiring SL corresponds to Fig.37A Any one of the wiring SLR, wiring SLG and wiring SLB shown in .

[0220] The gate of the transistor M1 is connected to the wiring GL, one of the source and the drain is connected to the wiring SL, and the other of the source and the drain is connected to one electrode of the capacitor C1 and the gate of the transistor M2. One of the source and the drain of the transistor M2 is connected to the wiring AL, and the other of the source and the drain is connected to one electrode of the light emitting device EL, the other electrode of the capacitor C1, and one of the source and the drain of the transistor M3. The gate of the transistor M3 is connected to the wiring GL, and the other of the source and the drain is connected to the wiring RL. The other electrode of the light emitting device EL is connected to the wiring CL.

[0221] The wiring SL is supplied with a data potential D. The wiring GL is supplied with a selection signal. The selection signal includes a potential for turning on the transistor and a potential for turning off the transistor.

[0222] The wiring RL is supplied with a reset potential. The wiring AL is supplied with an anode potential. The wiring CL is supplied with a cathode potential. The anode potential in the pixel 370 is higher than the cathode potential. In addition, the reset potential supplied to the wiring RL may be a potential that makes the potential difference between the reset potential and the cathode potential smaller than the threshold voltage of the light emitting device EL. The reset potential may be a potential higher than the cathode potential, a potential equal to the cathode potential, or a potential lower than the cathode potential.

[0223] The transistor M1 and the transistor M3 are used as switches. The transistor M2 is used as a transistor for controlling the current flowing through the light emitting device EL. For example, it can also be said that the transistor M1 is used as a selection transistor and the transistor M2 is used as a driving transistor.

[0224] Here, it is preferable to use LTPS transistors for all of the transistors M1 to M3. Alternatively, it is preferable to use OS transistors for the transistors M1 and M3 and use LTPS transistors for the transistor M2. Alternatively, it is preferable to use OS transistors for all of the transistors M1 to M3.

[0225] The OS transistor can achieve an extremely low off-state current. Due to its low off-state current, the charge stored in the capacitor connected in series with the transistor can be maintained for a long period of time. Therefore, in particular, the transistor M1 and the transistor M3 connected in series with the capacitor C1 preferably use a transistor containing an oxide semiconductor. By using a transistor containing an oxide semiconductor as the transistor M1 and the transistor M3, the charge maintained in the capacitor C1 can be prevented from leaking through the transistor M1 or the transistor M3. In addition, the charge stored in the capacitor C1 can be maintained for a long period of time, so a static image can be displayed for a long period of time without rewriting the data of the pixel 370.

[0226] Note that Fig.37B In the embodiment, the transistors M1 to M3 are n-channel transistors, but p-channel transistors may also be used. For example, p-channel transistors may be used as transistors for causing current to flow through the light emitting device EL, and n-channel transistors may be used as other transistors.

[0227] As the transistor included in the pixel 370, a transistor including a pair of gates overlapping with a semiconductor layer can be used. In the case where the transistor including a pair of gates has a structure in which a pair of gates are connected to each other and supplied with the same potential, there are advantages such as an increased on-state current of the transistor and improved saturation characteristics. In addition, a potential for controlling the threshold voltage of the transistor can also be supplied to one of the pair of gates. In addition, by supplying a constant potential to one of the pair of gates, the stability of the electrical characteristics of the transistor can be improved. For example, one gate of the transistor can be connected to a wiring supplied with a constant potential, and one gate of the transistor can be connected to the source or drain of the transistor itself.

[0228] Fig.37C The pixel 370 shown is an example of a case where a transistor including a pair of gates is used for the transistor M1 and the transistor M3. In each of the transistor M1 and the transistor M3, a pair of gates are connected to each other. By adopting such a structure, the data writing period for the pixel 370 can be shortened.

[0229] Fig.37D The pixel 370 shown is an example of a case where a transistor including a pair of gates is used not only for the transistors M1 and M3 but also for the transistor M2. The pair of gates of the transistor M2 is connected to each other. By using such a transistor for the transistor M2, the saturation characteristic is improved, so that the control of the light emitting brightness of the light emitting device EL becomes easier, and the display quality can be improved.

[0230] Fig.38A Shown with Fig.37ABlock diagram of a different display device 300B. The display device 300B includes a display unit 362, a gate line driving circuit 364, a light emission control driving circuit 384, and an IC 373. Fig.38A In, with Fig.37A The same parts are denoted by the same symbols, and description thereof is omitted.

[0231] The display portion 362 includes a plurality of pixels 363 arranged in a matrix. The pixel 363 includes a sub-pixel 371R, a sub-pixel 371G, and a sub-pixel 371B. The sub-pixel 371R, the sub-pixel 371G, and the sub-pixel 371B each include a light-emitting device serving as a display device.

[0232] The pixel 363 is connected to the wiring GLP, the wiring GLN, the wiring EMI, the wiring SLR, the wiring SLG, and the wiring SLB. The gate line driving circuit 364 is a gate line driving circuit including the unit circuit 100G described in Embodiment 1. Fig.38B As shown, the wirings GLP and GLN are wirings to which the output signals OUTP and OUTN outputted by the unit circuit 100G described in Embodiment 1 are supplied. The light emission control driving circuit 384 is a circuit that outputs a timing signal for controlling the light emission of the light emitting devices in the sub-pixel 371R, the sub-pixel 371G, and the sub-pixel 371B. The wiring EMI is a wiring for transmitting a timing signal for controlling the light emission of the light emitting device.

[0233] Fig.38C An example of a circuit diagram of a pixel 371 that can be used for the above-mentioned sub-pixel 371R, sub-pixel 371G, and sub-pixel 371B is shown. The pixel 371 includes transistors M11 to M17, a capacitor C2, and a light-emitting device EL. In addition, the pixel 371 is connected to the wiring GLP_k, the wiring GLP_k-1, GLN_k, the wiring EMI_k, the initialization line INI, and the wiring SL. The wiring SL corresponds to Fig.38A Any of the wiring SLR, wiring SLG, and wiring SLB shown.

[0234] The transistors M11 to M14 are p-channel transistors, in which LTPS transistors or the like are used. The transistor M15 is an n-channel transistor, in which an OS transistor or the like is used. The transistors M11 to M17, the capacitor C2, and the light emitting device EL are as follows. Fig.38C Connect as shown.

[0235] The wiring SL is supplied with a data potential D. The wiring GLP is supplied with a selection signal for selecting a p-channel transistor. In addition, the wiring GLN is supplied with a selection signal for selecting an n-channel transistor. The initialization line INI is supplied with an initialization potential. The unit circuit 100G described in Embodiment 1 can output a signal for selecting transistors of different polarities. Therefore, in Fig.38C In the pixel 371 including p-channel transistors and n-channel transistors shown, transistors with different polarities can be selected at different timings. As a result, it is not necessary to provide multiple unit circuits for outputting selection signals at different timings, so that the circuit area can be reduced and power consumption can be reduced.

[0236] In addition, in the display device 300B, both the pixel 371 included in the display unit 362 and the unit circuit 100G included in the gate line driver circuit 364 can have a circuit structure using the following transistors: p-channel transistors using LTPS transistors and n-channel transistors using OS transistors. Therefore, the transistors of the display unit 362 and the gate line driver circuit 364 can be manufactured in the same process, so that the manufacturing cost can be reduced.

[0237] This embodiment mode can be combined with other embodiment modes as appropriate.

[0238] Implementation 3 In this embodiment, refer to FIG. 39A to FIG. 41G An electronic device according to one embodiment of the present invention will be described. The electronic device of this embodiment includes a display device according to one embodiment of the present invention in a display portion. The display device according to one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, it can be used in the display portion of various electronic devices.

[0239] Electronic devices include, for example, television sets, desktop or notebook personal computers, displays for computers, etc., digital signage, large-scale game consoles such as pinball machines, and other electronic devices with larger screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, sound reproduction devices, and the like.

[0240] Fig.39A The electronic device 6500 shown is a portable information terminal device that can be used as a smartphone.

[0241] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like. The display portion 6502 has a touch panel function.

[0242] As the display portion 6502 , a display device which is one embodiment of the present invention can be used.

[0243] Fig.39B 6506 is a schematic cross-sectional view of an end portion of a housing 6501 on the microphone 6506 side.

[0244] A light-transmitting protective component 6510 is provided on one side of the display surface of the frame 6501, and a display panel 6511, an optical component 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the frame 6501 and the protective component 6510.

[0245] The display panel 6511 , the optical member 6512 , and the touch sensor panel 6513 are fixed to the protective member 6510 using an adhesive layer (not shown).

[0246] In a region outside the display portion 6502, a portion of the display panel 6511 is folded back, and the folded back portion is connected to an FPC 6515. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0247] The display panel 6511 can use a display device of one embodiment of the present invention. Thus, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be installed while suppressing the thickness of the electronic device. In addition, by folding back a portion of the display panel 6511 to provide a connection portion with the FPC 6515 on the back of the pixel portion, an electronic device with a narrow frame can be realized.

[0248] Fig.40A 100 shows an example of a television set. In a television set 7100, a display portion 7000 is incorporated in a housing 7101. Here, a structure in which the housing 7101 is supported by a stand 7103 is shown.

[0249] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0250] The operation can be performed by using the operation switch provided in the frame 7101 and the remote control operation machine 7111 provided separately. Fig.40A In addition, the display unit 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display unit 7000 with a finger or the like. In addition, the remote control unit 7111 may be provided with a display unit that displays information output from the remote control unit 7111. By using the operation keys or the touch panel provided in the remote control unit 7111, the channel and volume can be operated, and the image displayed on the display unit 7000 can be operated.

[0251] In addition, the television device 7100 includes a receiver and a modem. The receiver can receive general television broadcasts. Furthermore, the modem can be connected to a wired or wireless communication network to perform one-way (from a sender to a receiver) or two-way (between a sender and a receiver or between receivers, etc.) information communication.

[0252] Fig.40B 1 shows an example of a notebook personal computer. The notebook personal computer 7200 includes a housing 7211 , a keyboard 7212 , a pointing device 7213 , an external connection port 7214 , and the like. A display portion 7000 is incorporated in the housing 7211 .

[0253] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0254] Fig.40C and Fig.40D An example of digital signage is shown.

[0255] Fig.40C The digital signage 7300 shown includes a housing 7301, a display portion 7000, a speaker 7303, etc. In addition, an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, etc. may be included.

[0256] Fig.40D The digital signage 7400 is shown to be disposed on a cylindrical pillar 7401. The digital signage 7400 includes a display unit 7000 disposed along a curved surface of the pillar 7401.

[0257] exist Fig.40C and Fig.40D In the embodiment of the present invention, the display device can be used for the display portion 7000.

[0258] The larger the display unit 7000 is, the more information can be provided at one time. In addition, the larger the display unit 7000 is, the easier it is to attract people's attention, for example, the advertising effect can be improved.

[0259] By using a touch panel for the display unit 7000, not only can a static image or a dynamic image be displayed on the display unit 7000, but the user can also intuitively operate it, so it is preferred. In addition, when used for providing information such as route information or traffic information, the ease of use can be improved through intuitive operation.

[0260] like Fig.40C and Fig.40DAs shown, the digital signage 7300 or the digital signage 7400 can preferably be linked with the information terminal device 7311 or the information terminal device 7411 such as a smartphone carried by the user through wireless communication. For example, the advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal device 7311 or the information terminal device 7411. In addition, by operating the information terminal device 7311 or the information terminal device 7411, the display of the display unit 7000 can be switched.

[0261] The game can be executed on the digital signage 7300 or the digital signage 7400 using the screen of the information terminal device 7311 or the information terminal device 7411 as an operation unit (controller). Thus, an unspecified number of users can participate in the game at the same time and enjoy the game.

[0262] FIG. 41A to FIG. 41G The electronic device shown includes a frame 9000, a display portion 9001, a speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connecting terminal 9006, a sensor 9007 (the sensor has the function of measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, smell or infrared), a microphone 9008, etc.

[0263] FIG. 41A to FIG. 41G The electronic device shown has various functions. For example, it may have the following functions: a function of displaying various information (static images, dynamic images, text images, etc.) on a display unit; a function of a touch panel; a function of displaying a calendar, date, or time, etc.; a function of controlling processing by using various software (programs); a function of wireless communication; a function of reading out a program or data stored in a storage medium and processing it; etc. Note that the functions of the electronic device are not limited to the above functions, but may have various functions. The electronic device may also include multiple display units. In addition, a camera or the like may be provided in the electronic device so that it has the following functions: a function of taking a static image or a dynamic image, and storing the taken image in a storage medium (an external storage medium or a storage medium built into the camera); a function of displaying the taken image on a display unit; etc.

[0264] Below, the description FIG. 41A to FIG. 41G Details of the electronic device shown.

[0265] Fig.41A9101 is a perspective view showing a portable information terminal 9101. For example, the portable information terminal 9101 can be used as a smart phone. Note that a speaker 9003, a connection terminal 9006, a sensor 9007, and the like can also be provided in the portable information terminal 9101. In addition, as the portable information terminal 9101, text or image information can be displayed on multiple surfaces thereof. Fig.41A 9050. In addition, information 9051 indicated by a dotted rectangle may be displayed on another surface of the display unit 9001. An example of information 9051 may include a notification of receipt of an email, SNS, or phone call; a title of the email or SNS; a sender's name of the email or SNS; a date; a time; a remaining battery level; and radio wave strength. Alternatively, icon 9050 may be displayed at a location where information 9051 is displayed.

[0266] Fig.41B 9102 is a three-dimensional diagram showing a portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, when the portable information terminal 9102 is placed in a jacket pocket, the user can confirm the information 9053 displayed at a position viewed from above the portable information terminal 9102. For example, the user can confirm the display without taking the portable information terminal 9102 out of the pocket, thereby determining whether to answer a call.

[0267] Fig.41C 9103. The tablet terminal 9103 can execute various application software such as mobile phone, reading and editing of e-mails and articles, playing music, network communication, computer games, etc. The tablet terminal 9103 includes a display portion 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front of the frame 9000, an operation key 9005 used as a button for operation on the left side of the frame 9000, and a connection terminal 9006 on the bottom.

[0268] Fig.41D 9001 is a stereoscopic diagram showing a watch-type portable information terminal 9200. For example, the portable information terminal 9200 can be used as a smart watch (registered trademark). In addition, the display surface of the display unit 9001 is curved, and a display can be performed along its curved display surface. In addition, the portable information terminal 9200 can perform hands-free calls, for example, by communicating with a headset capable of wireless communication. In addition, by utilizing the connection terminal 9006, the portable information terminal 9200 can perform data transmission or charging with other information terminals. In addition, charging can also be performed by wireless power supply.

[0269] Figures 41E to 41G 9201 is a perspective view showing a foldable portable information terminal. Fig.41E is a perspective view of the portable information terminal 9201 in an unfolded state. Figure 41G This is a three-dimensional image of the folded state. Fig.41F is from Fig.41E Status and Figure 41G The portable information terminal 9201 is easy to carry when folded, and has a large display area with seamless splicing when unfolded, so the display is easy to browse. The display unit 9001 included in the portable information terminal 9201 is supported by three frames 9000 connected by hinges 9055. For example, the display unit 9001 can be bent within a range of a curvature radius of 0.1 mm or more and 150 mm or less.

[0270] This embodiment mode can be combined with other embodiment modes as appropriate.

[0271] (Notes on the Descriptions in This Manual, etc.) Hereinafter, comments will be added to the description of the above-mentioned embodiment and each configuration in the embodiment.

[0272] The structure described in each embodiment can be appropriately combined with the structure described in other embodiments to constitute one mode of the present invention. In addition, when a plurality of structural examples are described in one embodiment, these structural examples can be appropriately combined.

[0273] In addition, the content (or part thereof) described in a certain embodiment may be applied, combined or replaced with other content (or part thereof) described in that embodiment and / or content (or part thereof) described in one or more other embodiments.

[0274] The contents described in the embodiments refer to the contents described using various drawings in each embodiment or the contents described using articles described in the specification.

[0275] In addition, more figures may be formed by combining a drawing (or part thereof) shown in a certain embodiment with other parts of the drawing, other drawings (or parts thereof) shown in the embodiment, and / or drawings (or parts thereof) shown in one or more other embodiments.

[0276] In this specification, etc., constituent elements are classified according to function and are represented as mutually independent blocks in a block diagram. However, it is difficult to classify constituent elements according to function in an actual circuit, etc., and sometimes one circuit involves multiple functions or multiple circuits involve one function. Therefore, the division of blocks in a block diagram is not limited to the constituent elements described in the specification, but can be appropriately different.

[0277] In the drawings, the size, thickness of a layer or area is sometimes exaggerated for the sake of clarity. Therefore, the present invention is not limited to the dimensions in the drawings. The drawings are for the sake of clarity and are not limited to the shapes or values ​​shown in the drawings. For example, it may include uneven signals, voltages or currents caused by noise or timing deviations.

[0278] In this specification, etc., when describing the connection relationship of a transistor, the expressions "one of the source and the drain" (first electrode or first terminal) and "the other of the source and the drain" (second electrode or second terminal) are used. This is because the source and the drain of a transistor are interchangeable depending on the structure or operating conditions of the transistor. Note that the source and the drain of a transistor may be appropriately referred to as a source (drain) terminal or a source (drain) electrode, etc.

[0279] In addition, in this specification, "electrode" and "wiring" do not limit their components in terms of function. For example, sometimes an "electrode" is used as a part of a "wiring", and vice versa. Furthermore, "electrode" and "wiring" also include a case where a plurality of "electrodes" and "wiring" are formed as one.

[0280] In addition, in this specification, etc., voltage and potential can be appropriately exchanged. Voltage refers to the potential difference with the reference potential. For example, when the reference potential is the ground voltage (ground voltage), voltage can be exchanged for potential. The ground potential does not necessarily mean 0V. Note that potential is relative, and the potential supplied to wiring, etc. sometimes changes according to the reference potential.

[0281] In this specification, the words "film" and "layer" are interchangeable. For example, "conductive layer" may be replaced with "conductive film" or "insulating film" may be replaced with "insulating layer".

[0282] In this specification, etc., a switch refers to an element having a function of controlling whether current flows by changing to a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to an element having a function of selecting and switching a current path.

[0283] In this specification, etc., for example, the channel length refers to the distance between the source and the drain in the area where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in an on state) and the gate overlap or in the area where the channel is formed in a plan view of the transistor.

[0284] In this specification, etc., for example, the channel width refers to the length of the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in an on state) and the gate electrode overlap, or the portion where the source and drain electrodes face each other in the region where the channel is formed.

[0285] In this specification, etc., the "on state" of a transistor refers to, for example, a state that can be regarded as a short circuit between the source and the drain of the transistor. For example, the following state is sometimes referred to as the "on state": in an n-channel transistor, the voltage between the gate and the source is higher than the threshold voltage; or in a p-channel transistor, the voltage between the gate and the source is lower than the threshold voltage. Note that the "on state" of a transistor refers to a state in which current can flow between the source and the drain. Therefore, sometimes the transistor being in the "on state" is referred to as the transistor being in the "on state".

[0286] In this specification, etc., the "off state" of a transistor refers to a state that can be regarded as a state in which the source and drain of the transistor are disconnected. For example, the following state is sometimes referred to as the "off state": a state in which the voltage between the gate and the source is lower than the threshold voltage in an n-channel transistor; or a state in which the voltage between the gate and the source is higher than the threshold voltage in a p-channel transistor. In addition, the "off state" of a transistor is sometimes referred to as the "non-conducting state" of the transistor.

[0287] In this specification, etc., the voltage between the gate and the source (gate-source) is sometimes referred to as the "gate voltage", the voltage between the drain and the source (drain-source) is sometimes referred to as the "drain voltage", and the voltage between the back gate and the source (back gate-source) is sometimes referred to as the "back gate voltage". In addition, the current flowing from the drain to the source is sometimes referred to as the "drain current".

[0288] In this specification, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in the off state. Note that in this specification, the off-state current and the current flowing from the gate to the source and drain (also called gate leakage current) are sometimes referred to as leakage current.

[0289] The term “connected” in this specification includes, for example, “electrically connected”.

[0290] When expressing "electrical connection" in order to define the connection relationship of circuit elements as an object, "electrical connection" includes, for example, "direct connection" and "indirect connection". "A and B are directly connected" refers to, for example, a case where A and B are connected without a circuit element (for example, a transistor or a switch instead of wiring). On the other hand, "A and B are indirectly connected" refers to, for example, a case where A and B are connected through one or more circuit elements.

[0291] Here, when it is stipulated that "A and B are indirectly connected", it refers to the connection relationship in the following cases, for example. That is, when it is assumed that the circuit is working, when there is a sequence of transmission and reception of electric signals or interaction of electric potentials between A and B during the operation of the circuit, such a circuit can be stipulated as an object as "A and B are indirectly connected". In addition, even if there is a sequence in which transmission and reception of electric signals or interaction of electric potentials do not occur between A and B, when there is a sequence in which transmission and reception of electric signals or interaction of electric potentials between A and B during the operation of the circuit, it can also be stipulated as "A and B are indirectly connected". Note that the expression "A and B are indirectly connected" stipulates the connection relationship of circuit elements as an object. Therefore, for example, even when the circuit does not work because the power supply voltage is not supplied, the circuit can be stipulated as an object as "A and B are indirectly connected" (however, for example, it is limited to the case where when the circuit works because the power supply voltage is supplied, transmission and reception of electric signals or interaction of electric potentials occur between A and B during the operation of the circuit).

[0292] The following is a specific example of the case of "indirect connection". First, as an example of "A and B are indirectly connected", Fig.42A1 and Figure 42A2As shown, A and B are connected through the source and drain of one or more transistors. As other examples of the case of "A and B are indirectly connected", there are cases where A and B are connected through one or more switches. In the case of "A and B are indirectly connected", there is a timing in which a transistor between A and B becomes an open state, a conductive state, or a state where current may flow at least once when the circuit is assumed to be working. In addition, in the case of "A and B are indirectly connected", there is a timing in which a transistor between A and B becomes a closed state or a non-conductive state. In the case of "A and B are indirectly connected", if multiple transistors are connected between A and B, each of the multiple transistors between A and B becomes an open state, a conductive state, or a state where current may flow at least once when the circuit is assumed to be working. That is to say, in the case of "A and B are indirectly connected", multiple transistors do not necessarily need to be in an open state, a conductive state, or a state where current may flow at the same time. Therefore, the case of "A and B are indirectly connected" includes the case where a plurality of transistors between A and B become off or non-conductive at the same time or at different timings. As another example, Figure 42A3 As shown in FIG. 1 , when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be specified as "A and C are indirectly connected", "B and C are indirectly connected", or "A and B are indirectly connected". Note that, as described below, when a fixed potential V is supplied to C from a power supply or GND, etc., it can be stated that "A and C are indirectly connected" or "B and C are indirectly connected", but it cannot be stated that "A and B are indirectly connected".

[0293] The above shows examples of situations where you can or cannot say "indirect connection", but the following shows other examples of situations where you cannot say "indirect connection". Even if there are situations where electric signals are transferred or received between A and B or electric potentials interact with each other during circuit operation, sometimes it is an exception and you cannot say "A and B are indirectly connected". As an example of this exceptional case, there is a case where A and B are connected through an insulator. That is to say, when A and B are connected through an insulator, you cannot say "A and B are indirectly connected". As specific examples of situations where A and B are connected through an insulator, there are the following. Figure 42A4 As shown in FIG. 1 , a capacitor is connected between A and B. As another example of a case where A and B are connected via an insulator, there is Figure 42A5 As shown in the figure, a gate insulating film of a transistor is interposed between A and B. In this case, it cannot be said that "A (gate of the transistor) and B (source or drain of the transistor) are indirectly connected".

[0294] As another example where it is not possible to say that "A and B are indirectly connected", there is a situation where there is no sequence of electric signal transmission or potential interaction between A and B. For example, there is the following situation: Figure 42A6 and Figure 42A7 As shown, on the path from A to B, multiple transistors are connected through source and drain, and a fixed potential V is supplied from a power supply or GND at the node between the transistors. In this case, although it cannot be said that "A and B are indirectly connected", it can also be said that "A and V are indirectly connected" or "B and V are indirectly connected". Figure 42A3 In the embodiment, when A and C are connected through the source and drain of transistor TrP, B and C are connected through the source and drain of transistor TrQ, and a fixed potential V is supplied to C from a power supply or GND, the same as Figure 42A6 and Figure 42A7 The same connection relationship, so we cannot say "A and B are indirectly connected" but can say "A and C are indirectly connected" or "B and C are indirectly connected".

[0295] Although the example of “indirect connection” is shown above, the definition of “indirect connection” is included in the definition of “electrical connection”, so in the case of “A and B are indirectly connected”, it can be said that “A and B are electrically connected”.

[0296] A specific example of the case of "direct connection" is shown below. As an example of the case of "A and B are directly connected", Fig.42B1 , Figure 42B2 and Figure 42B3 As shown in , there is a case where A and B are not connected through a circuit element. In addition, Figure 42B4 and Figure 42B5 As shown in FIG. 1 , when A and B are connected to a power supply or GND that supplies a fixed potential V without a circuit element, it can be said that “A and B are directly connected”, “A and V are directly connected”, or “B and V are directly connected”. Figure 42B6 As shown, even when A (or B) is connected to the fixed potential V through the source and drain of the transistor, it can be said that "A and B are directly connected." In addition, since A and V or B and V are connected through the source and drain of the transistor, it cannot be said that they are directly connected but that "A and V are indirectly connected" or "B and V are indirectly connected."

[0297] Although the example of “direct connection” is shown above, the definition of “direct connection” is included in the definition of “electrical connection”, so in the case of “A and B are directly connected”, it can be said that “A and B are electrically connected”.

Claims

1. A display device comprising a gate line driving circuit, in, The unit circuit in the gate line driving circuit includes first to fifth p-channel transistors and an n-channel transistor, One of the source and the drain of the first p-channel transistor is electrically connected to a first clock signal line, One of the source and the drain of the second p-channel transistor is electrically connected to the first power line, the other of the source and the drain of the first p-channel transistor is electrically connected to the other of the source and the drain of the second p-channel transistor, The gate of the first p-channel transistor is electrically connected to one of the source and the drain of the third p-channel transistor, The gate of the first p-channel transistor is directly connected to the gate of the n-channel transistor, The gate of the third p-channel transistor is electrically connected to the second power supply line, the other of the source and the drain of the third p-channel transistor is electrically connected to one of the source and the drain of the fourth p-channel transistor, The other of the source and the drain of the third p-channel transistor is electrically connected to the gate of the fifth p-channel transistor, The gate of the fourth p-channel transistor is electrically connected to the second clock signal line. One of the source and the drain of the fifth p-channel transistor is electrically connected to the first power line, The other of the source and the drain of the fifth p-channel transistor is electrically connected to the gate of the second p-channel transistor, the other of the source and the drain of the fifth p-channel transistor is electrically connected to one of the source and the drain of the n-channel transistor, Furthermore, the other of the source and the drain of the n-channel transistor is electrically connected to the second power supply line.

2. The display device according to claim 1, wherein the n-channel transistor comprises a first semiconductor layer, And the first semiconductor layer includes an oxide semiconductor.

3. The display device according to claim 1, wherein the first to fifth p-channel transistors all include a second semiconductor layer, And the second semiconductor layer includes silicon.

4. A display device comprising a gate line driving circuit, in, The unit circuit in the gate line driving circuit includes first to seventh p-channel transistors and n-channel transistors, One of the source and the drain of the first p-channel transistor is electrically connected to a first clock signal line, One of the source and the drain of the second p-channel transistor is electrically connected to the first power line, the other of the source and the drain of the first p-channel transistor is electrically connected to the other of the source and the drain of the second p-channel transistor, The gate of the first p-channel transistor is electrically connected to one of the source and the drain of the third p-channel transistor, The gate of the first p-channel transistor is directly connected to the gate of the n-channel transistor, The gate of the third p-channel transistor is electrically connected to the second power supply line, the other of the source and the drain of the third p-channel transistor is electrically connected to one of the source and the drain of the fourth p-channel transistor, the other of the source and the drain of the third p-channel transistor is electrically connected to one of the source and the drain of the sixth p-channel transistor, The other of the source and the drain of the third p-channel transistor is electrically connected to the gate of the fifth p-channel transistor, The gate of the fourth p-channel transistor is electrically connected to the second clock signal line. One of the source and the drain of the fifth p-channel transistor is electrically connected to the first power line, The other of the source and the drain of the fifth p-channel transistor is electrically connected to the gate of the second p-channel transistor, The other of the source and the drain of the fifth p-channel transistor is electrically connected to the gate of the seventh p-channel transistor, the other of the source and the drain of the fifth p-channel transistor is electrically connected to one of the source and the drain of the n-channel transistor, The other of the source and the drain of the n-channel transistor is electrically connected to the second power supply line, The gate of the sixth p-channel transistor is electrically connected to the first clock signal line, the other of the source and the drain of the sixth p-channel transistor is electrically connected to one of the source and the drain of the seventh p-channel transistor, Furthermore, the other of the source and the drain of the seventh p-channel transistor is electrically connected to the first power line.

5. The display device according to claim 4, wherein the n-channel transistor comprises a first semiconductor layer, And the first semiconductor layer includes an oxide semiconductor.

6. The display device according to claim 4, wherein the first to seventh p-channel transistors all include a second semiconductor layer, And the second semiconductor layer includes silicon.

Images