Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a substrate, a plurality of light-emitting devices and a reference wiring layer. The substrate is provided with a display area and a non-display area. The light-emitting devices are arranged in the display area at intervals. The light-emitting device comprises an anode, a light-emitting part and a cathode which are stacked on a substrate. The reference wiring layer comprises a first wiring combination at least partially located in the display area and a second wiring combination located in the non-display area. And the first wiring combination is connected with the cathode of each light-emitting device. The second wiring combination comprises a wiring collection part, at least three first connecting lines and at least two second connecting lines, and the wiring collection part is connected with the first connecting lines and the second connecting lines respectively. The first connecting line is connected with the first wiring combination, and the second connecting line is used for being connected with a display driving chip.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and specifically relates to a display panel and a display device. Background Art

[0002] AMOLED (Active-matrix organic light-emitting diode) has the advantages of self-luminescence, wide color gamut, high contrast, flexibility, high response, etc., and has a wide range of application prospects. Compared with conventional collection, medium and large-sized products require higher brightness, and medium and large-sized products have a larger load, so optimization is needed to reduce the current density. Summary of the invention

[0003] The present application provides a display panel and a display device, aiming to solve the problem of reducing current density to at least a certain extent.

[0004] In a first aspect of the present application, a display panel is provided, the display panel comprising: A base substrate having a display area and a non-display area; A plurality of light-emitting devices are arranged at intervals in the display area; the light-emitting devices include an anode, a light-emitting portion and a cathode, and the light-emitting portion is connected to the anode and the cathode respectively; The reference routing layer includes a first routing combination at least partially located in the display area and a second routing combination located in the non-display area; the first routing combination is connected to the cathode of each of the light-emitting devices; the second routing combination includes a routing collection portion, at least three first connecting wires and at least two second connecting wires, the routing collection portion is respectively connected to the first connecting wires and the second connecting wires; the first connecting wires are connected to the first routing combination, and the second connecting wires are used to connect to the display driver chip.

[0005] In some embodiments, the first connection line, the wiring collection portion, and the second connection line are sequentially arranged along a first direction away from the display area; The non-display area includes a first border area located on one side of the display area and a peripheral area located on a side of the first border area away from the display area; the first connecting line is located in the first border area, the wiring collection part is at least partially located in the first border area, and the second connecting line is located in the peripheral area.

[0006] In some embodiments, in a second direction parallel to the base substrate and perpendicular to the first direction, the width of the routing collection portion is greater than the sum of the widths of each of the second connecting lines in the second routing combination; the routing collection portion is also located in the peripheral area.

[0007] In some embodiments, in the first direction, the length of the wiring collection portion is greater than the length of the second connecting line.

[0008] In some implementations, the first routing combination includes: A plurality of first voltage lines are arranged at intervals in the display area; A voltage connection line is arranged along a boundary line of the display area and is connected to the first voltage line and the first connection line respectively.

[0009] In some implementations, the first routing combination further includes: A plurality of second voltage lines are arranged at intervals in the display area and are cross-connected with the plurality of first voltage lines to form a mesh structure; and the voltage connection line at least partially surrounds the mesh structure.

[0010] In some embodiments, the reference routing layer is located between the light-emitting device and the base substrate, and the cathode of the light-emitting device is connected to the first routing combination through a first connecting hole; the orthographic projection of the first connecting hole on the base substrate is located between the orthographic projections of two adjacent light-emitting devices on the base substrate.

[0011] In some embodiments, the display panel further includes: The first transfer part is located in the display area; the cathode of the light-emitting device is connected to the first transfer part through the first connecting hole, and the first transfer part is connected to the first wiring combination through the second connecting hole.

[0012] In some embodiments, the second connecting holes are evenly distributed in the display area.

[0013] In some embodiments, the reference wiring layer is located on a side of the anode of the light-emitting device away from the cathode of the light-emitting device, and the first transition portion is arranged on the same layer as the anode of the light-emitting device.

[0014] In some embodiments, the non-display area includes a first frame area located on one side of the display area and a peripheral area located on a side of the first frame area away from the display area; the display panel further includes: The second transfer portion is located in the first frame area; the cathode of the light-emitting device is connected to the first wiring combination through the second transfer portion.

[0015] In some embodiments, the second transition portion is disposed at the same layer as the first transition portion.

[0016] In some embodiments, the display panel further includes: The protection line is arranged along the boundary line of the display panel.

[0017] In some embodiments, in a third direction parallel to the base substrate and perpendicular to the extension direction of the protection line, the width of the protection line is 10 μm to 50 μm.

[0018] In a second aspect of the present application, a display device is provided, comprising the display panel provided in the first aspect.

[0019] According to one or more embodiments of the present application, the display panel and display device provided include a substrate, a plurality of light-emitting devices and a reference wiring layer. The substrate has a display area and a non-display area, and the plurality of light-emitting devices are arranged at intervals in the display area. The light-emitting device includes an anode, a light-emitting portion and a cathode, and the light-emitting portion is connected to the anode and the cathode respectively. The reference wiring layer includes a first wiring combination at least partially located in the display area and a second wiring combination located in the non-display area, and the first wiring combination is connected to the cathode of each light-emitting device. The second wiring combination includes a wiring collection portion, at least three first connecting wires and at least two second connecting wires, the wiring collection portion is connected to the first connecting wire and the second connecting wire respectively, the first connecting wire is connected to the first wiring combination, and the second connecting wire is used to connect to the display driver chip. In this way, after the reference voltage signal provided by the display driver chip is transmitted to the wiring collection portion through the second connecting wire, it will be transmitted to the first wiring combination through at least three first connecting wires respectively, so as to be transmitted to the cathode of each light-emitting device. By increasing the number of first connecting wires to optimize the reference wiring layer, the current of each first connecting wire can be effectively dispersed, the current density can be reduced, and the current concentration at the reference voltage signal access position can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 A schematic structural diagram of a display panel in the related art is shown.

[0022] Figure 2 Shows Figure 1 Schematic diagram of temperature distribution of the display panel when it is lit.

[0023] Figure 3 A schematic diagram of the structure of a display panel in one or more embodiments of the present application is shown.

[0024] Figure 4 Shows Figure 3 A top-down diagram of the reference routing layer.

[0025] Figure 5 Shows Figure 3 Schematic diagram of part of the structure near the outer area.

[0026] Figure 6 A top view schematic diagram of a reference routing layer in another embodiment of the present application is shown.

[0027] Figure 7 A top view schematically shows a reference routing layer in yet another embodiment of the present application.

[0028] Figure 8 A top view schematically shows a reference routing layer in yet another embodiment of the present application.

[0029] Fig. 9 A top view schematically shows a reference routing layer in yet another embodiment of the present application.

[0030] Fig.10 A schematic top view of a portion of a light emitting device in yet another embodiment of the present application is shown.

[0031] Fig.11 Shows Fig.10 A schematic diagram of the local structure of a display panel where the light-emitting device is located along the AA' section line.

[0032] Fig.12 Shows Fig.11 A schematic structural diagram of the left and right frames of a display panel.

[0033] Fig.13 Shows Figure 8 and Fig. 9 A schematic diagram of the structure of the left and right borders of the display panel where the reference routing layer is located.

[0034] Fig.14 Shows Fig.11 A schematic structural diagram of an upper frame of a display panel.

[0035] Fig.15 Shows Figure 8 and Fig. 9 A schematic diagram of the structure of the upper frame of the display panel where the reference routing layer is located.

[0036] Fig.16 Shows Figure 4 Schematic diagram of the partial structure of the display panel.

[0037] Fig.17 Shows Figure 7 Schematic diagram of the partial structure of the display panel.

[0038] Fig.18 Shows Figure 8 Schematic diagram of the partial structure of the display panel.

[0039] Fig.19 Shows Fig. 9 Schematic diagram of the partial structure of the display panel.

[0040] Fig. 20 A partial structural schematic diagram of a display panel in another embodiment of the present application is shown.

[0041] Fig.21 A partial structural schematic diagram of a display panel in another embodiment of the present application is shown.

[0042] Fig. 22 A partial structural schematic diagram of a display panel in another embodiment of the present application is shown.

[0043] Fig.23 A partial structural schematic diagram of a display panel in another embodiment of the present application is shown.

[0044] Explanation of reference numerals: 10': substrate; 11': display area; 12': frame area; 13': peripheral area; 20': reference routing layer; 21': mesh structure; 22': ring structure; 23': routing collection part; 24': first connecting line; 25': second connecting line; 10: substrate; 11: display area; 12: non-display area; 121: first frame area; 122: peripheral area; 123: second frame area; 124: third frame area; 125: fourth frame area; 20: light-emitting device; 21: first electrode layer; 22: light-emitting layer; 23: second electrode layer; 30: reference routing Layer; 31: first routing combination; 311: first voltage line; 312: voltage connection line; 313: second voltage line; 314: strip connection line; 32: second routing combination; 321: routing collection part; 322: first connection line; 323: second connection line; 33: third routing combination; 331: first routing collection block; 332: third connection line; 34: fourth routing combination; 341: second routing collection block; 342: fourth connection line; 343: fifth connection line; 41: first connection hole; 42: second connection hole; 51: first transfer part; 52: second transfer part; 53: protection line. DETAILED DESCRIPTION

[0045] In order to make the technical personnel in the technical field to which the present application belongs to understand the present application more clearly, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0046] Figure 1 For a schematic diagram of the structure of a display panel in the related art, please refer to Figure 1 The display panel includes a base substrate 10' and a reference routing layer 20' located on the base substrate 10'. The base substrate 10' has a display area 11', a frame area 12' and a peripheral area 13'. The frame area 12' surrounds the display area 11'. The peripheral area 13' is located on a side of the frame area 12' away from the display area 11'. The reference routing layer 20' includes a mesh structure 21', a strip structure 22', a plurality of routing collection parts 23' and their corresponding first connection lines 24' and second connection lines 25'. The mesh structure 21' is located on the display area 11' and the side of the frame area 12' close to the display area 11'. A plurality of routing collection parts 23' and their corresponding first connection lines 24' are located on one side of the border area 12' close to the peripheral area 13'. The plurality of routing collection parts 23' are arranged in sequence and arranged in a row along the boundary line of the mesh structure 21'. Each routing collection part 23' is connected to the mesh structure 21' through two corresponding first connection lines 24'. The second connection line 25' corresponding to the routing collection part 23' is located in the peripheral area 13', and one end of the second connection line 25' is connected to the routing collection part 23'. The belt structure 22' is located in other areas of the border area 12' and is partially arranged around the mesh structure 21'. The side of the mesh structure 21' away from the peripheral area 13' is connected to the belt structure 22'.

[0047] The inventors analyzed that the magnitude of the current density in the wiring can be expressed as the temperature in the lit state, and the current density distribution in the wiring can be determined according to the temperature distribution of the display panel in the lit state. Figure 2 for Figure 1 Schematic diagram of the temperature distribution of the display panel in the lit state, please refer to Figure 2 , the temperature of the areas corresponding to the various colors on the left increases from top to bottom, that is, the temperature of the blue area, the temperature of the green area, the temperature of the yellow area, and the temperature of the red area gradually increase. The temperature of the red areas at positions 1, 2, and 3 is higher, indicating that the current density at positions 1, 2, and 3 is larger. Since positions 1, 2, and 3 correspond to Figure 1 At the first connection line 24' corresponding to the three wiring collection parts 23' ( Figure 1 Therefore, the first connecting line 24' corresponding to the wiring collection part 23' needs to be optimized in design.

[0048] Figure 3 is a schematic diagram of the structure of a display panel in one or more embodiments of the present application, Figure 4 for Figure 3 For a top view of the reference routing layer, see Figure 3 and Figure 4In a first aspect of the present application, a display panel is provided, which includes a substrate substrate 10, a plurality of light-emitting devices 20 and a reference wiring layer 30. The substrate substrate 10 has a display area 11 and a non-display area 12. A plurality of light-emitting devices 20 are arranged at intervals in the display area 11. The light-emitting device 20 includes an anode, a light-emitting portion and a cathode, and the light-emitting portion is connected to the anode and the cathode respectively. The reference wiring layer 30 includes a first wiring combination 31 at least partially located in the display area 11 and a second wiring combination 32 located in the non-display area 12. The first wiring combination 31 is connected to the cathode of each light-emitting device 20. The second wiring combination 32 includes a wiring collection portion 321, at least three first connecting wires 322 and at least two second connecting wires 323, and the wiring collection portion 321 is connected to the first connecting wire 322 and the second connecting wire 323 respectively. The first connecting wire 322 is connected to the first wiring combination 31, and the second connecting wire 323 is used to connect to the display driver chip. At this time, the reference voltage signal provided by the display driver chip is transmitted to the cathode of each light-emitting device 20 through the second connecting line 323 , the wiring collection portion 321 , the first connecting line 322 , and the first wiring combination 31 in sequence.

[0049] The display panel includes a base substrate 10, a plurality of light-emitting devices 20 and a reference wiring layer 30. The base substrate 10 has a display area 11 and a non-display area 12, and a plurality of light-emitting devices 20 are arranged in the display area 11 at intervals. The light-emitting device 20 includes an anode, a light-emitting portion and a cathode, and the light-emitting portion is connected to the anode and the cathode respectively. The reference wiring layer 30 includes a first wiring combination 31 at least partially located in the display area 11 and a second wiring combination 32 located in the non-display area 12, and the first wiring combination 31 is connected to the cathode of each light-emitting device 20. The second wiring combination 32 includes a wiring collection portion 321, at least three first connecting wires 322 and at least two second connecting wires 323, the wiring collection portion 321 is connected to the first connecting wire 322 and the second connecting wire 323 respectively, the first connecting wire 322 is connected to the first wiring combination 31, and the second connecting wire 323 is used to connect to the display driver chip. In this way, after the reference voltage signal provided by the display driver chip is transmitted to the wiring collection part 321 through the second connecting line 323, it will be transmitted to the first wiring combination 31 through at least three first connecting lines 322 respectively, so as to be transmitted to the cathode of each light-emitting device 20. By increasing the number of first connecting lines 322 to optimize the reference wiring layer 30, the current of each first connecting line 322 can be effectively dispersed, the current density can be reduced, and the current concentration at the reference voltage signal access position can be avoided.

[0050] In some embodiments, see Figure 4 The non-display area 12 may include a first frame area 121 located at one side of the display area 11 and a peripheral area 122 located at a side of the first frame area 121 away from the display area 11 .

[0051] Figure 5 for Figure 3 For a partial structural diagram near the outer area of Figure 5 For example, the peripheral area 122 may include a bending area 129, a chip bonding area 128 for bonding a display driver chip, a circuit board bonding area 127 for bonding an FPC (Flexible Printed Circuit) and a wiring area 126. The bending area 129, the chip bonding area 128 and the circuit board bonding area 127 are sequentially arranged along a first direction away from the display area 11, and the wiring area 126 is located between the bending area 129, the chip bonding area 128 and the circuit board bonding area 127. The peripheral area 122 may include a plurality of chip bonding areas 128, and the plurality of chip bonding areas 128 are sequentially spaced along a second direction parallel to the base substrate 10 and perpendicular to the first direction. In addition, the data line can be arranged in the bending area 129, and the power routing combination (represented by a filled graphic in the figure) can be arranged between the bending area 129 and the chip bonding area 128, and between two adjacent chip bonding areas 128, and extend from the first border area 121 through the bending area 129 to the circuit board bonding area 127.

[0052] For example, see Figure 4 The non-display area 12 may further include a second frame area 123, a third frame area 124 and a fourth frame area 125. The second frame area 123 and the first frame area 121 are arranged on both sides of the display area 11, and the third frame area 124 and the fourth frame area 125 are arranged on both sides of the display area 11 and are adjacent to the first frame area 121. That is, the first frame area 121, the third frame area 124, the second frame area 123 and the fourth frame area 125 are connected end to end in sequence along the boundary line of the display area 11.

[0053] In some embodiments, the anode, the light emitting portion, and the cathode of the light emitting device 20 may be arranged in sequence in a direction away from the base substrate 10 .

[0054] In some embodiments, see Figure 3 , the reference wiring layer 30 may be located between the light emitting device 20 and the substrate 10 .

[0055] For example, the reference wiring layer 30 may be located on a side of the anode of the light emitting device 20 away from the cathode of the light emitting device 20 .

[0056] In some embodiments, the second routing combination 32 may include three first connecting lines 322, four first connecting lines 322, five first connecting lines 322, etc. The number of first connecting lines 322 in the second routing combination 32 may be designed according to the space size and process accuracy.

[0057] In some embodiments, see Figure 4 The first connection line 322 , the wiring collection portion 321 , and the second connection line 323 may be sequentially arranged along a first direction away from the display area 11 .

[0058] Exemplarily, the first connection line 322 is located in the first border area 121 , the wiring collection portion 321 is at least partially located in the first border area 121 , and the second connection line 323 is located in the peripheral area 122 .

[0059] In some embodiments, see Figure 4 In a second direction parallel to the base substrate 10 and perpendicular to the first direction, the width of the routing collection portion 321 may be greater than the sum of the widths of the first connecting lines 322 in the second routing combination 32, and may also be greater than the sum of the widths of the second connecting lines 323 in the second routing combination 32.

[0060] In one possible embodiment, see Figure 4 , the routing collection part 321 can also be located in the peripheral area 122, that is, the routing collection part 321 is located in both the first border area 121 and the peripheral area 122. By making the width of the routing collection part 321 greater than the sum of the widths of the second connecting lines 323 in the second routing combination 32, the routing collection part 321 is extended to the peripheral area 122 to partially replace the second connecting lines 323 in the same second routing combination 32, so as to increase the overall width and reduce the current density.

[0061] For example, see Figure 4 In the first direction, the length of the wiring collection portion 321 can be greater than the length of the second connection line 323, and the wiring collection portion 321 can be used to increase the overall width and reduce the current density.

[0062] For example, see Figure 4 The second connection line 323 can extend from the wiring collection portion 321 to a side of the peripheral area 122 away from the first border area 121 .

[0063] Figure 6 For another example of the present application, please refer to Figure 6 In another possible embodiment, the wiring collection portion 321 may be located only in the first border area 121 .

[0064] In some embodiments, see Figure 4 and Figure 6 The reference routing layer 30 may include a plurality of second routing combinations 32, and the plurality of second routing combinations 32 are sequentially spaced apart along the second direction.

[0065] For example, see Figure 4 and Figure 6The first connection line 322 and the second connection line 323 can extend along the first direction and be arranged in sequence and spaced apart along the second direction.

[0066] Exemplarily, the second connection line 323 may extend to a FOP (Flexible Printed Circuit on Panel) region in the peripheral region 122 , namely, a circuit board bonding region 127 , to be connected to the FPC.

[0067] In some embodiments, see Figure 4 and Figure 6 , the reference routing layer 30 may further include a third routing combination 33 located only in the first border area 121. The third routing combination 33 includes a first routing collection block 331 and at least three third connecting lines 332. The third connecting lines 332 are respectively connected to the first routing collection block 331 and the first routing combination 31, that is, the first routing collection block 331 is connected to the first routing combination 31 through at least three third connecting lines 332.

[0068] For example, see Figure 4 and Figure 6 The reference routing layer 30 may include a plurality of third routing combinations 33, and the plurality of third routing combinations 33 are sequentially spaced apart along the second direction.

[0069] For example, see Figure 4 and Figure 6 , the second routing combination 32 can be located between two adjacent third routing combinations 33, that is, the third routing combination 33 and the second routing combination 32 are alternately arranged along the second direction. In practical applications, the second routing combination 32 can be located between two adjacent power routing combinations, and the third routing combination 33 is only located in the first border area 121, so that the power routing combination is conveniently arranged in the vacant peripheral area 122. The power routing combination can be connected to the display driver chip in a one-to-one correspondence.

[0070] For example, see Figure 4 and Figure 6 The third connection lines 332 may extend along the first direction and be sequentially spaced apart along the second direction.

[0071] In some embodiments, see Figure 4 and Figure 6, the reference routing layer 30 may further include a fourth routing combination 34. The fourth routing combination 34 includes a second routing collection block 341 and two fourth connecting lines 342 located only in the first border area 121, and a fifth connecting line 343 located in the peripheral area 122. The second routing collection block 341 is connected to the fourth connecting line 342 and the fifth connecting line 343, respectively. The fourth connecting line 342 is connected to the first routing combination 31. The fifth connecting line 343 is used to connect to the display driver chip.

[0072] For example, see Figure 4 and Figure 6 The reference routing layer 30 may include two fourth routing combinations 34 , and the two fourth routing combinations 34 are located at two ends of the first border area 121 close to the peripheral area 122 , that is, the second routing combination 32 and the third routing combination 33 are both located between the two fourth routing combinations 34 .

[0073] For example, see Figure 4 and Figure 6 The fourth connection line 342 and the fifth connection line 343 may extend along the first direction and be sequentially spaced along the second direction. The fifth connection line 343 may extend from the second wiring collection block 341 to the FOP area, that is, the circuit board bonding area 127 .

[0074] In some embodiments, see Figure 4 and Figure 6 The first wiring combination 31 may include a plurality of first voltage lines 311 and voltage connection lines 312. The plurality of first voltage lines 311 are arranged at intervals in the display area 11. The voltage connection lines 312 are arranged along the boundary lines of the display area 11, and are respectively connected to the first voltage lines 311 and the first connection lines 322. In this way, the first voltage lines 311 are connected through the voltage connection lines 312.

[0075] For example, see Figure 4 and Figure 6 The first voltage lines 311 may extend along the first direction and be sequentially spaced apart along the second direction.

[0076] For example, see Figure 4 and Figure 6 , multiple first voltage lines 311 can be located in the display area 11 and the first frame area 121 and the second frame area 123 on the side close to the display area 11, and the voltage connection line 312 is at least partially located in the first frame area 121, the third frame area 124 and the fourth frame area 125.

[0077] In one possible embodiment, see Figure 4 and Figure 6The first wiring combination 31 may further include a plurality of second voltage lines 313. The plurality of second voltage lines 313 are arranged at intervals in the display area 11 and cross-connected with the plurality of first voltage lines 311 to form a mesh structure. The voltage connection line 312 at least partially surrounds the mesh structure.

[0078] For example, see Figure 4 and Figure 6 The second voltage lines 313 may extend along the first direction and be sequentially spaced apart along the second direction.

[0079] For example, see Figure 4 and Figure 6 , the plurality of second voltage lines 313 may be located in the display area 11 and a side of the third frame area 124 and the fourth frame area 125 close to the display area 11 .

[0080] Figure 7 For a top view of a reference wiring layer in another embodiment of the present application, please refer to Figure 7 In another possible embodiment, the first wiring combination 31 only includes a plurality of first voltage lines 311 and a voltage connection line 312. The plurality of first voltage lines 311 are arranged at intervals in the display area 11. The voltage connection line 312 is arranged along the boundary line of the display area 11, and is respectively connected to the first voltage line 311 and the first connection line 322. That is, the first wiring combination 31 does not include the second voltage line 313.

[0081] Figure 8 and Fig. 9 For a top view of a reference wiring layer in another embodiment of the present application, please refer to Figure 8 and Fig. 9 In a possible embodiment, the first wiring combination 31 may also include a strip-shaped connecting line 314 located in the second frame area 123, the third frame area 124 and the fourth frame area 125, and the strip-shaped connecting line 314 partially surrounds the voltage connecting line 312. The strip-shaped connecting line 314 located in the second frame area 123 is respectively connected to the plurality of first voltage lines 311. The strip-shaped connecting line 314 located in the third frame area 124 and the fourth frame area 125 is connected to the cathode of each light-emitting device 20 through a metal wiring. At this time, the reference voltage signal provided by the driving display chip is transmitted to the cathode of each light-emitting device 20 through the second wiring combination 32, the voltage connecting line 312, the first voltage line 311, and the strip-shaped connecting line 314 in sequence.

[0082] For example, see Figure 8 and Fig. 9 The two ends of the strip-shaped connecting line 314 can be connected to the two fourth routing combinations 34 respectively, and specifically can be connected to the second routing collection block 341 in the fourth routing combination 34.

[0083] For example, in a direction perpendicular to the extending direction of the strip-shaped connecting line 314 and parallel to the base substrate 10 , the width of the strip-shaped connecting line 314 may be greater than 500 μm, such as 500 μm, 600 μm, 700 μm, 800 μm, 900 μm, 1000 μm, etc.

[0084] Fig.10 This is a schematic top view of a portion of a light emitting device in another embodiment of the present application. Fig.10 In another possible embodiment, the cathode of the light-emitting device 20 can be connected to the first wiring combination 31 through the first connecting hole 41. The orthographic projection of the first connecting hole 41 on the base substrate 10 is located between the orthographic projections of two adjacent light-emitting devices 20 on the base substrate 10. At this time, the reference voltage signal provided by the driving display chip is transmitted to the cathode of each light-emitting device 20 through the second wiring combination 32, the voltage connecting line 312, and the mesh structure (or the first voltage line 311) in sequence. In this way, there is no need to set the strip connecting line 314, which can greatly reduce the frame width and achieve a narrow frame. It is also beneficial to disperse the current, avoid current concentration, and reduce the current density.

[0085] Fig.11 for Fig.10 The schematic diagram of the local structure of the display panel along the A-A' section line where the light emitting device is located is shown in FIG. Figure 4-Figure 7 and Fig.11 Exemplarily, the display panel may further include a first adapter 51, which is located in the display area 11. The cathode of the light emitting device 20 is connected to the first adapter 51 through the first connecting hole 41, and the first adapter 51 is connected to the first wiring assembly 31 through the second connecting hole 42.

[0086] Fig.12 for Fig.11 A schematic diagram of the structure of the left and right borders of the display panel, Fig.13 for Figure 8 and Fig. 9 The structure diagram of the left and right borders of the display panel where the reference routing layer is located, see Fig.12 and Fig.13 When the strip connecting line 314 is not required, the left and right frames of the display panel do not need to lead out the cathode of the light-emitting device 20, and the strip connecting line 314 is not required. The number of retaining walls can be reduced, and the frame width is smaller than when the strip connecting line 314 is set.

[0087] Fig.14 for Fig.11 A schematic diagram of the structure of the upper frame of the display panel, Fig.15 for Figure 8 and Fig. 9 The schematic diagram of the structure of the upper frame of the display panel where the reference routing layer is located, see Fig.14 and Fig.15 When the strip connecting line 314 is not required, the left and right frames of the display panel do not need to lead out the cathode of the light-emitting device 20, and the strip connecting line 314 is not required. The number of retaining walls can be reduced, and the frame width is smaller than when the strip connecting line 314 is set.

[0088] In one possible embodiment, see Figure 4-Figure 6 The first wiring combination 31 includes multiple first voltage lines 311 and multiple second voltage lines 313. When the multiple first voltage lines 311 and the multiple second voltage lines 313 are cross-connected to form a mesh structure, the cathode of the light-emitting device 20 is connected to the mesh structure through the first connecting hole 41, the first connecting part 51, and the second connecting hole 42. At this time, the current dispersion effect is better.

[0089] In another possible embodiment, see Figure 7 When the first wiring combination 31 does not include the second voltage line 313 , the cathode of the light emitting device 20 is connected to the first voltage line 311 through the first connecting hole 41 , the first transition portion 51 , and the second connecting hole 42 .

[0090] For example, see Figure 4-Figure 7 The second connecting holes 42 can be evenly distributed in the display area 11, which is beneficial to reducing the current density. In practical applications, the distribution density of the second connecting holes 42 can be adjusted according to actual needs.

[0091] For example, see Fig.11 , the first transfer part 51 can be arranged in the same layer as the anode of the light-emitting device 20. In practical applications, the first electrode layer 21 can be formed first, and the first electrode layer 21 includes the anode of each light-emitting device 20 and the first transfer part 51, and the first transfer part 51 is connected to the mesh structure through the second connecting hole 42. Then, the light-emitting layer 22 is laid on the first electrode layer 21 to form the light-emitting part of each light-emitting device 20. Then, a part of the light-emitting layer 22 is removed by a laser device, and the first connecting hole 41 is opened to expose the first transfer part 51. Finally, the second electrode layer 23 is laid on the light-emitting layer 22 to form the cathode of each light-emitting device 20, and the second electrode layer 23 is connected to the first transfer part 51 in the first connecting hole 41. In this way, by overlapping the cathode of the light-emitting device 20 with the first transfer part 51 on the same layer as the anode, the reference routing in the display area 11 can be realized, and the routing resistance can be reduced.

[0092] Exemplarily, the orthographic projection of the first connecting hole 41 on the base substrate 10 may overlap with the orthographic projection of the second connecting hole 42 on the base substrate 10 , or may not intersect with the orthographic projection of the second connecting hole 42 on the base substrate 10 .

[0093] Fig.16 for Figure 4 A schematic diagram of a partial structure of a display panel, Fig.17 for Figure 7 For a partial structural diagram of the display panel, please refer to Figure 16-Figure 17 In some embodiments, the display panel may further include a second transfer portion 52, and the second transfer portion 52 is at least partially located in the first frame area 121. The cathode of the light emitting device 20 is connected to the first wiring combination 31 through the second transfer portion 52.

[0094] Fig.18 for Figure 8 A schematic diagram of a partial structure of a display panel, Fig.19 for Fig. 9 For a partial structural diagram of the display panel, please refer to Figure 18-19 In a possible embodiment, when the second border area 123, the third border area 124 and the fourth border area 125 are provided with a strip connecting line 314, the second adapter 52 can be located in the first border area 121, the third border area 124, the second border area 123 and the fourth border area 125, the second adapter 52 located in the first border area 121 is connected to the wiring collection part 321, and the second adapter 52 located in the third border area 124, the second border area 123 and the fourth border area 125 is connected to the strip connecting line 314.

[0095] Exemplarily, the orthographic projection of the strip-shaped connecting line 314 on the base substrate 10 may at least partially overlap with the orthographic projection of the second transition portion 52 on the base substrate 10 .

[0096] For example, see Figure 18-19 The orthographic projection of the second transfer portion 52 located in the first frame area 121 on the base substrate 10 may overlap with the orthographic projection of the routing collection portion 321 on the base substrate 10. The orthographic projection of the second transfer portion 52 located in the third frame area 124, the second frame area 123 and the fourth frame area 125 on the base substrate 10 may overlap with the orthographic projection of the strip-shaped connecting line 314 on the base substrate 10.

[0097] In another possible embodiment, see Figure 16-Figure 17 When the second frame area 123 , the third frame area 124 and the fourth frame area 125 are not provided with the strip connecting line 314 , the second adapter portion 52 can be located only in the first frame area 121 , and the cathode of the light-emitting device 20 is connected to the wiring collection portion 321 through the second adapter portion 52 .

[0098] For example, see Fig.16 The orthographic projection of the second transfer portion 52 on the base substrate 10 may overlap with the orthographic projection of the wiring collection portion 321 on the base substrate 10 .

[0099] Exemplarily, the second transition portion 52 may be disposed at the same layer as the first transition portion 51 .

[0100] Fig. 20 , Fig.21 , Fig. 22 and Fig.23 This is a partial structural diagram of a display panel in another embodiment of the present application. Figure 20-23 In some embodiments, the display panel may further include protection lines 53 located in the second frame area 123, the third frame area 124 and the fourth frame area 125. The protection lines 53 are arranged along the boundary lines of the display panel, and can protect metal wiring such as GOA (English: Gate On Array, Chinese: gate drive circuit integrated on array substrate) in the display panel to avoid cutting and external electric field influences.

[0101] For example, see Figure 20-23 , the protection line 53 can partially surround the voltage communication line 312.

[0102] Exemplarily, the protection line 53 may be located between the cutting street of the display panel and the GOA.

[0103] Exemplarily, in a third direction parallel to the base substrate 10 and perpendicular to the extension direction of the protection line 53, the width of the protection line 53 may be 10 μm to 50 μm, such as 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, etc. The width of the protection line 53 is 10 μm to 50 μm, which can prevent the protection line 53 from being too narrow to cause ESD (Electro-Static discharge) on the one hand, and prevent the protection line 53 from being too wide to affect the realization of a narrow frame on the other hand.

[0104] Exemplarily, the protection line 53 may be located in at least two layers. The orthographic projections of at least two layers of the protection line 53 on the base substrate 10 partially overlap and are connected through a connecting hole. The protection line 53 adopts a jumper design, which can effectively avoid ESD. For example, a part of the protection line 53 can be arranged in the same layer as the source and drain layer, and another part can be arranged in the same layer as the gate layer, and the protection line 53 is alternately arranged in the source and drain layer and the gate layer in the extension direction.

[0105] For example, the protection line 53 can be connected to the reference wiring layer 30 or the power wiring combination. Fig.18 , both ends of the protection line 53 can be connected to two fourth wiring combinations 34 .

[0106] In some embodiments, the display panel can be suitable for products having at least one COF (Chip On Flex) or COP (Chip On Pi), and can be suitable for products using technologies such as LTPS (Low Temperature Polycrystalline Oxide) and LTPO (Low Temperature Poly-Silicon).

[0107] A second aspect of the present application provides a display device, which includes a display panel provided in any of the above embodiments.

[0108] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0109] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise" and "counterclockwise" indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0110] In this application, unless otherwise clearly specified and limited, the terms "connection", "fixation", etc. should be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0111] In addition, the descriptions of "first", "second", etc. in this application are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0112] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A display panel, characterized in that: The display panel comprises: A base substrate (10) having a display area (11) and a non-display area (12); A plurality of light-emitting devices (20) are arranged at intervals in the display area (11); the light-emitting devices (20) include an anode, a light-emitting portion and a cathode stacked on the base substrate (10); A reference wiring layer (30) comprises a first wiring combination (31) at least partially located in the display area (11) and a second wiring combination (32) located in the non-display area (12); the first wiring combination (31) is connected to the cathode of each of the light-emitting devices (20); the second wiring combination (32) comprises a wiring collection portion (321), at least three first connecting wires (322) and at least two second connecting wires (323); the wiring collection portion (321) is respectively connected to the first connecting wires (322) and the second connecting wires (323); the first connecting wires (322) are connected to the first wiring combination (31), and the second connecting wires (323) are used to connect to a display driver chip.

2. The display panel according to claim 1, characterized in that: The first connecting line (322), the wiring collection portion (321), and the second connecting line (323) are arranged in sequence along a first direction away from the display area (11); The non-display area (12) comprises a first frame area (121) located on one side of the display area (11) and a peripheral area (122) located on a side of the first frame area (121) away from the display area (11); the first connecting line (322) is located in the first frame area (121), the wiring collection portion (321) is at least partially located in the first frame area (121), and the second connecting line (323) is located in the peripheral area (122).

3. The display panel according to claim 2, characterized in that: In a second direction parallel to the base substrate (10) and perpendicular to the first direction, the width of the routing collection portion (321) is greater than the sum of the widths of each of the second connecting lines (323) in the second routing combination (32); the routing collection portion (321) is also located in the peripheral area (122).

4. The display panel according to claim 3, characterized in that: In the first direction, the length of the wiring collection portion (321) is greater than the length of the second connecting line (323).

5. The display panel according to any one of claims 1 to 4, characterized in that: The first routing combination (31) comprises: A plurality of first voltage lines (311) are arranged at intervals in the display area (11); A voltage connection line (312) is arranged along a boundary line of the display area (11) and is respectively connected to the first voltage line (311) and the first connection line (322).

6. The display panel according to claim 5, characterized in that: The first routing assembly (31) further comprises: A plurality of second voltage lines (313) are arranged at intervals in the display area (11) and are cross-connected with the plurality of first voltage lines (311) to form a mesh structure; the voltage connection line (312) at least partially surrounds the mesh structure.

7. The display panel according to claim 5, characterized in that: The reference wiring layer (30) is located between the light-emitting device (20) and the base substrate (10); the cathode of the light-emitting device (20) is connected to the first wiring combination (31) via a first connecting hole (41); and the orthographic projection of the first connecting hole (41) on the base substrate (10) is located between the orthographic projections of two adjacent light-emitting devices (20) on the base substrate (10).

8. The display panel according to claim 7, characterized in that: The display panel further includes: A first adapter (51) is located in the display area (11); the cathode of the light-emitting device (20) is connected to the first adapter (51) through the first connecting hole (41), and the first adapter (51) is connected to the first wiring assembly (31) through the second connecting hole (42).

9. The display panel according to claim 8, characterized in that: The second communication holes (42) are evenly distributed in the display area (11).

10. The display panel according to claim 8, characterized in that: The reference wiring layer (30) is located on a side of the anode of the light-emitting device (20) away from the cathode of the light-emitting device (20), and the first transition portion (51) is arranged on the same layer as the anode of the light-emitting device (20).

11. The display panel according to claim 10, characterized in that: The non-display area (12) comprises a first frame area (121) located on one side of the display area (11) and a peripheral area (122) located on a side of the first frame area (121) away from the display area (11); the display panel further comprises: The second transfer portion (52) is located in the first frame area (121); the cathode of the light-emitting device (20) is connected to the first wiring combination (31) via the second transfer portion (52).

12. The display panel according to claim 11, characterized in that: The second transition portion (52) is arranged at the same layer as the first transition portion (51).

13. The display panel according to claim 7, characterized in that: The display panel further includes: A protection line (53) is arranged along a boundary line of the display panel.

14. The display panel according to claim 13, characterized in that: In a third direction parallel to the base substrate (10) and perpendicular to the extension direction of the protection line (53), the width of the protection line (53) is 10 μm to 50 μm.

15. A display device, characterized in that: The display device comprises the display panel according to claims 1-14.

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