CrSi thin film resistor preparation method, resistor device preparation method, and resistor device

Abstract

The application discloses a CrSi thin film resistor preparation method, a resistor device preparation method and a resistor device, and relates to the technical field of semiconductor manufacturing. The CrSi thin film resistor preparation method comprises the following steps: depositing a CrSi thin film layer on an NDC film layer of a wafer; depositing a SiON film layer above the CrSi thin film layer, and the SiON film layer covering the CrSi thin film layer; performing high-temperature annealing treatment on the CrSi thin film layer; etching a metal electrode contact hole on the SiON film layer and the CrSi thin film layer by adopting dry etching; depositing a TIN film layer on the front surface of the wafer, and the TIN film layer covering the SiON film layer, the CrSi thin film layer and the metal electrode contact hole; and etching the TIN film layer into a metal electrode by adopting dry etching. Through the above technical means, the SiON film layer prevents the outward diffusion of Cr atoms when the CrSi thin film layer is subjected to high-temperature annealing, and the dry etching is performed on the CrSi thin film layer and the TIN film layer, so that the problems of Cr atom contamination of etching liquid and the problems of TIN side etching and exposure of both ends of the CrSi thin film layer are avoided.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of semiconductor preparation, in particular to a CrSi thin film resistor preparation method, a resistor device preparation method and a resistor device. BACKGROUND

[0002] The CrSi thin film resistor refers to a resistor material composed of chromium (Cr) and silicon (Si). Due to its high performance and high stability, the CrSi thin film resistor is widely used in various electronic devices, such as smart devices, wearable technology and Internet of Things devices. With the continuous progress of technology and the increasing demand for high-performance resistors in smart devices, the application prospect of the CrSi thin film resistor will be more promising. With the continuous decrease of the process node of integrated circuits and the continuous improvement of the performance of advanced processes, the preparation of the CrSi thin film resistor is paid more and more attention.

[0003] In the prior art, the preparation process of the CrSi thin film resistor is as follows: depositing a CrSi thin film layer on an NDC and etching out a resistor pattern; high-temperature annealing; depositing TIN on the CrSi; depositing SiON on the TIN layer and etching out a pattern of a metal electrode contact hole; etching the TIN into a metal electrode pattern by wet etching; depositing Oxide and making a wiring hole. There are three serious Cr contamination processes in this process flow: first, the CrSi thin film layer is directly exposed to high temperature during high-temperature annealing, causing the Cr atoms in the CrSi thin film layer to diffuse violently in the annealing chamber; second, when wet etching TIN, the wafer is sent into a container containing etching liquid for reaction, and in the reaction process, a large area of the CrSi thin film layer is exposed due to the large amount of TIN etched out, and due to the anisotropy of the reaction between the etching liquid and the film layer, side notching of the TIN occurs, further increasing the exposed area of the CrSi thin film layer, and a large amount of Cr atoms will quickly enter the etching liquid, and after other devices enter the container for reaction, the Cr atoms in the etching liquid will adhere to the surface of the devices or diffuse into the interior, causing heavy metal pollution; third, after the TIN metal electrode, the wiring hole and the upper film layer are prepared, the CrSi thin film layer will be exposed in a hollow due to the side notching of the TIN, and in this case, the Cr atoms in the exposed CrSi thin film layer will diffuse into the air, causing heavy metal pollution to the machines, containers used in the subsequent process steps. Therefore, the existing preparation process will cause pollution to the equipment, environment and other resistor devices in production when preparing the CrSi thin film resistor, seriously affecting the production efficiency and safety of the resistor devices. SUMMARY

[0004] The application provides a CrSi thin film resistor preparation method, a resistor device preparation method and a resistor device, and solves the problem of heavy metal pollution caused by the outward diffusion of Cr atoms in the CrSi thin film resistor in the prior art, and improves the production efficiency and safety of the resistor device.

[0005] In a first aspect, the application provides a CrSi thin film resistor preparation method, comprising:

[0006] depositing a CrSi thin film layer on an NDC film layer of a wafer;

[0007] depositing a SiON film layer above the CrSi thin film layer, the SiON film layer covering the CrSi thin film layer;

[0008] performing high-temperature annealing treatment on the CrSi thin film layer;

[0009] etching a metal electrode contact hole on the SiON film layer and the CrSi thin film layer by dry etching;

[0010] depositing a TIN film layer on the front surface of the wafer, the TIN film layer covering the SiON film layer, the CrSi thin film layer and the metal electrode contact hole;

[0011] etching the TIN film layer into a metal electrode by dry etching.

[0012] Optionally, the step of depositing a CrSi thin film layer on an NDC film layer of a wafer comprises:

[0013] depositing a CrSi thin film layer on an NDC film layer of a wafer by a physical vapor deposition process.

[0014] Optionally, after the high-temperature annealing, the method further comprises:

[0015] etching the SiON film layer and the CrSi thin film layer into a resistor pattern by dry etching.

[0016] Optionally, the step of etching the SiON film layer and the CrSi thin film layer into a resistor pattern by dry etching comprises:

[0017] coating a layer of photoresist above the SiON film layer;

[0018] developing the photoresist above the SiON film layer based on a resistor pattern mask to expose part of the SiON film layer;

[0019] etching the exposed SiON film layer and the corresponding underlying CrSi thin film layer by a plasma etching process, so that the remaining SiON film layer and CrSi thin film layer form a resistor pattern.

[0020] Optionally, the dry etching forms a metal electrode contact hole in the SiON film layer and the CrSi thin film layer, comprising:

[0021] A photoresist layer is coated on the SiON film layer;

[0022] The photoresist layer on the SiON film layer is developed based on a contact hole pattern mask to expose part of the SiON film layer;

[0023] The exposed SiON film layer and the corresponding underlying CrSi thin film layer are etched by a plasma etching process to form a metal electrode contact hole in the SiON film layer and the CrSi thin film layer.

[0024] Optionally, the dry etching forms a metal electrode contact hole in the SiON film layer and the CrSi thin film layer, comprising:

[0025] A photoresist layer is coated on the SiON film layer;

[0026] The photoresist layer on the SiON film layer is developed based on a contact hole pattern mask to expose part of the SiON film layer;

[0027] The exposed SiON film layer and the corresponding underlying CrSi thin film layer are etched by a plasma etching process to form a metal electrode contact hole in the SiON film layer and the CrSi thin film layer.

[0028] Optionally, the metal electrode wraps the two ends of the CrSi thin film layer.

[0029] Optionally, after the dry etching forms a metal electrode contact hole in the SiON film layer and the CrSi thin film layer, the method further comprises:

[0030] An NDC film layer is deposited on the front side of the wafer.

[0031] In a second aspect, the application provides a resistor device preparation method, comprising the CrSi thin film resistor preparation method of the first aspect.

[0032] In a third aspect, the application provides a resistor device prepared by the resistor device preparation method of the second aspect.

[0033] In the present application, a CrSi thin film layer is deposited on the NDC film layer of the wafer; a SiON film layer is deposited above the CrSi thin film resistor, the SiON film layer covering the CrSi thin film layer; high-temperature annealing treatment is performed on the CrSi thin film resistor; a metal electrode contact hole is etched on the SiON film layer and the CrSi thin film layer by dry etching; a TIN film layer is deposited on the front surface of the wafer, the TIN film layer covering the SiON film layer, the CrSi thin film layer and the metal electrode contact hole; and the TIN film layer is etched into a metal electrode by dry etching. Through the above technical means, the upper surface of the CrSi thin film layer is entirely covered by the SiON film layer, and the SiON film layer can effectively prevent the diffusion of Cr atoms in the CrSi thin film layer outward during high-temperature annealing of the CrSi thin film layer, thereby reducing the risk of heavy metal pollution. Dry etching is used to etch the CrSi thin film layer, thereby avoiding the problem of Cr atom pollution in the CrSi thin film layer. Dry etching is used to etch the TIN film layer, thereby avoiding the problem of TIN side digging, which exposes both ends of the CrSi thin film layer, further reducing the risk of heavy metal pollution and improving the production efficiency and safety of the resistor device. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a structural schematic diagram of a traditional CrSi thin film resistor during high-temperature annealing provided by an embodiment of the present application;

[0035] Figure 2 is a structural schematic diagram of a traditional CrSi thin film resistor during etching of a TIN layer provided by an embodiment of the present application;

[0036] Figure 3 is a structural schematic diagram of a traditional CrSi thin film resistor after being manufactured provided by an embodiment of the present application;

[0037] Figure 4 is a flowchart of a CrSi thin film resistor preparation method provided by an embodiment of the present application;

[0038] Figure 5 is a structural schematic diagram of a wafer after deposition of a CrSi thin film layer provided by an embodiment of the present application;

[0039] Figure 6 is a structural schematic diagram of a wafer after deposition of a SiON film layer provided by an embodiment of the present application;

[0040] Figure 7 is a structural schematic diagram of a wafer in which a SiON film layer and a CrSi thin film layer are etched into a resistor pattern provided by an embodiment of the present application;

[0041] Figure 8 is a structural schematic diagram of a wafer in which a metal electrode contact hole is etched provided by an embodiment of the present application;

[0042] Figure 9is a structure schematic diagram of a wafer provided by an embodiment of the present application for depositing a TIN film layer;

[0043] Figure 10 is a structure schematic diagram of a wafer provided by an embodiment of the present application for forming a metal electrode of a TIN film layer;

[0044] Figure 11 is a structure schematic diagram of a wafer provided by an embodiment of the present application for depositing a third NDC film layer;

[0045] Figure 12 is a structure schematic diagram of a CrSi thin film resistor provided by an embodiment of the present application;

[0046] In the figure, 11 is a substrate; 12 is an interlayer dielectric layer; 13 is an NDC film layer; 14 is a BD film layer; 15 is a first metal layer; 16 is a CrSi thin film layer; 17 is a SiON film layer; 18 is a metal electrode contact hole; 19 is a TIN film layer; 20 is a metal via hole; and 21 is a second metal layer. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the present application more clear, the following will further describe the specific embodiments of the present application in combination with the drawings. It can be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. In addition, it should be noted that, for the convenience of description, only the parts related to the present application are shown in the drawings, but not all the contents. Before discussing the example embodiments in more detail, it should be mentioned that some example embodiments are described as processes or methods depicted by flowcharts. Although the flowcharts describe the operations (or steps) as sequential processes, many of the operations can be implemented in parallel, concurrently or simultaneously. In addition, the order of the operations can be rearranged. The process can be terminated when the operations are completed, but can also have additional steps not included in the drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0048] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of a kind, and do not limit the number of objects, for example, the first object can be one or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / ", generally means that the objects before and after are in an "or" relationship.

[0049] In a more common existing implementation, the preparation process of the CrSi thin-film resistor is as follows: depositing a CrSi thin-film resistor on an NDC and etching a resistor pattern; high-temperature annealing; depositing TIN on the CrSi; depositing SiON on the TIN layer and etching a pattern of a metal electrode contact hole; etching the TIN into a metal electrode pattern by wet etching; depositing Oxide and making a wiring hole. There are three serious Cr contamination processes in this process flow, which are high-temperature annealing, wet etching of TIN, and after the resistor is made. Figure 1 is a structural schematic diagram of a conventional CrSi thin-film resistor in high-temperature annealing provided by an embodiment of the present application. As shown in Figure 1 , the CrSi is exposed to high temperature without any shielding in high-temperature annealing, so that the Cr atoms are diffused violently in the annealing machine cavity. Figure 2 is a structural schematic diagram of a conventional CrSi thin-film resistor in etching a TIN layer provided by an embodiment of the present application. As shown in Figure 2 , when the TIN is etched by wet etching, the wafer is sent into a container containing etching liquid for reaction. In the reaction process, the TIN is etched a lot and leaks out of the underlying large-area CrSi thin-film layer. A large amount of Cr atoms in the CrSi thin-film layer will quickly enter the etching liquid. When other devices are subsequently reacted in the container containing the etching liquid, the Cr atoms remaining in the etching liquid will adhere to the surface of the devices or diffuse into the devices, causing serious heavy metal contamination to other devices. Moreover, due to the anisotropy of the reaction between the etching liquid and the film layer, the TIN will appear side notching phenomenon (as shown in Figure 2 that the TIN film layer is recessed inward), further increasing the exposed area of the CrSi thin-film layer, thereby further increasing the risk of heavy metal contamination. Figure 3 is a structural schematic diagram of a conventional CrSi thin-film resistor after being made provided by an embodiment of the present application. As shown in Figure 3 , although the two sides of the CrSi thin-film layer are covered by the BD film layer, the side notching problem of the TIN will cause the upper surface of the CrSi thin-film layer at both ends to be uncovered and exposed in a hollow. The Cr atoms in the exposed CrSi thin-film layer will diffuse into the air, causing heavy metal contamination to the machines, containers, and other devices used in the subsequent process steps. Therefore, the existing preparation process will cause contamination to the instruments, environment, and other resistor devices in the production of the CrSi thin-film resistor, seriously affecting the production efficiency and safety of the resistor devices.

[0050] To solve the above problems, the embodiment provides a CrSi thin film resistor preparation method, a resistor device preparation method and a resistor device, so as to deposit a SiON film layer above the CrSi thin film layer, prevent the Cr atoms from diffusing outward through the SiON film layer when the CrSi thin film layer is subjected to high-temperature annealing, perform dry etching on the CrSi thin film layer and the TIN film layer, avoid the problems of Cr atom contamination of the etching liquid and exposure of both ends of the CrSi thin film layer due to TIN side etching, and improve the production efficiency and safety of the resistor device.

[0051] Figure 4 A flowchart of the CrSi thin film resistor preparation method provided by the embodiment is shown in FIG. 1. Figure 4 As shown in FIG. 1, the CrSi thin film resistor preparation method comprises the following steps.

[0052] S110, depositing a CrSi thin film layer 16 on the NDC film layer 13 of the wafer.

[0053] For example, before the CrSi thin film layer 16 is deposited, the wafer is formed by stacking the substrate 11, the interlayer dielectric layer (ILD TEOS) 12, the bottom NDC film layer 13, the BD film layer 14 and the second NDC film layer 13, and the first metal layer 15 is formed in the interlayer dielectric layer 12, the bottom NDC film layer 13 and the BD film layer 14. Before the CrSi thin film layer 16 is deposited, a silicon dioxide material is first deposited on the substrate 11 to form the interlayer dielectric layer 12, a nitrogen-doped silicon carbide material is deposited above the interlayer dielectric layer 12 to form the bottom NDC film layer 13, a SiCOH material is deposited above the bottom NDC film layer 13 to form the BD film layer 14, the pattern of the first metal layer 15 is etched on the BD film layer 14, the bottom NDC film layer 13 and the interlayer dielectric layer 12, and then the copper material is deposited in the pattern of the first metal layer 15 etched on the BD film layer 14, the bottom NDC film layer 13 and the interlayer dielectric layer 12, so that the copper material deposited in the interlayer dielectric layer 12, the bottom NDC film layer 13 and the BD film layer 14 forms the first metal layer 15. Then, a nitrogen-doped silicon carbide material is deposited above the BD film layer 14 and the first metal layer 15 to form the second NDC film layer 13. A CrSi material is deposited above the second NDC film layer 13 to form the CrSi thin film layer 16, and the CrSi thin film layer 16 completely covers the second NDC film layer 13.

[0054] For example, Figure 5 FIG. 2 is a structural schematic diagram of the wafer after the CrSi thin film layer 16 is deposited according to the embodiment of the present application. As shown in FIG. 2, the CrSi thin film layer 16 covers the second NDC film layer 13, and the BD film layer 14, the bottom NDC film layer 13, the interlayer dielectric layer 12 and the substrate 11 are sequentially formed below the second NDC film layer 13. Figure 5

[0055] ​Optionally, a CrSi thin film layer 16 is deposited on the NDC film layer 13 of the wafer by a physical vapor deposition process. The physical vapor deposition (PVD) converts CrSi into atoms, molecules or ions by physical methods such as evaporation, sputtering or ion implantation, and deposits the atoms, molecules or ions on the surface of the second NDC film layer 13 of the wafer to form the CrSi thin film layer 16.

[0056] S120, depositing a SiON film layer 17 above the CrSi thin film layer 16, the SiON film layer 17 covering the CrSi thin film layer 16.

[0057] For example, the SiON material is deposited above the CrSi thin film layer 16 of the wafer to form the SiON film layer 17, the SiON film layer 17 covering the CrSi thin film layer 16.

[0058] For example, Figure 6 is a structure diagram of the wafer provided by the embodiment of the present application for depositing the SiON film layer 17. As shown in Figure 6 , the SiON film layer 17 covers the CrSi thin film layer 16. It should be noted that since the current passes through the CrSi thin film layer 16, the type of material deposited above the CrSi thin film layer 16 does not affect the use of the CrSi thin film layer 16. That is, whether the SiON film layer 17 is formed on the CrSi thin film layer 16 like the traditional CrSi thin film resistor shown in Figure 1 , or is formed above the CrSi thin film layer 16 as shown in Figure 6 , it will not affect the conductive effect of the CrSi thin film layer 16. However, by using the SiON film layer 17 provided by the embodiment to cover the CrSi thin film layer 16, the diffusion of Cr atoms in the CrSi thin film layer 16 can be effectively prevented by the SiON film layer 17 during high-temperature annealing of the CrSi thin film layer 16, thereby reducing the risk of heavy metal pollution.

[0059] S130, performing high-temperature annealing treatment on the CrSi thin film layer 16.

[0060] For example, since the CrSi thin film layer 16 may have defects during deposition, the CrSi thin film layer 16 can be subjected to high-temperature annealing treatment to repair the defects of the CrSi thin film layer 16 and improve the resistance quality of the CrSi thin film layer 16. During high-temperature annealing, although the CrSi thin film layer 16 is subjected to high temperature, since the SiON film layer 17 is covered above the CrSi thin film layer 16, the SiON film layer 17 can prevent the diffusion of Cr atoms in the CrSi thin film layer 16 to the outside, thereby reducing the risk of heavy metal pollution.

[0061] Optionally, different types of CrSi thin film resistors have different resistance pattern requirements for the CrSi thin film layer 16. After high-temperature annealing treatment of the CrSi thin film layer 16, the SiON film layer 17 and the CrSi thin film layer 16 can be etched into a resistance pattern by dry etching. For example, when the resistance pattern is a long strip pattern, the SiON film layer 17 and the CrSi thin film layer 16 are etched into a long strip pattern by dry etching, that is, the SiON film layer 17 and the CrSi thin film layer 16 remaining on the wafer are in a long strip pattern. Figure 7 is a structural schematic diagram of etching the SiON film layer 17 and the CrSi thin film layer 16 of the wafer into a resistance pattern provided by the embodiment of the present application. As shown in Figure 7 , the two ends of the SiON film layer 17 and the CrSi thin film layer 16 are etched away, and the remaining middle part forms a resistance pattern corresponding to the CrSi thin film resistor.

[0062] In this embodiment, when etching the SiON film layer 17 and the CrSi thin film layer 16 into a resistance pattern, a layer of photoresist can be coated on the SiON film layer 17; the photoresist on the SiON film layer 17 is developed based on a resistance pattern mask to expose part of the SiON film layer 17; and the exposed SiON film layer 17 and the corresponding underlying CrSi thin film layer 16 are etched by a plasma etching process, so that the remaining SiON film layer 17 and CrSi thin film layer 16 form a resistance pattern. For example, a layer of photoresist is coated on the upper surface of the wafer, that is, the upper surface of the SiON film layer 17, and the photoresist on the SiON film layer 17 is exposed through a pre-set resistance pattern mask, so that the exposed photoresist is eliminated to expose the corresponding underlying SiON film layer 17, at this time, part of the exposed SiON film layer 17 does not belong to the resistance part. The exposed SiON film layer 17 and the corresponding underlying CrSi thin film layer 16 are etched by a plasma etching process, and the SiON film layer 17 and the CrSi thin film layer 16 corresponding to the resistance pattern are retained. Finally, the remaining photoresist on the SiON film layer 17 is removed.

[0063] It should be noted that when etching the SiON film layer 17 and the CrSi thin film layer 16 into a resistance pattern, dry etching is used, and the problem of contamination of the etching liquid and the container by Cr atoms in the CrSi thin film layer 16 caused by contact between the CrSi thin film layer 16 and the etching liquid in wet etching does not occur, effectively reducing the risk of heavy metal pollution.

[0064] S140, a metal electrode contact hole 18 is etched on the SiON film layer 17 and the CrSi thin film layer 16 by dry etching.

[0065] For example, the dry etching is used to etch the metal electrode contact hole 18 on the SiON film layer 17 and the CrSi thin film layer 16 forming the resistance pattern. When etching the CrSi thin film layer 16, only the upper half of the corresponding etching area is etched without being etched completely, that is, the NCD film layer under the corresponding etching area of the CrSi thin film layer 16 is not exposed. Figure 8 is a structural schematic diagram of etching the metal electrode contact hole 18 of the wafer provided by the embodiment of the present application. As shown in Figure 8 , the SiON film layer 17 and the CrSi thin film layer 16 form two metal electrode contact holes 18 therebetween, the bottom of the metal electrode contact hole 18 contacts the CrSi thin film layer 16, and the TIN material can be deposited in the metal electrode contact hole 18 to form a metal electrode subsequently.

[0066] It should be noted that when the dry etching is performed on the CrSi thin film layer 16, the CrSi thin film layer 16 does not contact the etching liquid used in the wet etching, so that the problem of the Cr atoms in the CrSi thin film layer 16 contaminating the etching liquid and the container does not occur, and the risk of heavy metal pollution is effectively reduced.

[0067] Optionally, when the metal electrode contact hole 18 is etched on the SiON film layer 17 and the CrSi thin film layer 16, a layer of photoresist can be coated on the SiON film layer 17; the photoresist on the SiON film layer 17 is developed based on the contact hole pattern mask to expose part of the SiON film layer 17; and the exposed SiON film layer 17 and the corresponding CrSi thin film layer 16 therebelow are etched by using the plasma etching process to form the metal electrode contact hole 18 on the SiON film layer 17 and the CrSi thin film layer 16. For example, referring to Figure 7 , a layer of photoresist is coated on the upper surface of the wafer, that is, the upper surface of the SiON film layer 17 and the upper surface of the second layer of NDC film layer 13 exposed on both sides, and the photoresist on the upper surface of the wafer is exposed by using a preset contact hole pattern mask, so that the exposed photoresist is eliminated to expose the corresponding SiON film layer 17 therebelow, at this time, the area of the exposed SiON film layer 17 is the area of the SiON film layer 17 to be etched to form the metal electrode contact hole 18. The exposed SiON film layer 17 and the corresponding CrSi thin film layer 16 therebelow are etched by using the plasma etching process, so that the etched area forms the metal electrode contact hole 18. Finally, the photoresist remaining on the SiON film layer 17 and the second layer of NDC film layer 13 is removed.

[0068] S150, depositing a TIN film layer 19 on the front surface of the wafer, the TIN film layer 19 covering the SiON film layer 17, the CrSi thin film layer 16 and the metal electrode contact hole 18.

[0069] Exemplarily, a TIN (Titanium Nitride) material is deposited on the front side, i.e. the upper surface, of the wafer to form a TIN film layer 19. Figure 9 is a structural diagram of the wafer provided by the embodiment of the present application, in which the TIN film layer 19 is deposited on the wafer. Figure 9 As shown, the TIN film layer 19 covers the SiON film layer 17, the CrSi thin film layer 16 and the metal electrode contact hole 18.

[0070] S160, the TIN film layer 19 is etched into a metal electrode by dry etching.

[0071] Exemplarily, the TIN film layer 19 deposited on the SiON film layer 17, the CrSi thin film layer 16 and the metal electrode contact hole 18 is etched into a metal electrode by a dry etching process. When the TIN film layer 19 is etched, the TIN material at both ends of the CrSi thin film layer 16 is reserved to wrap the sidewalls of both ends of the CrSi thin film layer 16 in the finally formed metal electrode, so that the sidewalls of both ends of the CrSi thin film layer 16 are not exposed to the air, avoiding the diffusion of Cr atoms in the CrSi thin film layer 16 into the air to pollute the machines and devices involved in subsequent processes. Figure 10 is a structural diagram of the wafer provided by the embodiment of the present application, in which the TIN film layer 19 is deposited on the wafer. Figure 10 As shown, the TIN film layer 19 is etched in the middle and at both ends, corresponding to the exposure of the underlying SiON film layer 17 and the second layer NDC film layer 13, and the remaining TIN film layer 19 forms a metal electrode, which wraps both ends of the CrSi thin film layer 16 to avoid the exposure of the sidewalls of both ends of the CrSi thin film layer 16 to the air.

[0072] It should be noted that, since the TIN film layer 19 is dry etched, the dry etching can accurately etch both ends of the TIN film layer 19, so that the remaining TIN material wraps the sidewalls of both ends of the CrSi thin film layer 16, and the TIN film layer 19 does not have the side digging phenomenon as in wet etching, thus avoiding the exposure of the sidewalls of both ends of the CrSi thin film layer 16, effectively reducing the risk of heavy metal pollution.

[0073] Optionally, a photoresist is coated on the TIN film layer 19 when etching the TIN film layer 19; the photoresist on the TIN film layer 19 is developed based on the metal electrode pattern mask to expose part of the TIN film layer 19; the exposed TIN film layer 19 is etched by the plasma etching process, so that the remaining TIN film layer 19 forms the metal electrode. For example, a photoresist is coated on the upper surface of the wafer, i.e., the upper surface of the TIN film layer 19, and the photoresist on the upper surface of the TIN film layer 19 is exposed by the preset metal electrode pattern mask, so that the exposed photoresist is removed to expose the corresponding underlying TIN film layer 19, at this time, the exposed part of the TIN film layer 19 does not belong to the metal electrode part. The exposed TIN film layer 19 is etched by the plasma etching process, so that the remaining TIN film layer 19 forms the metal electrode, and finally the remaining photoresist on the TIN film layer 19 is removed.

[0074] It should be noted that in order to ensure that the metal electrode can wrap the two ends of the CrSi thin film layer 16, the photoresist on the two sides of the outer wall of the CrSi thin film layer 16 is reserved after the photoresist is exposed, so as to protect the corresponding underlying TIN material from being etched away through the photoresist, thereby successfully reserving the TIN material that can wrap the two ends of the CrSi thin film layer 16.

[0075] Further, after the TIN film layer 19 is etched into a metal electrode, the NDC film layer 13 is deposited on the front surface of the wafer, at this time, the deposited NDC film layer 13 can be regarded as the third layer NDC film layer 13 on the wafer. Figure 11 is a structure diagram of the wafer provided by the embodiment of the present application for depositing the third layer NDC film layer 13. As shown in Figure 11 The third layer NDC film layer 13 covers the metal electrode and contacts the second layer NDC film layer 13 exposed at both ends, and the third layer NDC film layer 13 and the second layer NDC film layer 13 can completely wrap the metal electrode.

[0076] Then, the SiCOH material is deposited on the third layer NDC film layer 13 to form the BD film layer 14, and the BD film layer 14 above the third layer NDC film layer 13 can be regarded as the second layer BD film layer 14. The contact hole is etched on the second layer BD film layer 14 and the third layer NDC film layer 13, the bottom of the contact hole contacts the TIN film layer 19, and the copper material is deposited in the contact hole to form the metal via 20. The second metal layer 21 pattern is etched on both sides of the second layer BD film layer 14, and the copper material is deposited in the second metal layer 21 pattern etched on the second layer BD film layer 14 to form the second metal layer 21, and the preparation of the CrSi thin film resistor is completed. Figure 12 is a structure diagram of the CrSi thin film resistor provided by the embodiment of the present application. As shown in Figure 12As shown, the second layer BD film layer 14 is formed above the third layer NDC film layer 13, the metal through hole 20 is formed between the second layer BD film layer 14 and the third layer NDC film layer 13, and the metal through hole 20 connects the TIN film layer 19 below the third layer NDC film layer 13 and the second metal layer 21 above the second layer BD film layer 14.

[0077] On the basis of the above-mentioned embodiments, the application further provides a resistor device preparation method and a resistor device prepared by the resistor device preparation method. The resistor device preparation method comprises the CrSi thin film resistor preparation method described in the above-mentioned embodiments. In the process of preparing the resistor device, the CrSi thin film resistor preparation method provided in the above-mentioned embodiments is used to deposit the SiON film layer 17 on the upper surface of the CrSi thin film layer 16, so that the Cr atoms in the CrSi thin film layer 16 diffuse outward through the SiON film layer 17 when the CrSi thin film layer 16 is subjected to high-temperature annealing, thereby reducing the risk of heavy metal pollution. The CrSi thin film layer 16 is etched by dry etching, thereby avoiding the problem of Cr atom pollution in the etching liquid in the CrSi thin film layer 16. The TIN film layer 19 is etched by dry etching, thereby avoiding the problem of TIN side etching, which causes the two ends of the CrSi thin film layer 16 to be exposed, further reducing the risk of heavy metal pollution and improving the production efficiency and safety of the resistor device.

[0078] The above-mentioned are only the preferred embodiments of the application and the technical principles applied. The application is not limited to the specific embodiments herein, and various obvious changes, re-adjustments and replacements made by those skilled in the art will not deviate from the protection scope of the application. Therefore, although the application is described in more detail through the above-mentioned embodiments, the application is not limited to the above-mentioned embodiments, and more other equivalent embodiments can be included without deviating from the concept of the application, and the scope of the application is determined by the scope of the claims.

Claims

1. A method for preparing a CrSi thin film resistor, characterized by, Comprising: depositing a CrSi thin film layer on a NDC film layer of a wafer; wherein the NDC film layer is deposited by a nitrogen-doped silicon carbide material; depositing a SiON film layer above the CrSi thin film layer, the SiON film layer covering the CrSi thin film layer; performing high-temperature annealing treatment on the CrSi thin film layer; etching a metal electrode contact hole on the SiON film layer and the CrSi thin film layer by dry etching; depositing a TIN film layer on a front surface of the wafer, the TIN film layer covering the SiON film layer, the CrSi thin film layer and the metal electrode contact hole; wherein the TIN film layer is deposited by a titanium nitride material; etching the TIN film layer into a metal electrode by dry etching.

2. The method for preparing CrSi thin film resistors according to claim 1, characterized in that, The depositing a CrSi thin film layer on a NDC film layer of a wafer comprises: depositing a CrSi thin film layer on a NDC film layer of a wafer by physical vapor deposition process.

3. The method of claim 1, wherein the CrSi thin film resistor is prepared by a process comprising: After the high-temperature annealing, further comprising: etching the SiON film layer and the CrSi thin film layer into a resistance pattern by dry etching.

4. The method of claim 3, wherein the CrSi thin film resistor is prepared by the steps of: The etching the SiON film layer and the CrSi thin film layer into a resistance pattern by dry etching comprises: coating a layer of photoresist above the SiON film layer; developing the photoresist above the SiON film layer based on a resistance pattern mask to expose part of the SiON film layer; etching the exposed SiON film layer and the corresponding CrSi thin film layer below by plasma etching process, so that the remaining SiON film layer and CrSi thin film layer form a resistance pattern.

5. The method of claim 1, wherein the CrSi thin film resistor is prepared by a process comprising: The etching a metal electrode contact hole on the SiON film layer and the CrSi thin film layer by dry etching comprises: coating a layer of photoresist above the SiON film layer; developing the photoresist above the SiON film layer based on a contact hole pattern mask to expose part of the SiON film layer; etching the exposed SiON film layer and the corresponding CrSi thin film layer below by plasma etching process, so that a metal electrode contact hole is formed on the SiON film layer and the CrSi thin film layer.

6. The method of claim 1, wherein the CrSi thin film resistor is prepared by a process comprising: The etching the TIN film layer into a metal electrode by dry etching comprises: coating a layer of photoresist above the TIN film layer; developing the photoresist above the TIN film layer based on a metal electrode pattern mask to expose part of the TIN film layer; etching the exposed TIN film layer by plasma etching process, so that the remaining TIN film layer forms a metal electrode.

7. The method of claim 1, wherein the CrSi thin film resistor is prepared by a process comprising: The metal electrode wraps two ends of the CrSi thin film layer.

8. The method for preparing CrSi thin film resistors according to claim 6, characterized in that, After the etching the TIN film layer into a metal electrode by dry etching, further comprising: depositing a NDC film layer on a front surface of the wafer.

9. A method of manufacturing a resistive device, characterized by, A CrSi thin film resistance preparation method as claimed in any one of claims 1-8.

10. A resistive device, characterized by, Prepared by a resistor preparation method as claimed in claim 9.

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