Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device is provided with: a gate trench (22) formed in an active region (50); a gate insulating film (10) and a gate electrode layer (11) formed in the gate trench (22); a gate wiring electrode (15) formed on an interlayer insulating film (13) covering the gate electrode layer (11); and an external trench (6) formed in the drift layer (2) in the termination region (60). A potential fixing layer (8) covering an upper end corner portion (6a) of the external trench (6) and an insulating layer (9) formed on the potential fixing layer (8) are formed in the external trench (6). The gate insulating film (10) and the gate electrode layer (11) extend into the external trench (6), and the gate electrode layer (11) is connected to the gate wiring electrode (15) through a contact hole formed in the interlayer insulating film (13) in the external trench (6).

Description

Technical Field

[0001] The present disclosure relates to a trench gate semiconductor device and a method for manufacturing the same, and in particular to a structure of a gate electrode on the outer periphery of a semiconductor device. Background Art

[0002] Semiconductor devices such as insulated gate bipolar transistors (IGBT: Insulated Gate Bipolar Transistor) and insulated gate field effect transistors (MOSFET: Metal Oxide Semiconductor Field Effect Transistor) having a trench gate structure are used for power control applications in vehicle-mounted equipment, industrial equipment, and the like.

[0003] In a semiconductor device having a trench gate structure, a "gate lead" is provided so that a trench in which a gate electrode is buried (hereinafter referred to as a "gate trench") extends from an active region where a main current flows to a terminal region outside the active region. When the semiconductor device is turned on, although the drain voltage is low, the electric field generated in the gate insulating film becomes high because a voltage is applied to the gate electrode, and the electric field is particularly likely to be concentrated at the upper corner of the gate trench.

[0004] Patent Document 1 below discloses a technique in which a gate insulating film is formed in a gate trench of a gate lead portion so as to be in contact with a thick field insulating film formed by LOCOS (Local Oxidation of Silicon) oxidation, thereby reducing electric field concentration at the upper corner of the gate trench.

[0005] In addition, Patent Document 2 listed below discloses a technique in which a field plate electrode is provided in a gate trench of a gate lead portion together with a gate electrode, and the potential of the field plate electrode is set to a gate potential or a source potential.

[0006] Patent Document 1: Japanese Patent Application Publication No. 2001-102572

[0007] Patent Document 2: Japanese Patent Application Publication No. 2011-199109 Summary of the invention

[0008] Problem that the invention aims to solve

[0009] Even if a field insulating film is used to improve the withstand voltage of the gate insulating film in the gate lead portion as in Patent Document 1, for example, when the upper corner of the gate trench has an eave-shaped portion that deviates from a right angle, the field insulating film is locally thin and therefore the effect of improving the withstand voltage of the gate insulating film cannot be fully obtained.

[0010] In the gate lead-out portion disclosed in Patent Document 2, when the potential of the field plate electrode is set to the gate potential, if the thickness of the gate insulating film is not thick enough, the gate insulating film may be destroyed at the upper corner of the gate trench. On the other hand, when the potential of the field plate electrode is set to the source potential, a gate-source leakage current may be generated through the insulating film between the gate electrode and the field plate electrode. In addition, depending on the shape of the field plate electrode, a portion where the gate insulating film formed on the field plate electrode is thin may be formed locally, causing destruction of the gate insulating film.

[0011] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to provide a semiconductor device capable of preventing the gate insulating film at the upper corner of the gate trench of the gate lead portion from being destroyed.

[0012] Solutions for solving problems

[0013] The semiconductor device involved in the present disclosure includes: a drift layer of a first conductivity type; a well region of a second conductivity type formed in a surface portion of the drift layer; an impurity region of the first conductivity type formed in a surface portion of the well region; a gate trench formed in a manner penetrating the impurity region and the well region in an active region and reaching the drift layer; a gate insulating film formed in a manner contacting an inner surface of the gate trench; a gate electrode layer formed on the gate insulating film; an interlayer insulating film covering the gate electrode layer; a gate wiring electrode formed on the interlayer insulating film and connected to the gate electrode layer; an outer trench formed in the drift layer at a terminal region outside the active region; a potential fixing layer formed in the outer trench and covering an upper corner portion of the outer trench; and an insulating layer formed on the potential fixing layer, the gate insulating film and the gate electrode layer extending into the outer trench in the terminal region, the gate electrode layer being connected to the gate wiring electrode via a contact hole formed in the interlayer insulating film in the outer trench.

[0014] Effects of the Invention

[0015] According to the present disclosure, the upper corner of the outer trench is covered by the potential fixing layer and the insulating layer, so the gate electrode and the gate insulating film led out to the outer trench are formed on the insulating layer and isolated from the upper corner of the outer trench. Therefore, the gate insulating film is prevented from being destroyed due to the electric field concentration caused by the shape of the upper corner of the outer trench.

[0016] The objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1It is a schematic plan view showing a schematic structure of a semiconductor device according to the first embodiment.

[0018] Figure 2 This is a schematic diagram showing a schematic structure of a boundary portion between an active region 50 and a termination region 60 in the semiconductor device according to the first embodiment.

[0019] Figure 3 It means that along the Figure 2 A schematic cross-sectional view of the schematic structure of the semiconductor device along the A1-A2 line.

[0020] Figure 4 It means that along the Figure 2 A schematic cross-sectional view of the schematic structure of the semiconductor device along the line B1-B2.

[0021] Figure 5 It means that along the Figure 2 A schematic cross-sectional view of the schematic structure of the semiconductor device along the line C1-C2.

[0022] Figure 6 It means that along the Figure 2 A cross-sectional schematic diagram of the schematic structure of the semiconductor device along the D1-D2 line.

[0023] Figure 7 It means that along the Figure 2 A partial cross-sectional view of the semiconductor device manufacturing method taken along line B1-B2.

[0024] Figure 8 It means that along the Figure 2 A partial cross-sectional view of the semiconductor device manufacturing method taken along line B1-B2.

[0025] Fig. 9 It means that along the Figure 2 A partial cross-sectional view of the semiconductor device manufacturing method taken along line B1-B2.

[0026] Fig.10 It means that along the Figure 2 A partial cross-sectional view of the semiconductor device manufacturing method taken along line B1-B2.

[0027] Fig.11 It means that along the Figure 2 A partial cross-sectional view of the semiconductor device manufacturing method taken along line B1-B2.

[0028] Fig.12 It means that along the Figure 2A partial cross-sectional view of the semiconductor device manufacturing method taken along line B1-B2.

[0029] Fig.13 It means that along the Figure 2 A partial cross-sectional view of the D1-D2 line of the semiconductor device manufacturing method.

[0030] Fig.14 It means that along the Figure 2 A partial cross-sectional view of the D1-D2 line of the semiconductor device manufacturing method.

[0031] Fig.15 It means that along the Figure 2 A partial cross-sectional view of the D1-D2 line of the semiconductor device manufacturing method.

[0032] Fig.16 It means that along the Figure 2 A partial cross-sectional view of the D1-D2 line of the semiconductor device manufacturing method.

[0033] Fig.17 It means that along the Figure 2 A partial cross-sectional view of the D1-D2 line of the semiconductor device manufacturing method.

[0034] Fig.18 It means that along the Figure 2 A partial cross-sectional view of the D1-D2 line of the semiconductor device manufacturing method.

[0035] Fig.19 It means that along the Figure 2 A partial cross-sectional view of the D1-D2 line of the semiconductor device manufacturing method.

[0036] Fig. 20 It means that along the Figure 2 A partial cross-sectional view of the D1-D2 line of the semiconductor device manufacturing method.

[0037] Fig.21 It means that along the Figure 2 A partial cross-sectional view of the D1-D2 line of the semiconductor device manufacturing method.

[0038] Fig. 22 It means that along the Figure 2 A schematic cross-sectional view of the schematic structure of the semiconductor device along the line B1-B2.

[0039] Fig.23 It means that along the Figure 2A schematic cross-sectional view of the schematic structure of the semiconductor device along the line C1-C2.

[0040] Fig.24 It means that along the Figure 2 A partial cross-sectional view of the semiconductor device manufacturing method taken along line B1-B2.

[0041] Fig.25 It means that along the Figure 2 A partial cross-sectional view of the semiconductor device manufacturing method taken along line B1-B2.

[0042] Fig.26 It means that along the Figure 2 A partial cross-sectional view of the semiconductor device manufacturing method taken along line B1-B2.

[0043] Fig. 27 It means that along the Figure 2 A partial cross-sectional view of the semiconductor device manufacturing method taken along line B1-B2.

[0044] Fig.28 It means that along the Figure 2 A partial cross-sectional view of the semiconductor device manufacturing method taken along line B1-B2.

[0045] Fig.29 It means that along the Figure 2 A partial cross-sectional view of the semiconductor device manufacturing method taken along line B1-B2.

[0046] Fig.30 It means that along the Figure 2 A partial cross-sectional view of the semiconductor device manufacturing method taken along line B1-B2.

[0047] Fig.31 It means that along the Figure 2 A partial cross-sectional view of the method for manufacturing a semiconductor device along line C1-C2.

[0048] Fig.32 It means that along the Figure 2 A partial cross-sectional view of the method for manufacturing a semiconductor device along line C1-C2.

[0049] Fig.33 It means that along the Figure 2 A partial cross-sectional view of the method for manufacturing a semiconductor device along line C1-C2.

[0050] Fig.34 It means that along the Figure 2A partial cross-sectional view of the method for manufacturing a semiconductor device along line C1-C2.

[0051] Fig.35 It means that along the Figure 2 A partial cross-sectional view of the method for manufacturing a semiconductor device along line C1-C2.

[0052] Fig.36 It means that along the Figure 2 A partial cross-sectional view of the method for manufacturing a semiconductor device along line C1-C2.

[0053] Fig.37 It means that along the Figure 2 A partial cross-sectional view of the method for manufacturing a semiconductor device along line C1-C2.

[0054] Fig.38 It is a schematic plan view showing a schematic structure of a semiconductor device according to a third embodiment.

[0055] Fig.39 This is a schematic diagram showing a schematic structure of a semiconductor device according to a third embodiment.

[0056] Fig.40 It means that along the Fig.39 A cross-sectional schematic diagram of the schematic structure of the semiconductor device along the D1-D2 line.

[0057] Fig.41 This is a schematic diagram showing a schematic structure of a semiconductor device according to a fourth embodiment.

[0058] Fig.42 It means that along the Fig.41 A cross-sectional schematic diagram of the schematic structure of the semiconductor device along the D1-D2 line.

[0059] Fig.43 It means that along the Figure 2 A cross-sectional schematic diagram of the schematic structure of the semiconductor device along the D1-D2 line.

[0060] Fig.44 It means that along the Fig.39 A cross-sectional schematic diagram of the schematic structure of the semiconductor device along the D1-D2 line.

[0061] Fig.45 It means that along the Fig.41 A cross-sectional schematic diagram of the schematic structure of the semiconductor device along the D1-D2 line.

[0062] Fig.46 It means that along the Figure 2, Fig.39 or Fig.41 A schematic cross-sectional view of the schematic structure of the semiconductor device along the line B1-B2.

[0063] Fig.47 It means that along the Figure 2 A cross-sectional schematic diagram of the schematic structure of the semiconductor device along the D1-D2 line.

[0064] Fig.48 It means that along the Fig.39 A cross-sectional schematic diagram of the schematic structure of the semiconductor device along the D1-D2 line.

[0065] Fig.49 It means that along the Fig.41 A cross-sectional schematic diagram of the schematic structure of the semiconductor device along the D1-D2 line. DETAILED DESCRIPTION

[0066] Hereinafter, the embodiments of the technology involved in the present disclosure will be described with reference to the drawings. The drawings are schematically shown, and the relationship between the sizes and positions of the images shown in different drawings may not be accurately recorded and may be changed appropriately. In addition, the same symbols are attached to the same structural elements for illustration, and their names and functions are also the same. Therefore, their detailed description is sometimes omitted.

[0067] In the description, terms such as "upper", "lower", "side", "bottom", "front" or "back" are sometimes used to indicate specific positions and directions. These terms are used to facilitate understanding of the implementation methods and have nothing to do with the position and direction in actual use.

[0068] Unless there is any contradiction, a structural element described as including "one" may include "more than one". In addition, a structural element is a conceptual unit, and one structural element may be composed of a plurality of structures or one structural element may correspond to a part of a certain structure.

[0069] In the following embodiments, the first conductivity type of the semiconductor is set to n-type and the second conductivity type is set to p-type for description, but conversely, the first conductivity type may be set to p-type and the second conductivity type may be set to n-type. In addition, MOSFET is described as an example of a semiconductor device, but the semiconductor device may also be an IGBT. In addition, the materials of the semiconductor substrate and the drift layer are described as silicon carbide (SiC), which is a wide bandgap semiconductor with a larger bandgap than silicon, but they may be silicon, other wide bandgap semiconductors such as gallium nitride and diamond, or a combination thereof.

[0070] In the following description, “impurity concentration” refers to the peak value of the impurity concentration in each region.

[0071] <Implementation Method 1>

[0072] Figure 1 It is a schematic plan view showing a schematic structure of a semiconductor device according to the first embodiment. Figure 2 is a schematic diagram showing a schematic structure of a boundary portion between an active region 50 and a termination region 60 in a semiconductor device according to Embodiment 1, showing Figure 1 The portion of the area 40 surrounded by the dotted line. Figure 2 In order to simplify the description, the interlayer insulating film 13, the surface electrode 14, the surface ohmic electrode 19, etc. are omitted. Figures 3 to 6 is a schematic diagram showing a cross-sectional structure of a semiconductor device according to Embodiment 1, Figure 3 Indicates along Figure 2 A1-A2 line cross-sectional view, Figure 4 Indicates along Figure 2 The cross-sectional view of the B1-B2 line, Figure 5 Indicates along Figure 2 The cross-sectional view of the C1-C2 line, Figure 6 Indicates along Figure 2 Cross-sectional view of line D1-D2.

[0073] The active region 50 is a region where a current flows by forming a channel in the on state of the semiconductor device, and the terminal region 60 is a region surrounding the active region 50. The terminal region 60 is provided at the periphery of the chip of the semiconductor device so as to surround the active region 50, and a p-type terminal electric field relaxation region 18 such as an FLR (Field Limiting Ring) and an n-type channel blocking region 31 for suppressing the extension of the depletion layer to the end of the chip are formed in the terminal region 60.

[0074] A gate trench 22 is provided in the drift layer 2 of the active region 50, and an external trench 6 corresponding to the gate trench of the gate lead portion is provided in the drift layer 2 of the terminal region 60. Figure 2 In this way, the gate trench 22 is formed in a stripe shape in a plan view. A plurality of regions divided by the gate trench 22 in the active region 50 form cells. Figure 2 , an example is shown in which a plurality of quadrilateral units are arranged in strips, but the shape of the unit may be a polygonal shape such as a circular shape or a hexagonal shape, and the unit may be arranged in a checkerboard shape, a staggered grid shape, or the like.

[0075] like Figures 3 to 6As shown, a drift layer 2, a well region 3, an impurity region 4, a contact region 5, etc. are provided on the surface side of a semiconductor substrate 1 constituting a semiconductor device. A gate trench 22, a trench bottom electric field relaxation region 16, a gate insulating film 10, and a gate electrode layer 11 are provided in an active region 50. An external trench 6, a trench bottom electric field relaxation region 16, a trench bottom high concentration well region 17, a terminal electric field relaxation region 18, a bottom insulating film 7, a potential fixing layer 8, an insulating layer 9, a gate insulating film 10, a gate electrode layer 11, a field insulating film 12, and a gate wiring electrode 15 are provided in a terminal region 60. The gate electrode layer 11 formed in the external trench 6 of the terminal region 60 extends in a manner surrounding the gate trench 22 in a plan view. On the surface of the semiconductor substrate 1, a surface ohmic electrode 19, an interlayer insulating film 13, and a surface electrode 14 are provided in a manner common to the active region 50 and the terminal region 60. On the back surface of the semiconductor substrate 1 , a back surface ohmic electrode 20 and a back surface electrode 21 are provided in common to the active region 50 and the termination region 60 .

[0076] The drift layer 2 is provided on the semiconductor substrate 1 composed of n-type silicon carbide and is composed of n-type silicon carbide. The n-type impurity of the drift layer 2 may be nitrogen or phosphorus, and the impurity concentration of the drift layer 2 is 1×10 14 cm -3 Above and 1×10 18 cm -3 The thickness of the drift layer 2 may be about 5 μm or more and 300 μm or less.

[0077] The well region 3 is a p-type region provided in the surface portion of the drift layer 2 and is composed of silicon carbide. The p-type impurity of the well region 3 may be aluminum, boron or gallium, and the impurity concentration of the well region 3 is 1×10 15 cm -3 Above and 1×10 20 cm -3 Here, the impurity concentration of the well region 3 may be constant or not constant in the depth direction. The thickness of the well region 3 may be about 0.3 μm or more and 3 μm or less.

[0078] The impurity region 4 is an n-type region provided in the surface layer of the well region 3 and is composed of silicon carbide. The n-type impurity of the impurity region 4 may be nitrogen or phosphorus, and the impurity concentration of the impurity region 4 is 1×10 17 cm -3 Above and 1×10 22 cm -3 The thickness of the impurity region 4 may be less than or equal to the thickness of the well region 3 .

[0079] The contact region 5 is provided at the surface of the well region 3 and is a p-type region having a higher impurity concentration than the well region 3 and is composed of silicon carbide. The p-type impurity of the contact region 5 may be aluminum, boron or gallium, and the impurity concentration of the contact region 5 is 1×10 18 cm -3 Above and 1×10 22 cm -3 The thickness of the contact region 5 may be less than or equal to the thickness of the well region 3 .

[0080] A contact hole 25 (hereinafter referred to as "source contact hole 25") reaching the impurity region 4 and the contact region 5 is formed in the interlayer insulating film 13, and a surface ohmic electrode 19 connected to the impurity region 4 and the contact region 5 is formed at the bottom of the source contact hole 25. The impurity region 4 and the contact region 5 are electrically connected to the surface electrode 14 as the main electrode through the surface ohmic electrode 19 in the source contact hole 25.

[0081] Here, the contact region 5 is connected to the impurity region 4 through the surface ohmic electrode 19. When the contact region 5 is formed, a path is formed from the well region 3 to the surface ohmic electrode 19 via the contact region 5, and the electrical connection from the well region 3 to the surface ohmic electrode 19 becomes good. The contact region 5 may also be omitted.

[0082] The gate trench 22 penetrates the well region 3 from the surface of the impurity region 4 and reaches the drift layer 2. The gate trench 22 is as shown in FIG. Figure 2 As shown in FIG. 1 , the gate trench 22 is arranged in a strip shape (that is, a plurality of parallel lines) in the active region 50. If the gate trench 22 is arranged in a strip shape, when the semiconductor device is a trench-gate silicon carbide MOSFET, a surface such as a (1-100) surface with high channel mobility can be used as a channel, and the characteristics of the semiconductor device can be improved. In addition, the gate trench 22 extends in the direction of the terminal region 60. Hereinafter, the direction in which the gate trench 22 extends is referred to as the "extension direction" of the gate trench 22.

[0083] The width of the gate trench 22 may be, for example, about 0.5 μm or more and about 10 μm or less. When the shape of the gate trench 22 is tapered in a cross-sectional view, the width of the gate trench 22 refers to the width of the widest part of the tapered shape. The depth of the gate trench 22 may be, for example, about 0.5 μm or more and about 6 μm or less.

[0084] The trench bottom electric field relaxation region 16 is a p-type region provided below the bottom surface of the gate trench 22 and is composed of silicon carbide. The trench bottom electric field relaxation region 16 has a conductivity type opposite to that of the drift layer 2, and functions to relax the electric field applied to the gate insulating film 10 formed on the bottom surface of the gate trench 22 in the operating state of the semiconductor device, thereby preventing the gate insulating film 10 from being damaged. The depth of the trench bottom electric field relaxation region 16 is about 0.1 μm or more and 3.0 μm or less from the bottom surface of the gate trench 22 downward. The trench bottom electric field relaxation region 16 may also be in contact with the bottom surface of the gate trench 22. The p-type impurity of the trench bottom electric field relaxation region 16 may be aluminum, boron or gallium, and the impurity concentration of the trench bottom electric field relaxation region 16 is 1×10 15 cm -3 Above and 1×10 19 cm -3 The following will do.

[0085] The outer trench 6 is a wide trench formed in the termination region 60 to a depth substantially equal to that of the gate trench 22. A trench bottom electric field alleviation region 16 is also provided below the outer trench 6.

[0086] The trench bottom high concentration well region 17 has a conductivity type opposite to that of the drift layer 2, and is provided in the trench bottom electric field relaxation region 16 below the outer trench 6. The trench bottom high concentration well region 17 is a region of p-type with a higher concentration than the trench bottom electric field relaxation region 16, and is composed of silicon carbide. A contact hole 26 (hereinafter referred to as "peripheral well region contact hole 26") reaching the trench bottom high concentration well region 17 is formed in the interlayer insulating film 13, and a surface ohmic electrode 19 connected to the trench bottom high concentration well region 17 is formed at the bottom of the peripheral well region contact hole 26. The trench bottom electric field relaxation region 16 is electrically connected to the surface electrode 14 through the trench bottom high concentration well region 17 and the surface ohmic electrode 19 in the peripheral well region contact hole 26.

[0087] The trench bottom surface high concentration well region 17 has the effect of reducing the contact resistance between the trench bottom surface electric field relaxation region 16 and the surface ohmic electrode 19 and the effect of reducing the surface sheet resistance of the trench bottom surface electric field relaxation region 16. The depth of the trench bottom surface high concentration well region 17 can be about 0.1 μm or more and 2.0 μm or less from the bottom surface of the external trench 6 downward. The trench bottom surface high concentration well region 17 can also be in contact with the bottom surface of the external trench 6. The p-type impurity of the trench bottom surface high concentration well region 17 can be aluminum, boron or gallium, and the impurity concentration of the trench bottom surface high concentration well region 17 is 1×10 18 cm -3 Above and 1×10 22 cm -3The following will do.

[0088] The terminal electric field relaxation region 18 is a p-type electric field relaxation region formed continuously or intermittently in a manner surrounding the active region 50, such as an FLR (Field Limiting Ring). The terminal electric field relaxation region 18 is formed by, for example, ion implantation of aluminum, boron, gallium, etc. to a depth of about 0.2 μm to 3 μm from the surface of the drift layer 2 and not exceeding the depth of the drift layer 2. The p-type impurity concentration of the terminal electric field relaxation region 18 exceeds the impurity concentration of the drift layer 2 and is 1×10 15 cm -3 Above and 1×10 19 cm -3 The following will do.

[0089] The field insulating film 12 is formed to be in contact with the surface of the drift layer 2 from the inside of the outer trench 6 to the chip end. The field insulating film 12 can be made of an insulating material such as silicon dioxide. The thickness of the field insulating film 12 can be set to, for example, 0.1 μm to 5.0 μm.

[0090] The bottom insulating film 7 is formed in a manner covering the inside of the outer trench 6 and the upper corner 6a of the outer trench 6 (hereinafter referred to as "the upper corner 6a of the outer trench"), and is in contact with the well region 3, the drift layer 2, the trench bottom electric field relaxation region 16, and the trench bottom high concentration well region 17. A portion of the bottom insulating film 7 is also formed on the field insulating film 12. The bottom insulating film 7 is made of an insulating material such as silicon dioxide. The thickness of the bottom insulating film 7 is, for example, about 10 nm or more and about 1000 nm or less.

[0091] The potential fixing layer 8 is a conductive layer such as polysilicon, which is formed on the bottom insulating film 7 and covers the inner part of the outer groove 6 and the upper corner 6a of the outer groove through the bottom insulating film 7. A part of the potential fixing layer 8 is also formed on the field insulating film 12. In the present embodiment, the potential fixing layer 8 is a first polysilicon layer composed of polysilicon. A contact hole 27 (hereinafter referred to as "the potential fixing layer connection contact hole 27") is formed in the interlayer insulating film 13 to reach the potential fixing layer 8 on the field insulating film 12, and the potential fixing layer 8 is connected to the surface electrode 14 through the potential fixing layer connection contact hole 27. The potential of the surface electrode 14 becomes the source potential, so the potential of the potential fixing layer 8 also becomes the source potential. The potential fixing layer 8 has a thickness exceeding that of the gate insulating film 10, and preferably has a thickness exceeding 3 times that of the gate insulating film 10.

[0092] The insulating layer 9 is formed so as to cover the potential fixing layer 8. The insulating layer 9 suppresses the gate leakage current flowing between the potential fixing layer 8 and the gate electrode layer 11. The insulating layer 9 is made of an insulating material such as silicon dioxide. The thickness of the insulating layer 9 is, for example, about 10 nm or more and 1000 nm or less, and preferably has a thickness greater than that of the gate insulating film 10.

[0093] The gate insulating film 10 is made of silicon dioxide and is formed in contact with the inner surface of the gate trench 22, a part of the surface of the drift layer 2, the insulating layer 9, and the field insulating film 12. The thickness of the gate insulating film 10 can be set to about 10 nm to about 200 nm.

[0094] The gate electrode layer 11 is formed on the gate insulating film 10 in the gate trench 22 and on the gate insulating film 10 formed on the insulating layer 9 in the outer trench 6. In this way, the gate insulating film 10 and the gate electrode layer 11 extend from the inside of the gate trench 22 to the inside of the outer trench 6. The height of the upper end of the gate electrode layer 11 in the gate trench 22 is preferably below the surface position of the drift layer 2, and more preferably lower than the surface position of the drift layer 2. In the present embodiment, the gate electrode layer 11 is a second polysilicon layer composed of polysilicon. The gate electrode layer 11 formed in the termination region 60 has a thickness exceeding the gate insulating film 10, for example. A contact hole 28 (hereinafter referred to as "gate contact hole 28") reaching the gate electrode layer 11 is formed in the interlayer insulating film 13, and the gate electrode layer 11 is connected to the gate wiring electrode 15 connected to the gate electrode pad 29 via the gate contact hole 28.

[0095] The surface electrode 14 , the gate wiring electrode 15 , and the gate electrode pad 29 are formed on the interlayer insulating film 13 and are made of a metal material such as aluminum. The surface electrode 14 is arranged to be separated from the gate wiring electrode 15 and the gate electrode pad 29 .

[0096] The back ohmic electrode 20 is formed on the back side of the semiconductor substrate 1 and is composed of a reaction product, such as nickel silicide, of a metal film mainly composed of nickel and the semiconductor substrate 1. The back electrode 21 is formed in contact with the back ohmic electrode 20 and is composed of titanium, nickel, silver, gold, aluminum, etc.

[0097] The semiconductor device according to the first embodiment is composed of the above-mentioned components.

[0098] Next, regarding the method for manufacturing the semiconductor device according to the first embodiment, refer to Figures 7 to 21 to explain. Figures 7 to 21 is an illustration of the various manufacturing stages of a semiconductor device, Figures 7 to 12 Corresponding to along Figure 2 The cross section of the B1-B2 line, Figures 13 to 21 Corresponding to along Figure 2 The cross section of the D1-D2 line.

[0099] First, an n-type silicon carbide semiconductor substrate 1 having a polytype of 4H is prepared, and an n-type drift layer 2 is epitaxially grown thereon by chemical vapor deposition (CVD). At this time, the impurity concentration of the n-type drift layer 2 is set to 1×10 14 cm -3 Up to 1×10 18 cm -3 The thickness of the drift layer 2 is set in the range of 5 μm to 300 μm.

[0100] Next, aluminum, boron or gallium is ion-implanted using a resist mask formed on the drift layer 2 by photolithography, thereby forming a p-type well region 3 in the surface layer of the drift layer 2. The well region 3 may also be formed by epitaxial growth.

[0101] Next, nitrogen or phosphorus is ion-implanted using a resist mask formed on the well region 3 by photolithography, thereby forming an n-type impurity region 4 in the surface layer portion of the well region 3 .

[0102] Next, a silicon dioxide film with a thickness of about 1 μm to 2 μm is formed on the well region 3 and the impurity region 4, and an etching mask with openings for the formation regions of the gate trench 22 and the outer trench 6 is formed by reactive ion etching (RIE). Then, when the gate trench 22 and the outer trench 6 are formed by RIE, Figure 7 and Fig.13 status.

[0103] Next, while leaving the etching mask, a resist mask covering a portion of the external trench 6 is formed by photolithography, and then aluminum, boron or gallium is ion-implanted from the surface side of the drift layer 2, thereby forming a trench bottom electric field relaxation region 16 below the gate trench 22 and the external trench 6.

[0104] Next, the etching mask and the resist mask are removed, and after forming a resist mask by photolithography, aluminum, boron or gallium is ion-implanted from the surface side of the drift layer 2 , thereby forming a terminal electric field relaxation region 18 in the terminal region 60 .

[0105] Next, after forming a resist mask by photolithography, aluminum, boron or gallium is ion-implanted, thereby forming a p-type contact region 5 on the surface of the well region 3, and forming a trench bottom surface high-concentration well region 17 on the surface of the trench bottom surface electric field relaxation region 16. The heating temperature of the semiconductor substrate 1 during the ion implantation is preferably set to 150° C. or higher. When the heating temperature is set to 150° C. or higher, the resistance of the contact region 5 can be reduced, and the resistance loss in the operating state of the semiconductor device can be reduced.

[0106] Next, after removing the etching mask, an annealing process is performed to activate the ion-implanted impurities. The annealing process is performed in an inert gas atmosphere such as argon or in a vacuum at a temperature of about 1500°C to about 1900°C for about 30 seconds to about 1 hour. Here, in order to prevent the degradation of silicon carbide caused by high-temperature heating, that is, surface roughness, a carbon film may be formed on the semiconductor substrate 1 before the annealing process. In this way, it becomes Figure 8 and Fig.14 status.

[0107] Next, an insulating film such as silicon dioxide to be the field insulating film 12 is formed by CVD or the like, and a resist mask is formed on the insulating film by photolithography. Then, the insulating film is opened by etching to form the field insulating film 12, and the resist mask is removed. In this way, Fig.15 status.

[0108] Next, a bottom insulating film 7 is formed by thermal oxidation or CVD to cover the inner part and the upper corner of the outer trench 6 and to be in contact with the well region 3, the drift layer 2, the trench bottom electric field relaxation region 16, and the trench bottom high concentration well region 17. A part of the bottom insulating film 7 is also formed on the field insulating film 12.

[0109] Next, a conductive material such as polysilicon to be the potential fixing layer 8 is formed on the bottom insulating film 7 by CVD method, and a resist mask is formed on the polysilicon by photolithography. Then, the polysilicon is etched to form the potential fixing layer 8 in the terminal region 60. A portion of the potential fixing layer 8 is also formed on the field insulating film 12. At this time, the polysilicon in the active region 50 is completely removed by etching by an etch-back process until the bottom insulating film 7 is exposed. Thereafter, the resist mask is removed. In this way, Fig.16 status.

[0110] Next, a layer of silicon dioxide or the like to be the insulating layer 9 is formed by a CVD method or the like so as to cover the potential fixing layer 8. When the potential fixing layer 8 is made of polysilicon, the layer of silicon dioxide or the like can also be formed by thermally oxidizing the surface of the potential fixing layer 8. Next, a resist mask is formed by photolithography, and etching is performed to form the insulating layer 9. The base insulating film 7 and the insulating layer 9 in the gate trench 22 in the active region 50 are completely removed by etching, thereby exposing the drift layer 2. In this way, the gate electrode 22 is formed. Fig.17 status.

[0111] Next, the gate insulating film 10 is formed on the surface of the drift layer 2, the inner surface of the gate trench 22, and the insulating layer 9 and the field insulating film 12 in the termination region 60 by thermal oxidation or CVD. Fig. 9 and Fig.18 status.

[0112] Then, a conductive material such as polysilicon to be the gate electrode layer 11 is formed by CVD method or the like, and a resist mask is formed on the polysilicon by photolithography. Next, the polysilicon is etched to form the gate electrode layer 11, and the resist mask is removed. At this time, the polysilicon is etched back in the active region 50, and the upper end of the gate electrode layer 11 is made below the surface position of the drift layer 2 in the gate trench 22. In this way, the gate electrode layer 11 is formed. Fig.10 and Fig.19 status.

[0113] Next, the interlayer insulating film 13 is formed by a reduced pressure CVD method or the like, and a resist mask is formed by photolithography on the interlayer insulating film 13. Next, the interlayer insulating film 13 is etched to form a source contact hole 25 reaching the impurity region 4 and the contact region 5, and a peripheral well region contact hole 26 reaching the trench bottom high concentration well region 17.

[0114] Then, a metal film mainly composed of Ni or the like is formed on the impurity region 4 and the contact region 5 exposed in the source contact hole 25 and on the trench bottom high concentration well region 17 exposed in the peripheral well region contact hole 26, and annealing is performed to form the surface ohmic electrode 19. Then, the metal film on the interlayer insulating film 13 is removed by etching, and the resist mask is removed.

[0115] Furthermore, a metal film mainly composed of Ni or the like is formed on the back surface of the semiconductor substrate 1 and annealed to form the back surface ohmic electrode 20. Here, the heating temperature of each annealing treatment may be about 600°C or more and 1100°C or less.

[0116] Next, a resist mask is formed on the interlayer insulating film 13 by photolithography, and the interlayer insulating film 13 is etched to form a potential fixing layer connection contact hole 27 reaching the potential fixing layer 8 and a gate contact hole 28 reaching the gate electrode layer 11, and the resist mask is removed. Fig.11 and Fig. 20 status.

[0117] Then, a metal film such as aluminum is formed on the interlayer insulating film 13 and the surface ohmic electrode 19 and inside the potential fixing layer connection contact hole 27 and the gate contact hole 28 by sputtering or evaporation, and a resist mask is formed on the metal film by photolithography. Next, the metal film is patterned by etching to form the surface electrode 14, the gate wiring electrode 15 and the gate electrode pad 29, and then the resist mask is removed. In this way, Fig.12 and Fig.21 status.

[0118] Finally, the back electrode 21 is formed on the back ohmic electrode 20 by sputtering or evaporation. Figure 4 and Figure 6 The construction of the semiconductor device shown is completed.

[0119] In the terminal area 60, it is also possible to Figure 1 As shown in the figure, a channel stop region 31 is provided to suppress the expansion of the depletion layer to the end of the semiconductor device. The channel stop region 31 is an n-type region provided at a position closer to the outer peripheral side than the external trench 6, and is composed of silicon carbide. The n-type impurity of the channel stop region 31 can be nitrogen or phosphorus, and the impurity concentration of the channel stop region 31 is 1×10 17 cm -3 Above and 1×10 22 cm -3 The thickness of the channel stop region 31 may be the same as or different from the thickness of the impurity region 4. The channel stop region 31 may be formed by ion implantation, or may be formed simultaneously with the impurity region 4 using a resist mask for setting the impurity region 4, or may be formed before or after the formation of the impurity region 4. When the channel stop region 31 is formed simultaneously with the impurity region 4, for example, the channel stop region 31 and the impurity region 4 may be formed after the gate trench 22 and the external trench 6 are formed.

[0120] In addition, the order of the process of forming the well region 3 and the process of forming the impurity region 4 may be reversed. As for the method of forming the well region 3 and the impurity region 4, after ion implantation of n-type impurities into the surface layer of the well region 3 to set the impurity region 4, a resist mask may be formed thereon by photolithography, and ion implantation of p-type impurities into the position other than the impurity region 4 to set the well region 3.

[0121] In the manufacturing method described above, the thickness of the etching mask and the RIE process are adjusted so that the etching mask is left after the gate trench 22 and the outer trench 6 are formed, and the trench bottom electric field relaxation region 16 is formed by ion implantation using the etching mask left and the resist mask formed by the photolithography process. However, the etching mask may be removed without leaving it, and the trench bottom electric field relaxation region 16 may be formed by ion implantation using only the resist mask formed by the photolithography process.

[0122] In addition, the trench bottom electric field relaxation region 16 below the external trench 6 may be formed simultaneously with the trench bottom electric field relaxation region 16 below the gate trench 22, or may be formed before or after the formation of the trench bottom electric field relaxation region 16 below the gate trench 22. Furthermore, p-type impurities may be ion-implanted into the gate trench 22 from an oblique direction, a p-type semiconductor layer may be formed in the drift layer 2 in contact with the side surface of the gate trench 22, and the trench bottom electric field relaxation region 16 may be electrically connected to the well region 3 via the semiconductor layer. When the trench bottom electric field relaxation region 16 is electrically connected to the well region 3, the frequency characteristics of the semiconductor device are improved because the trench bottom electric field relaxation region 16 is connected to the surface electrode 14 via the well region 3 and is grounded, compared to a state where the trench bottom electric field relaxation region 16 is floating.

[0123] In the present embodiment, an example in which the semiconductor device is a MOSFET is shown. However, when the semiconductor device is an IGBT, the conductivity type of the semiconductor substrate 1 may be set to a p-type, and the semiconductor substrate 1 may be polished to be thinner.

[0124] Next, the operation of the semiconductor device according to this embodiment will be described.

[0125] When a gate voltage above the threshold is applied between the gate electrode pad 29 and the surface electrode 14, a channel is formed in the well region 3 facing the gate electrode layer 11, and electrons flow from the impurity region 4 to the drift layer 2. When a voltage is applied between the surface electrode 14 and the back electrode 21 to generate an electric field, the electrons reach the back electrode 21 via the drift layer 2 and the semiconductor substrate 1, that is, a current is generated from the back electrode 21 to the surface electrode 14, and the semiconductor device becomes conductive.

[0126] Here, when the gate insulating film 10 is formed in contact with the surface and the inner side of the gate trench 22 and the outer trench 6, an electric field is generated in the gate insulating film 10 near the upper corner 22a of the outer trench 6 (hereinafter referred to as "gate trench upper corner 22a") and the outer trench upper corner 6a. However, in the active region 50, the gate electrode layer 11 is formed at a position lower than the gate trench upper corner 22a, and the electric field concentration caused by the shape of the gate trench upper corner 22a is suppressed, thereby preventing the gate insulating film 10 from being destroyed.

[0127] On the other hand, in the terminal region 60, the gate insulating film 10 is formed on the insulating layer 9 and isolated from the outer trench upper corner 6a, thereby preventing the gate insulating film 10 from being destroyed due to the electric field concentration caused by the shape of the outer trench upper corner 6a. The outer trench upper corner 6a is covered with the bottom insulating film 7, but the well region 3 and the potential fixing layer 8 become the source potential, and the potential fixing layer 8 is insulated from the gate electrode layer 11 by the insulating layer 9 and the gate insulating film 10, so the bottom insulating film 7 of the outer trench upper corner 6a is not destroyed by the gate voltage.

[0128] Here, when the thickness of the potential fixing layer 8 is sufficiently thick, since the potential fixing layer 8 covers the upper corner and the inside of the outer groove 6 via the bottom insulating film 7, the curvature of the upper portion of the potential fixing layer 8 can be increased by the height difference of the outer groove 6. By increasing the curvature of the upper portion of the potential fixing layer 8, the thickness of the insulating layer 9 and the gate insulating film 10 formed on the potential fixing layer 8 can be prevented from being locally thinned, and the effect of preventing the insulating layer 9 and the gate insulating film 10 from being destroyed due to electric field concentration is further improved.

[0129] In addition, when the thickness of the insulating layer 9 is thin, the insulation between the potential fixing layer 8 and the gate electrode layer 11 becomes insufficient, and the gate-source leakage increases as in the case where the potential of the field plate electrode is set to the source potential in Patent Document 2, and the potential fixing layer 8 and the gate electrode layer 11 may be destroyed by the electric field and short-circuited. In order to avoid this situation, for example, it is preferable to set the thickness of the insulating layer 9 to a thickness exceeding the thickness of the gate insulating film 10. In this way, the potential fixing layer 8 and the gate electrode layer 11 can be insulated by a thickness at least twice that of the gate insulating film 10, and the insulation between the gate and the source in the terminal region 60 can be improved compared to the active region 50, and the gate-source leakage current in the terminal region 60 can be suppressed, and the effect of preventing the destruction of the insulating layer 9 and the gate insulating film 10 is further improved.

[0130] On the other hand, when a voltage less than the threshold is applied between the gate electrode pad 29 and the surface electrode 14, a channel is not formed in the well region 3 facing the gate electrode layer 11, and no current is generated from the back electrode 21 to the surface electrode 14, and the semiconductor device becomes cut-off. In the cut-off state of the semiconductor device, a voltage higher than the voltage in the on state is applied between the surface electrode 14 and the back electrode 21, and the depletion layer expands from the well region 3 to the drift layer 2.

[0131] At this time, the depletion layer also extends from the trench bottom electric field relaxation region 16 to the drift layer 2. Thus, the gate insulating film 10 at the bottom or bottom corner of the gate trench 22 and the outer trench 6 is prevented from being destroyed by the electric field generated by the high voltage applied between the surface electrode 14 and the back electrode 21.

[0132] When the semiconductor device changes from the off state to the on state, the voltage applied between the front electrode 14 and the back electrode 21 decreases, and the depletion layer extending toward the drift layer 2 shrinks. The semiconductor device operates by alternately repeating the on state and the off state.

[0133] According to the semiconductor device according to the first embodiment, it is possible to prevent the gate insulating film 10 from being destroyed at the gate trench upper corner 22 a and the outer trench upper corner 6 a .

[0134] <Implementation Method 2>

[0135] Fig. 22 and Fig.23 is a diagram showing a structure of a semiconductor device according to Embodiment 2, Fig. 22 Corresponding to along Figure 2 The cross-sectional view of the B1-B2 line, Fig.23 Corresponding to along Figure 2 In this embodiment, along the C1-C2 line Figure 2 The cross-sectional structure along the lines A1 - A2 and D1 - D2 is the same as that in the first embodiment.

[0136] In the second embodiment, the bottom insulating film 7 and the potential fixing layer 8 are provided below the gate insulating film 10 and the gate electrode layer 11 in the gate trench 22 of the active region 50. In the gate trench 22, the bottom insulating film 7 is formed in contact with the inner surface of the gate trench 22, and the potential fixing layer 8 is formed on the bottom insulating film 7. The gate insulating film 10 is formed in contact with the inner surface of the gate trench 22 and the upper surface of the potential fixing layer 8, and the gate electrode layer 11 is formed on the gate insulating film 10.

[0137] In this embodiment, the potential of the potential fixing layer 8 formed in the gate trench is set to a floating potential. The bottom insulating film 7 is formed thicker than the gate insulating film 10 to mitigate the influence of the electric field generated on the bottom surface of the gate trench 22 due to the drain voltage.

[0138] exist Fig. 22 In the embodiment, a trench bottom electric field relaxation region 16 is formed below the gate trench 22, but the trench bottom electric field relaxation region 16 may be omitted. In the case where the trench bottom electric field relaxation region 16 is not formed, the electric field generated at the bottom of the gate trench 22 due to the drain voltage when the semiconductor device is turned off is shared by the depletion layer formed between the well region 3 and the drift layer 2, the bottom insulating film 7, and the potential fixing layer 8. If the concentration of phosphorus in the polysilicon of the potential fixing layer 8 is low, the depletion of the polysilicon increases, and the electric field relaxation effect can be improved.

[0139] In addition, when the trench bottom electric field relaxation region 16 is not formed, the current narrowing when the semiconductor device is turned on caused by the depletion layer extending from the well region 3 to the drift layer 2 and the depletion layer extending from the trench bottom electric field relaxation region 16 to the drift layer 2 is eliminated, thereby also achieving the effect of improving the conduction characteristics.

[0140] Next, regarding the method for manufacturing a semiconductor device according to Embodiment 2, refer to Figures 24 to 37 to explain. Figures 24 to 37 is an illustration of the various manufacturing stages of a semiconductor device, Figures 24 to 30 Corresponding to along Figure 2 The cross section of the B1-B2 line, Figure 31 to Figure 37 Corresponding to along Figure 2 A cross section of the C1-C2 line.

[0141] First, similarly to the first embodiment, an n-type silicon carbide semiconductor substrate 1 having a polytype of 4H is prepared, and an n-type drift layer 2 is epitaxially grown thereon by chemical vapor deposition (CVD) to form a well region 3, an impurity region 4, a gate trench 22, and a trench bottom electric field relaxation region 16. In this way, Fig.24 and Fig.31 status.

[0142] Next, an insulating film of silicon dioxide or the like to be the field insulating film 12 is formed by CVD or the like, and a resist mask is formed on the insulating film by photolithography. Then, the insulating film is opened by etching to form the field insulating film 12, and the resist mask is removed.

[0143] Then, a base insulating film 7 is formed by thermal oxidation or CVD. Fig.25 and Fig.32 status.

[0144] Next, a conductive material such as polysilicon to be the potential fixing layer 8 is formed on the base insulating film 7 by CVD or the like, and is etched by an etch-back process so that a desired thickness remains in the gate trench 22. Thereafter, a resist mask is formed by photolithography so that the potential fixing layer 8 in the active region 50 becomes a floating potential, and the potential fixing layer 8 in the active region 50 is separated from the potential fixing layer 8 in the terminal region 60 by etching, and the resist mask is removed. In this way, Fig.26 and Fig.33 status.

[0145] Next, an insulating layer 9 made of silicon dioxide or the like is formed by CVD method or the like so as to cover the potential fixing layer 8. When the potential fixing layer 8 is made of polysilicon, the insulating layer 9 may be formed by thermally oxidizing the potential fixing layer 8. Fig. 27 and Fig.34 status.

[0146] Next, a resist mask is formed by photolithography, and etching is performed until the upper side and the upper end of the side wall of the potential fixing layer 8 in the gate trench 22 are exposed. Thereafter, a gate insulating film 10 is formed on the surface of the drift layer 2, the inner side of the gate trench 22, and the insulating layer 9 by thermal oxidation or CVD. Fig.28 and Fig.35 status.

[0147] Then, a conductive material such as polysilicon to be the gate electrode layer 11 is formed by CVD method or the like, and a resist mask is formed on the polysilicon by photolithography. Next, the polysilicon is etched to form the gate electrode layer 11, and the resist mask is removed. At this time, the polysilicon is etched back in the active region 50, and the upper end of the gate electrode layer 11 is made below the surface position of the drift layer 2 in the gate trench 22. In this way, the gate electrode layer 11 is formed. Fig.29 and Fig.36 status.

[0148] Next, the interlayer insulating film 13 is formed by a reduced pressure CVD method or the like, and a resist mask is formed by photolithography on the interlayer insulating film 13. Next, the interlayer insulating film 13 is etched to form a source contact hole 25 reaching the impurity region 4 and the contact region 5, and a peripheral well region contact hole 26 reaching the trench bottom high concentration well region 17.

[0149] Then, a metal film mainly composed of Ni or the like is formed on the impurity region 4 and the contact region 5 exposed in the source contact hole 25 and on the trench bottom high concentration well region 17 exposed in the peripheral well region contact hole 26, and annealing is performed to form the surface ohmic electrode 19. Then, the metal film on the interlayer insulating film 13 is removed by etching, and the resist mask is removed.

[0150] Furthermore, a metal film mainly composed of Ni or the like is formed on the back surface of the semiconductor substrate 1, and an annealing process is performed to form the back surface ohmic electrode 20. Here, the heating temperature of each annealing process may be 600° C. or higher and 1100° C. or lower. Fig.30 and Fig.37 status.

[0151] Then, a metal film of aluminum or the like is formed by sputtering or vapor deposition on the interlayer insulating film 13 and the surface ohmic electrode 19 and inside the potential fixing layer connection contact hole 27 and the gate contact hole 28, and a resist mask is formed on the metal film by photolithography. Next, the metal film is patterned by etching to form the surface electrode 14, the gate wiring electrode 15, and the gate electrode pad 29, and then the resist mask is removed.

[0152] Finally, the back electrode 21 is formed on the back ohmic electrode 20 by sputtering or evaporation. Fig. 22 and Fig.23 The construction of the semiconductor device shown is completed.

[0153] In Embodiment 2, an example is described in which the potential fixing layer 8 of the activation region 50 and the potential fixing layer 8 of the terminal region 60 are separated by etching in such a manner that the potential fixing layer 8 in the activation region 50 is set to a floating potential. However, in the case where the potential fixing layer 8 of the terminal region 60 is not connected to an external electrode but is set to a floating potential as described in Embodiment 4, the potential fixing layer 8 of the activation region 50 and the potential fixing layer 8 of the terminal region 60 may be connected to each other.

[0154] The semiconductor device according to the second embodiment also achieves the same effects as those of the first embodiment. In addition, the thickness of the bottom insulating film 7 formed on the bottom surface of the gate trench 22 is thicker than the gate insulating film 10, and the gate electrode layer 11 is not located on the bottom surface of the gate trench 22. Therefore, compared with the case where only the gate insulating film 10 is formed on the bottom surface of the gate trench 22, the influence of the electric field generated in the insulating film (silicon dioxide, etc.) on the bottom surface of the gate trench 22 due to the drain voltage or the gate voltage when the semiconductor device is in the off state is alleviated.

[0155] <Implementation Method 3>

[0156] Figures 38 to 40 This is a diagram showing the structure of a semiconductor device according to a third embodiment. Fig.38 is a schematic plan view showing a schematic structure of a semiconductor device according to Embodiment 3. Fig.39 express Fig.38 The structure of the region 41 surrounded by a dotted line. Fig.40 It is along Fig.39 The cross-sectional view of the D1-D2 line. Fig.39 In order to simplify the description, the interlayer insulating film 13, the surface electrode 14, the surface ohmic electrode 19, etc. are omitted from illustration.

[0157] The semiconductor device according to the third embodiment includes a ground electrode pad 30 to which a ground potential of 0 V is supplied and a ground wiring electrode 23 connected thereto. In the first and second embodiments, an example is shown in which the potential fixing layer 8 is connected to the surface electrode 14 to set the potential of the potential fixing layer 8 to the source potential. In the third embodiment, the potential fixing layer 8 is connected to the ground wiring electrode 23, and the potential of the potential fixing layer 8 is set to the ground potential. The other structures are the same as those in the first embodiment.

[0158] Even when the potential fixing layer 8 is set to the ground potential, since the gate insulating film 10 is formed in a manner isolated from the outer trench upper corner 6a in the terminal region 60, the electric field concentration caused by the shape of the outer trench upper corner 6a is suppressed, and the destruction of the gate insulating film 10 is prevented. The outer trench upper corner 6a is covered with the bottom insulating film 7, but the well region 3 becomes the source potential, the potential fixing layer 8 becomes the ground potential, and the potential fixing layer 8 is insulated from the gate electrode layer 11 by the insulating layer 9 and the gate insulating film 10, so the bottom insulating film 7 of the outer trench upper corner 6a is not destroyed by the gate voltage.

[0159] <Implementation Method 4>

[0160] Fig.41 and Fig.42 This is a diagram showing the structure of a semiconductor device according to a fourth embodiment. Fig.41 is a schematic diagram showing a schematic structure of a semiconductor device according to Embodiment 4, showing Figure 1 The structure of the area 40 surrounded by the dotted line. Fig.42 It is along Fig.41 The cross-sectional view of the D1-D2 line. Fig.41 In order to simplify the description, the interlayer insulating film 13, the surface electrode 14, the surface ohmic electrode 19, etc. are omitted from illustration.

[0161] In the fourth embodiment, the potential fixing layer connection contact hole 27 is not formed in the interlayer insulating film 13, and the potential fixing layer 8 is not connected to any other electrode. In other words, the potential of the potential fixing layer 8 is set to a floating potential. The other structures are the same as those of the first to third embodiments.

[0162] Even when the potential fixing layer 8 is set to a floating potential, since the gate insulating film 10 is formed in a manner isolated from the outer trench upper corner 6a in the terminal region 60, the electric field concentration caused by the shape of the outer trench upper corner 6a is suppressed, and the destruction of the gate insulating film 10 is prevented. The outer trench upper corner 6a is covered with the bottom insulating film 7, but the well region 3 becomes the source potential, the potential fixing layer 8 becomes the floating potential, and the potential fixing layer 8 is insulated from the gate electrode layer 11 by the insulating layer 9 and the gate insulating film 10, so the bottom insulating film 7 of the outer trench upper corner 6a is not destroyed by the gate voltage.

[0163] <Implementation method 5>

[0164] Figure 43 to Figure 45 This is a diagram showing the structure of a semiconductor device according to the fifth embodiment. Fig.43 It is along Figure 2 The cross-sectional view of the D1-D2 line, Fig.44 It is along Fig.39 The cross-sectional view of the D1-D2 line, Fig.45 It is along Fig.41 Cross-sectional view of line D1-D2.

[0165] In the first to fourth embodiments, an example is shown in which the well region 3 and the trench bottom electric field relaxation region 16 are isolated from each other in the terminal region 60. In the fifth embodiment, the well region 3 and the trench bottom electric field relaxation region 16 are connected to each other through a p-type external trench side connection layer 24 formed on the side of the external trench 6. The structure other than this is the same as that of the first to fourth embodiments. In addition, Fig.43 Equivalent to Figure 6 The structure is formed by setting the outer groove side connection layer 24, Fig.44 Equivalent to Fig.40 The structure is formed by setting the outer groove side connection layer 24, Fig.45 Equivalent to Fig.42 The structure is formed by setting an external groove side connection layer 24.

[0166] The outer trench side connection layer 24 is formed by ion implantation after the formation of the trench bottom electric field relaxation region 16, and the p-type impurity can be aluminum, boron or gallium, and the impurity concentration is 1×10 17 cm -3 Above and 1×10 22 cm -3The following will do.

[0167] On the side of the external trench 6, the well region 3 is connected to the trench bottom electric field relaxation region 16, thereby increasing the path for the displacement current generated at the time of shutdown to flow to the surface electrode 14. Therefore, the potential rise of the bottom insulating film 7 at the corner 6a of the upper end of the external trench caused by the displacement current is suppressed, and the destruction of the bottom insulating film 7 is prevented.

[0168] <Implementation Method 6>

[0169] Figure 46 to Figure 49 This is a diagram showing the structure of a semiconductor device according to the fifth embodiment. Fig.46 It is along Figure 2 , Fig.39 or Fig.41 The cross-sectional view of the B1-B2 line, Fig.47 It is along Figure 2 The cross-sectional view of the D1-D2 line, Fig.48 It is along Fig.39 The cross-sectional view of the D1-D2 line, Fig.49 It is along Fig.41 Cross-sectional view of line D1-D2.

[0170] In the sixth embodiment, the base insulating film 7 is not formed, and the potential fixing layer 8 is in contact with the inner surface of the outer groove 6 and the upper corner 6a of the outer groove. The other structures are the same as those of the first to fifth embodiments. Fig.47 Equivalent to Fig.43 The structure is formed by omitting the bottom insulating film 7. Fig.48 Equivalent to Fig.44 The structure is formed by omitting the bottom insulating film 7. Fig.49 Equivalent to Fig.45 The structure is formed by omitting the bottom insulating film 7.

[0171] Even when the base insulating film 7 is omitted, since the gate insulating film 10 is formed in the terminal region 60 in a manner isolated from the upper corner portion 6a of the outer trench, the electric field concentration caused by the shape of the upper corner portion 6a of the outer trench is suppressed, thereby preventing the gate insulating film 10 from being destroyed.

[0172] As in Embodiments 1 to 5, the potential of the potential fixing layer 8 is set to any one of the source potential, the ground potential, and the floating potential. Even if the potential of the potential fixing layer 8 is the source potential or the ground potential, the current is not easy to flow from the back electrode 21 to the potential fixing layer 8 due to the influence of the well region 3, the external trench side connection layer 24, the trench bottom electric field relaxation region 16, and the PN junction between the trench bottom high concentration well region 17 and the drift layer 2, and the influence on the loss is small.

[0173] In addition, each embodiment can be freely combined, or each embodiment can be appropriately modified or omitted.

[0174] The above description is by way of example only in all aspects, and it is understood that numerous modifications not shown in the examples are conceivable.

[0175] (Explanation of Reference Numerals)

[0176] 1: semiconductor substrate; 2: drift layer; 3: well region; 4: impurity region; 5: contact region; 6: external trench; 6a: upper corner of external trench; 7: bottom insulating film; 8: potential fixing layer; 9: insulating layer; 10: gate insulating film; 11: gate electrode layer; 12: field insulating film; 13: interlayer insulating film; 14: surface electrode; 15: gate wiring electrode; 16: trench bottom electric field relaxation region; 17: trench bottom high concentration well region; 18: terminal electric field relaxation region Domain; 19: Surface ohmic electrode; 20: Back ohmic electrode; 21: Back electrode; 22: Gate groove; 22a: Upper corner of gate groove; 23: Ground wiring electrode; 24: External groove side connection layer; 25: Source contact hole; 26: Peripheral well region contact hole; 27: Contact hole for connecting potential fixing layer; 28: Gate contact hole; 29: Gate electrode pad; 30: Ground electrode pad; 31: Channel blocking region; 50: Activation region; 60: Terminal region.

Claims

1. A semiconductor device comprising: a drift layer of a first conductivity type; A well region of a second conductivity type is formed in a surface portion of the drift layer; An impurity region of a first conductivity type is formed in a surface portion of the well region; a gate trench formed in such a manner as to penetrate the impurity region and the well region of the active region and reach the drift layer; a gate insulating film formed in contact with an inner surface of the gate trench; a gate electrode layer formed on the gate insulating film; an interlayer insulating film covering the gate electrode layer; a gate wiring electrode formed on the interlayer insulating film and connected to the gate electrode layer; an outer trench formed in the drift layer at a termination region outside the active region; A potential fixing layer is formed in the outer groove and covers the upper corner of the outer groove; as well as an insulating layer formed on the potential fixing layer, The gate insulating film and the gate electrode layer extend into the outer trench of the termination region, and the gate electrode layer is connected to the gate wiring electrode through a contact hole formed in the interlayer insulating film in the outer trench.

2. The semiconductor device according to claim 1, wherein The potential fixing layer has a thickness exceeding a thickness of the gate insulating film.

3. The semiconductor device according to claim 1 or 2, wherein: It further includes an underlying insulating film formed under the potential fixing layer.

4. The semiconductor device according to claim 3, wherein: The thickness of the base insulating film is greater than or equal to the thickness of the gate insulating film.

5. The semiconductor device according to any one of claims 1 to 4, wherein: A portion of the potential fixing layer is formed at the bottom of the gate trench, and the gate insulating film and the gate electrode layer in the gate trench are formed on the gate trench. The potential fixing layer at the bottom of the gate trench is configured to have a floating potential.

6. The semiconductor device according to any one of claims 1 to 5, further comprising: A second conductivity type trench bottom electric field relaxation region formed below the outer trench; and The outer trench side connection layer of the second conductivity type is formed on the side of the outer trench and connects the well region with the trench bottom electric field relaxation region.

7. The semiconductor device according to any one of claims 1 to 6, wherein: It also includes a surface electrode formed on the interlayer insulating film and connected to the well region. The potential fixing layer is connected to the surface electrode through a contact hole formed in the interlayer insulating film.

8. The semiconductor device according to any one of claims 1 to 6, wherein: further comprising a ground wiring electrode formed on the interlayer insulating film, The potential fixing layer is connected to the ground wiring electrode through a contact hole formed in the interlayer insulating film.

9. The semiconductor device according to any one of claims 1 to 6, wherein: The potential fixing layer is configured to have a floating potential.

10. The semiconductor device according to any one of claims 1 to 9, wherein: The gate electrode layer of the termination region surrounds the gate trench in a plan view.

11. The semiconductor device according to any one of claims 1 to 10, wherein: The thickness of the potential fixing layer is three times or more than the thickness of the gate insulating film.

12. The semiconductor device according to any one of claims 1 to 11, wherein: The thickness of the insulating layer is greater than or equal to the thickness of the gate insulating film.

13. The semiconductor device according to any one of claims 1 to 12, wherein: An upper end of the gate electrode layer of the gate trench is located lower than an upper end of the gate trench.

14. A method for manufacturing a semiconductor device, comprising the following steps: forming a drift layer of a first conductivity type; forming a well region of a second conductivity type in a surface portion of the drift layer; forming an impurity region of a first conductivity type in a surface portion of the well region; forming a gate trench penetrating the impurity region and the well region of the active region and reaching the drift layer; forming an outer trench in the drift layer at a termination region outside the active region; forming a potential fixing layer in the outer groove and covering the upper corner of the outer groove; forming an insulating layer on the potential fixing layer; forming a gate insulating film in the gate trench and in the outer trench; forming a gate electrode layer on the gate insulating film in the gate trench and in the outer trench; forming an interlayer insulating film covering the gate electrode layer; forming a contact hole reaching the gate electrode layer in the interlayer insulating film in the outer trench; as well as A gate wiring electrode connected to the gate electrode layer through the contact hole is formed on the interlayer insulating film.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: The potential fixing layer is formed to have a thickness exceeding that of the gate insulating film.

16. The method for manufacturing a semiconductor device according to claim 14 or 15, wherein: The method further comprises forming an underlying insulating film provided under the potential fixing layer before forming the potential fixing layer.

17. The method for manufacturing a semiconductor device according to any one of claims 14 to 16, wherein: In the step of forming the potential fixing layer, a portion of the potential fixing layer is formed in the gate trench.

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