Light detection substrate, image sensor, and electronic apparatus

Abstract

The invention provides an optical detection base plate, which comprises a substrate base plate; the plurality of detection pixel units are located on the substrate, and each detection pixel unit comprises a signal reading circuit and a photoelectric conversion structure; the signal reading circuit comprises at least one transistor, the transistor comprises a grid electrode and an active layer pattern, and the active layer pattern comprises a channel region and a source-drain doped region; at least one transistor in the signal reading circuit is a stacked transistor, and the stacked transistor is located on the side, away from the substrate, of the photoelectric conversion structure. The orthographic projection of the active layer pattern of the stacked transistor on the substrate is overlapped with the orthographic projection of the photoelectric conversion structure in the same detection pixel unit on the substrate, and the material of the grid electrode of the stacked transistor comprises a transparent conductive material. The embodiment of the invention further provides an image sensor and electronic equipment.

Description

Light detection substrates, image sensors, and electronics Technical Field

[0001] The present invention relates to the field of display, and in particular to a light detection substrate, an image sensor and an electronic device. Background Art

[0002] The Active Pixel Sensor (APS) is characterized by combining thin-film transistors and photodiodes to form pixel units. Compared with traditional Passive Pixel Sensors (PPS), APS has advantages such as low noise and high reading speed. APS has been widely used in glass-based image sensors.

[0003] Summary of the Invention

[0004] In a first aspect, an embodiment of the present disclosure provides a light detection substrate, comprising:

[0005] substrate;

[0006] A plurality of detection pixel units are located on the substrate, and the detection pixel units include: a signal reading circuit and a photoelectric conversion structure;

[0007] The signal reading circuit includes: at least one transistor, the transistor includes a gate and an active layer pattern, the active layer pattern includes: a channel region and a source-drain doped region;

[0008] At least one of the transistors in the signal reading circuit is a stacked transistor, which is located on a side of the photoelectric conversion structure away from the substrate. The positive projection of the active layer pattern of the stacked transistor on the substrate overlaps with the positive projection of the photoelectric conversion structure in the same detection pixel unit on the substrate. The material of the gate of the stacked transistor includes: a transparent conductive material.

[0009] In some embodiments, a material of the active layer pattern of the stacked transistor includes an oxide semiconductor material doped with a rare earth element.

[0010] In some embodiments, the orthographic projection of the active layer pattern of the stacked transistor on the substrate is located within an area covered by the orthographic projection of the photoelectric conversion structure on the substrate within the same detection pixel unit.

[0011] In some embodiments, the method further includes: a plurality of gate lines sequentially arranged along a first direction and a plurality of signal readout lines sequentially arranged along a second direction, wherein the gate lines extend along the second direction, the signal readout lines extend along the first direction, and the first direction intersects the second direction;

[0012] A plurality of the gate lines and the plurality of the signal reading lines define a plurality of the detection pixel units, and the signal reading circuits in the detection pixel units are connected to the corresponding gate lines and the corresponding signal reading lines;

[0013] The light detection substrate further includes: a plurality of bias voltage supply lines;

[0014] The photoelectric conversion structure includes: a first electrode, a photoelectric conversion layer, and a second electrode sequentially arranged in a direction away from the base substrate. The first electrode is connected to the corresponding signal reading circuit, and the second electrode is connected to the corresponding bias voltage supply line.

[0015] In some embodiments, it further includes:

[0016] The circuit connection pattern layer is located on a side of the stacked transistor away from the base substrate. The circuit connection pattern layer includes a plurality of circuit connection patterns connected to source and drain doping regions corresponding to the transistors.

[0017] In some embodiments, the signal reading line is located on a side of the circuit connection pattern layer away from the base substrate;

[0018] The circuit connection pattern layer includes: a first circuit connection pattern; a signal reading line is connected to the source and drain doping regions of the corresponding transistor in the signal reading circuit through the corresponding first circuit connection pattern.

[0019] In some embodiments, the material of the circuit connection pattern layer includes: a transparent conductive material.

[0020] In some embodiments, the first electrode, the bias voltage supply line, and the gate line are disposed in the same layer.

[0021] In some embodiments, the device further comprises: a bias transmission pattern, wherein the second electrode of the photoelectric conversion structure is connected to the corresponding bias voltage supply line via the bias transmission pattern;

[0022] The bias transmission pattern is arranged in the same layer as the gate of the stacked transistor.

[0023] In some embodiments, the signal reading circuit includes: a switching transistor;

[0024] The gate of the switching transistor is connected to the corresponding gate line, the first electrode of the switching transistor is connected to the first electrode of the photoelectric conversion structure, and the second electrode of the switching transistor is connected to the corresponding signal reading line;

[0025] The switching transistor is the stacked transistor.

[0026] In some embodiments, the bias voltage supply line and the gate line are provided in the same layer, and the signal reading line extends along the second direction;

[0027] The bias voltage supply line and the gate line corresponding to the detection pixel unit are respectively located on two opposite sides of the photoelectric conversion structure in the detection pixel unit in the first direction.

[0028] In some embodiments, the second electrode has a third edge and a fourth edge, and the third edge and the fourth edge are arranged opposite to each other in the first direction;

[0029] A gate line corresponding to the detection pixel unit is located on a side close to a fourth edge of the second electrode in the detection pixel unit, and an orthographic projection of the gate of the switching transistor on the plane where the second electrode is located intersects with the fourth edge;

[0030] A bias voltage supply line corresponding to the detection pixel unit is located on a side close to the third edge of the second electrode in the detection pixel unit;

[0031] The light detection substrate also includes: a bias transmission pattern, through which the second electrode of the photoelectric conversion structure is connected to the corresponding bias voltage supply line, the bias transmission pattern is arranged on the same layer as the gate of the stacked transistor, and the orthographic projection of the bias transmission pattern on the plane where the second electrode is located intersects with the third edge.

[0032] In some embodiments, the second electrode further has a first edge and a second edge, and the first edge and the second edge are arranged opposite to each other in the second direction;

[0033] The light detection substrate further comprises: a wiring arrangement layer, located on a side of the stacked transistor away from the base substrate, the wiring arrangement layer comprising: the signal reading line;

[0034] One of the signal reading lines corresponding to the detection pixel unit is located on a side close to the first edge of the second electrode in the detection pixel unit;

[0035] The light detection substrate further comprises: a circuit connection pattern layer located between the stacked transistor and the wiring arrangement layer, the circuit connection pattern layer comprising: a first circuit connection pattern and a second circuit connection pattern;

[0036] A portion of the source / drain doped region of the active layer pattern of the switching transistor, serving as the first electrode of the switching transistor, is connected to the corresponding signal reading line via the corresponding first circuit connection pattern, and an orthographic projection of the first circuit connection pattern on the plane where the second electrode is located intersects with the first edge;

[0037] The portion of the source-drain doped region of the active layer pattern of the switching transistor serving as the second electrode of the switching transistor is connected to the first electrode of the photoelectric conversion structure in the same detection pixel unit through the corresponding second circuit connection pattern, and the orthographic projection of the second circuit connection pattern on the plane where the second electrode is located intersects with the fourth edge.

[0038] In some embodiments, the signal reading circuit includes: a reset transistor, a source follower transistor, and a select transistor;

[0039] The gate of the reset transistor is connected to the reset control line, the first electrode of the reset transistor is connected to the reset voltage supply line, and the second electrode of the reset transistor is connected to the first electrode of the photoelectric conversion structure;

[0040] The gate of the source follower transistor is connected to the first electrode of the photoelectric conversion structure, the first electrode of the source follower transistor is connected to the working voltage supply line, and the second electrode of the source follower transistor is connected to the first electrode of the selection transistor;

[0041] A gate electrode of the selection transistor is connected to a corresponding gate line, and a second electrode of the selection transistor is connected to a corresponding signal reading line.

[0042] In some embodiments, the reset transistor, the source follower transistor, and the select transistor are all stacked transistors.

[0043] In some embodiments, the second electrode has a first edge, a second edge, a third edge, and a fourth edge, the first edge and the second edge are arranged opposite to each other in the second direction, and the third edge and the fourth edge are arranged opposite to each other in the first direction;

[0044] The second electrode includes: a first sub-region and a second sub-region arranged in the second direction, the channel region of the source follower transistor is located in the first sub-region, and the channel region of the reset transistor and the channel region of the select transistor are both located in the second sub-region;

[0045] The orthographic projection of the gate of the source follower transistor on the plane where the second electrode is located intersects with the third edge, the orthographic projection of the gate of the reset transistor on the plane where the second electrode is located intersects with the second edge, and the orthographic projection of the gate of the selection transistor on the plane where the second electrode is located intersects with the fourth edge.

[0046] In some embodiments, the reset control line, the bias voltage supply line, the gate line, and the first electrode are arranged in the same layer, and the reset control line and the bias voltage supply line both extend along the second direction;

[0047] One of the bias voltage supply line and the reset control line corresponding to the detection pixel unit is located on a side close to the third edge of the second electrode in the detection pixel unit, and the other is located on a side close to the fourth edge of the second electrode in the detection pixel unit;

[0048] A gate line corresponding to the detection pixel unit is located on a side close to the fourth edge of the second electrode in the detection pixel unit;

[0049] The portion of the first electrode of the photoelectric conversion structure that contacts the gate of the corresponding source follower transistor is located on a side close to the third edge of the second electrode in the detection pixel unit.

[0050] In some embodiments, it further includes:

[0051] a wiring arrangement layer, located on a side of the stacked transistor away from the substrate, the wiring arrangement layer comprising: the reset voltage supply line, the working voltage supply line, and the signal reading line, wherein the reset voltage supply line and the working voltage supply line both extend along a first direction;

[0052] One of the working voltage supply lines corresponding to the detection pixel unit is located on a side close to the first edge of the second electrode in the detection pixel unit;

[0053] The reset voltage supply line and the signal reading line corresponding to the detection pixel unit are both located on a side close to the second edge of the second electrode in the detection pixel unit.

[0054] In some embodiments, it further includes:

[0055] a circuit connection pattern layer, located between the stacked transistor and the wiring arrangement layer, the circuit connection pattern layer comprising: a first circuit connection pattern, a second circuit connection pattern, a third circuit connection pattern, and a fourth circuit connection pattern;

[0056] A portion of the source / drain doped region of the active layer pattern of the selection transistor, serving as the second electrode of the selection transistor, is connected to the corresponding signal readout line via the corresponding first circuit connection pattern, and an orthographic projection of the first circuit connection pattern on the plane where the second electrode is located intersects with the second edge;

[0057] A portion of the source / drain doped region of the active layer pattern of the reset transistor, serving as the first electrode of the reset transistor, is connected to the corresponding first electrode of the photoelectric conversion structure via the corresponding second circuit connection pattern, and an orthographic projection of the second circuit connection pattern on the plane where the second electrode is located intersects with the third edge;

[0058] A portion of the source / drain doped region of the active layer pattern of the reset transistor, serving as the second electrode of the reset transistor, is connected to the corresponding reset voltage supply line via the corresponding third circuit connection pattern, and an orthographic projection of the third circuit connection pattern on the plane where the second electrode is located intersects with the second edge;

[0059] The part of the source-drain doping region of the active layer pattern of the source follower transistor, which serves as the first electrode of the source follower transistor, is connected to the corresponding working voltage supply line through the corresponding fourth circuit connection pattern, and the orthographic projection of the fourth circuit connection pattern on the plane where the second electrode is located intersects with the first edge.

[0060] In some embodiments, the source follower transistor is the stacked transistor.

[0061] In some embodiments, the gate of the reset transistor is disposed on the same layer as the gate of the source follower transistor, and the gate of the select transistor is disposed on the same layer as the gate of the source follower transistor;

[0062] The active layer pattern of the reset transistor and the active layer pattern of the source follower transistor are arranged on the same layer, and the orthographic projection of the active layer pattern of the reset transistor on the substrate does not overlap with the orthographic projection of the photoelectric conversion structure located in the same detection pixel unit on the substrate;

[0063] The active layer pattern of the selection transistor is arranged on the same layer as the active layer pattern of the source follower transistor, and the orthographic projection of the active layer pattern of the selection transistor on the substrate does not overlap with the orthographic projection of the photoelectric conversion structure located in the same detection pixel unit on the substrate.

[0064] In some embodiments, the reset transistor and the select transistor are both the stacked transistors;

[0065] The source follower transistor is located between the photoelectric conversion structure and the substrate.

[0066] In some embodiments, a material of the active layer pattern of the source follower transistor includes amorphous silicon or polycrystalline silicon.

[0067] In some embodiments, the channel region of the active layer pattern of the source follower transistor is located within the region covered by the orthographic projection of the photoelectric conversion structure on the substrate within the same detection pixel unit;

[0068] The orthographic projection of at least part of the source-drain doping region of the active layer pattern of the source follower transistor on the substrate is located outside the area covered by the orthographic projection of the photoelectric conversion structure on the substrate in the same detection pixel unit.

[0069] In a second aspect, an embodiment of the present disclosure further provides an image sensor, which includes: a light detection substrate as provided in the first aspect.

[0070] In a third aspect, an embodiment of the present disclosure further provides an electronic device, comprising:

[0071] The image sensor as provided in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] FIG1 is a schematic diagram of a circuit structure of a detection pixel unit in a light detection substrate provided by an embodiment of the present disclosure;

[0073] FIG2 is a schematic top view of the detection pixel unit shown in FIG1 ;

[0074] FIG3 is a schematic top view of a plurality of detection pixel units in the present disclosure;

[0075] FIG4 is a schematic cross-sectional view taken along the line AA' in FIG2 ;

[0076] 5A to 5E are schematic cross-sectional views of an intermediate structure of a light detection substrate during the process of preparing the light detection substrate;

[0077] 6A to 6E are schematic top views of the intermediate structure of the light detection substrate during the process of preparing the light detection substrate;

[0078] 7 is a schematic diagram of a curve showing the light transmittance of the active layer pattern and the gate of the stacked transistor and the quantum energy efficiency of the photoelectric conversion structure in an embodiment of the present disclosure;

[0079] 8 is a schematic diagram comparing negative bias temperature illumination stress characteristics of a transistor whose active layer pattern uses an oxide semiconductor material doped with a rare earth element and a transistor whose active layer pattern uses a conventional oxide semiconductor material not doped with a rare earth element;

[0080] FIG9 is a schematic diagram comparing the threshold voltages of transistors when a shielding electrode is provided below the transistor and when no shielding electrode is provided below the transistor;

[0081] FIG10 is a schematic diagram of another circuit structure of a detection pixel unit in a light detection substrate provided by an embodiment of the present disclosure;

[0082] FIG11 is a schematic top view of the detection pixel unit shown in FIG10 ;

[0083] FIG12 is a schematic cross-sectional view taken along the line BB' in FIG11;

[0084] FIG13 is a schematic cross-sectional view taken along the CC' line in FIG11;

[0085] FIG14 is a schematic cross-sectional view of FIG11 along the DD' direction;

[0086] FIG15 is a cross-sectional schematic diagram of a portion of the light detection substrate in which the detection pixel unit in the light detection substrate adopts the circuit structure shown in FIG10 ;

[0087] FIG16 is another cross-sectional schematic diagram of a portion of the light detection substrate when the detection pixel unit in the light detection substrate adopts the circuit structure shown in FIG10 . DETAILED DESCRIPTION

[0088] To enable those skilled in the art to better understand the technical solution of the present invention, a light detection substrate, an image sensor, and an electronic device provided by the present invention are described in detail below with reference to the accompanying drawings.

[0089] Many specific details of the present disclosure are described below, such as component structures, materials, dimensions, processing techniques, and technologies, to provide a clearer understanding of the present disclosure. However, as will be appreciated by those skilled in the art, the present disclosure may be implemented without following these specific details.

[0090] The terms "first", "second" and similar terms used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms "include" or "comprise" and similar terms mean that the elements or objects preceding the term include the elements or objects listed after the term and their equivalents, without excluding other elements or objects. The terms "coupled" or "connected" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0091] The transistors used in the embodiments of the present disclosure can all be thin film transistors or field effect transistors or other devices with the same characteristics. The transistor in the present disclosure includes a gate and an active layer pattern, wherein the active layer pattern includes a channel region and a source and drain doped region. Among them, the source and drain doped region refers to a region in which the corresponding position has a certain conductivity by conducting a conductor process on the semiconductor material, such as by doping. The source and drain doped region on the active layer pattern can be used as the source and drain of the transistor; the drain and source of each transistor in the embodiment of the present disclosure are actually no different. Here, only in order to distinguish the two poles of the transistor other than the control electrode (i.e., the gate), one of the drain and source is called the first pole, and the other is called the second pole. The channel region refers to the region on the active pattern that is confined between the source and drain and can conduct electricity when the transistor is in the on state (controlled by the gate voltage); generally, the channel region is the region on the active layer pattern that overlaps with the gate in a direction perpendicular to the substrate.

[0092] In addition, the two structures described in the embodiment of the present disclosure are arranged in the same layer, which means that the two structures are formed based on patterning of the same material film layer; that is, the two structures can be simultaneously manufactured by patterning the same material film layer.

[0093] As used in the embodiments of the present disclosure, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean that the difference from the stated value is within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5%.

[0094] In an APS structure, the operating state of the thin-film transistors (TFTs) within the signal readout circuit directly impacts the reading of electrical signals, making the stability of the TFTs particularly important. However, in actual applications, it has been found that the semiconductor materials contained in the active layer patterns within TFTs are extremely susceptible to the effects of water, oxygen, and hydrogen, leading to reduced stability. Hydrogen permeation is particularly susceptible, as hydrogen can cause the semiconductor materials contained in the active layer patterns to become conductive, altering the electrical properties of the TFTs.

[0095] Specifically, in the related art, all thin-film transistors within the signal readout circuit are located between the photodiode and the substrate; that is, the fabrication process for all thin-film transistors in the related art is completed before the photodiode fabrication process. The deposition process of the photodiode generates a large number of hydrogen-related particles. When these hydrogen-related particles penetrate into the channel region of the active layer pattern within the thin-film transistor, they can cause changes in the electrical characteristics of the channel region, such as a significant shift in the threshold voltage of the thin-film transistor, thereby affecting the overall performance of the APS.

[0096] In addition, in related technologies, thin-film transistors and photodiodes are staggered; in high-resolution products, when the pixel size is small, the effective area of ​​the photodiode is compressed, resulting in a weaker electrical signal output by the photodiode, which is not conducive to subsequent detection.

[0097] In order to effectively improve at least one of the technical problems existing in the related art, an embodiment of the present disclosure provides a light detection substrate.

[0098] Figure 1 is a schematic diagram of a circuit structure of a detection pixel unit in a light detection substrate provided in an embodiment of the present disclosure, Figure 2 is a schematic diagram of a top view of the detection pixel unit shown in Figure 1, Figure 3 is a schematic diagram of a top view of multiple detection pixel units in the present disclosure, Figure 4 is a schematic diagram of a cross-section taken along the A-A' line in Figure 2, Figures 5A to 5E are schematic diagrams of a cross-section of an intermediate structure of a light detection substrate during the preparation of the light detection substrate, and Figures 6A to 6E are schematic diagrams of a top view of an intermediate structure of a light detection substrate during the preparation of the light detection substrate. As shown in Figures 1 to 6E, the light detection substrate includes: a base substrate and multiple detection pixel units.

[0099] Among them, the detection pixel unit is located on the substrate GL, and the detection pixel unit includes: a signal reading circuit 1 and a photoelectric conversion structure 3; the signal reading circuit 1 includes: at least one transistor, the transistor includes a gate and an active layer pattern, the active layer pattern includes: a channel region and a source-drain doping region; at least one transistor in the signal reading circuit 1 is a stacked transistor MR, the stacked transistor MR is located on the side of the photoelectric conversion structure 3 away from the substrate GL, the positive projection of the active layer pattern of the stacked transistor MR on the substrate GL overlaps with the positive projection of the photoelectric conversion structure 3 in the same detection pixel unit on the substrate GL, and the material of the gate of the stacked transistor MR includes: a transparent conductive material.

[0100] In the disclosed embodiment, at least one transistor in the signal readout circuit 1 is configured as a stacked transistor MR, which is located on the side of the photoelectric conversion structure 3 away from the substrate GL. In other words, the stacked transistor MR is fabricated after the photoelectric conversion structure 3. This prevents hydrogen-related particles from penetrating into the channel region of the stacked transistor MR during the fabrication of the photoelectric conversion structure 3, thereby ensuring stable electrical characteristics of the channel region of the stacked transistor MR. Furthermore, optionally, the orthographic projection of the channel region of the active layer pattern of the stacked transistor MR on the substrate GL overlaps with the orthographic projection of the photoelectric conversion structure 3 within the same detection pixel unit on the substrate GL.

[0101] At the same time, the active layer pattern of the stacked transistor MR overlaps with the positive projection of the photoelectric conversion structure 3 on the substrate GL. Such a design allows the stacked transistor MR and the photoelectric conversion structure 3 to be stacked in a direction perpendicular to the substrate GL, which is beneficial to increasing the overall size of the photoelectric conversion structure 3 in the detection pixel unit; in addition, by stacking the stacked transistor MR and the photoelectric conversion structure 3, the gate of the stacked transistor MR will inevitably overlap with the photoelectric conversion structure 3 in a direction perpendicular to the substrate GL. At this time, the gate material of the stacked transistor MR is prepared with a transparent conductive material, which can avoid the gate of the stacked transistor MR blocking the light directed to the photoelectric conversion structure 3, and can effectively increase the actual lighting area of ​​the photoelectric conversion structure 3, thereby increasing the intensity of the electrical signal output by the photodiode, which is convenient for subsequent detection.

[0102] Based on the above content, it can be seen that the technical solution disclosed in the present invention can, on the one hand, effectively avoid the influence of the preparation process of the photoelectric conversion structure 3 on the channel area of ​​at least part of the transistors in the signal reading circuit 1 (which can be designed according to actual needs, and specific examples can be seen in the following description); on the other hand, it is beneficial to improve the overall size and actual lighting area of ​​the photoelectric conversion structure 3, which is beneficial to improve the intensity of the electrical signal output by the photodiode, and facilitate subsequent detection.

[0103] In some embodiments, the gate material of the stacked transistor MR includes indium tin oxide (ITO).

[0104] FIG7 is a diagram showing the curves of the light transmittance of the active layer pattern of the stacked transistor MR, the light transmittance of the gate, and the quantum energy efficiency of the photoelectric conversion structure in the embodiment of the present disclosure. As shown in FIG7 , FIG7 shows the curves of the light transmittance of the active layer pattern and the gate of the stacked transistor MR corresponding to light of different wavelengths, and the curves of the quantum energy efficiency of the photoelectric conversion structure 3 corresponding to light of different wavelengths. Based on FIG7 , it can be seen that when the wavelength of light is in the range of 530nm to 570nm, the active layer pattern and the gate of the stacked transistor MR exhibit better light transmittance and the photoelectric conversion structure 3 has a higher quantum energy efficiency. Therefore, in the embodiment of the present disclosure, the light used for detection is preferably green light, and the central wavelength is about 550nm.

[0105] In the disclosed embodiment, the gate of the stacked transistor MR is made of a transparent conductive material. This means that light passing through the gate of the stacked transistor MR can illuminate the channel region of the stacked transistor MR (and subsequently pass through the channel region to reach the photoelectric conversion structure 3). In this case, the light will have a certain impact on the electrical characteristics of the channel region of the stacked transistor MR, causing the electrical characteristics of the channel region of the stacked transistor MR to shift.

[0106] To this end, in the embodiments of the present disclosure, the material of the active layer pattern of the stacked transistor MR is improved; specifically, the material of the active layer pattern of the stacked transistor MR adopts a metal oxide semiconductor material with high mobility and high photostability, such as any one or more of indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium gallium oxide (IGO), and indium zinc tin oxide (IZTO) series materials doped with rare earth elements. Specifically, it can be indium zinc oxide doped with lanthanum (La) or praseodymium (Pr), indium zinc oxide doped with cerium (Ce), indium gallium zinc oxide (IGZO) doped with praseodymium, etc.

[0107] FIG8 is a schematic diagram comparing the negative bias temperature illumination stress (NBTIS) characteristics of a transistor whose active layer pattern uses an oxide semiconductor material doped with a rare earth element and a transistor whose active layer pattern uses a conventional oxide semiconductor material not doped with a rare earth element. As shown in FIG8 , the negative shift in threshold voltage under illumination (approximately 0.5 V) of the transistor whose active layer pattern uses an oxide semiconductor material doped with a rare earth element is significantly smaller than the negative shift in threshold voltage under illumination (approximately 3.0 V) of the transistor whose active layer pattern uses an oxide semiconductor material not doped with a rare earth element. In other words, the negative bias temperature illumination stress (NBTIS) characteristics of the transistor whose active layer pattern uses an oxide semiconductor material doped with a rare earth element are superior to those of the transistor whose active layer pattern uses an oxide semiconductor material not doped with a rare earth element. Therefore, by doping the oxide semiconductor material with rare earth elements, the light stability of the transistor can be improved.

[0108] In the embodiment of the present disclosure, by using a rare earth element-doped oxide semiconductor material as the material of the active layer pattern of the stacked transistor MR, the light stability of the channel region of the stacked transistor MR can be effectively improved.

[0109] In some embodiments, the orthographic projection of the active layer pattern of the stacked transistor MR on the base substrate GL is located within the area covered by the orthographic projection of the photoelectric conversion structure 3 on the base substrate GL within the same detection pixel unit. In this case, the active layer pattern of the stacked transistor MR is completely placed above the photoelectric conversion structure 3, which helps to increase the overall size of the photoelectric conversion structure 3.

[0110] In some embodiments, the photoelectric conversion structure 3 includes: a PIN photodiode and a PN photosensitive diode. The operating state of the optical sensor can be controlled by controlling the voltage applied to the first electrode 301 and the second electrode 303. The photoelectric conversion layer 302 may include a stacked P-type semiconductor layer (e.g., a P-type Si layer) and an N-type semiconductor layer (e.g., an N-type Si layer). In this case, the photoelectric conversion structure 3 is a PN photodiode. The photoelectric conversion layer 302 may also include a stacked P-type semiconductor layer, an intrinsic semiconductor layer (e.g., an intrinsic Si layer), and an N-type semiconductor layer. In this case, the photoelectric conversion structure 3 is a PIN photodiode. For example, the intrinsic semiconductor layer is a-Si material, the P-type semiconductor layer is a-Si doped with B ions, and the N-type semiconductor layer is a-Si doped with P ions.

[0111] In some embodiments, the second electrode 303 is a transparent electrode and can be made of a transparent metal oxide material such as indium tin oxide, indium zinc oxide, or gallium zinc oxide. The first electrode 301 is a metal electrode and can be made of a metal material or alloy such as copper, aluminum, titanium, or molybdenum. It should be noted that in the embodiments of the present disclosure, "transparent" refers to the ability of a structure to transmit light, not to 100% transmittance.

[0112] In some embodiments, the orthographic projection area of ​​the first electrode 301 on the substrate GL is larger than the orthographic projection area of ​​the photoelectric conversion layer 302 on the substrate GL, and the orthographic projection area of ​​the photoelectric conversion layer 302 on the substrate GL is greater than or equal to the orthographic projection area of ​​the second electrode 303 on the substrate GL.

[0113] In some embodiments, the orthographic projection of the active layer pattern of the stacked transistor MR on the base substrate GL is located within the area covered by the orthographic projection of the second electrode 303 of the photoelectric conversion structure 3 on the base substrate GL in the same detection pixel unit.

[0114] In practical applications, a DC bias voltage is applied to the second electrode 303. In this case, the second electrode 303 can act as a shielding electrode to shield and protect the active layer pattern (including the channel region) of the stacked transistor MR. For example, this can suppress the influence of substrate-induced charge on the electrical characteristics of the channel region of the stacked transistor MR. This is beneficial for improving the uniformity of the threshold voltage of the stacked transistor MR within different detection pixel units.

[0115] FIG9 is a schematic diagram comparing the threshold voltages of transistors when a shielding electrode is provided under the transistor and when no shielding electrode is provided. As shown in FIG9 , the difference in the threshold voltages of 10 different samples S1 to S10 when a shielding electrode is provided under the transistor is significantly smaller than the difference in the threshold voltages of the 10 different samples S1 to S10 when no shielding electrode is provided.

[0116] In some embodiments, the light detection substrate further includes: a plurality of gate lines GATE arranged in sequence along a first direction X and a plurality of signal read lines RL arranged in sequence along a second direction Y, the gate lines GATE extending along the second direction Y, the signal read lines RL extending along the first direction X, and the first direction X intersecting with the second direction Y; the plurality of gate lines GATE and the plurality of signal read lines RL define a plurality of detection pixel units, and the signal read circuits 1 in the detection pixel units are connected to the corresponding gate lines GATE and the corresponding signal read lines RL; the light detection substrate further includes: a plurality of bias voltage supply lines Vin; the photoelectric conversion structure 3 includes: a first electrode 301, a photoelectric conversion layer 302, and a second electrode 303 arranged in sequence along a direction away from the base substrate GL, the first electrode 301 being connected to the corresponding signal read circuit 1, and the second electrode 303 being connected to the corresponding bias voltage supply line Vin.

[0117] In some embodiments, the light detection substrate further includes: a circuit connection pattern layer, the circuit connection pattern layer is located on the side of the stacked transistor MR away from the base substrate GL, the circuit connection pattern layer includes: multiple circuit connection patterns, the circuit connection patterns are connected to the source and drain doping regions of the corresponding transistors.

[0118] In some embodiments, the signal reading line RL is located on a side of the circuit connection pattern layer away from the base substrate GL; the circuit connection pattern layer includes: a first circuit connection pattern CL1; the signal reading line RL is connected to the source and drain doping regions of the corresponding transistor in the signal reading circuit 1 through the corresponding first circuit connection pattern CL1.

[0119] In some embodiments, the material of the circuit connection pattern layer includes a transparent conductive material. In the disclosed embodiment, the circuit connection pattern in the circuit connection pattern layer needs to be connected to the source and drain doped regions of the corresponding transistor. In other words, the circuit connection pattern will overlap with the region where the photoelectric conversion structure 3 (particularly the second electrode 303) is located. To prevent the circuit connection pattern from blocking light directed to the photoelectric conversion structure 3, the circuit connection pattern layer is preferably made of a transparent conductive material, such as indium tin oxide.

[0120] In some embodiments, the first electrode 301, the bias voltage supply line Vin, and the gate line GATE are disposed in the same layer. That is, the first electrode 301, the bias voltage supply line Vin, and the gate line GATE can be simultaneously manufactured in one patterning process, which is beneficial for shortening the production cycle.

[0121] In some embodiments, the light detection substrate further includes a bias transmission pattern CP, through which the second electrode 303 of the photoelectric conversion structure 3 is connected to a corresponding bias voltage supply line Vin. The bias transmission pattern CP is provided on the same layer as the gate of the stacked transistor MR. In other words, the bias transmission pattern CP can be fabricated simultaneously with the gate of the stacked transistor MR using a single patterning process, thereby shortening the production cycle.

[0122] The light detection substrate in the present disclosure will be described in detail below with reference to specific examples.

[0123] Continuing to refer to Figures 1 to 6E, in some embodiments, the signal reading circuit 1 includes: a switching transistor M0; a gate M0_g of the switching transistor M0 is connected to the corresponding gate line GATE, a first electrode of the switching transistor M0 is connected to the first electrode 301 of the photoelectric conversion structure 3, and a second electrode of the switching transistor M0 is connected to the corresponding signal reading line RL; the switching transistor M0 is a stacked transistor MR.

[0124] In the drawings, M0_g represents the gate of the switching transistor M0, and M0_a represents the active layer pattern (including the channel region and the source and drain doping regions) of the switching transistor M0.

[0125] In some embodiments, the bias voltage supply line Vin and the gate line GATE are arranged in the same layer, and the signal read line RL extends along the second direction Y; the bias voltage supply line Vin and the gate line GATE corresponding to the detection pixel unit are respectively located on opposite sides of the photoelectric conversion structure 3 in the detection pixel unit in the first direction X.

[0126] In some embodiments, the second electrode 303 has a third edge EG3 and a fourth edge EG4, and the third edge EG3 and the fourth edge EG4 are arranged opposite to each other in the first direction X; a gate line GATE corresponding to the detection pixel unit is located on a side close to the fourth edge EG4 of the second electrode 303 in the detection pixel unit, and the orthographic projection of the gate M0_g of the switching transistor M0 on the plane where the second electrode 303 is located intersects with the fourth edge EG4; a bias voltage supply line Vin corresponding to the detection pixel unit is located on a side close to the third edge EG3 of the second electrode 303 in the detection pixel unit; the light detection substrate further includes: a bias transmission pattern CP, the second electrode 303 of the photoelectric conversion structure 3 is connected to the corresponding bias voltage supply line Vin via the bias transmission pattern CP, the bias transmission pattern CP is arranged on the same layer as the gate of the stacked transistor MR, and the orthographic projection of the bias transmission pattern CP on the plane where the second electrode 303 is located intersects with the third edge EG3.

[0127] In some embodiments, the second electrode 303 further has a first edge EG1 and a second edge EG2 , and the first edge EG1 and the second edge EG2 are disposed opposite to each other in the second direction Y.

[0128] The light detection substrate further includes: a wiring arrangement layer, which is located on the side of the stacked transistor MR away from the base substrate GL, and the wiring arrangement layer includes: a signal read line RL; a signal read line RL corresponding to the detection pixel unit, which is located on a side close to the first edge EG1 of the second electrode 303 in the detection pixel unit.

[0129] The light detection substrate further includes a circuit connection pattern layer, which is located between the stacked transistor MR and the wiring layout layer. The circuit connection pattern layer includes a first circuit connection pattern CL1 and a second circuit connection pattern CL2.

[0130] The portion of the source-drain doped region of the active layer pattern M0_a of the switching transistor M0, which serves as the first electrode of the switching transistor M0, is connected to the corresponding signal reading line RL through the corresponding first circuit connection pattern CL1, and the orthographic projection of the first circuit connection pattern CL1 on the plane where the second electrode 303 is located intersects with the first edge EG1.

[0131] The portion of the source-drain doped region of the active layer pattern M0_a of the switching transistor M0, which serves as the second electrode of the switching transistor M0, is connected to the first electrode 301 of the photoelectric conversion structure 3 in the same detection pixel unit through the corresponding second circuit connection pattern CL2. The orthographic projection of the second circuit connection pattern CL2 on the plane where the second electrode 303 is located intersects with the fourth edge EG4.

[0132] 5A to 6E , the preparation process of the light detection substrate may include the following steps:

[0133] First, referring to Figures 5A and 6A, a first conductive layer is formed on one side of the substrate GL, and the first conductive layer includes: a first electrode 301 of the photoelectric conversion structure 3 and a structure arranged on the same layer as the first electrode 301, for example, a gate line GATE and a bias voltage supply line Vin; optionally, the material of the first conductive layer is a metal material.

[0134] 5B and 6B , a photoelectric conversion layer 302 and a second electrode 303 are sequentially formed to obtain a photoelectric conversion structure 3. Then, a buffer layer BUF is formed on a side of the photoelectric conversion structure 3 away from the base substrate GL.

[0135] 5C and 6C , an active functional layer is formed on the side of the buffer layer BUF away from the substrate GL. The active functional layer includes active layer patterns of each transistor. Optionally, the active layer pattern includes an oxide semiconductor material doped with a rare earth element.

[0136] Next, a gate insulating layer GI is formed on a side of the active layer pattern away from the base substrate GL.

[0137] Next, referring to Figures 5D and 6D, a second conductive layer is formed on the side of the gate insulation layer GI away from the base substrate GL, and the second conductive layer includes: a gate of the stacked transistor MR and a structure arranged on the same layer as the gate of the stacked transistor MR, such as a bias transmission pattern CP; optionally, the material of the second conductive layer is a transparent conductive material.

[0138] Next, an interlayer dielectric layer ILD is formed.

[0139] Next, as shown in FIG. 5E and FIG. 6E , a circuit connection pattern layer is formed on a side of the interlayer dielectric layer ILD away from the substrate GL. The circuit connection pattern layer includes a plurality of circuit connection patterns connected to the source and drain doped regions of corresponding transistors. Optionally, the circuit connection pattern layer includes a transparent conductive material.

[0140] Taking the preparation of the detection pixel unit shown in Figure 2 as an example, the circuit connection pattern layer includes: a first circuit connection pattern CL1 and a second circuit connection pattern CL2. The portion of the source and drain doped regions of the active layer pattern M0_a of the switching transistor M0, which serves as the first electrode of the switching transistor M0, is connected to the signal readout line RL to be formed later via the corresponding first circuit connection pattern CL1. The portion of the source and drain doped regions of the active layer pattern M0_a of the switching transistor M0, which serves as the second electrode of the switching transistor M0, is connected to the first electrode 301 of the photoelectric conversion structure 3 within the same detection pixel unit via the corresponding second circuit connection pattern CL2.

[0141] Next, a first passivation layer PVX1 and a planarization layer PLN are formed in sequence.

[0142] 2 and 4 , a wiring arrangement layer is formed, which includes a signal readout line RL connected to the source and drain doped regions of the corresponding transistor via a corresponding first circuit connection pattern CL1. Optionally, the wiring arrangement layer is made of a metal material.

[0143] Optionally, a second passivation layer PVX2 is further provided on a side of the wiring arrangement layer away from the substrate GL.

[0144] Figure 10 is another circuit structure schematic diagram of a detection pixel unit in a light detection substrate provided in an embodiment of the present disclosure. Figure 11 is a top view schematic diagram of the detection pixel unit shown in Figure 10. Figure 12 is a cross-sectional schematic diagram along the BB' direction in Figure 11. Figure 13 is a cross-sectional schematic diagram along the C-C' direction in Figure 11. Figure 14 is a cross-sectional schematic diagram along the D-D' direction in Figure 11. As shown in Figures 10 to 14, the signal reading circuit 1 includes: a reset transistor M1, a source follower transistor M2, and a selection transistor M3.

[0145] The gate M1_g of the reset transistor M1 is connected to the reset control line RESET, the first electrode of the reset transistor M1 is connected to the reset voltage supply line Vrst, and the second electrode of the reset transistor M1 is connected to the first electrode 301 of the photoelectric conversion structure 3. The gate M2_g of the source follower transistor M2 is connected to the first electrode 301 of the photoelectric conversion structure 3, the first electrode of the source follower transistor M2 is connected to the operating voltage supply line Vdd, and the second electrode of the source follower transistor M2 is connected to the first electrode of the select transistor M3. The gate M3_g of the select transistor M3 is connected to the corresponding gate line GATE, and the second electrode of the select transistor M3 is connected to the corresponding signal read line RL.

[0146] In the accompanying drawings, M1_g represents the gate of the reset transistor M1, M1_a represents the active layer pattern of the reset transistor M1 (including the channel region and the source-drain doped region); M2_g represents the gate of the source follower transistor M2, M2_a represents the active layer pattern of the source follower transistor M2 (including the channel region and the source-drain doped region); M3_g represents the gate of the selection transistor M3, M2_a represents the active layer pattern of the selection transistor M3 (including the channel region and the source-drain doped region).

[0147] 11 to 14 , in some embodiments, the reset transistor M1 , the source follower transistor M2 , and the select transistor M3 are all stacked transistors MR.

[0148] In some embodiments, the second electrode 303 has a first edge EG1, a second edge EG2, a third edge EG3, and a fourth edge EG4. The first edge EG1 and the second edge EG2 are oppositely disposed in the second direction Y, and the third edge EG3 and the fourth edge EG4 are oppositely disposed in the first direction X.

[0149] The second electrode 303 includes a first subregion and a second subregion arranged in the second direction Y. The channel region of the source follower transistor M2 is located in the first subregion, and the channel regions of the reset transistor M1 and the select transistor M3 are both located in the second subregion.

[0150] The orthographic projection of the gate M2_g of the source follower transistor M2 on the plane where the second electrode 303 is located intersects with the third edge EG3, the orthographic projection of the gate M2_1 of the reset transistor M1 on the plane where the second electrode 303 is located intersects with the second edge EG2, and the orthographic projection of the gate M3_g of the selection transistor M3 on the plane where the second electrode 303 is located intersects with the fourth edge EG4.

[0151] In some embodiments, the reset control line RESET, the bias voltage supply line Vin, the gate line GATE, and the first electrode 301 are arranged in the same layer, and the reset control line RESET and the bias voltage supply line Vin both extend along the second direction Y.

[0152] One of the bias voltage supply line Vin and the reset control line RESET corresponding to the detection pixel unit is located near the third edge EG3 of the second electrode 303 in the detection pixel unit, and the other is located near the fourth edge EG4 of the second electrode 303 in the detection pixel unit.

[0153] A gate line GATE corresponding to the detection pixel unit is located on a side close to the fourth edge EG4 of the second electrode 303 in the detection pixel unit;

[0154] The portion of the first electrode 301 of the photoelectric conversion structure 3 that contacts the gate M2_g of the corresponding source follower transistor M2 is located on a side close to the third edge EG3 of the second electrode 303 in the detection pixel unit.

[0155] In some embodiments, the light detection substrate further includes: a wiring arrangement layer, which is located on a side of the stacked transistor MR away from the base substrate GL, and the wiring arrangement layer includes: a reset voltage supply line Vrst, an operating voltage supply line Vdd, and a signal reading line RL, and the reset voltage supply line Vrst and the operating voltage supply line Vdd both extend along the first direction X.

[0156] An operating voltage supply line Vdd corresponding to the detection pixel unit is located on a side close to the first edge EG1 of the second electrode 303 in the detection pixel unit.

[0157] A reset voltage supply line Vrst and a signal reading line RL corresponding to the detection pixel unit are both located on a side close to the second edge EG2 of the second electrode 303 in the detection pixel unit.

[0158] In some embodiments, the optical detection substrate further includes: a circuit connection pattern layer, the circuit connection pattern layer being located between the stacked transistor MR and the routing layout layer, the circuit connection pattern layer including: a first circuit connection pattern CL1, a second circuit connection pattern CL2, a third circuit connection pattern CL3, and a fourth circuit connection pattern CL4.

[0159] Among them, the part of the source-drain doped region of the active layer pattern M3_a of the selection transistor M3, which serves as the second electrode of the selection transistor M3, is connected to the corresponding signal reading line RL through the corresponding first circuit connection pattern CL1, and the orthographic projection of the first circuit connection pattern CL1 on the plane where the second electrode 303 is located intersects with the second edge EG2.

[0160] The portion of the source-drain doped region of the active layer pattern M1_a of the reset transistor M1, which serves as the first electrode of the reset transistor M1, is connected to the first electrode 301 of the corresponding photoelectric conversion structure 3 through the corresponding second circuit connection pattern, and the orthographic projection of the second circuit connection pattern CL2 on the plane where the second electrode 303 is located intersects with the third edge EG3.

[0161] The portion of the source / drain doped region of the active layer pattern M1_a of the reset transistor M1, which serves as the second electrode of the reset transistor M1, is connected to the corresponding reset voltage supply line Vrst through the corresponding third circuit connection pattern. The orthographic projection of the third circuit connection pattern CL3 on the plane where the second electrode 303 is located intersects with the second edge EG2.

[0162] The portion of the source-drain doped region of the active layer pattern M2_a of the source follower transistor M2, which serves as the first electrode of the source follower transistor M2, is connected to the corresponding operating voltage supply line Vdd through the corresponding fourth circuit connection pattern, and the orthographic projection of the fourth circuit connection pattern CL4 on the plane where the second electrode 303 is located intersects with the first edge EG1.

[0163] FIG11 only illustrates an example of a source follower transistor M2 including two gates M2_g. Setting two gates is beneficial to improving the current saturation of the source follower transistor M2. This is only an optional implementation in the embodiment of the present disclosure and does not limit the technical solution of the present disclosure.

[0164] It should be noted that when the reset transistor M1, the source follower transistor M2 and the selection transistor M3 are all stacked transistors MR, the arrangement of the reset transistor M1, the source follower transistor M2 and the selection transistor M3 above the photoelectric conversion structure 3 shown in Figure 11 is only an optional real-time solution in the embodiment of the present disclosure, and it will not limit the technical solution of the present disclosure.

[0165] It should be noted that the preparation process of the light detection substrate including the detection pixel unit shown in Figure 11 is similar to the preparation process of the light detection substrate including the detection pixel unit shown in Figure 2. For related descriptions, please refer to the corresponding content in the previous embodiment and will not be repeated here.

[0166] FIG15 is a cross-sectional schematic diagram of a portion of the light detection substrate when the detection pixel unit in the light detection substrate adopts the circuit structure shown in FIG10 . As shown in FIG15 , unlike the previous embodiment in which the reset transistor M1, the source follower transistor M2, and the selection transistor M3 are all stacked transistors MR, in the scheme shown in FIG15 , the source follower transistor M2 is selectively designed as a stacked transistor MR, while the reset transistor M1 and the selection transistor M3 are not stacked transistors.

[0167] As an optional embodiment, the gate M1_g of the reset transistor M1 is disposed on the same layer as the gate M2_g of the source-follower transistor M2, and the gate M3_g of the select transistor M3 is disposed on the same layer as the gate M2_g of the source-follower transistor M2. The active layer pattern M1_a of the reset transistor M1 is disposed on the same layer as the active layer pattern M2_a of the source-follower transistor M2, and the orthographic projection of the active layer pattern M1_a of the reset transistor M1 on the substrate GL does not overlap with the orthographic projection of the photoelectric conversion structure 3 located within the same detection pixel unit on the substrate GL. The active layer pattern M3_a of the select transistor M3 is disposed on the same layer as the active layer pattern M2_a of the source-follower transistor M2, and the orthographic projection of the active layer pattern M3_a of the select transistor M3 on the substrate GL does not overlap with the orthographic projection of the photoelectric conversion structure 3 located within the same detection pixel unit on the substrate GL.

[0168] That is to say, although the reset transistor and the selection transistor M3 are located on the side of the photoelectric conversion structure 3 away from the base substrate GL, the active layer pattern M3_a of the reset transistor and the selection transistor M3 does not overlap with the photoelectric conversion structure 3 in the direction perpendicular to the base substrate GL.

[0169] Generally, the source follower transistor M2 is the largest and has the highest requirement for electrical characteristic stability. Therefore, the source follower transistor M2 can be selectively placed directly above the photoelectric conversion structure 3 as a reset transistor, while the other reset transistors are placed on the sides of the photoelectric conversion structure 3. This design can facilitate the wiring design of the detection pixel unit while meeting the electrical characteristic stability requirement of the source follower transistor M2.

[0170] It should be noted that the preparation process of the light detection substrate including the detection pixel unit shown in FIG15 is similar to the preparation process of the light detection substrate including the detection pixel unit shown in FIG2 . For related descriptions, please refer to the corresponding contents in the previous embodiments and will not be repeated here.

[0171] FIG16 is another cross-sectional schematic diagram of a portion of the light detection substrate when the detection pixel unit in the light detection substrate adopts the circuit structure shown in FIG10 . As shown in FIG16 , unlike the scheme shown in FIG15 in which the source follower transistor M2 is selectively designed as a stacked transistor MR, the scheme shown in FIG16 selectively designs both the reset transistor M1 and the selection transistor M3 as stacked transistors MR, and the source follower transistor M2 is located between the photoelectric conversion structure 3 and the substrate GL.

[0172] Optionally, the active layer pattern M2_a of the source-follower transistor M2 includes amorphous silicon or polycrystalline silicon; low-temperature polycrystalline silicon is used for illustration herein. In this case, the light detection substrate is a light detection substrate based on LTPO technology. The source-follower transistor M2 is a low-temperature polycrystalline silicon transistor, which improves transconductance and signal amplification. The reset transistor M1 and the select transistor M3 are sampling metal oxide transistors, which effectively reduces off-state leakage current.

[0173] In some embodiments, the channel region M2_a1 of the active layer pattern M2_a of the source follower transistor M2 is located within the area covered by the orthographic projection of the photoelectric conversion structure 3 on the substrate GL in the same detection pixel unit; the orthographic projection of at least part of the source-drain doping region M2_a2 of the active layer pattern M2_a of the source follower transistor M2 on the substrate GL is located outside the area covered by the orthographic projection of the photoelectric conversion structure 3 on the substrate GL in the same detection pixel unit.

[0174] In the present disclosure, the low-temperature polysilicon source follower transistor M2 is placed below the photoelectric conversion structure 3 and stacked with the photoelectric conversion structure 3 , which is beneficial to increasing the overall size of the photoelectric conversion structure 3 .

[0175] It should be noted that the preparation process of the light detection substrate including the detection pixel unit shown in Figure 16 not only includes the preparation steps of the light detection substrate used for the detection pixel unit shown in Figure 2, but also includes the step of forming the source follower transistor M2 before the step of forming the first conductive layer (for example, the source follower transistor can be prepared using a low-temperature polysilicon transistor preparation process). The specific process will not be repeated here.

[0176] It should be noted that the present disclosure does not limit the relative positions of the reset transistor M1 , the source follower transistor M2 , and the selection transistor M3 in the detection pixel unit in FIG. 15 and FIG. 16 in a direction parallel to the base substrate GL.

[0177] Based on the same inventive concept, an embodiment of the present disclosure further provides an image sensor, which includes the light detection substrate provided in the above embodiment. For a detailed description of the light detection substrate, please refer to the previous description herein and will not be repeated here.

[0178] In addition to the light detection substrate, the image sensor may also include peripheral circuits such as row driver circuits, column driver circuits, amplifier circuits, and pre-processing circuits. These circuits are conventional structures in the art, and the specific circuit structures and working processes are not described in detail herein.

[0179] Based on the same inventive concept, an embodiment of the present disclosure further provides an electronic device, which includes an image sensor. The image sensor adopts the above-mentioned image sensor. The electronic device can be a digital camera, a mobile phone, a tablet computer, a laptop computer, etc.

[0180] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A light detection substrate, wherein: include: substrate substrate; A plurality of detection pixel units are located on the substrate, and the detection pixel units include: a signal reading circuit and a photoelectric conversion structure; The signal reading circuit includes: at least one transistor, the transistor includes a gate and an active layer pattern, the active layer pattern includes: a channel region and a source-drain doping region; At least one of the transistors in the signal reading circuit is a stacked transistor, which is located on a side of the photoelectric conversion structure away from the substrate. The positive projection of the active layer pattern of the stacked transistor on the substrate overlaps with the positive projection of the photoelectric conversion structure in the same detection pixel unit on the substrate. The material of the gate of the stacked transistor includes: a transparent conductive material.

2. The light detection substrate according to claim 1, wherein: The material of the active layer pattern of the stacked transistor includes: an oxide semiconductor material doped with a rare earth element.

3. The light detection substrate according to claim 1 or 2, wherein: The orthographic projection of the active layer pattern of the stacked transistor on the substrate is located within the area covered by the orthographic projection of the photoelectric conversion structure on the substrate in the same detection pixel unit.

4. The light detection substrate according to any one of claims 1 to 3, wherein: Also includes: A plurality of gate lines arranged in sequence along a first direction and a plurality of signal readout lines arranged in sequence along a second direction, the gate lines extending along the second direction, the signal readout lines extending along the first direction, the first direction intersecting the second direction; A plurality of the gate lines and a plurality of the signal reading lines define a plurality of the detection pixel units, and the signal reading circuits in the detection pixel units are connected to the corresponding gate lines and the corresponding signal reading lines; The light detection substrate further includes: a plurality of bias voltage supply lines; The photoelectric conversion structure includes: a first electrode, a photoelectric conversion layer, and a second electrode which are sequentially arranged in a direction away from the base substrate, the first electrode is connected to the corresponding signal reading circuit, and the second electrode is connected to the corresponding bias voltage supply line.

5. The light detection substrate according to claim 4, wherein: Also includes: The circuit connection pattern layer is located at a side of the stacked transistor away from the substrate, and the circuit connection pattern layer includes: a plurality of circuit connection patterns, and the circuit connection patterns are connected to the source and drain doping regions corresponding to the transistor.

6. The light detection substrate according to claim 5, wherein: The signal reading line is located on a side of the circuit connection pattern layer away from the base substrate; The circuit connection pattern layer includes: a first circuit connection pattern; a signal reading line is connected to the source and drain doping regions of the corresponding transistor in the signal reading circuit through the corresponding first circuit connection pattern.

7. The light detection substrate according to claim 5 or 6, wherein: The material of the circuit connection pattern layer includes: transparent conductive material.

8. The light detection substrate according to any one of claims 4 to 7, wherein: The first electrode, the bias voltage supply line and the gate line are arranged in the same layer.

9. The light detection substrate according to claim 8, wherein: Also includes: A bias transmission pattern, through which the second electrode of the photoelectric conversion structure is connected to the corresponding bias voltage supply line; The bias transmission pattern is arranged in the same layer as the gate of the stacked transistor.

10. The light detection substrate according to any one of claims 4 to 9, wherein: The signal reading circuit comprises: a switching transistor; The gate of the switch transistor is connected to the corresponding gate line, the first electrode of the switch transistor is connected to the first electrode of the photoelectric conversion structure, and the second electrode of the switch transistor is connected to the corresponding gate line. The pole is connected to the corresponding signal reading line; The switch transistor is the stacked transistor.

11. The light detecting substrate according to claim 10, wherein: The bias voltage supply line is arranged in the same layer as the gate line, and the signal reading line extends along the second direction; The bias voltage supply line and the gate line corresponding to the detection pixel unit are respectively located at two opposite sides of the photoelectric conversion structure in the detection pixel unit in the first direction.

12. The light detecting substrate according to claim 11, wherein: The second electrode has a third edge and a fourth edge, and the third edge and the fourth edge are arranged opposite to each other in the first direction; A gate line corresponding to the detection pixel unit is located on a side close to a fourth edge of the second electrode in the detection pixel unit, and an orthographic projection of the gate of the switch transistor on the plane where the second electrode is located intersects with the fourth edge; A bias voltage supply line corresponding to the detection pixel unit is located on a side close to the third edge of the second electrode in the detection pixel unit; The optical detection substrate also includes: a bias transmission pattern, through which the second electrode of the photoelectric conversion structure is connected to the corresponding bias voltage supply line, the bias transmission pattern is arranged on the same layer as the gate of the stacked transistor, and the orthographic projection of the bias transmission pattern on the plane where the second electrode is located intersects with the third edge.

13. The light detecting substrate according to claim 12, wherein: The second electrode further has a first edge and a second edge, and the first edge and the second edge are arranged opposite to each other in the second direction; The light detection substrate further comprises: a wiring arrangement layer, which is located on a side of the stacked transistor away from the base substrate, the wiring arrangement layer comprising: the signal readout line; One of the signal reading lines corresponding to the detection pixel unit is located on a side close to the first edge of the second electrode in the detection pixel unit; The optical detection substrate further comprises: a circuit connection pattern layer located on the stacked crystal The circuit connection pattern layer comprises: a first circuit connection pattern and a second circuit connection pattern between the tube and the wiring arrangement layer; A portion of the source-drain doped region of the active layer pattern of the switch transistor, which serves as the first electrode of the switch transistor, is connected to the corresponding signal reading line through the corresponding first circuit connection pattern, and the orthographic projection of the first circuit connection pattern on the plane where the second electrode is located intersects with the first edge; The portion of the source-drain doped region of the active layer pattern of the switching transistor serving as the second electrode of the switching transistor is connected to the first electrode of the photoelectric conversion structure in the same detection pixel unit through the corresponding second circuit connection pattern, and the orthographic projection of the second circuit connection pattern on the plane where the second electrode is located intersects with the fourth edge.

14. The light detection substrate according to any one of claims 4 to 9, wherein: The signal reading circuit includes: a reset transistor, a source follower transistor and a selection transistor; The gate of the reset transistor is connected to the reset control line, the first electrode of the reset transistor is connected to the reset voltage supply line, and the second electrode of the reset transistor is connected to the first electrode of the photoelectric conversion structure; The gate of the source follower transistor is connected to the first electrode of the photoelectric conversion structure, the first electrode of the source follower transistor is connected to the working voltage supply line, and the second electrode of the source follower transistor is connected to the first electrode of the selection transistor; The gate electrode of the selection transistor is connected to the corresponding gate line, and the second electrode of the selection transistor is connected to the corresponding signal reading line.

15. The light detecting substrate according to claim 14, wherein: The reset transistor, the source follower transistor, and the selection transistor are all stacked transistors.

16. The light detecting substrate according to claim 15, wherein: The second electrode has a first edge, a second edge, a third edge and a fourth edge, the first edge and the second edge are arranged opposite to each other in the second direction, and the third edge and the fourth edge are arranged opposite to each other in the first direction; The second electrode includes: a first sub-region and a second sub-region arranged in the second direction two sub-regions, the channel region of the source follower transistor is located in the first sub-region, and the channel region of the reset transistor and the channel region of the select transistor are both located in the second sub-region; The orthographic projection of the gate of the source follower transistor on the plane where the second electrode is located intersects with the third edge, the orthographic projection of the gate of the reset transistor on the plane where the second electrode is located intersects with the second edge, and the orthographic projection of the gate of the selection transistor on the plane where the second electrode is located intersects with the fourth edge.

17. The light detecting substrate according to claim 16, wherein: The reset control line, the bias voltage supply line, the gate line, and the first electrode are arranged in the same layer, and the reset control line and the bias voltage supply line both extend along the second direction; One of the bias voltage supply line and the reset control line corresponding to the detection pixel unit is located on a side close to the third edge of the second electrode in the detection pixel unit, and the other is located on a side of the fourth edge of the second electrode in the detection pixel unit; A gate line corresponding to the detection pixel unit is located at a side close to the fourth edge of the second electrode in the detection pixel unit; The portion of the first electrode of the photoelectric conversion structure that contacts the gate of the corresponding source follower transistor is located on a side close to the third edge of the second electrode in the detection pixel unit.

18. The light detection substrate according to claim 16 or 17, wherein: Also includes: A wiring arrangement layer is located at a side of the stacked transistor away from the substrate, the wiring arrangement layer comprising: the reset voltage supply line, the working voltage supply line and the signal reading line, the reset voltage supply line and the working voltage supply line both extending along a first direction; One of the working voltage supply lines corresponding to the detection pixel unit is located on a side close to the first edge of the second electrode in the detection pixel unit; The reset voltage supply line and the signal reading line corresponding to the detection pixel unit are both located near the second edge of the second electrode in the detection pixel unit. side.

19. The light detecting substrate according to claim 18, wherein: Also includes: A circuit connection pattern layer, located between the stacked transistor and the wiring arrangement layer, the circuit connection pattern layer comprising: a first circuit connection pattern, a second circuit connection pattern, a third circuit connection pattern and a fourth circuit connection pattern; A portion of the source-drain doped region of the active layer pattern of the selection transistor, which serves as the second electrode of the selection transistor, is connected to the corresponding signal reading line through the corresponding first circuit connection pattern, and the orthographic projection of the first circuit connection pattern on the plane where the second electrode is located intersects with the second edge; A portion of the source-drain doped region of the active layer pattern of the reset transistor, which serves as the first electrode of the reset transistor, is connected to the corresponding first electrode of the photoelectric conversion structure through the corresponding second circuit connection pattern, and the orthographic projection of the second circuit connection pattern on the plane where the second electrode is located intersects with the third edge; A portion of the source-drain doped region of the active layer pattern of the reset transistor, which serves as the second electrode of the reset transistor, is connected to the corresponding reset voltage supply line through the corresponding third circuit connection pattern, and the orthographic projection of the third circuit connection pattern on the plane where the second electrode is located intersects with the second edge; The part of the source-drain doped region of the active layer pattern of the source follower transistor which serves as the first electrode of the source follower transistor is connected to the corresponding working voltage supply line through the corresponding fourth circuit connection pattern, and the orthographic projection of the fourth circuit connection pattern on the plane where the second electrode is located intersects with the first edge.

20. The light detecting substrate according to claim 14, wherein: The source follower transistor is the stacked transistor.

21. The light detecting substrate according to claim 20, wherein: The gate of the reset transistor is disposed on the same layer as the gate of the source follower transistor, and the gate of the selection transistor is disposed on the same layer as the gate of the source follower transistor; The active layer pattern of the reset transistor and the active layer pattern of the source follower transistor The same layer arrangement is adopted, and the orthographic projection of the active layer pattern of the reset transistor on the substrate does not overlap with the orthographic projection of the photoelectric conversion structure located in the same detection pixel unit on the substrate; The active layer pattern of the selection transistor is arranged in the same layer as the active layer pattern of the source follower transistor, and the orthographic projection of the active layer pattern of the selection transistor on the substrate does not overlap with the orthographic projection of the photoelectric conversion structure located in the same detection pixel unit on the substrate.

22. The light detecting substrate according to claim 14, wherein: The reset transistor and the selection transistor are both the stacked transistors; The source follower transistor is located between the photoelectric conversion structure and the substrate.

23. The light detecting substrate according to claim 22, wherein: The material of the active layer pattern of the source follower transistor includes amorphous silicon or polycrystalline silicon.

24. The light detecting substrate according to claim 22 or 23, wherein: The channel region of the active layer pattern of the source follower transistor is located within the region covered by the orthographic projection of the photoelectric conversion structure on the substrate in the same detection pixel unit; The orthographic projection of at least part of the source-drain doping region of the active layer pattern of the source follower transistor on the substrate is located outside the area covered by the orthographic projection of the photoelectric conversion structure on the substrate in the same detection pixel unit.

25. An image sensor, wherein: include: A light detecting substrate as claimed in any one of claims 1 to 24.

26. An electronic device, wherein: include: An image sensor as claimed in claim 25.

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