High-speed turn-off gating circuit, device and system for single-photon detector

Abstract

The invention discloses a high-speed turn-off gating circuit, device and system for a single-photon detector, and belongs to the field of optical time domain reflectometers. A quenching broadening circuit is used for carrying out delay broadening on signal output of a discrimination circuit to generate a quenching pulse signal; a turn-off gate control pulse signal is generated through an FPGA module, the turn-off gate control pulse signal and the turn-off gate control pulse signal are combined to form a first mixed signal, and the first mixed signal is amplified by a driving circuit and then added to a negative electrode high-voltage bias end of an avalanche diode; the de-noising broadening circuit is used for generating a pulse signal which is synchronous with a quenching pulse but is delayed in phase, the FPGA module is used for generating a de-noising gating signal which is synchronous with a turn-off gating pulse but is delayed in phase, and the two signals are combined and superposed on a screening reference signal of the screening circuit; and the FPGA module is used for controlling and discriminating that a denoising pulse superposed by the reference signal is higher than the amplitude of an overshoot signal coupled in the load signal. According to the invention, false signals coupled to the load by gating can be eliminated, the gating mode does not influence photon response signals, and the response speed is high.

Description

Technical Field

[0001] The present invention relates to the field of single-light time-domain reflectometers, and more specifically, to a single-photon detector high-speed shutoff gating circuit, device and system. Background Art

[0002] The single photon detector operates at a bias voltage higher than the breakdown voltage V br In the Geiger mode, once a photon generates an electron-hole pair, the avalanche effect generates a large number of electron-hole pairs, and the current flows through the tube core and the load resistor R L The load voltage signals under different conditions of no quenching, large resistance passive quenching, and pulse active quenching are as follows: Figure 1 As shown. Without quenching, the current rises to a certain value and remains relatively stable. A large current that continues to flow through the die will eventually cause the device to burn out. Therefore, a quenching circuit must be added to the single-photon detection receiving circuit. Passive quenching is to connect a large resistor in series at the bias end, and the diode bias voltage is reduced to V through the large resistor voltage drop. br The time constant of the large resistor is large, and the time to restore the normal bias voltage is very long, which is not suitable for high-speed detection applications. Active quenching is to generate a quenching pulse after receiving the photogenerated pulse and add it to the bias terminal, and the voltage quickly drops to V br In this case, the bias is restored immediately after the pulse ends, and then the normal receiving state is restored.

[0003] At present, the high-precision optical time domain reflectometer (OTDR) based on single-photon detection technology adopts active quenching, and its signal time is in the nanosecond level. How to ensure the time efficiency of OTDR is a technical problem that needs to be solved urgently by people in this field. In the existing scheme, the commonly used gating signal is a periodic sine wave or square wave. Since the gating signal will be partially coupled to the load through the diode to form a false signal, the subsequent circuit is required to eliminate this influence, mainly filtering and signal cancellation.

[0004] The periodic gating method has the following disadvantages: on the one hand, the detection time efficiency is only 50%; on the other hand, adding subsequent circuits to the signal chain will introduce various unfavorable factors such as noise, reduced high-frequency characteristics, and reduced signal amplitude, which affects the detection signal characteristics. Summary of the invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a single-photon detector high-speed shut-off gating circuit, device and system, which can eliminate the false signal coupled to the load by gating without substantially reducing the time efficiency of OTDR testing, and the gating method does not affect the photon response signal, and the response speed is fast.

[0006] The object of the present invention is achieved through the following solutions: A high-speed shutdown gating circuit for a single-photon detector comprises: a discrimination circuit, a driving circuit, a quenching and widening circuit, a noise-removing and widening circuit and an FPGA module; the quenching and widening circuit is used to delay and widen the signal output of the discrimination circuit to generate a quenching pulse signal; a shutdown gating pulse signal is generated by the FPGA module; the two are combined to form a mixed signal one, and the mixed signal one is amplified by the driving circuit and added to the negative high-voltage bias end of the avalanche diode; the noise-removing and widening circuit is used to generate a pulse signal that is synchronized with the quenching pulse but delayed in phase, and the FPGA module is used to generate a noise-removing gating signal that is synchronized with the shutdown gating pulse but delayed in phase, and the two signals are combined and superimposed on a discrimination reference signal of the discrimination circuit; the FPGA module is used to control the noise-removing pulse superimposed on the discrimination reference signal to be higher than the amplitude of the overshoot signal coupled into the load signal.

[0007] Furthermore, the noise removal and widening circuit adopts RC delay.

[0008] Furthermore, the delay accuracy of the noise removal gating signal is 0.1ns.

[0009] Furthermore, the FPGA module also includes a photon counting unit for performing photon counting after pulse shaping of the discrimination circuit output.

[0010] Furthermore, a high-voltage DC-isolating coupling capacitor is provided between the driving circuit and the cathode high-voltage bias terminal of the diode.

[0011] Furthermore, a load R is connected to the cathode high voltage bias end of the diode. D .

[0012] A single-photon detector high-speed shutdown gating device comprises the single-photon detector high-speed shutdown gating circuit as described in any one of the above items.

[0013] A single-photon detector high-speed shutoff gating system comprises the single-photon detector high-speed shutoff gating device as described above.

[0014] The beneficial effects of the present invention include: The scheme of the present invention proposes a more effective shut-off gating and related processing circuit, which only adds gating to saturated optical pulses, does not add other circuits to the signal chain, but adds a synchronous noise removal signal to the discrimination comparison reference signal, thereby eliminating the false signal coupled to the load by the gating without substantially reducing the time efficiency of the OTDR test, and the gating method does not affect the photon response signal, and the response speed is fast. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0016] Figure 1 is the load response signal diagram; Figure 2 : is a block diagram of the shutoff gating circuit principle of an embodiment of the present invention; wherein SPD represents a single photon detector; Figure 3 for Figure 2 Circuit node waveform diagram in . DETAILED DESCRIPTION

[0017] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or expanded or replaced in any manner.

[0018] The present invention aims to eliminate the false signal coupled to the load by gating without substantially reducing the time efficiency of OTDR testing. In a specific implementation scheme, a more effective shut-off gating and related processing circuit is proposed, which only adds gating to saturated optical pulses, and does not add other circuits to the signal link. Instead, a synchronous noise removal signal is added to the discrimination comparison reference signal to eliminate the false signal coupled to the load by gating. In the scheme of the present invention, the gating method does not affect the photon response signal, the response speed is fast, and the detection time efficiency is substantially not reduced.

[0019] More specifically, the working principle of the shutdown gating conceived by the present invention is to turn off the saturated pulse response when receiving strong light, receive pulses in a non-saturated state when receiving weak light, and add the pulses in the weak light curve to the corresponding position of the strong light curve to synthesize a complete light signal detection curve, thereby reducing the overall test time of the system. In terms of further design, the block diagram of the single-photon detector shutdown gating circuit of the present invention is as follows Figure 2As shown, it includes a discrimination circuit, a driving circuit, a quenching and widening circuit, a noise-removing and widening circuit, and an FPGA module. A quenching pulse signal is generated by delaying and widening the output of the discrimination circuit and the quenching and widening circuit. Specifically, the quenching and widening circuit is used to delay and widen the signal output of the discrimination circuit to generate a quenching pulse signal; and a shutdown gate control pulse signal is generated by the FPGA module. The two are combined to form a mixed signal one, and the mixed signal one is amplified by the driving circuit and added to the negative high-voltage bias end of the avalanche diode; the noise-removing and widening circuit is used to generate a pulse signal that is synchronized with the quenching pulse but delayed in phase, and the FPGA module generates a noise-removing gate control signal that is synchronized with the shutdown gate control pulse but delayed in phase, and the two signals are combined and superimposed on the discrimination reference signal of the discrimination circuit. The noise-removing pulse superimposed on the discrimination reference signal is higher than the amplitude of the overshoot signal coupled into the load signal. This signal is of standard level amplitude, and the signal end of the discrimination comparison is a weak level signal. The signal level of the quenching noise removal pulse and the gated noise removal pulse is controlled to be higher than the overshoot signal. The signal time width covers the overshoot signal, so that the discrimination output signal no longer has an overshoot signal, thereby eliminating the quenching and gated overshoot effects of the photon detection signal.

[0020] In one embodiment of the present invention, based on Figure 2 The principle block diagram of the shutdown gate control circuit in the figure, the circuit node waveforms are as follows Figure 3 As shown, a load R is connected between the cathode high voltage bias terminal of the diode and the Vh terminal. D Furthermore, the gated pulse is generated by the 10G rate FPGA to generate a 0.1ns precision pulse, and the active quenching is generated by the discrimination output delay widening. The two are combined to form a mixed signal, which is driven and amplified and then added to the negative high voltage bias end of the diode. The waveform is as follows Figure 3 In the middle curve ①, when a pulse appears, the bias voltage drops to the breakdown voltage V br The pulse signal of the bias waveform will be partially coupled to the load R at the anode of the diode. L On, such as Figure 3 The coupling overshoot shown in the middle curve ③ is related to the bias pulse amplitude and the diode distribution parameters. Some overshoot signal amplitudes are higher than the photon response signal amplitude. If not processed, the overshoot will form an output pulse through the discrimination circuit, resulting in excess counts. More serious consequences will cause the circuit system to collapse. The overshoot effect must be eliminated.

[0021] Further, as the principle box Figure 2 As shown in the figure, once there is a photon input or the avalanche effect of thermal noise on R L The pulse signal is generated on the circuit, the discrimination circuit outputs the signal electric pulse P1, the quenching and broadening circuit generates the active quenching pulse M1, which is added to the bias terminal, and the quenching pulse M1 overshoots and couples to R LIf there is no de-noising, the discrimination circuit will generate an output pulse P2 with overshoot, and the quenching and broadening circuit will also generate M2 with P2, and this cycle will continue, and continuous output P1, P2, P3... will be obtained at the signal output end, forming a quenching cycle pulse; similarly, once a gate pulse is added to the bias end, a gated cycle pulse will be formed. In addition, even if there is no light input and gate input, the single-photon detector will continue to have thermal noise at R L A dark count signal is generated on the circuit, resulting in the superposition of various cycles and circuit failure. Therefore, a coupled overshoot noise elimination circuit must be further added to eliminate invalid cycles.

[0022] Noise removal circuit Figure 2 As shown in , the noise elimination and broadening generate pulses that are synchronized with the quenching pulse but with a phase delay, and the FPGA module generates a noise elimination gating that is synchronized with the shutdown gating but with a phase delay. The two signals are combined and superimposed on the discrimination reference signal, as shown in Figure 3 In the middle curve ②, in the discrimination comparison of the discrimination circuit, the noise-removing pulse superimposed on the discrimination reference signal is higher than R L The overshoot signal amplitude coupled into the load signal can identify the output and only the valid photon signal forms the output pulse, while the invalid overshoot will not form the output, such as the photon response output pulse in curve ④, thus avoiding invalid cycles in the circuit.

[0023] The synchronous delay noise removal and widening relative to the quenching pulse, if the time delay is too much, it is only equivalent to the dead time caused by quenching, which has little impact on the system. Therefore, the noise removal and widening circuit in the present invention adopts RC delay. The high-precision OTDR gating function is to turn off the photoelectric response of the strong reflected light pulse, and at the same time requires the normal reception to be quickly restored after the gating. Signal output will be prohibited during the overshoot elimination time period after the gating. If the gating time and the overshoot elimination time are within the attenuation blind area of ​​the light reflection pulse, the gating will not affect the attenuation blind area. If the gating time and the overshoot elimination time exceed the attenuation blind area of ​​the light reflection pulse, it will be manifested as an increase in the attenuation blind area and a decrease in the system resolution accuracy. The attenuation blind area of ​​the high-precision OTDR is less than 40cm, corresponding to a time of 4ns, so the time span affected by the gating should be minimized. The present invention is conceived to reduce the delay error from two aspects. On the one hand, the delay accuracy is controlled. The shutdown gating and the noise reduction gating are both generated by the FPGA, and the delay accuracy is controlled to 0.1ns, which can accurately control the delay accuracy to reduce the delay error. On the other hand, on the circuit link, the overshoot delay of the identification and comparison node is minimized. Therefore, a noise reduction pulse is added to the identification and comparison reference signal to prohibit overshoot output, and the time taken to eliminate the overshoot is minimized.

[0024] The specific implementation of the present invention is not limited to the above-mentioned methods. The above description is only the preferred embodiment of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein. It is possible for those skilled in the art to make various obvious changes, adjustments and substitutions without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may also include more other equivalent embodiments without departing from the principles and concepts of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

[0025] The units involved in the embodiments of the present invention are based on hardware implementation, and some functions can be implemented by software. The units described can also be set in a processor. Among them, the names of these units do not constitute a limitation on the units themselves under certain circumstances. The embodiments of the present invention can provide a corresponding computer program product or a computer program, and the computer program product or the computer program includes a computer instruction, and the computer instruction is stored in a corresponding hardware device. The corresponding hardware device reads and executes the computer instruction, so that the hardware device executes the method provided in the above-mentioned various optional implementations.

Claims

1. A single-photon detector high-speed shut-off gating circuit, characterized in that: include: Identification circuit, driving circuit, quenching and widening circuit, noise elimination and widening circuit and FPGA module; The signal output of the discrimination circuit is delayed and widened by using the quenching and widening circuit to generate a quenching pulse signal; a shut-off gate pulse signal is generated by using the FPGA module; The two are combined to form a mixed signal 1, which is amplified by the driving circuit and then added to the negative high voltage bias terminal of the avalanche diode; A noise-cancelling and stretching circuit is used to generate a pulse signal that is synchronized with the quenching pulse but has a phase delay. The FPGA module generates a noise-cancelling gating signal that is synchronized with the shutdown gating pulse but has a phase delay. The two signals are combined and superimposed on the discrimination reference signal of the discrimination circuit. The FPGA module controls the noise-cancelling pulse superimposed on the discrimination reference signal to be higher than the amplitude of the overshoot signal coupled into the load signal.

2. The single-photon detector high-speed shutdown gating circuit according to claim 1, characterized in that: The noise removal and widening circuit adopts RC delay.

3. The single-photon detector high-speed shutdown gating circuit according to claim 1, characterized in that: The delay accuracy of the noise removal gating signal is 0.1ns.

4. The single-photon detector high-speed shutdown gating circuit according to claim 1, characterized in that: The FPGA module also includes a photon counting unit, which is used to perform photon counting after pulse shaping on the output of the discrimination circuit.

5. The single-photon detector high-speed shutdown gating circuit according to claim 1, characterized in that: A high-voltage DC-isolating coupling capacitor is arranged between the driving circuit and the cathode high-voltage bias terminal of the diode.

6. The single-photon detector high-speed shut-off gating circuit according to claim 5, characterized in that: A load R is also connected to the negative high voltage bias end of the diode. D .

7. A high-speed shut-off gating device for a single-photon detector, characterized in that: A single-photon detector high-speed shutdown gating circuit comprising any one of claims 1 to 6.

8. A single photon detector high-speed shut-off gating system, characterized in that: It includes the single-photon detector high-speed shutoff gating device as described in claim 7.

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