Avalanche test circuit and method

Abstract

The invention provides an avalanche test circuit and method.The avalanche test circuit comprises a controller, a power module, a pulse generation module, a driving signal change-over switch, a driving module and a test module.The positive power signal output end of the power module is connected to the driving module, and the positive power signal output end of the pulse generation module is connected to the test module; two switching ends of the driving signal change-over switch are respectively connected to a negative power supply signal output end and a reference power supply output end of the power supply module, a common end of the driving signal change-over switch is connected to the driving module, and the controller is respectively connected to the pulse generation module, a control end of the driving signal change-over switch and the test module. The pulse generation module is also connected to the driving module, and the driving module is connected to the test module. The test range is expanded through the driving signal change-over switch, the adaptability of the avalanche test circuit is improved, manual work is replaced with the avalanche test circuit, and the test efficiency is improved while the avalanche test process is simplified.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor device reliability testing, and in particular to an avalanche testing circuit and method. Background Art

[0002] Existing avalanche test circuits for semiconductor devices, especially avalanche test circuits for field effect transistors, generally have a one-to-one correspondence between an avalanche test circuit and the type of field effect transistor being tested. That is, the same avalanche test circuit only supports testing one type of field effect transistor, which reduces the overall applicability of the avalanche test circuit and has low integration.

[0003] In addition, the existing avalanche test performed on the device under test is to manually adjust the pulse time to adjust the current size to complete the test process. The manual adjustment of the pulse time increases the test time and reduces the test efficiency. Summary of the invention

[0004] In view of this, the purpose of this application is to provide at least one avalanche test circuit and method, which not only expands the test range by driving the signal switching switch to improve the adaptability of the avalanche test circuit, but also provides an automated testing method to replace manual testing, thereby simplifying the test process and improving test efficiency.

[0005] This application mainly includes the following aspects:

[0006] In the first aspect, an embodiment of the present application provides an avalanche test circuit, which includes a controller, a power supply module, a pulse generating module, a drive signal switching switch, a drive module and a test module. The positive power signal output terminal of the power supply module is connected to the drive module, the two switching ends of the drive signal switching switch are respectively connected to the negative power signal output terminal and the reference power output terminal of the power supply module, the common end of the drive signal switching switch is connected to the drive module, the controller is respectively connected to the pulse generating module, the control end of the drive signal switching switch and the test module, the pulse generating module is also connected to the drive module, and the drive module is connected to the test module.

[0007] In one possible implementation, the test module includes a first diode, an auxiliary device, an inductor, a device under test, and a second diode, wherein a first pole of the auxiliary device is connected to a driving module, an anode of the first diode is connected to a first input power supply, a cathode of the first diode is connected to a third pole of the auxiliary device, a second pole of the auxiliary device is respectively connected to one end of the inductor, the driving module, and a cathode of the second diode, a first pole of the device under test is connected to the driving module, a third pole of the device under test is connected to the other end of the inductor, a second pole of the device under test is respectively connected to the driving module, a controller, and an anode of the second diode, and a heat sink is placed under the device under test.

[0008] In a possible implementation, the avalanche test circuit also includes a current detection feedback module and a first resistor, the input end of the current detection feedback module is connected to the second pole of the device under test, the output end of the current detection feedback module is connected to the controller, the ground end of the current detection feedback module is grounded, and the ground end of the current detection feedback module is also connected to the ground end of the power supply module through the first resistor.

[0009] In a possible embodiment, the power supply module includes a first power supply output unit and its corresponding first capacitor, the input end of the first power supply output unit is connected to the second input power supply and one end of the first capacitor, the ground end of the first power supply output unit is connected to the other end of the first capacitor and then grounded, and the ground end of the first power supply output unit is also connected to the ground end of the current detection feedback module through a first resistor; the positive power signal output end of the first power supply output unit is connected to the driving module, the negative power signal output end of the first power supply output unit is connected to the first switching end of the driving signal switching switch, and the reference power supply output end of the first power supply output unit is connected to the second switching end of the driving signal switching switch.

[0010] In a possible implementation, the driving module includes a second resistor, a first push-pull circuit, a second capacitor, a transformer, a third capacitor, a fourth capacitor, a fast shutdown structure, an auxiliary device driving circuit and a first device under test driving circuit, wherein one end of the second resistor is connected to the output end of the pulse generating module, the other end of the second resistor is connected to the first input end of the first push-pull circuit, the second input end of the first push-pull circuit is connected to the positive power signal output end of the first power output unit, the third input end of the first push-pull circuit is respectively connected to the common end of the drive signal switching switch and the opposite end of the primary coil of the transformer, the output end of the first push-pull circuit is connected to the same end of the primary coil of the transformer through the second capacitor; the same end of the first secondary coil of the transformer is connected to one end of the third capacitor, the other end of the third capacitor is connected to the first input end of the auxiliary device driving circuit, and the first secondary The opposite-name ends of the coils are respectively connected to the second input end of the auxiliary device driving circuit, the first output end of the auxiliary device driving circuit is connected to the first pole of the auxiliary device, and the second output end of the auxiliary device driving circuit is connected to the second pole of the auxiliary device; the same-name ends of the second secondary coil of the transformer are respectively connected to one end of the fourth capacitor and the first connection end of the fast shutdown structure, the other end of the fourth capacitor is respectively connected to the first input end of the first device under test driving circuit and the second connection end of the fast shutdown structure, the opposite-name ends of the second secondary coil are respectively connected to the second input end of the first device under test driving circuit and the third connection end of the fast shutdown structure, the first output end of the first device under test driving circuit is connected to the first pole of the device under test, and the second output end of the first device under test driving circuit is connected to the second pole of the device under test, and the winding ratio between the primary coil of the transformer and any secondary coil is 1:1.

[0011] In a possible implementation, the fast shutdown structure includes a third resistor and a first triode, the auxiliary device driving circuit includes a third diode, a fourth resistor, a fifth resistor and a fourth diode, and the first device under test driving circuit includes a sixth resistor, a seventh resistor and a fifth diode, wherein one end of the fourth resistor is respectively connected to the other end of the third capacitor and the cathode of the third diode, the other end of the fourth resistor is respectively connected to one end of the fifth resistor, the cathode of the fourth diode and the first electrode of the auxiliary device, and the other end of the fifth resistor is respectively connected to the anode of the third diode, the opposite end of the first secondary coil, the anode of the fourth diode, the second electrode of the auxiliary device, and the other end of the fifth resistor. one end of the third resistor is respectively connected to the like-name end of the second secondary coil and one end of the fourth capacitor, the other end of the third resistor is connected to the base of the first triode, the emitter of the first triode is respectively connected to one end of the sixth resistor and the other end of the fourth capacitor, the other end of the sixth resistor is respectively connected to one end of the seventh resistor, the cathode of the fifth diode and the first pole of the device under test, the other end of the seventh resistor is respectively connected to the collector of the first triode, the opposite-name end of the second secondary coil and the anode of the fifth diode, the anode of the second diode, the second pole of the device under test and the input end of the current detection feedback module.

[0012] In a possible implementation, the power supply module includes a second power supply output unit and a corresponding fifth capacitor and a third power supply output unit and a corresponding sixth capacitor, wherein the input end of the second power supply output unit is connected to the second input power supply and one end of the fifth capacitor, the ground end of the second power supply output unit is respectively connected to the other end of the fifth capacitor and the ground end of the third power supply output unit and then grounded, the ground end of the second power supply output unit is also connected to the ground end of the current detection feedback module through a first resistor, the positive power supply signal output end of the second power supply output unit is connected to the driving module, the reference power supply output end of the second power supply output unit is connected to the driving module, the input end of the third power supply output unit is respectively connected to the second input power supply and one end of the sixth capacitor, the ground end of the third power supply output unit is respectively connected to the other end of the sixth capacitor and then grounded, the ground end of the third power supply output unit is also connected to the ground end of the current detection feedback module through a first resistor, the positive power supply signal output end of the third power supply output unit is connected to the driving module, the negative power supply signal output end of the third power supply output unit is connected to the first switching end of the driving signal switching switch, and the reference power supply output end of the third power supply output unit is connected to the second switching end of the driving signal switching switch.

[0013] In a possible implementation, the driving module includes an eighth resistor and a second push-pull circuit corresponding thereto, a ninth resistor and a third push-pull circuit corresponding thereto, an auxiliary device driving circuit and a second device under test driving circuit, wherein the output end of the pulse generating module is respectively connected to one end of the eighth resistor and one end of the ninth resistor, the other end of the eighth resistor is connected to a first connection end of the second push-pull circuit, the second connection end of the second push-pull circuit is connected to a positive power signal output end of the second power output unit, the third connection end of the second push-pull circuit is respectively connected to a positive reference power output end of the second power output unit and a second input end of the auxiliary device driving circuit, the output end of the second push-pull circuit is connected to the first input end of the auxiliary device driving circuit, and the auxiliary device driving circuit is connected to a positive reference power signal output end of the second power output unit and a third connection end of the second push-pull circuit. The first output end of the auxiliary device driving circuit is connected to the first pole of the auxiliary device, and the second output end of the auxiliary device driving circuit is connected to the second pole of the auxiliary device; the other end of the ninth resistor is connected to the first connection end of the third push-pull circuit, the second connection end of the third push-pull circuit is connected to the positive power signal output end of the third power output unit, the third connection end of the third push-pull circuit is respectively connected to the common end of the drive signal switching switch and the second input end of the second device under test driving circuit, the output end of the third push-pull circuit is connected to the first input end of the second device under test driving circuit, the first output end of the second device under test driving circuit is connected to the first pole of the device under test, and the second output end of the second device under test driving circuit is connected to the second pole of the device under test.

[0014] In the second aspect, an embodiment of the present application also provides an avalanche test method, which is applied to a controller in an avalanche test circuit provided by any of the above-mentioned embodiments, and the method includes: according to the type of the device under test in the test module, controlling the drive signal switching switch to perform a target switching action so that the drive module is connected to the negative power supply input signal corresponding to the type of the device under test; controlling the pulse generating module to perform an avalanche test on the device under test in the test module according to a given pulse width time; determining whether the device under test has failed, and if the device under test has not failed, controlling the pulse generating module to stop working for a preset time period; after the pulse generating module stops working for a preset time period, applying a given pulse width time increment to the given pulse width time to obtain an updated given pulse width time, and controlling the pulse generating module to perform an avalanche test on the device under test in the test module according to the updated given pulse width time; if the device under test fails, collecting the current data corresponding to the device under test before the avalanche; and calculating the single pulse avalanche energy of the device under test using the current data.

[0015] In a possible implementation, the device under test is divided into a silicon field effect transistor and a silicon carbide field effect transistor, wherein, according to the type of the device under test in the test module, the step of controlling the drive signal to perform a target switching action includes: if the device under test is a silicon field effect transistor, then controlling the drive signal switching switch to switch to the reference power output terminal of the power module; if the device under test is a silicon carbide field effect transistor, then controlling the drive signal switching switch to switch to the negative power signal output terminal of the power module.

[0016] In one possible implementation, whether the device under test has failed is determined in the following manner: a target current flowing through the device under test is collected through a current detection feedback module; whether the target current is greater than a preset instantaneous current threshold is determined; if the target current is greater than or equal to the preset instantaneous current threshold, it is determined that the device under test has failed; if the target current is less than the preset instantaneous current threshold, it is determined that the device under test has not failed.

[0017] In a possible implementation, the current data includes a maximum target current flowing through the device under test before avalanche failure occurs in the device under test, wherein the single pulse avalanche energy corresponding to the device under test is determined by the following formula:

[0018]

[0019] In this formula, E AS It represents the single pulse avalanche energy corresponding to the device under test, L represents the inductance value in the test module, I AS It indicates the maximum target current that flows through the device under test before avalanche failure occurs.

[0020] An avalanche test circuit and method provided by an embodiment of the present application, the avalanche test circuit includes a controller, a power module, a pulse generating module, a drive signal switching switch, a drive module and a test module, wherein the positive power signal output terminal of the power module is connected to the drive module, the two switching terminals of the drive signal switching switch are respectively connected to the negative power signal output terminal and the reference power output terminal of the power module, the common terminal of the drive signal switching switch is connected to the drive module, the controller is respectively connected to the pulse generating module, the control terminal of the drive signal switching switch and the test module, the pulse generating module is also connected to the drive module, and the drive module is connected to the test module. The present application expands the test range through the drive signal switching switch, improves the adaptability of the avalanche test circuit, and replaces manual testing using a fixture through the avalanche test circuit, simplifies the avalanche test process and improves the test efficiency and safety.

[0021] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 One of the avalanche test circuits provided in the embodiment of the present application is shown;

[0024] Figure 2 A flow chart of an avalanche testing method provided by an embodiment of the present application is shown;

[0025] Figure 3 A schematic diagram of the structure of a test module provided in an embodiment of the present application is shown;

[0026] Figure 4 A second structural schematic diagram of an avalanche test circuit provided in an embodiment of the present application is shown;

[0027] Figure 5 A third structural schematic diagram of an avalanche test circuit provided in an embodiment of the present application is shown;

[0028] Figure 6 A fourth structural schematic diagram of an avalanche test circuit provided in an embodiment of the present application is shown;

[0029] Figure 7 A schematic diagram of voltage and current changes during an avalanche test of a device under test provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0030] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art, under the guidance of the content of the present application, can add one or more other operations to the flowchart, or remove one or more operations from the flowchart.

[0031] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0032] Existing avalanche test circuits for semiconductor devices, especially avalanche test circuits for field effect transistors, generally have a one-to-one correspondence between an avalanche test circuit and a model of the field effect transistor being tested. That is to say, the same avalanche test circuit only supports testing one model of field effect transistor, which reduces the overall applicability of the avalanche test circuit and has low integration. In addition, the existing avalanche test performed on the device under test is a process of manually debugging the pulse time to adjust the current size to complete the test. Manually debugging the pulse time increases the test time and reduces the test efficiency.

[0033] Based on this, the embodiment of the present application provides an avalanche test circuit and method, which expands the test range by driving a signal switching switch, improves the adaptability of the avalanche test circuit, and provides an automated test method to replace manual testing, thereby simplifying the test process and improving the test efficiency. The details are as follows:

[0034] See also Figure 1 , Figure 1 FIG. 1 shows one avalanche test circuit provided by an embodiment of the present application. Figure 2 , Figure 2 FIG. 1 is a flow chart of an avalanche testing method provided by an embodiment of the present application. Figure 1 As shown, the avalanche test circuit provided in the present application includes a power supply module 1, a pulse generation module 2, a drive signal switching switch 3, a drive module 4 and a test module 5.

[0035] Preferably, the input end of the power supply module 1 is connected to the second input power supply VCC2, the positive power signal output end +VOUT of the power supply module 1 is connected to the driving module 4, the two switching ends of the driving signal switching switch 3 are respectively connected to the negative power signal output end -VOUT and the reference power output end COM of the power supply module 1, the common end of the driving signal switching switch 3 is connected to the driving module 4, the controller 6 is respectively connected to the pulse generating module 2, the control end of the driving signal switching switch 3 and the testing module 5, the pulse generating module 2 is also connected to the driving module 4, the driving module 4 is connected to the testing module 5, and the second input power supply VCC2 can be +15V.

[0036] like Figure 2As shown, the method provided in the embodiment of the present application comprises the following steps:

[0037] S101 . According to the type of the device under test in the test module, control the drive signal switching switch to perform a target switching action.

[0038] So that the driver module can access the negative power input signal corresponding to the type of device under test.

[0039] S102 , controlling the pulse generating module to perform an avalanche test on the device under test in the testing module according to a given pulse width time.

[0040] S103: Determine whether the device under test fails.

[0041] S104: If the device under test has not failed, the pulse generating module is controlled to stop working for a preset period of time.

[0042] S105 , applying a given pulse width time increment to the given pulse width time to obtain an updated given pulse width time.

[0043] Return to step S102.

[0044] S106 : If the device under test fails, collect current data corresponding to the device under test before avalanche.

[0045] S107. Calculate the single pulse avalanche energy corresponding to the device under test using the current data.

[0046] In a specific implementation, in steps S101 to S107, the power module 1 is used to provide a driving voltage for the module under test, and the driving voltage is determined by a positive driving voltage and a negative driving voltage. The driving signal switching switch 3 is a single-pole double-throw switch, which is responsible for switching between the negative power signal output terminal -VOUT and the reference power output terminal COM of the power module 1 according to the type of the device under test. The positive power signal output terminal of the power module 1 is used to provide a positive driving voltage for the device under test. The driving signal switching switch 3 is used to combine the negative power signal output terminal -VOUT of the power module 1 and the reference power output terminal COM to provide different negative driving voltages for the device under test. , the device under test is an N-type communication field effect transistor. Depending on the driving voltage required by different types of devices under test, the device under test can be connected to different negative driving voltages by switching the driving signal switching switch 3, thereby achieving different types of on-voltages of devices under test. That is, by adding the driving signal switching switch 3, the driving voltage range provided by the power supply module 1 to the module under test is increased, so that the avalanche test method and avalanche test circuit of the present application are adapted to different types of devices under test, so that the application scope of the avalanche test method and avalanche test circuit is effectively expanded. In the present application, the device under test and the auxiliary device can be metal oxide field effect transistors (MOS tubes or SIC MOSFETs). When the device under test and the auxiliary device are metal oxide field effect transistors, the first stage of the device under test or the auxiliary device is the gate of the MOS tube, the second stage of the device under test or the auxiliary device is the source of the MOS tube, and the third stage of the device under test or the auxiliary device is the drain of the MOS tube.

[0047] In addition, the method shown in steps S101 to S107 of the present application is integrated inside the controller 6. Through the connection relationship between the controller 6 and the entire avalanche test circuit, by pre-setting a preset time period and a given pulse width time increment, manual dependence is eliminated and the avalanche test of the device under test is automatically completed. While improving test efficiency, it can also eliminate the errors caused by manual avalanche testing, further improving the accuracy of the entire avalanche test.

[0048] Preferably, in step S101, the device under test is divided into a silicon field effect transistor and a silicon carbide field effect transistor, wherein step S101 includes:

[0049] If the device under test is a silicon field effect transistor, the drive signal switching switch 3 is controlled to switch to the reference power output terminal COM of the power module. If the device under test is a silicon carbide field effect transistor, the drive signal switching switch 3 is controlled to switch to the negative power signal output terminal of the power module.

[0050] In a specific embodiment, the positive driving voltage range of the positive power signal output terminal +VOUT of the power module 1 can be selected as 10 to 15V, and the preferred embodiment is 10V. The negative driving voltage range of the negative power signal output terminal -VOUT of the power module 1 can be selected as -3 to -8V, and the preferred embodiment is -5V. The negative driving signal outputted by the reference power output terminal COM of the power module 1 is 0V, and the driving voltage Vgs corresponding to the device under test = positive driving voltage - negative driving voltage. Therefore, specifically, in this embodiment, for the silicon field effect transistor, it is turned on when its driving voltage Vgs = 10V. Therefore, the driving signal switching switch 3 is switched to the reference power output terminal COM of the power module, so that the driving voltage Vgs corresponding to the silicon field effect transistor is Vgs = 10-0V = 10V, thereby controlling the conduction of the silicon field effect transistor. When the silicon field effect transistor is turned off, Vgs = 0V.

[0051] For the silicon carbide field effect transistor, it needs to be turned off at a negative voltage. Therefore, the drive signal switching switch 3 is switched to the negative power signal output terminal -VOUT of the power module 1. At this time, when the silicon carbide field effect transistor is turned on, its corresponding drive voltage Vgs = 10V-(-5V) = 15V, and when the silicon carbide field effect transistor is turned off, its corresponding drive voltage Vgs = -5V, which can achieve complete shutdown of the silicon carbide field effect transistor.

[0052] See also Figure 3 , Figure 3 FIG. 1 is a schematic diagram showing the structure of a test module provided in an embodiment of the present application. Figure 3 As shown, the test module 5 includes a first diode D1, an auxiliary device Q1, an inductor L, a device under test Q2 and a second diode D2.

[0053] Among them, the first electrode of the auxiliary device Q1 is connected to the driving module 4, the anode of the first diode D1 is connected to the first input power supply VCC1, the cathode of the first diode D1 is connected to the third electrode of the auxiliary device Q1, the second electrode of the auxiliary device Q1 is respectively connected to one end of the inductor L, the driving module 4 and the cathode of the second diode D2, the first electrode of the device under test Q2 is connected to the driving module 4, the third electrode of the device under test Q2 is connected to the other end of the inductor L, the second electrode of the device under test Q2 is respectively connected to the driving module 4, the controller 6 and the anode of the second diode D2, and a heat sink CHE is placed under the device under test Q2. Figure 3 In the structural diagram of the test module shown in , the auxiliary device Q1 and the device under test Q2 both use NMOS tubes.

[0054] The first diode D1 is an anti-reverse diode, and the second diode D2 is a clamping diode.

[0055] In a specific embodiment, the first input power source VCC1 in the test module 5 is connected to the test circuit. The specific value of the first input power source VCC1 is determined by the specifications of the device under test Q1 or the auxiliary device Q2. The auxiliary device Q1 has the same specifications as the device under test Q2. Figure 3 As shown, both use NMOS field effect tubes, the auxiliary device Q1 and the device under test Q2 are switched synchronously, the auxiliary device Q1 and the device under test Q2 are connected in series through an inductor L, the inductor L and the device under test Q2 are connected in parallel with D2 for clamping protection, when the auxiliary device Q1 and the device under test Q2 are turned on, the loop where the first input power supply VCC is located is connected, and the first input power supply VCC charges the inductor L, after the auxiliary device Q1 and the device under test Q2 are turned off, the inductor L releases energy along the original charging direction to impact the device under test Q2 to perform an avalanche test on the device under test Q2, and at the same time, a heat sink CHE is placed under the device under test Q2, so that the heat generated during the avalanche test of the device under test Q2 can be quickly discharged and dissipated, so that the avalanche tolerance test of the device under test Q2 eliminates the influence of heat, is more likely to be close to the true value, and improves the test accuracy.

[0056] See also Figure 4 , Figure 4 FIG. 2 shows a second structural diagram of an avalanche test circuit provided in an embodiment of the present application. Figure 4 As shown, the avalanche test circuit also includes a current detection feedback module 7 and a first resistor R1, the first resistor R1 is a first resistor, the input end of the current detection feedback module 7 is connected to the second pole of the device under test Q2, the output end of the current detection feedback module 7 is connected to the controller 6, the ground end of the current detection feedback module 7 is grounded, and the ground end of the current detection feedback module 7 is also connected to the ground end GND of the power supply module 1 through the first resistor R1.

[0057] In a preferred embodiment, step S103 includes:

[0058] The target current flowing through the device under test is collected through the current detection feedback module to determine whether the target current is greater than the preset instantaneous current threshold. If the target current is greater than or equal to the preset instantaneous current threshold, it is determined that the device under test has failed. If the target current is less than the preset instantaneous current threshold, it is determined that the device under test has not failed.

[0059] Specifically, the function of the current detection feedback module 7 is to detect whether the current data generated by the device under test Q2 in the test module is controllable. When the target current flowing through the device under test exceeds the preset instantaneous current threshold, it means that the target current flowing through the device under test has become uncontrollable, that is, the device under test Q2 is avalanche broken down. Then the current detection feedback module 7 generates a test termination signal and sends it to the controller 6. After receiving the test termination signal, the controller 6 will stop sending the corresponding signal to the pulse generating module 2 and generate a test end signal to send to the pulse generating module 2, so that the pulse generating module 2 will no longer generate a signal after receiving the test end signal to prevent further burning of the device under test Q2.

[0060] A first resistor R1 is connected between the power module 1 and the ground terminal of the current detection feedback module 7, so as to prevent the oscillations between the power module 1 and the test module 5 from affecting each other, thereby realizing a dual-isolation drive avalanche test circuit.

[0061] See also Figure 5 , Figure 5 FIG4 shows a fourth structural diagram of an avalanche test circuit provided in an embodiment of the present application. Figure 5 As shown, the power module 1 includes a first power output unit 11 and a corresponding first capacitor C1.

[0062] The input terminal VIN of the first power output unit 11 is connected to the second input power supply VCC2 and one end of the first capacitor C1, the ground terminal GND of the first power output unit 11 is connected to the other end of the first capacitor C1 and then grounded, and the ground terminal GND of the first power output unit 11 is also connected to the ground terminal of the current detection feedback module 7 through the first resistor R1.

[0063] The positive power signal output terminal +VOUT of the first power output unit 11 is connected to the driving module 4, the negative power signal output terminal -VOUT of the first power output unit 11 is connected to the first switching terminal of the driving signal switching switch 3, the reference power output terminal COM of the first power output unit 11 is connected to the second switching terminal of the driving signal switching switch 3, and the control terminal of the first power output unit 11 is connected to the controller 6.

[0064] like Figure 5 As shown, the driving module 4 includes a second resistor R2, a first push-pull circuit 41, a second capacitor C2, a transformer T, a third capacitor C3, a fourth capacitor C4, a fast shutdown structure 42, an auxiliary device driving circuit 43 and a first device under test driving circuit 44.

[0065] Among them, one end of the second resistor R2 is connected to the output end of the pulse generating module 2, the other end of the second resistor R2 is connected to the first input end of the first push-pull circuit 41, the second input end of the first push-pull circuit 41 is connected to the positive power signal output end +VOUT of the first power output unit 11, the third input end of the first push-pull circuit 41 is respectively connected to the common end of the drive signal switching switch 3 and the opposite end of the primary coil of the transformer T, and the output end of the first push-pull circuit 41 is connected to the same end of the primary coil of the transformer T through the second capacitor C2.

[0066] The like-name end of the first secondary coil of the transformer T is connected to one end of the third capacitor C3, the other end of the third capacitor C3 is respectively connected to the first input end of the auxiliary device driving circuit 43, the opposite-name ends of the first secondary coil are respectively connected to the second input end of the auxiliary device driving circuit 43, the first output end of the auxiliary device driving circuit 43 is connected to the first pole of the auxiliary device Q1, and the second output end of the auxiliary device driving circuit 43 is connected to the second pole of the auxiliary device Q1 and the cathode of the second diode D2.

[0067] The like-name ends of the second secondary coil of the transformer T are respectively connected to one end of the fourth capacitor C4 and the first connection end of the fast shutdown structure 42, the other end of the third DC blocking capacitor C4 is respectively connected to the first input end of the first device under test drive circuit 44 and the second connection end of the fast shutdown structure 42, the opposite-name ends of the second secondary coil are respectively connected to the second input end of the first device under test drive circuit 44 and the third connection end of the fast shutdown structure 42, the first output end of the first device under test drive circuit 44 is connected to the first pole of the device under test Q2, the second output end of the first device under test drive circuit 44 is connected to the second pole of the device under test Q2, the input end of the current detection feedback module 7 and the anode of the second diode D2, and the winding ratio between the primary coil of the transformer T and any secondary coil is 1:1.

[0068] like Figure 5 As shown, in a preferred embodiment, the fast shutdown structure 42 includes a third resistor R3 and a first transistor K1, the auxiliary device driving circuit 43 includes a third diode D3, a fourth resistor R4, a fifth resistor R5 and a fourth diode D4, and the first device under test driving circuit 44 includes a sixth resistor R6, a seventh resistor R7 and a fifth diode D5.

[0069] One end of the fourth resistor R4 is respectively connected to the other end of the third capacitor C3 and the cathode of the third diode D3, the other end of the fourth resistor R4 is respectively connected to one end of the fifth resistor R5, the cathode of the fourth diode D4 and the first electrode of the auxiliary device Q1, the other end of the fifth resistor R5 is respectively connected to the anode of the third diode D3, the opposite end of the first secondary coil, the anode of the fourth diode D4, the second electrode of the auxiliary device Q1, the cathode of the second diode D2 and one end of the inductor L;

[0070] One end of the third resistor R3 is respectively connected to the same-name end of the second secondary coil and one end of the fourth capacitor C4, the other end of the third resistor R3 is connected to the base of the first transistor K1, the emitter of the first transistor K1 is respectively connected to one end of the sixth resistor R6 and the other end of the fourth capacitor C4, the other end of the sixth resistor R6 is respectively connected to one end of the seventh resistor R7, the cathode of the fifth diode D5 and the first electrode of the device under test Q2, the other end of the seventh resistor R7 is respectively connected to the collector of the first transistor K1, the opposite-name end of the second secondary coil and the anode of the fifth diode D5, the anode of the second diode D2, the second electrode of the device under test Q2 and the input end of the current detection feedback module 7.

[0071] In a preferred embodiment, the first push-pull circuit includes a second transistor K2 and a third transistor K3, wherein the second transistor K2 is an NPN transistor and the third transistor K3 is a PNP transistor. Specifically, the second transistor K2 and the third transistor K3 are connected in series, the base of the second transistor K2 is connected to the base of the third transistor K3 and then connected to the other end of the second resistor, one end of the second resistor R2 is connected to the output end of the pulse generating module 2, the collector of the second transistor K2 is connected to the positive power signal output end of the first power output unit 11, the emitter of the second transistor K2 is respectively connected to the emitter of the third transistor K3 and one end of the second capacitor C2, the other end of the second capacitor C2 is connected to the same-name end of the primary coil, and the collector of the third transistor K3 is respectively connected to the common end of the drive signal switching switch 3 and the opposite-name end of the primary coil.

[0072] exist Figure 5 In the avalanche test circuit shown, the push-pull circuits are formed by a NPN transistor and a PNP transistor connected in series. The output of the first push-pull circuit 41 flows through the primary coil of the transformer T after passing through the second capacitor C2. All capacitors in the driving module 4 play a role in isolating DC, which helps to maintain signal integrity.

[0073] The third capacitor C3 and the fourth capacitor C4 can provide a negative voltage when turning off the auxiliary device they drive, thereby accelerating the turning off of the device they drive, and have a higher anti-interference ability. The third capacitor C3 drives the device Q1, and the fourth capacitor C4 drives the device Q2.

[0074] The primary coil in the transformer T generates an alternating magnetic field, which induces a voltage in the secondary coil, thereby transmitting energy. Figure 5 The winding ratio between the primary coil and the secondary coil in the avalanche test circuit shown is 1:1, that is, the secondary coil induces a voltage with the same magnitude and direction as the two ends of the primary coil. The third capacitor C3, the fourth capacitor C4 and the third diode D3 function to achieve signal recovery after isolation.

[0075] The fast shutdown structure formed by the third resistor R3 and the first transistor facilitates the fast shutdown of the device under test Q2, thereby ensuring that the device under test Q2 can be reliably shut down regardless of the large dynamic conditions. The fourth resistor R4 and the sixth resistor R6 are respectively the first pole driving resistor of the auxiliary device Q1 and the first pole driving resistor of the device under test Q2, which mainly play a damping role. The fifth resistor R5 and the seventh resistor R7 are protection resistors. D4 and D5 are voltage-stabilizing diodes used for clamping protection to ensure that the auxiliary device Q1 and the device under test Q2 are normally turned on.

[0076] In steps S102 to S107 provided in the present application, the pulse generating module 2 outputs a continuous single pulse under the control of the controller 6. Specifically, the controller outputs a given pulse time (different pulse times, different test currents) to the pulse generating module 2. The pulse generating module 2 generates a corresponding single pulse control signal according to the received given pulse time, and performs an avalanche test on the device under test Q2 through the driving module 4. Under the single pulse control signal, if the device under test Q2 has not failed, the pulse generating module 2 is stopped from working for a preset time period, for example, it is controlled to pause for 0.5 seconds or 1S (predetermined), and the given pulse width time increment is automatically increased (that is, the given current is increased) to obtain the updated given pulse time and send it to the control pulse generating module. After the preset time period, the pulse generating module re-performs an avalanche test on the device under test Q2 according to the updated given pulse time, and so on, gradually increasing the current until the device under test Q2 fails. After the device under test Q2 fails, the corresponding avalanche tolerance of the device under test is determined.

[0077] In a preferred embodiment, if the device under test Q2 is a silicon field effect transistor, Figure 5 For example, under each single pulse signal output by the pulse generating module 2, the avalanche test circuit performs the following actions:

[0078] The control driving signal switching switch is connected to the reference power output terminal COM in the power module 1. At this time, the high potential of the first push-pull circuit is 15V, and the low potential is 0V. The single pulse signal output by the pulse generating module 2 is input into the first push-pull circuit through the second resistor R2. When the single pulse signal is at a high level, the second transistor K2 (NPN) is turned on, and the third transistor K3 (PNP) is turned off. At this time, the primary coil voltage flows from the positive power signal output terminal +VOUT of the first power output unit 11 to the reference power output terminal COM of the first power output unit 11. Therefore, the voltage at the same-name end of the primary coil is +15V, and the voltage at the opposite-name end of the primary coil is 0V. The energy in the transformer T is respectively converted to the same-name end voltage corresponding to the first secondary coil and the second secondary coil, which is +15V, and the voltage at the opposite-name end voltage corresponding to the first secondary coil and the second secondary coil is 0V. Finally, it is determined that the gate-source voltage VGS corresponding to the auxiliary device Q1 and the device under test Q2 are +15V respectively.

[0079] When the high level time of the single pulse signal ends and the single pulse signal enters the low level, the second transistor K2 (NPN) is cut off and the third transistor K3 (PNP) is turned on, changing the voltage across the primary coil to zero potential. At the same time, the voltage across the secondary coil also changes to zero potential synchronously. At this time, the gate-source voltage VGS corresponding to the auxiliary device Q1 and the device under test Q2 are 0V respectively, and the auxiliary device Q1 and the device under test Q2 are turned off.

[0080] In a preferred embodiment, if the device under test Q2 is a silicon carbide field effect transistor, Figure 5 For example, under each single pulse signal output by the pulse generating module 2, the avalanche test circuit performs the following actions:

[0081] The control driving signal switching switch 3 is connected to the negative power signal output terminal -VOUT in the first power output unit 11. At this time, the high potential of the first push-pull circuit 41 is 15V, and the low potential is -5V. The single pulse high level output by the pulse generating module 2 is input into the first push-pull circuit through the second resistor R2. When the single pulse signal is high, the second transistor K2 (NPN) is turned on, and the third transistor K3 (PNP) is turned off. At this time, the primary coil voltage flows from the positive power signal output terminal +VOUT in the first power output unit 11 to the negative power signal output terminal -VOUT in the first power output unit 11. Therefore, the voltage at the same-name end of the primary coil is +15V, and the voltage at the opposite-name end of the primary coil is -5V. The voltage at the same-name end corresponding to the energy conversion to the secondary coil in the transformer T is +15V, and the voltage at the opposite-name end of the secondary coil is -5V. Therefore, the gate-source voltage VGS corresponding to the auxiliary device Q1 and the device under test Q2 are +20V respectively.

[0082] When the high level time of the single pulse signal ends and it enters the low level, the second transistor K2 (NPN) is cut off and the third transistor K3 (PNP) is turned on. Both ends of the primary coil are -5V. At the same time, both ends of the secondary coil are also -5V. Therefore, the VGS corresponding to the auxiliary device Q1 is 0V. Since the second pole of the device under test Q2 is grounded, the VGS corresponding to the device under test Q2 is -5V for negative voltage shutdown. Due to the parasitic effect of the silicon carbide field effect tube, VGS = -5V can completely close the channel of the silicon carbide field effect tube for avalanche testing.

[0083] See also Figure 6 , Figure 6 FIG5 shows a fifth structural diagram of an avalanche test circuit provided in an embodiment of the present application. Figure 6 As shown, the power module 1 includes a second power output unit 12 and a corresponding fifth capacitor C5 and a third power output unit 13 and a corresponding sixth capacitor C6.

[0084] Among them, the input terminal VIN of the second power output unit 12 is connected to the second input power supply VCC2 and one end of the fifth capacitor C5, the ground terminal GND of the second power output unit 12 is respectively connected to the other end of the fifth capacitor C5 and the ground terminal GND of the third power output unit 13 and then grounded, the ground terminal GND of the second power output unit 12 is also connected to the ground terminal of the current detection feedback module 7 through the first resistor R1, the positive power signal output terminal +VOUT of the second power output unit 12 is connected to the driving module 4, the reference power output terminal COM of the second power output unit 12 is connected to the driving module 4, and the negative power signal output terminal of the second power output unit 12 is suspended.

[0085] The input terminal VIN of the third power output unit 13 is respectively connected to the second input power supply VCC2 and one end of the sixth capacitor C6, the ground terminal GND of the third power output unit 13 is respectively connected to the other end of the sixth capacitor C6 and then grounded, the ground terminal GND of the third power output unit 13 is also connected to the ground terminal of the current detection feedback module 7 through the first resistor R1, the positive power signal output terminal +VOUT of the third power output unit 13 is connected to the driving module 4, the negative power signal output terminal -VOUT of the third power output unit 13 is connected to the first switching terminal of the driving signal switching switch 3, and the reference power output terminal COM of the third power output unit 13 is connected to the second switching terminal of the driving signal switching switch 3.

[0086] The driving module 4 includes an eighth resistor R8 and a corresponding second push-pull circuit 45 , a ninth resistor R9 and a corresponding third push-pull circuit 46 , an auxiliary device driving circuit 43 and a second device under test driving circuit 47 .

[0087] Among them, the output end of the pulse generating module 2 is respectively connected to one end of the eighth resistor R8 and one end of the ninth resistor R9, the other end of the eighth resistor R8 is connected to the first connection end of the second push-pull circuit 45, the second connection end of the second push-pull circuit 45 is connected to the positive power signal output end +VOUT of the second power output unit 12, the third connection end of the second push-pull circuit 42 is respectively connected to the positive reference power output end COM of the second power output unit 12 and the second input end of the auxiliary device driving circuit 43, the output end of the second push-pull circuit 45 is connected to the first input end of the auxiliary device driving circuit 43, the first output end of the auxiliary device driving circuit 43 is connected to the first pole of the auxiliary device Q1, and the second output end of the auxiliary device driving circuit 43 is connected to the second pole of the auxiliary device Q1.

[0088] The other end of the ninth resistor R9 is connected to the first connection end of the third push-pull circuit 46, the second connection end of the third push-pull circuit 46 is connected to the positive power signal output end +VOUT of the third power output unit 13, the third connection end of the third push-pull circuit 46 is respectively connected to the common end of the drive signal switching switch 3 and the second input end of the second device under test drive circuit 47, the output end of the third push-pull circuit 46 is connected to the first input end of the second device under test drive circuit 47, the first output end of the second device under test drive circuit 47 is connected to the first pole of the device under test Q2, and the second output end of the second device under test drive circuit 47 is connected to the second pole of the device under test Q2.

[0089] In a preferred embodiment, the second push-pull circuit 45 includes a fourth transistor K4 and a fifth transistor K5, the fourth transistor K4 is an NPN transistor, the fifth transistor K5 is a PNP transistor, the base of the fourth transistor K4 is connected to the base of the fifth transistor K5 and then connected to the other end of the eighth resistor R8, the collector of the fourth transistor K4 is connected to the positive power signal output terminal +VOUT of the second power output unit 12, the emitter of the fourth transistor K4 is respectively connected to the emitter of the fifth transistor K5, the cathode of the third transistor D3 in the auxiliary device driving circuit 43 and one end of the fourth resistor R4, and the other end of the fourth resistor R4 is respectively connected to one end of the fifth resistor R5, the cathode of the fourth diode D4 and the first pole of the auxiliary device Q1.

[0090] The collector of the fifth transistor K5 is respectively connected to the reference power output terminal COM of the second power output unit 12, the anode of the third transistor D3, the other end of the fifth resistor R5, the anode of the fourth diode D4, the second pole of the auxiliary device Q1, one end of the inductor L and the cathode of the second diode D2.

[0091] The third push-pull circuit 46 includes a sixth transistor K6 and a seventh transistor K7, the fourth transistor K6 is an NPN transistor, the fifth transistor K7 is a PNP transistor, and the second device under test driving circuit 47 includes a sixth diode D6, a seventh diode D7, a tenth resistor R10 and an eleventh resistor R11.

[0092] Among them, the base of the sixth transistor K6 is connected to the base of the seventh transistor K7 and then connected to the other end of the ninth resistor R9, the collector of the sixth transistor K6 is connected to the positive power signal output end +VOUT of the third power output unit 13, the emitter of the sixth transistor K6 is respectively connected to the emitter of the seventh transistor K7, one end of the tenth resistor R10 and the cathode of the sixth diode D6, the other end of the tenth resistor R10 is respectively connected to one end of the eleventh resistor R11, the cathode of the seventh diode D7 and the first electrode of the device under test Q2, and the collector of the seventh transistor K7 is respectively connected to the common end of the drive signal switching switch 3, the anode of the sixth diode, the other end of the eleventh resistor R11, the anode of the seventh diode D7, the second electrode of the device under test Q2, the anode of the second diode D2 and the input end of the current detection feedback module 7.

[0093] for Figure 6 The avalanche test circuit shown in the figure is different in that two power output units and two push-pull circuits are provided to provide corresponding drives for the auxiliary device Q1 and the device under test Q2 respectively, and the control method of the drive signal switching switch is the same as that of the avalanche test circuit shown in the figure. Figure 5 The control method of the driving signal switching switch in the avalanche test circuit shown is the same and will not be described in detail here.

[0094] In a preferred embodiment, if the device under test Q2 is a silicon field effect transistor, Figure 6 For example, under each single pulse signal output by the pulse generating module 2, the avalanche test circuit performs the following actions:

[0095] The control drive signal switching switch is connected to the reference power supply output terminal COM in the power supply module 1. At this time, the high potential of the second push-pull circuit is 10V, and the low potential is 0V. The high potential of the third push-pull circuit is 10V, and the low potential is 0V. The single pulse signal output by the pulse generating module 2 is input into the second push-pull circuit through the eighth resistor R8 and into the third push-pull circuit through the ninth resistor R9.

[0096] When the single pulse signal is at a high level, the fourth transistor K4 (NPN) is turned on, the fifth transistor K5 (PNP) is turned off, the sixth transistor K6 (NPN) is turned on, and the seventh transistor K7 (PNP) is turned off. At this time, the second push-pull circuit and the third push-pull circuit output a high level, and the gate-source voltage VGS corresponding to the auxiliary device Q1 and the device under test Q2 are respectively at a high level, and the auxiliary device Q1 and the device under test Q2 are turned on.

[0097] When the high level time of the single pulse signal ends and the single pulse signal enters a low level, the fourth transistor K4 (NPN) is cut off, the fifth transistor K5 (PNP) is turned on, the sixth transistor K6 (NPN) is cut off, and the seventh transistor K7 (PNP) is turned on. At this time, the gate-source voltage VGS corresponding to the auxiliary device Q1 and the device under test Q2 are 0V respectively, and the auxiliary device Q1 and the device under test Q2 are turned off.

[0098] In another preferred embodiment, if the device under test Q2 is a silicon carbide field effect transistor, Figure 6 For example, under each single pulse signal output by the pulse generating module 2, the avalanche test circuit performs the following actions:

[0099] The control drive signal switching switch 3 is connected to the negative power signal output terminal -VOUT in the third power output unit 13. At this time, the high potential of the second push-pull circuit is 10V, and the low point is 0V. The high potential of the third push-pull circuit is 10V, and the low point is -5V. The single pulse signal output by the pulse generating module 2 is input into the second push-pull circuit through the eighth resistor R8 and into the third push-pull circuit through the ninth resistor R9.

[0100] When the single pulse signal is at a high level, the fourth transistor K4 (NPN) is turned on, the fifth transistor K5 (PNP) is turned off, the sixth transistor K6 (NPN) is turned on, and the seventh transistor K7 (PNP) is turned off. At this time, the second push-pull circuit and the third push-pull circuit output a high level, and the gate-source voltage VGS corresponding to the auxiliary device Q1 and the device under test Q2 are respectively at a high level, and the auxiliary device Q1 and the device under test Q2 are turned on.

[0101] When the high level time of the single pulse signal ends and the single pulse signal enters a low level, the fourth transistor K4 (NPN) is cut off, the fifth transistor K5 (PNP) is turned on, the sixth transistor K6 (NPN) is cut off, and the seventh transistor K7 (PNP) is turned on. At this time, the gate-source voltage VGS corresponding to the auxiliary device Q1 and the device under test Q2 are 0V respectively, and the auxiliary device Q1 and the device under test Q2 are turned off.

[0102] In a preferred embodiment, the current data includes a target maximum current flowing between the third pole and the second pole of the device under test before avalanche failure occurs in the device under test, wherein the single pulse avalanche energy corresponding to the device under test is determined by the following formula:

[0103]

[0104] In this formula, E AS It represents the single pulse avalanche energy corresponding to the device under test, L represents the inductance value in the test module, I ASIt indicates the target maximum current flowing between the third and second poles of the device under test before avalanche failure occurs.

[0105] In one specific embodiment, see Figure 7 , Figure 7 FIG. 1 is a schematic diagram showing the voltage and current changes during an avalanche test of a device under test provided by an embodiment of the present application. Figure 7 As shown, I D Indicates the third-pole current corresponding to the device under test Q2, V DS Indicates the drain-source voltage corresponding to the device under test, V GS Indicates the gate-source voltage corresponding to the device under test. During the avalanche test, after the auxiliary device Q1 and the device under test Q2 are turned on at the same time, the test circuit is connected, and the first input power supply VCC1 charges the inductor L. Since the current flowing through the inductor L cannot change suddenly, the current I D It rises linearly until it reaches the maximum target current I that can be achieved by this single pulse. AR After the device under test Q2 is turned off, the inductor stops charging and releases energy in the original charging direction to impact the device under test Q2. At this time, the captured current I flowing through the device under test D It decreases linearly according to Figure 7 The voltage, current and energy release time can be integrated to calculate the single pulse avalanche energy generated by the device under test Q2 during the inductor energy release phase. The integral conversion of the formula can be simplified to:

[0106]

[0107] In this formula, E AS It represents the single pulse avalanche energy corresponding to the device under test, L represents the inductance value in the test module, I AS It indicates the maximum target current that flows through the device under test before avalanche failure occurs.

[0108] In a specific embodiment, the inductance L is 0.87 mH, the maximum current before avalanche failure is 32 A, and the above formula is substituted to obtain:

[0109]

[0110] The current I flowing through the device under test D The relationship between the inductor, the first input power supply VCC1, and the single pulse time is I D =U×t / L, where U represents the voltage corresponding to the first input power supply VCC1, L represents the inductance, and t represents the single pulse time. Therefore, when U and the inductance L are fixed, the current I flowing through the device under test can be realized by reasonably changing the single pulse time (in this application, by increasing the given pulse width time increment corresponding to the appropriate high potential). D The voltage rises until the avalanche breakdown of the device under test stops.

[0111] The benefits of this application are:

[0112] 1. Expand the avalanche test range so that the test method of this application can adapt to different devices under test, including silicon carbide field effect transistors and silicon field effect transistors.

[0113] 2. Improve test efficiency and safety by integrating test methods into the controller for automatic operation.

[0114] 3. Simplify the test process, optimize the test methods, and achieve higher integration.

[0115] 4. The use of heat sink improves test accuracy.

[0116] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In the several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0117] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0118] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0119] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0120] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An avalanche test circuit, characterized in that: The avalanche test circuit includes a controller, a power supply module, a pulse generation module, a drive signal switching switch, a drive module and a test module. Among them, the positive power signal output end of the power module is connected to the driving module, the two switching ends of the driving signal switching switch are respectively connected to the negative power signal output end and the reference power output end of the power module, the common end of the driving signal switching switch is connected to the driving module, the controller is respectively connected to the pulse generating module, the control end of the driving signal switching switch and the testing module, the pulse generating module is also connected to the driving module, and the driving module is connected to the testing module.

2. The avalanche test circuit according to claim 1, characterized in that: The test module includes a first diode, an auxiliary device, an inductor, a device under test, and a second diode. The first electrode of the auxiliary device is connected to the driving module, the anode of the first diode is connected to the first input power supply, the cathode of the first diode is connected to the third electrode of the auxiliary device, and the second electrode of the auxiliary device is respectively connected to one end of the inductor, the driving module and the cathode of the second diode. The first pole of the device under test is connected to the driving module, the third pole of the device under test is connected to the other end of the inductor, the second pole of the device under test is respectively connected to the driving module, the controller and the anode of the second diode, and a heat sink is placed under the device under test.

3. The avalanche test circuit according to claim 2, characterized in that: The avalanche test circuit also includes a current detection feedback module and a first resistor, the input end of the current detection feedback module is connected to the second pole of the device under test, the output end of the current detection feedback module is connected to the controller, the ground end of the current detection feedback module is grounded, and the ground end of the current detection feedback module is also connected to the ground end of the power supply module through the first resistor.

4. The avalanche test circuit according to claim 3, characterized in that: The power module includes a first power output unit and a first capacitor corresponding thereto. The input end of the first power output unit is connected to the second input power supply and one end of the first capacitor, the ground end of the first power output unit is connected to the other end of the first capacitor and then grounded, and the ground end of the first power output unit is also connected to the ground end of the current detection feedback module through the first resistor; The positive power signal output terminal of the first power output unit is connected to the driving module, the negative power signal output terminal of the first power output unit is connected to the first switching terminal of the driving signal switching switch, and the reference power output terminal of the first power output unit is connected to the second switching terminal of the driving signal switching switch.

5. The avalanche test circuit according to claim 4, characterized in that: The driving module includes a second resistor, a first push-pull circuit, a second capacitor, a transformer, a third capacitor, a fourth capacitor, a fast shutdown structure, an auxiliary device driving circuit and a first device under test driving circuit. Wherein, one end of the second resistor is connected to the output end of the pulse generating module, the other end of the second resistor is connected to the first input end of the first push-pull circuit, the second input end of the first push-pull circuit is connected to the positive power signal output end of the first power output unit, the third input end of the first push-pull circuit is respectively connected to the common end of the drive signal switching switch and the opposite-name end of the primary coil of the transformer, and the output end of the first push-pull circuit is connected to the same-name end of the primary coil of the transformer through the second capacitor; The same-name end of the first secondary coil of the transformer is connected to one end of the third capacitor, the other end of the third capacitor is connected to the first input end of the auxiliary device driving circuit, the opposite-name ends of the first secondary coil are respectively connected to the second input end of the auxiliary device driving circuit, the first output end of the auxiliary device driving circuit is connected to the first pole of the auxiliary device, and the second output end of the auxiliary device driving circuit is connected to the second pole of the auxiliary device; The like-name ends of the second secondary coil of the transformer are respectively connected to one end of the fourth capacitor and the first connection end of the fast shutdown structure, the other end of the fourth capacitor is respectively connected to the first input end of the first device under test drive circuit and the second connection end of the fast shutdown structure, the opposite-name ends of the second secondary coil are respectively connected to the second input end of the first device under test drive circuit and the third connection end of the fast shutdown structure, the first output end of the first device under test drive circuit is connected to the first pole of the device under test, the second output end of the first device under test drive circuit is connected to the second pole of the device under test, and the winding ratio between the primary coil of the transformer and any secondary coil is 1:

1.

6. The avalanche test circuit according to claim 5, characterized in that: The fast shutdown mechanism includes a third resistor and a first triode, the auxiliary device driving circuit includes a third diode, a fourth resistor, a fifth resistor and a fourth diode, and the first device under test driving circuit includes a sixth resistor, a seventh resistor and a fifth diode, One end of the fourth resistor is respectively connected to the other end of the third capacitor and the cathode of the third diode, the other end of the fourth resistor is respectively connected to one end of the fifth resistor, the cathode of the fourth diode and the first pole of the auxiliary device, and the other end of the fifth resistor is respectively connected to the anode of the third diode, the opposite end of the first secondary coil, the anode of the fourth diode, the second pole of the auxiliary device, the cathode of the second diode and one end of the inductor; One end of the third resistor is respectively connected to the same-name end of the second secondary coil and one end of the fourth capacitor, the other end of the third resistor is connected to the base of the first transistor, the emitter of the first transistor is respectively connected to one end of the sixth resistor and the other end of the fourth capacitor, the other end of the sixth resistor is respectively connected to one end of the seventh resistor, the cathode of the fifth diode and the first pole of the device under test, and the other end of the seventh resistor is respectively connected to the collector of the first transistor, the opposite-name end of the second secondary coil and the anode of the fifth diode, the anode of the second diode, the second pole of the device under test and the input end of the current detection feedback module.

7. The avalanche test circuit according to claim 3, characterized in that: The power module includes a second power output unit and a corresponding fifth capacitor and a third power output unit and a corresponding sixth capacitor. Among them, the input end of the second power output unit is connected to the second input power supply and one end of the fifth capacitor, the ground end of the second power output unit is connected to the other end of the fifth capacitor and the ground end of the third power output unit respectively and then grounded, the ground end of the second power output unit is also connected to the ground end of the current detection feedback module through the first resistor, the positive power signal output end of the second power output unit is connected to the driving module, and the reference power output end of the second power output unit is connected to the driving module. The input end of the third power output unit is respectively connected to the second input power supply and one end of the sixth capacitor, the ground end of the third power output unit is respectively connected to the other end of the sixth capacitor and then grounded, the ground end of the third power output unit is also connected to the ground end of the current detection feedback module through the first resistor, the positive power signal output end of the third power output unit is connected to the driving module, the negative power signal output end of the third power output unit is connected to the first switching end of the driving signal switching switch, and the reference power output end of the third power output unit is connected to the second switching end of the driving signal switching switch.

8. The avalanche test circuit according to claim 7, characterized in that: The driving module includes an eighth resistor and a corresponding second push-pull circuit, a ninth resistor and a corresponding third push-pull circuit, an auxiliary device driving circuit and a second device under test driving circuit, The output end of the pulse generating module is connected to one end of the eighth resistor and one end of the ninth resistor respectively. The other end of the eighth resistor is connected to the first connection end of the second push-pull circuit, the second connection end of the second push-pull circuit is connected to the positive power signal output end of the second power output unit, the third connection end of the second push-pull circuit is respectively connected to the positive reference power output end of the second power output unit and the second input end of the auxiliary device driving circuit, the output end of the second push-pull circuit is connected to the first input end of the auxiliary device driving circuit, the first output end of the auxiliary device driving circuit is connected to the first pole of the auxiliary device, and the second output end of the auxiliary device driving circuit is connected to the second pole of the auxiliary device; The other end of the ninth resistor is connected to the first connection end of the third push-pull circuit, the second connection end of the third push-pull circuit is connected to the positive power signal output end of the third power output unit, the third connection end of the third push-pull circuit is respectively connected to the common end of the drive signal switching switch and the second input end of the second device under test drive circuit, the output end of the third push-pull circuit is connected to the first input end of the second device under test drive circuit, the first output end of the second device under test drive circuit is connected to the first pole of the device under test, and the second output end of the second device under test drive circuit is connected to the second pole of the device under test.

9. An avalanche testing method, characterized in that: A controller used in the avalanche test circuit provided in any one of claims 1 to 8, the method comprising: According to the type of the device under test in the test module, the drive signal switch is controlled to perform a target switching action so that the drive module is connected to a negative power input signal corresponding to the type of the device under test; Controlling the pulse generation module to perform an avalanche test on the device under test in the test module according to a given pulse width time; Determining whether the device under test has failed, and if the device under test has not failed, controlling the pulse generating module to stop working for a preset time period; After the pulse generation module stops working for a preset time period, a given pulse width time increment is applied to the given pulse width time to obtain an updated given pulse width time, and the pulse generation module is controlled to perform an avalanche test on the device under test in the test module according to the updated given pulse width time; If the device under test fails, collecting current data corresponding to the device under test before avalanche; The single pulse avalanche energy of the device under test is calculated using the current data.

10. The method according to claim 9, characterized in that The devices under test are divided into silicon field effect transistors and silicon carbide field effect transistors. Wherein, according to the type of the device under test in the test module, the step of controlling the drive signal to perform the target switching action includes: If the device under test is a silicon field effect transistor, the drive signal switch is controlled to switch to the reference power output terminal of the power module; If the device under test is a silicon carbide field effect transistor, the drive signal switch is controlled to switch to the negative power signal output terminal of the power module.

11. The method according to claim 10, characterized in that Determine whether the device under test fails by: Collecting the target current flowing through the device under test by a current detection feedback module; Determining whether the target current is greater than a preset instantaneous current threshold; If the target current is greater than or equal to a preset instantaneous current threshold, determining that the device under test has failed; If the target current is less than the preset instantaneous current threshold, it is determined that the device under test has not failed.

12. The method according to claim 10, characterized in that The current data includes the maximum target current flowing through the device under test before avalanche failure occurs in the device under test, The single pulse avalanche energy corresponding to the device under test is determined by the following formula: In this formula, E AS It represents the single pulse avalanche energy corresponding to the device under test, L represents the inductance value in the test module, I AS It indicates the maximum target current that flows through the device under test before avalanche failure occurs.

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