Automatic Test Vector Generation Method and System Based on Decision Tree

Abstract

The present invention discloses a method and system for automatic test vector generation based on a decision tree. The method first extracts node feature data of a circuit under test, and then uses a trained decision tree model to obtain the backtracking confidence level for each logic gate. The backtracking confidence level is the predicted probability value of the decision tree model for the successful propagation of a fault by the logic gate in the backtracking path. Finally, the logic gates with high backtracking confidence levels are selected as nodes to be added to the backtracking path, and test vectors are generated according to the backtracking path. The present invention can effectively reduce the number of test vectors, reduce the time complexity of fault detection, and solve the problems of high backtracking frequency, large resource consumption, and interference from noise data in traditional methods.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit testability design, and particularly to an automatic test vector generation method and system based on a decision tree. Background Art

[0002] ATPG (Automatic Test Pattern Generation) is the process of automatically generating test vectors used in integrated circuit testing. As the complexity of circuit logic increases, ATPG has problems such as excessive backtracking times and large computational overhead when dealing with large-scale circuits. In addition, the characteristic data generated in the backtracking path is easily affected by noise, making the selection of the fault propagation path inaccurate, resulting in low quality of test vector generation and affecting the overall test efficiency.

[0003] In recent years, artificial intelligence technology has gradually been applied to the field of automatic test vector generation to improve the efficiency and accuracy of fault detection. An artificial neural network is used to assist in the path selection during the backtracking process. However, traditional artificial neural networks are prone to overfitting problems when dealing with complex circuit structures and noisy data, resulting in unstable backtracking path selection, increasing the number of test vectors, and reducing the test efficiency and coverage. Therefore, how to reduce the number of backtracking times and the number of test vectors while ensuring test accuracy and improving the efficiency of automatic test vector generation is an urgent problem to be solved. Summary of the Invention

[0004] Object of the Invention: The object of the present invention is to provide an automatic test vector generation method and system based on a decision tree to solve the problems of excessive backtracking times and low test vector generation efficiency in the traditional automatic test vector generation process.

[0005] Technical Solution: The automatic test vector generation method based on a decision tree according to the present invention includes the following steps:

[0006] Extract the node feature data of the circuit under test, and use the trained decision tree model to calculate the backtracking confidence of each logic gate. The backtracking confidence is the predicted probability value of the decision tree model for the successful propagation of faults by the logic gate in the backtracking path; select the logic gates with high backtracking confidence as nodes and add them to the backtracking path, and generate test vectors according to the backtracking path.

[0007] Among them, the training method of the decision tree model includes:

[0008] Parse the circuit netlist file, extract the node feature data on the backtracking path during the backtracking process, add real labels to the backtracking path, and establish a circuit feature data set; establish a decision tree model, input the circuit feature data set into the decision tree model for training and verification, and obtain the predicted labels of each node.

[0009] Further, the node feature data includes logic gate type, controllability, observability, circuit level, and decision tendency.

[0010] Further, the logic gate types include AND gate, NOT gate, and OR gate; the controllability is divided into high testability and low testability according to the controllability risk reduction threshold; the observability is divided into high observability and low observability according to the observability risk reduction threshold; the circuit level is divided into high level and low level according to the circuit level risk reduction threshold; the decision tendency is divided into tendency to select 1 and tendency to select 0 according to the decision tendency risk reduction threshold.

[0011] Further, selecting the logic gate with a high backtracking confidence as a node and adding it to the backtracking path includes: selecting the fault occurrence source node as the backtracking starting point, and each time during backtracking, selecting the logic gate with the highest backtracking confidence from the logic gates connected to the current node and adding it to the backtracking path.

[0012] Further, the loss function of the decision tree model is the negative exponential loss function.

[0013] The automatic test vector generation system based on a decision tree according to the present invention includes:

[0014] A feature extraction unit for extracting node feature data of a circuit under test;

[0015] A backtracking confidence calculation unit for obtaining the backtracking confidence of each logic gate by using a trained decision tree model, where the backtracking confidence is the predicted probability value of the decision tree model for the successful propagation of a fault by the logic gate in the backtracking path;

[0016] Among them, the training method of the decision tree model includes:

[0017] Parsing a circuit netlist file, extracting node feature data on the backtracking path during backtracking, adding true labels to the backtracking path, and establishing a circuit feature data set; establishing a decision tree model, inputting the circuit feature data set into the decision tree model for training and verification, and obtaining the predicted label of each node

[0018] A test vector generation unit for selecting the logic gate with a high backtracking confidence as a node and adding it to the backtracking path, and generating a test vector according to the backtracking path.

[0019] Further, the node feature data includes logic gate type, controllability, observability, circuit level, and decision tendency;

[0020] The types of logic gates include AND gates, NOT gates, and OR gates; the controllability is divided into high testability and low testability according to the controllability risk reduction threshold; the observability is divided into high observability and low observability according to the observability risk reduction threshold; the circuit level is divided into high level and low level according to the circuit level risk reduction threshold; the decision tendency is divided into tendency to select 1 and tendency to select 0 according to the decision tendency risk reduction threshold.

[0021] Further, in the test vector generation unit, the selection of the logic gate with a high backtracking confidence as a node and adding it to the backtracking path includes: selecting the fault occurrence source node as the backtracking starting point, and each time backtracking, selecting the logic gate with the highest backtracking confidence from the logic gates connected to the current node and adding it to the backtracking path.

[0022] The electronic device of the present invention includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the computer program is loaded into the processor, the automatic test vector generation method based on the decision tree is implemented.

[0023] The computer-readable storage medium of the present invention stores a computer program. When the computer program is executed by a processor, the automatic test vector generation method based on the decision tree is implemented.

[0024] Beneficial effects: Compared with the prior art, the advantages of the present invention are as follows: (1) By establishing a decision tree model, the present invention effectively learns and analyzes the circuit feature data generated during the backtracking process, and optimizes the selection of the backtracking path in fault detection; (2) The present invention uses information such as logic gate type, controllability, observability, circuit level, and decision tendency to establish a circuit feature data set, and trains the decision tree model so that it can accurately learn the complex relationship between the backtracking path and the circuit features; (3) The present invention designs a robust loss function, calculates the backtracking confidence through the negative exponential loss function, effectively smooths the predicted output, enhances the anti-interference ability of the model to noise data, and ensures that the backtracking confidence of the logic gate can still be stably predicted in a complex circuit. In summary, the present invention can effectively reduce the number of test vectors, reduce the time complexity of fault detection, and greatly improve the efficiency of automatic test vector generation on the premise of ensuring the fault coverage rate, and solves the problems of high backtracking frequency, large resource consumption, and interference of noise data in traditional methods. Description of the Drawings

[0025] Figure 1 It is a flowchart of the automatic test vector generation method of the present invention.

[0026] Figure 2 It is a schematic diagram of the generation of the circuit feature data set in the embodiment of the present invention.

[0027] Figure 3Schematic diagram of the circuit feature dataset file for the embodiments of the present invention.

[0028] Figure 4 Schematic diagram of the recursive partitioning of decision tree features for the embodiments of the present invention.

[0029] Figure 5 Flowchart of the decision tree training process for the embodiments of the present invention.

[0030] Figure 6 Schematic diagram of the statistical report for automatic test vector generation for the embodiments of the present invention.

[0031] Figure 7 Schematic diagram of the detailed data of the test vectors for the embodiments of the present invention. Specific implementation manners

[0032] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0033] As Figure 1 shown, in this embodiment, a basic combinational circuit is taken as an example for illustration. The circuit includes: three NAND gates G1, G2, G3, two AND gates G5, G6, and two OR gates G4, G7. The lines between adjacent logic gates are represented by h, i, j, k, l, m, n, o, p. The automatic test vector generation method based on decision tree of the present invention includes the following steps.

[0034] Step 1: Read the netlist file, collect five types of feature data generated by each logic gate on the backtracking path, including logic gate type, controllability, observability, circuit hierarchy, and decision tendency; make a circuit feature dataset, and randomly divide the circuit feature dataset into a training set, a validation set, and a test set according to a preset ratio.

[0035] Step 2: Construct a decision tree model, input the training set and the validation set into the decision tree model for training and validation, obtain a training model file, and adjust the robustness parameter to optimize the decision tree model.

[0036] The decision tree model includes four core parameters: loss function, maximum tree depth, maximum number of leaf nodes, and minimum number of samples in a leaf node, and four core steps: training, inference, evaluation, and feature importance analysis. Among them:

[0037] The training step includes data preprocessing, parameter initialization, recursive construction of the tree structure, recursive partitioning of leaf nodes, and storage of node depth information;

[0038] The inference step includes traversing samples, indexing leaf nodes, and calculating the prediction result of the class distribution according to the negative exponential loss function;

[0039] The evaluation steps include predicting the matching degree between the predicted label and the true label, and calculating the total loss based on the risks of the leaf nodes.

[0040] The feature importance steps include calculating the risk reduction of each node and measuring the dependence of the tree on the input features.

[0041] The loss function of the decision tree model is the negative exponential loss function (NE), and its expression is as follows, where represents the value of the loss function, y represents the true label, represents the confidence or output value predicted by the model, represents the adjustable robustness parameter, represents the exponential loss between the predicted value and the true label:

[0042] ;

[0043] The recursive partitioning expression of the leaf nodes in the training step is as follows, where D represents the sample set on the current node, and S represents the sample set on the parent node. represents the purity or impurity measure of the set S, represents the sample subset that satisfies of the sample subset, represents the sample subset that satisfies of the sample subset, represents the subset of the purity or impurity measure, represents the subset of the purity or impurity measure:

[0044] ;

[0045] The expression for calculating the class distribution in the inference step is as follows, where represents the probability distribution of the th class, represents the numerical value of the th class label, represents the confidence or output value predicted by the model, represents the robustness parameter, represents the set of all classes:

[0046] ;

[0047] The expression for calculating the total loss of risk in the feature importance step is as follows, where represents the risk reduction brought by the split, represents the risk value of the current node, represents the risk value of the left child node, represents the risk value of the right child node, Represents the minimum threshold for risk reduction:

[0048] 。

[0049] Step 3: Read the netlist file of the circuit to be tested, extract its circuit feature data, and input it into the optimized robustness decision tree model. Calculate the backtracking confidence of each logic gate. The backtracking confidence is the predicted probability value of the model for the successful propagation of faults by the logic gate in the backtracking path. Store the predicted backtracking confidence results and mark the circuit nodes to form a backtracking confidence mapping table.

[0050] Step 4: Select the fault occurrence source node as the backtracking starting point. When generating the backtracking path, for each node, select the logic gate with the highest backtracking confidence value among the logic gates it is connected to and add it to the backtracking path.

[0051] Step 5: Finally, generate a backtracking path that can effectively propagate faults. Under the guidance of the backtracking path, generate test vectors with the highest fault coverage and the least redundancy.

[0052] For a better understanding of the present invention, it will be separately explained from the following four aspects.

[0053] (1) Overall process of the automatic test vector generation method based on decision tree.

[0054] A complete automatic test vector generation process is divided into four stages, namely reading the netlist, generating the fault list, generating the test vector, and detecting the fault. In the traditional automatic test vector generation method, when facing complex large-scale circuits, there are problems such as a large number of backtracking times and low test vector generation efficiency. To solve this problem, the present invention proposes an automatic test vector generation method based on decision tree, which collects the feature data generated during the backtracking process of automatic test vector generation; constructs a dedicated circuit feature data set and divides it into a training set, a validation set, and a test set according to a preset ratio; designs a robustness loss function, constructs and trains a decision tree model; applies the optimized decision tree model to the circuit netlist file of the circuit under test to predict the confidence of each logic gate; guides the selection of the backtracking path based on the prediction results, and finally generates test vectors.

[0055] The present invention reduces the waste of computing resources caused by backtracking through optimizing the backtracking path selection, and reduces the automatic test cost while maintaining the fault coverage, resulting in a significant reduction in the number of backtracking times and the number of test vectors.

[0056] (2) Generation process of the circuit feature data set.

[0057] Refer to Figure 2, Parse the netlist file to extract the path information and node feature data generated during the backtracking process. Collect the node features on multiple backtracking paths through the ATPG algorithm. For example, when detecting a fault on a certain line at the output of the sample circuit, the ATPG algorithm will generate multiple backtracking paths. These paths include the paths that successfully propagate the fault (marked as "success") and the paths that fail to propagate the fault (marked as "failure"). For example, a successful path can be represented as path n-j-g, and a failed path can be represented as path m-l-h-a. By analyzing these paths, extract the feature information related to logic gates, including logic gate type, controllability, observability, circuit hierarchy, and decision tendency.

[0058] Each node on the backtracking path will contain the above feature information, and the collection of this information is carried out during the entire process from the start of the ATPG program to the completion of all fault detections. In the circuit feature dataset, the nodes on the successful backtracking paths are marked as "1", and the nodes on the failed backtracking paths are marked as "0", forming a dataset with clear labels.

[0059] Refer to Figure 3 , This circuit feature dataset of the backtracking path shows a successful decision path, with the starting decision point being GateID 16. The relevant logic gate information is listed in the path, including the attribute values of each gate and its depth relationship with the main output terminal. Specifically, each logic gate has the following fields: GateID is the unique identifier of the logic gate, numFO represents the output fan-out number of the logic gate, which is 2 in this data, indicating that the output of each logic gate is connected to two subsequent logic gates; cc0 and cc1 represent the control 0 condition and control 1 condition of the logic gate respectively, with values of 2 and 3; co represents controllability and observability, with a value of 1; the depthFromPo field represents the depth of the logic gate from the main output terminal. In this path, the cc0, cc1, and co values of all logic gates are consistent, while the depthFromPo field gradually decreases, indicating that the logic gates gradually approach the main output terminal from the deep layer.

[0060] It should be noted that by annotating and preprocessing these backtracking feature data, the generated circuit feature dataset is randomly divided into a training set, a validation set, and a test set according to the ratio of 80%, 10%, and 10% for model training, validation, and evaluation. The ratio of the training set, validation set, and test set can be adjusted during actual use. The generation process of the circuit feature dataset not only retains the circuit structure information in the backtracking path but also captures the dynamically changing features during the fault propagation process, providing high-quality data input for the robust decision tree model.

[0061] (3) The training process of the robust decision tree model.

[0062] Refer toFigure 4 The training process of the decision tree starts from the root node and gradually divides the nodes based on the circuit feature data. The dataset is recursively divided into subsets according to the selected features. This process continues until a stopping condition is met, such as reaching the maximum depth, the node purity is high enough, or the number of samples is below the threshold. When it stops, the node becomes a leaf node, storing the class distribution and prediction values.

[0063] For example, if "gate type" is selected as the splitting feature, the dataset will be divided into three subsets: AND gate, NOT gate, and OR gate;

[0064] If "controllability" is selected as the splitting feature, the dataset will be divided into two subsets: high controllability and low controllability; the splitting criterion is determined according to the minimum threshold of controllability risk reduction. Those above this threshold will be divided into the high controllability subset, and those below this threshold will be divided into the low controllability subset;

[0065] If "observability" is selected as the splitting feature, the dataset will be divided into two subsets: high observability and low observability; the splitting criterion is determined according to the minimum threshold of observability risk reduction. Those above this threshold will be divided into the high observability subset, and those below this threshold will be divided into the low observability subset;

[0066] If "decision tendency" is selected as the splitting feature, the dataset will be divided into two subsets: tendency to select 1 and tendency to select 0; the splitting criterion is determined according to the minimum threshold of decision tendency risk reduction. Those above this threshold will be divided into the tendency to select 1 subset, and those below this threshold will be divided into the tendency to select 0 subset;

[0067] If "circuit level" is selected as the splitting feature, the dataset will be divided into two subsets: high level and low level; the splitting criterion is determined according to the minimum threshold of circuit level risk reduction.

[0068] Those above this threshold will be divided into the high level subset, and those below this threshold will be divided into the low level subset.

[0069] Refer to Figure 5, specifically, the model initializes an empty decision tree T and sets the maximum depth, minimum number of samples, and the robustness parameter μ. The training process starts from the root node and recursively calls the BuildTree function to construct the decision tree. At each node, the model selects the optimal feature and splitting threshold through FindBestSplit, calculates the splitting quality according to the negative exponential loss function, evaluates the risk reduction of the left and right child nodes, and updates the splitting rule of the decision node. During the splitting process, the model dynamically adjusts the threshold to optimize the feature segmentation, ensuring that each split can maximize the purity of the child nodes. By restricting the marginal loss, this loss function can effectively handle the noise in the training data and improve the robustness of the model on complex backtracking path data. When the number of samples in the node is lower than the set threshold or reaches the maximum depth, the splitting stops, the node is marked as a leaf node, and the distribution of class samples is recorded as the prediction output.

[0070] The advantage of optimizing the splitting quality through the robust loss function is that the model can smooth the impact of noisy data, making the splitting rule more robust, especially suitable for processing backtracking path data with dynamic weight characteristics and complex feature distributions. The recursive construction process of the tree ensures that the model can gradually capture the non-linear relationships between features, thereby deeply learning the key characteristics of the backtracking path. Through the optimization of the splitting rule, the model can not only effectively distinguish the successful path and the failure path, but also quantify the relative importance of circuit features, providing a reliable basis for optimizing the automatic test vector generation.

[0071] Furthermore, the decision tree model has good interpretability. By analyzing the decision path, it can be clearly seen which features play a key role in the node splitting. For example, certain specific gate types or dynamic backtracking tendency values frequently appear in the splitting rule of the model, indicating that they have a greater impact on path selection. In addition, the adjustment of the robustness parameter μ enables the model to adapt to the characteristics of different circuits. Especially when dealing with complex circuit structures, the optimized decision tree can significantly reduce the number of backtracking times and the number of test vectors.

[0072] (4) Model evaluation and feature importance analysis.

[0073] The evaluation process of the robust decision tree model is mainly carried out by comparing the matching degree between the prediction results and the true labels. The evaluation of the model includes not only accuracy but also loss calculation. First, the model calculates the prediction accuracy to evaluate the correct classification ability of the decision tree for the backtracking paths. The calculation method of the prediction accuracy is to calculate the proportion of correct predictions by comparing the predicted labels and the actual labels of each backtracking path of the model. For the test set, the model can distinguish successful paths and failed paths, and a high accuracy means that the decision tree has high reliability in the selection of backtracking paths. Secondly, the robust decision tree also calculates the loss function value and uses the negative exponential loss function to evaluate the splitting quality of the model. This loss function effectively smooths the influence of noisy data, enabling the model to maintain good stability when facing complex or noisy data. During the evaluation process, the robust decision tree model can automatically handle the non-linear features in the circuit data, ensuring that each split maximizes the prediction accuracy while reducing the risk of misclassification.

[0074] Furthermore, the performance of the model is also verified by testing different circuits. By conducting experiments on multiple circuits, the model demonstrates strong generalization ability, has good application effects in different circuit designs, maintains a high accuracy level, and has a low loss function value, indicating that the model can maintain good prediction ability in various test circuits. In this way, the evaluation process not only verifies the accuracy of the robust decision tree but also confirms its adaptability and robustness. Especially when facing complex circuit structures, the model can effectively avoid overfitting.

[0075] It should also be noted in this embodiment that during the feature importance analysis process, the robust decision tree model calculates the importance of features by evaluating the risk reduction amount at each node split. At each split, the model evaluates the contribution of the current feature to the split purity, calculates the contribution value of each feature, accumulates the contribution amounts at all splits, and finally obtains the weight value of each feature. These weight values reflect the influence degree of each feature in the selection of backtracking paths. That is, features such as logic gate type, controllability, observability, circuit level, and decision tendency will play different roles in the splitting process of the decision tree.

[0076] To verify the method described in the present invention, the method of the present invention is compared with traditional automatic test vector generation and the automatic test vector generation method based on an artificial neural network model, where the automatic test vector generation method based on an artificial neural network model is recorded in:

[0077] “S. Roy, S. K. Millican and V. D. Agrawal, "Machine Intelligence forEfficient Test Pattern Generation," 2020 IEEE International Test Conference(ITC), Washington, DC, USA, 2020, pp. 1-5, doi: 10.1109 / ITC44778.2020.9325250.”。

[0078] The experiment used benchmark circuits and referred to Figure 6 , presenting a statistical report including circuits C2670, C6288, S15850, and S38584, with key information such as fault classification, coverage rate, number of test patterns, and test running time. The test adopted the SAF (Stuck-At Fault) fault model, with a total of 86,824 faults. After simplification, the number of faults obtained was 61,840. Among these faults, the number of undetected faults was 3,272, the number of faults that were not testable by ATPG was 200, the number of faults aborted by ATPG was 5, the number of redundant and pending faults was 0, and the number of detected faults reached 83,347. The test coverage rate was 96.22%, and the ATPG efficiency was 96.23%. The test used 105 test vectors and the running time was 21.27 seconds.

[0079] Referring to Figure 7 , detailed test vector data is presented. The names of the input and output signals of the circuit, such as G0, G1, G2, etc., are listed at the top. Each row represents a test pattern, with pattern names such as pattern_1, pattern_2, etc. Each test pattern contains multiple binary vectors, which are separated by vertical bars and may correspond to the states of different signals in the circuit. For example, the test data in pattern_1 is "1111011011110010|1100110011100011|...". The total number of test vectors is 207, and each vector provides the states of multiple signals to verify the behavior of the circuit under different input conditions.

[0080] Referring to Table 1, for combinational circuits, the method of the present invention performs outstandingly compared with traditional methods on the C6288 circuit. The number of vectors is reduced by 75.2%, the number of backtracks is reduced by 74.1%, and the test coverage rate is increased by 1.34%. In the C2670 circuit, the number of vectors is reduced by 60.9%, the number of backtracks is decreased by 53.3%, and the test coverage rate is increased by 1.67%. For sequential circuits, the number of vectors of the method of the present invention is reduced by 24.8% on the S15850 circuit, the number of backtracks is reduced by 9.1%, and the test coverage rate is increased by 0.58%. On the S38584 circuit, the number of vectors is reduced by 3.8%, the number of backtracks is reduced by 24.1%, and the test coverage rate equivalent to that of the traditional method is maintained. Therefore, the method of the present invention can effectively reduce the number of test vectors, reduce the number of backtracks, and optimize the overall test efficiency while maintaining the test coverage rate.

[0081] Table 1 Statistical Table of Test Sample Data for Benchmark Circuits

[0082]

[0083] The automatic test vector generation system based on a decision tree according to the present invention includes:

[0084] A feature extraction unit for extracting node feature data of a circuit under test;

[0085] A backtrack confidence calculation unit for obtaining the backtrack confidence of each logic gate by using a trained decision tree model. The backtrack confidence is the predicted probability value of the decision tree model for the successful propagation of a fault by the logic gate in the backtrack path;

[0086] Among them, the training method of the decision tree model includes:

[0087] Parsing a circuit netlist file, extracting node feature data on the backtrack path during the backtrack process, adding a true label to the backtrack path, and establishing a circuit feature data set; establishing a decision tree model, inputting the circuit feature data set into the decision tree model for training and verification, and obtaining the predicted label of each node;

[0088] A test vector generation unit for selecting logic gates with high backtrack confidence as nodes and adding them to the backtrack path, and generating test vectors according to the backtrack path.

[0089] The electronic device according to the present invention includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the computer program is loaded into the processor, the automatic test vector generation method based on a decision tree is implemented.

[0090] The computer-readable storage medium of the present invention stores a computer program, and when the computer program is executed by a processor, the automatic test vector generation method based on a decision tree described above is implemented.

[0091] The computer-readable storage medium may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, flash memory, or any other medium that can be used to store program code in the form of instructions or data structures and can be accessed by a computer.

[0092] The processor is used to execute the computer program stored in the memory to implement each step in the method described in the above embodiments.

Claims

1. A method for automatically generating test vectors based on a decision tree, characterized in that: The steps include: Extract node feature data of the circuit to be tested, and use the trained decision tree model to calculate the backtracking confidence of each logic gate. The backtracking confidence is the predicted probability value of the decision tree model for the successful propagation of faults by the logic gate in the backtracking path. Select logic gates with high backtracking confidence as nodes and add them to the backtracking path, and generate test vectors according to the backtracking path; Among them, the training method of the decision tree model includes: Parse the circuit netlist file, extract node feature data on the backtracking path during the backtracking process, add real labels to the backtracking path, and establish a circuit feature data set; establish a decision tree model, input the circuit feature data set into the decision tree model for training and verification, and obtain a predicted label for each node; The method of inputting the circuit feature data set into a decision tree model for training and verification to obtain a predicted label for each node includes: Initialize parameters, recursively build tree structure, recursively divide leaf nodes and store node information; Traverse the samples and index leaf nodes, and calculate the prediction results of the category distribution based on the negative exponential loss function; Calculate the risk reduction for each node, which measures the tree's dependence on the input features; Among them, the expression of recursive partitioning of leaf nodes is as follows: ； D represents the sample set on the current node, S represents the sample set on the parent node, represents the purity or impurity measure of the set S, Express satisfaction A subset of samples, Express satisfaction A subset of samples, Representation Subset A measure of purity or impurity, Representation Subset A measure of purity or impurity: The expression for calculating the category distribution is as follows: ； Indicates The probability distribution of the class, Indicates The numerical value of the class label, represents the confidence or output value predicted by the model, represents the robustness parameter, Represents the set of all categories: The expression for calculating the risk reduction is as follows: ； Represents the risk value of the current node, represents the risk value of the left child node, represents the risk value of the right child node, Indicates the minimum threshold for risk reduction.

2. The automatic test vector generation method based on decision tree according to claim 1 is characterized in that: The node characteristic data includes logic gate type, controllability, observability, circuit level and decision tendency.

3. The automatic test vector generation method based on decision tree according to claim 2 is characterized in that: The logic gate type includes an AND gate, a NOT gate or an OR gate; the controllability is divided into high controllability or low controllability according to a controllability risk reduction threshold; the observability is divided into high observability or low observability according to an observability risk reduction threshold; the circuit level is divided into a high level or a low level according to a circuit level risk reduction threshold; the decision tendency is divided into a tendency to select 1 or a tendency to select 0 according to a decision tendency risk reduction threshold.

4. The automatic test vector generation method based on decision tree according to claim 1 is characterized in that: The selecting logic gates with high backtracking confidence as nodes to be added to the backtracking path includes: selecting the fault source node as the backtracking starting point, and selecting the logic gate with the highest backtracking confidence from the logic gates connected to the current node each time backtracking to add to the backtracking path.

5. An automatic test vector generation system based on a decision tree, characterized in that: include: A feature extraction unit, used to extract node feature data of the circuit to be tested; A backtracking confidence calculation unit is used to calculate the backtracking confidence of each logic gate using the trained decision tree model. The backtracking confidence is the predicted probability value of the decision tree model for the logic gate to successfully propagate a fault in the backtracking path. Among them, the training method of the decision tree model includes: Parse the circuit netlist file, extract node feature data on the backtracking path during the backtracking process, add real labels to the backtracking path, and establish a circuit feature data set; establish a decision tree model, input the circuit feature data set into the decision tree model for training and verification, and obtain a predicted label for each node; A test vector generation unit, used for selecting logic gates with high backtracking confidence as nodes to be added to the backtracking path, and generating a test vector according to the backtracking path; The method of inputting the circuit feature data set into a decision tree model for training and verification to obtain a predicted label for each node includes: Initialize parameters, recursively build tree structure, recursively divide leaf nodes and store node information; Traverse the samples and index leaf nodes, and calculate the prediction results of the category distribution based on the negative exponential loss function; Calculate the risk reduction for each node, which measures the tree's dependence on the input features; Among them, the expression of recursive partitioning of leaf nodes is as follows: ； D represents the sample set on the current node, S represents the sample set on the parent node, represents the purity or impurity measure of the set S, Express satisfaction A subset of samples, Express satisfaction A subset of samples, Representation Subset A measure of purity or impurity, Representation Subset A measure of purity or impurity: The expression for calculating the category distribution is as follows: ； Indicates The probability distribution of the class, Indicates The numerical value of the class label, Represents the confidence or output value predicted by the model, represents the robustness parameter, Represents the set of all categories: The expression for calculating the risk reduction is as follows: ； Represents the risk value of the current node, represents the risk value of the left child node, represents the risk value of the right child node, Indicates the minimum threshold for risk reduction.

6. The automatic test vector generation system based on decision tree according to claim 5, characterized in that: The node characteristic data includes logic gate type, controllability, observability, circuit level and decision tendency; The logic gate type includes an AND gate, a NOT gate or an OR gate; the controllability is divided into high controllability or low controllability according to a controllability risk reduction threshold; the observability is divided into high observability or low observability according to an observability risk reduction threshold; the circuit level is divided into a high level or a low level according to a circuit level risk reduction threshold; the decision tendency is divided into a tendency to select 1 or a tendency to select 0 according to a decision tendency risk reduction threshold.

7. The automatic test vector generation system based on decision tree according to claim 5, characterized in that: In the test vector generation unit, the selection of logic gates with high backtracking confidence as nodes to be added to the backtracking path includes: selecting the fault source node as the backtracking starting point, and selecting the logic gate with the highest backtracking confidence from the logic gates connected to the current node each time backtracking to add it to the backtracking path.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the computer program is loaded into a processor, the decision tree-based automatic test vector generation method according to any one of claims 1 to 4 is implemented.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the decision tree-based automatic test vector generation method according to any one of claims 1 to 4 is implemented.

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