RF chip test station calibration solution

Abstract

The present invention discloses a radio frequency chip test station calibration scheme, the calibration scheme is: 1) first take two chips to be tested, namely chip No. 1 and chip No. 2, and place the two chips in two test stations Site No. 1 and No. 2 in the test fixture Socket respectively; 2) when testing chip No. 1, first place chip No. 1 in station No. 1, then start the test fixture Socket, and the test fixture Socket will test chip No. 1 at least 10 times in a cycle. The present invention overcomes the problem that the traditional radio frequency chip calibration system in the prior art is prone to large data differences during the chip calibration process. The present invention has the advantages of accurate and reliable test results and simple and easy-to-operate test process.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and more specifically, to a radio frequency chip testing station calibration solution. Background Art

[0002] At present, a calibration waveform generator and a radio frequency chip calibration system, method, device, and medium are disclosed on the Chinese Patent Network, which relate to the field of radio frequency transceiver chip technology, with publication number CN118539994A, and are used to realize the calibration of zero intermediate frequency radio frequency transceiver chips. In view of the problem of slow I / Q mismatch calibration in traditional calibration schemes, a calibration waveform generator is provided, which can realize DCOS calibration and I / Q mismatch calibration of transceiver chips. By simultaneously generating multiple single tones of equal amplitude to realize multi-tone frequency sweeping, the calibration time required for I / Q mismatch mirror calibration can be greatly shortened, thereby speeding up the startup speed of the radio frequency transceiver chip, and facilitating the completion of background calibration without affecting the business, thereby improving the performance of broadband zero intermediate frequency transceivers.

[0003] Although the calibration waveform generator and RF chip calibration system, method, device, and medium in the above-mentioned patent have the advantages of short calibration time and startup speed, the RF chip testing method uses a single device for detection, and the main performance indicators of the RF chip are easily affected by factors such as test hardware, connection status, and spatial environment. If only a single device is used for calibration, the fluctuation of the RF chip test value will be difficult to control, and the yield of mass production testing will not be guaranteed. In addition, the above-mentioned calibration scheme is likely to cause large differences in site-to-site data, resulting in low quantity at individual sites. Summary of the invention

[0004] In order to overcome the problem that a traditional radio frequency chip calibration system in the prior art is prone to large data differences during chip calibration, the present invention provides a radio frequency chip test station calibration solution with a compensation function for the radio frequency chip calibration system.

[0005] A radio frequency chip test station calibration scheme of the present invention, the calibration scheme is: 1) First, take two chips to be tested, namely chip No. 1 and chip No. 2, and place the two chips in the two test stations Site No. 1 and Site No. 2 in the test fixture Socket respectively; 2) When testing chip No. 1, first place chip No. 1 in station No. 1, then start the test fixture Socket, which will test chip No. 1 at least 10 times in a cycle; 3) The test fixture will record the results of each test Sa1, Sa2, Sa3, Sa4, Sa5, Sa6, Sa7, Sa8, Sa9, Sa10, and get array A. The average value of array A is calculated as (Sa1+Sa2+Sa3+Sa4+Sa5+Sa6+Sa7+Sa8+Sa9+Sa10) / 10 to get S1; 4) Then take out chip No. 1 and place it in station No. 2, start the test fixture Socket again, and the test fixture Socket will cycle test chip No. 1 for at least 10 times; 5) The test fixture will record the results of each test Sb1, Sb2, Sb3, Sb4, Sb5, Sb6, Sb7, Sb8, Sb9, Sb10, and get array B. The average value of array B is calculated as (Sb1+Sb2+Sb3+Sb4+Sb5+Sb6+Sb7+Sb8+Sb9+Sb10) / 10 to get S2; 6) The value of (S1+S2) / 2 of chip No. 1 is taken as the final test value F1 of chip No. 1; 2) Then take out the chip No. 1 after the test, and put the chip No. 2 in the No. 1 station, and then start the test fixture Socket, which will test the chip No. 2 for at least 10 times; 3) The test fixture will record the results of each test Sc1, Sc2, Sc3, Sc4, Sc5, Sc6, Sc7, Sc8, Sc9, Sc10, and get array C. The average value of array C is calculated as (Sc1+Sc2+Sc3+Sc4+Sc5+Sc6+Sc7+Sc8+Sc9+Sc10) / 10 to get S11; 4) Then take out the No. 2 chip and place it in the No. 2 station, start the test fixture Socket again, and the test fixture Socket will cycle test the No. 1 chip again for at least 10 times; 5) The test fixture will record the results of each test Sd1, Sd2, Sd3, Sd4, Sd5, Sd6, Sd7, Sd8, Sd9, Sd10, and get array D. The average value of array D is calculated as (Sd1+Sd2+Sd3+Sd4+Sd5+Sd6+Sd7+Sd8+Sd9+Sd10) / 10 to get S22; 6) The value of (S11+S22) / 2 of chip No. 2 is taken as the final test value F2 of chip No. 2; 7) Calculate and compare F1 and F2 with the EVB test values ​​(E1, E2) of the corresponding chip; 8) Calculate the variances of array A, array B, array C and array D in sequence to obtain variance A, variance B, variance C and variance D respectively; 9) Substitute the variance A and array A into the formulas CP and CPK respectively. If CP>3 and CPK>1.33, and the difference between F1 and E1 is less than or equal to 5%, that is, |F1-E1| / E1≤5%, then the No. 1 station is normal, and the compensation value C1 of the No. 1 station can be obtained, C1=E1-F1; 9) If CP≤3, or CPK≤1.33, or the difference between F1 and E1>5%, i.e. |F1-E1| / E1>5%, is obtained after substituting array A, it means that there is a problem with the test hardware at station 1 and hardware maintenance is required; 10) Similarly, substitute variance B and array B into formulas CP and CPK respectively. If CP>3 and CPK>1.33, and the difference between F2 and E2 is less than or equal to 5%, that is, |F2-E2| / E2≤5%, then it means that station 1 is normal, and the compensation value C2 of station 1 can be obtained, C2=E2-F2; 11) If CP≤3, or CPK≤1.33, or the difference between F2 and E2>5%, that is, |F2-E2| / E2>5%, it means that there is a problem with the test hardware at station 1 and hardware maintenance is required; 12) Add the obtained C1 to the test program of station No. 1, add the obtained C12 to the test program of station No. 1, repeat the above process to obtain F1” and F2”. If |F1”-E1| / E1<2%, it means that the calibration of station No. 1 of the test fixture Socket is completed; if |F1”-E1| / E1≥2%, it is necessary to detect and manually adjust the test program of station No. 1, and test again after the adjustment until |F1”-E1| / E1<2%; if |F2”-E2| / E2<2%, it means that the calibration of station No. 2 of the test fixture Socket is completed; if |F2”-E2| / E2≥2%, it is necessary to detect and manually adjust the test program of station No. 2, and test again after the adjustment until |F2”-E2| / E2<2%; 13) After that, the chip No. 1 and chip No. 2 that are tested normally in the test fixture Socket are placed in the sorting machine No. 1 and sorting machine No. 2 for testing respectively; 14) When testing chip No. 1, first place chip No. 1 in the stress test mode of sorter No. 1, then start sorter No. 1, which will cycle test chip No. 1 at least 10 times; 15) Sorting machine No. 1 will record the results of each test Se1, Se2, Se3, Se4, Se5, Se6, Se7, Se8, Se9, Se10, and get array E. The average value of array E is calculated as (Se1+Se2+Se3+Se4+Se5+Se6+Se7+Se8+Se9+Se10) / 10 to get S1'; 16) Then take out chip No. 1 and put it into the stress test mode of sorter No. 2, start sorter No. 2, and sorter No. 2 will cycle test chip No. 1 at least 10 times; 17) Sorting machine No. 2 will record the results of each test Sf1, Sf2, Sf3, Sf4, Sf5, Sf6, Sf7, Sf8, Sf9, Sf10 to get array F. The average value of array F is calculated as (Sf1+Sf2+Sf3+Sf4+Sf5+Sf6+Sf7+Sf8+Sf9+Sf10) / 10 to get S2'; 18) The value of (S1'+ S2') / 2 of chip No. 1 is taken as the final test value F1' of chip No. 1; 19) After that, take out the chip No. 1 after the test, and put the chip No. 2 into the stress test mode of the sorter No. 1. Then start the sorter No. 1, and the sorter No. 1 will cycle test the chip No. 2 for at least 10 times; 20) Sorting machine No. 1 will record the results of each test Sg1, Sg2, Sg3, Sg4, Sg5, Sg6, Sg7, Sg8, Sg9, Sg10, and get array G. The average value of array G is calculated as (Sg1+Sg2+Sg3+Sg4+Sg5+Sg6+Sg7+Sg8+Sg9+Sg10) / 10 to get S11'; 21) Then take out chip No. 2 and put it into the stress test mode of sorter No. 2, start sorter No. 2, and sorter No. 2 will cycle test chip No. 2 at least 10 times; 22) The test fixture will record the results of each test Sh1, Sh2, Sh3, Sh4, Sh5, Sh6, Sh7, Sh8, Sh9, Sh10, and get array H. The average value of array H is calculated as (Sh1+Sh2+Sh3+Sh4+Sh5+Sh6+Sh7+Sh8+Sh9+Sh10) / 10 to get S22'; 23) The value of (S11'+S22') / 2 of chip No. 2 is taken as the final test value F2' of chip No. 2; 24) Calculate the variances of array E, array F, array G and array H in turn to obtain variance E, variance F, variance G and variance H respectively, and compare F1' and F2' with the EVB test values ​​(E1, E2) of the corresponding chip; Substitute the variance E and array E into the formulas CP and CPK respectively. If CP>3 and CPK>1.33, and the difference between F1' and E1 is less than or equal to 5%, that is, |F1'-E1| / E1≤5%, then the No. 1 sorter is normal, and the compensation value C1' of the No. 1 sorter can be obtained, C1'=E1-F1'; 26) If the difference between F1' and E1 is greater than 5%, it means that there is a problem with the test hardware on the No. 1 sorter, and hardware maintenance is required, and the pressure generated by the No. 1 sorter should be adjusted; 27) Similarly, substitute the variance F and array F into the formulas CP and CPK respectively. If CP>3 and CPK>1.33, and the difference between F2' and E2 is less than or equal to 5%, that is, |F2'-E2| / E2≤5%, then the No. 2 sorter is normal, and the compensation value C2' of the No. 2 sorter can be obtained, C2'=E2-F2'; 28) If the difference between F2' and E2 is greater than 5%, it means that there is a problem with the test hardware on the No. 2 sorter, and the hardware needs to be repaired and the pressure generated by the No. 2 sorter needs to be adjusted; 29) Add the obtained D1 obtained by C1'+C1 into the sorter No. 1, and add the obtained D2 obtained by C2'+C2 into the sorter No. 2. Place the chip No. 1 and chip No. 2 into the sorter No. 1 and sorter No. 2 respectively. Repeat the above process to obtain F1"" and F2"". If |F1""-E1| / E1<2%, it means that the calibration of the sorter No. 1 is completed; if |F1""-E1| / E1≥2%, it is necessary to check the test program of the sorter No. 1 and adjust it. After the adjustment is completed, test again until |F1""-E1| / E1<2%; if |F2""-E2| / E2<2%, it means that the calibration of the sorter No. 2 is completed; if |F2""-E2| / E2≥2%, it is necessary to check the test program of the sorter No. 2 and adjust it. After the adjustment is completed, test again until |F2""-E2| / E2<2%.

[0006] The E1 is the standard value of chip No. 1 when it leaves the factory, and E2 is the standard value of chip No. 2 when it leaves the factory.

[0007] The formula of CP is Cp=(USL-LSL) / 6sigma, where sigma is the variance value, USL is the maximum value in the array, and LSL is the minimum value in the array).

[0008] The formula of CPK is CPK=min[(USL-μ), (μ-LSL)] / 3sigma, where USL is the maximum value in the array, LSL is the minimum value in the array, and μ is the mean value of the array.

[0009] The No. 1 chip and the No. 2 chip used in the present invention are both qualified chips verified by the manufacturer.

[0010] The test fixture Socket performs manual detection on qualified chips. After the test fixture Socket completes the chip testing, the chip is sent to a sorting machine for automatic detection. Two detection environments for the chip are set up. The present invention compares the detection data with the standard test value when the chip leaves the factory. Since there is a certain difference between the test environment of the chip manufacturer and the test environment of the detection agency, the present invention performs manual and automatic detection, and calibrates the test station by inputting compensation values ​​in the test fixture Socket and the sorting machine, so that the test result of the chip at the test station is as close as possible to the standard value of the chip, thereby preventing bad chips from entering the market through the detection of the detection agency due to differences in the test environment.

[0011] The present invention has the following beneficial effects: the test result is accurate and reliable, and the test process is simple and easy to operate. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Attached Figure 1 It is a flowchart of the calibration scheme of the present invention. DETAILED DESCRIPTION

[0013] The technical solution of the present invention is further specifically described below through embodiments and in conjunction with the accompanying drawings.

[0014] Embodiment: According to the attached Figure 1 The present invention is further described in a calibration scheme of a radio frequency chip test station in this example, wherein the calibration scheme is: 1) First, take two chips to be tested, namely chip No. 1 and chip No. 2, and place the two chips in the two test stations Site No. 1 and Site No. 2 in the test fixture Socket respectively; 2) When testing chip No. 1, first place chip No. 1 in station No. 1, then start the test fixture Socket, which will test chip No. 1 at least 10 times in a cycle; 3) The test fixture will record the results of each test Sa1, Sa2, Sa3, Sa4, Sa5, Sa6, Sa7, Sa8, Sa9, Sa10, and get array A. The average value of array A is calculated as (Sa1+Sa2+Sa3+Sa4+Sa5+Sa6+Sa7+Sa8+Sa9+Sa10) / 10 to get S1; 4) Then take out chip No. 1 and place it in station No. 2, start the test fixture Socket again, and the test fixture Socket will cycle test chip No. 1 for at least 10 times; 5) The test fixture will record the results of each test Sb1, Sb2, Sb3, Sb4, Sb5, Sb6, Sb7, Sb8, Sb9, Sb10, and get array B. The average value of array B is calculated as (Sb1+Sb2+Sb3+Sb4+Sb5+Sb6+Sb7+Sb8+Sb9+Sb10) / 10 to get S2; 6) The value of (S1+S2) / 2 of chip No. 1 is taken as the final test value F1 of chip No. 1; 2) Then take out the chip No. 1 after the test, and put the chip No. 2 in the No. 1 station, and then start the test fixture Socket, which will test the chip No. 2 for at least 10 times; 3) The test fixture will record the results of each test Sc1, Sc2, Sc3, Sc4, Sc5, Sc6, Sc7, Sc8, Sc9, Sc10, and get array C. The average value of array C is calculated as (Sc1+Sc2+Sc3+Sc4+Sc5+Sc6+Sc7+Sc8+Sc9+Sc10) / 10 to get S11; 4) Then take out the No. 2 chip and place it in the No. 2 station, start the test fixture Socket again, and the test fixture Socket will cycle test the No. 1 chip again for at least 10 times; 5) The test fixture will record the results of each test Sd1, Sd2, Sd3, Sd4, Sd5, Sd6, Sd7, Sd8, Sd9, Sd10, and get array D. The average value of array D is calculated as (Sd1+Sd2+Sd3+Sd4+Sd5+Sd6+Sd7+Sd8+Sd9+Sd10) / 10 to get S22; 6) The value of (S11+S22) / 2 of chip No. 2 is taken as the final test value F2 of chip No. 2; 7) Calculate and compare F1 and F2 with the EVB test values ​​(E1, E2) of the corresponding chip; 8) Calculate the variances of array A, array B, array C and array D in sequence to obtain variance A, variance B, variance C and variance D respectively; 9) Substitute the variance A and array A into the formulas CP and CPK respectively. If CP>3 and CPK>1.33, and the difference between F1 and E1 is less than or equal to 5%, that is, |F1-E1| / E1≤5%, then the No. 1 station is normal, and the compensation value C1 of the No. 1 station can be obtained, C1=E1-F1; 9) If CP≤3, or CPK≤1.33, or the difference between F1 and E1>5%, i.e. |F1-E1| / E1>5%, is obtained after substituting array A, it means that there is a problem with the test hardware at station 1 and hardware maintenance is required; 10) Similarly, substitute variance B and array B into formulas CP and CPK respectively. If CP>3 and CPK>1.33, and the difference between F2 and E2 is less than or equal to 5%, that is, |F2-E2| / E2≤5%, then it means that station 1 is normal, and the compensation value C2 of station 1 can be obtained, C2=E2-F2; 11) If CP≤3, or CPK≤1.33, or the difference between F2 and E2>5%, that is, |F2-E2| / E2>5%, it means that there is a problem with the test hardware at station 1 and hardware maintenance is required; 12) Add the obtained C1 to the test program of station No. 1, add the obtained C12 to the test program of station No. 1, repeat the above process to obtain F1” and F2”. If |F1”-E1| / E1<2%, it means that the calibration of station No. 1 of the test fixture Socket is completed; if |F1”-E1| / E1≥2%, it is necessary to detect and manually adjust the test program of station No. 1, and test again after the adjustment until |F1”-E1| / E1<2%; if |F2”-E2| / E2<2%, it means that the calibration of station No. 2 of the test fixture Socket is completed; if |F2”-E2| / E2≥2%, it is necessary to detect and manually adjust the test program of station No. 2, and test again after the adjustment until |F2”-E2| / E2<2%; 13) Then, the chip No. 1 and chip No. 2 that are tested normally in the test fixture Socket are placed in the sorting machine No. 1 and sorting machine No. 2 for testing respectively; 14) When testing chip No. 1, first place chip No. 1 in the stress test mode of sorter No. 1, then start sorter No. 1, which will cycle test chip No. 1 at least 10 times; 15) Sorting machine No. 1 will record the results of each test Se1, Se2, Se3, Se4, Se5, Se6, Se7, Se8, Se9, Se10, and get array E. The average value of array E is calculated as (Se1+Se2+Se3+Se4+Se5+Se6+Se7+Se8+Se9+Se10) / 10 to get S1'; 16) Then take out chip No. 1 and put it into the stress test mode of sorter No. 2, start sorter No. 2, and sorter No. 2 will cycle test chip No. 1 at least 10 times; 17) Sorting machine No. 2 will record the results of each test Sf1, Sf2, Sf3, Sf4, Sf5, Sf6, Sf7, Sf8, Sf9, Sf10 to get array F. The average value of array F is calculated as (Sf1+Sf2+Sf3+Sf4+Sf5+Sf6+Sf7+Sf8+Sf9+Sf10) / 10 to get S2'; 18) The value of (S1'+ S2') / 2 of chip No. 1 is taken as the final test value F1' of chip No. 1; 19) After that, take out the chip No. 1 after the test, and put the chip No. 2 into the stress test mode of the sorter No. 1. Then start the sorter No. 1, and the sorter No. 1 will cycle test the chip No. 2 for at least 10 times; 20) Sorting machine No. 1 will record the results of each test Sg1, Sg2, Sg3, Sg4, Sg5, Sg6, Sg7, Sg8, Sg9, Sg10, and get array G. The average value of array G is calculated as (Sg1+Sg2+Sg3+Sg4+Sg5+Sg6+Sg7+Sg8+Sg9+Sg10) / 10 to get S11'; 21) Then take out chip No. 2 and put it into the stress test mode of sorter No. 2, start sorter No. 2, and sorter No. 2 will cycle test chip No. 2 at least 10 times; 22) The test fixture will record the results of each test Sh1, Sh2, Sh3, Sh4, Sh5, Sh6, Sh7, Sh8, Sh9, Sh10, and get array H. The average value of array H is calculated as (Sh1+Sh2+Sh3+Sh4+Sh5+Sh6+Sh7+Sh8+Sh9+Sh10) / 10 to get S22'; 23) The value of (S11'+S22') / 2 of chip No. 2 is taken as the final test value F2' of chip No. 2; 24) Calculate the variances of array E, array F, array G and array H in turn to obtain variance E, variance F, variance G and variance H respectively, and compare F1' and F2' with the EVB test values ​​(E1, E2) of the corresponding chip; Substitute the variance E and array E into the formulas CP and CPK respectively. If CP>3 and CPK>1.33, and the difference between F1' and E1 is less than or equal to 5%, that is, |F1'-E1| / E1≤5%, then the No. 1 sorter is normal, and the compensation value C1' of the No. 1 sorter can be obtained, C1'=E1-F1'; 26) If the difference between F1' and E1 is greater than 5%, it means that there is a problem with the test hardware on the No. 1 sorter, and hardware maintenance is required, and the pressure generated by the No. 1 sorter should be adjusted; 27) Similarly, substitute the variance F and array F into the formulas CP and CPK respectively. If CP>3 and CPK>1.33, and the difference between F2' and E2 is less than or equal to 5%, that is, |F2'-E2| / E2≤5%, then the No. 2 sorter is normal, and the compensation value C2' of the No. 2 sorter can be obtained, C2'=E2-F2'; 28) If the difference between F2' and E2 is greater than 5%, it means that there is a problem with the test hardware on the No. 2 sorter, and the hardware needs to be repaired and the pressure generated by the No. 2 sorter needs to be adjusted; 29) Add the obtained D1 obtained by C1'+C1 into the sorter No. 1, and add the obtained D2 obtained by C2'+C2 into the sorter No. 2. Place the chip No. 1 and chip No. 2 into the sorter No. 1 and sorter No. 2 respectively. Repeat the above process to obtain F1"" and F2"". If |F1""-E1| / E1<2%, it means that the calibration of the sorter No. 1 is completed; if |F1""-E1| / E1≥2%, it is necessary to check the test program of the sorter No. 1 and adjust it. After the adjustment is completed, test again until |F1""-E1| / E1<2%; if |F2""-E2| / E2<2%, it means that the calibration of the sorter No. 2 is completed; if |F2""-E2| / E2≥2%, it is necessary to check the test program of the sorter No. 2 and adjust it. After the adjustment is completed, test again until |F2""-E2| / E2<2%.

[0015] The E1 is the standard value of chip No. 1 when it leaves the factory, and E2 is the standard value of chip No. 2 when it leaves the factory.

[0016] The formula of CP is Cp=(USL-LSL) / 6sigma, where sigma is the variance value, USL is the maximum value in the array, and LSL is the minimum value in the array).

[0017] The formula of CPK is CPK=min[(USL-μ), (μ-LSL)] / 3sigma, where USL is the maximum value in the array, LSL is the minimum value in the array, and μ is the mean value of the array.

[0018] The above description is only a specific embodiment of the present invention, but the structural features of the present invention are not limited thereto. Any changes or modifications made by any technician in the field of the present invention are included in the patent scope of the present invention.

Claims

1. A radio frequency chip test station calibration scheme, characterized in that: The calibration scheme described is: 1) First, take two chips to be tested, namely chip No. 1 and chip No. 2, and place the two chips in the two test stations Site No. 1 and Site No. 2 in the test fixture Socket respectively; 2) When testing chip No. 1, first place chip No. 1 in station No. 1, then start the test fixture Socket, which will test chip No. 1 at least 10 times in a cycle; 3) The test fixture will record the results of each test Sa1, Sa2, Sa3, Sa4, Sa5, Sa6, Sa7, Sa8, Sa9, Sa10, and get array A. The average value of array A is calculated as (Sa1+Sa2+Sa3+Sa4+Sa5+Sa6+Sa7+Sa8+Sa9+Sa10) / 10 to get S1; 4) Then take out chip No. 1 and place it in station No. 2, start the test fixture Socket again, and the test fixture Socket will cycle test chip No. 1 for at least 10 times; 5) The test fixture will record the results of each test Sb1, Sb2, Sb3, Sb4, Sb5, Sb6, Sb7, Sb8, Sb9, Sb10, and get array B. The average value of array B is calculated as (Sb1+Sb2+Sb3+Sb4+Sb5+Sb6+Sb7+Sb8+Sb9+Sb10) / 10 to get S2; 6) The value of (S1+S2) / 2 of chip No. 1 is taken as the final test value F1 of chip No. 1; 2) Then take out the chip No. 1 after the test, and put the chip No. 2 in the No. 1 station, and then start the test fixture Socket, which will test the chip No. 2 for at least 10 times; 3) The test fixture will record the results of each test Sc1, Sc2, Sc3, Sc4, Sc5, Sc6, Sc7, Sc8, Sc9, Sc10, and get array C. The average value of array C is calculated as (Sc1+Sc2+Sc3+Sc4+Sc5+Sc6+Sc7+Sc8+Sc9+Sc10) / 10 to get S11; 4) Then take out the No. 2 chip and place it in the No. 2 station, start the test fixture Socket again, and the test fixture Socket will cycle test the No. 1 chip again for at least 10 times; 5) The test fixture will record the results of each test Sd1, Sd2, Sd3, Sd4, Sd5, Sd6, Sd7, Sd8, Sd9, Sd10, and get array D. The average value of array D is calculated as (Sd1+Sd2+Sd3+Sd4+Sd5+Sd6+Sd7+Sd8+Sd9+Sd10) / 10 to get S22; 6) The value of (S11+S22) / 2 of chip No. 2 is taken as the final test value F2 of chip No. 2; 7) Calculate and compare F1 and F2 with the EVB test values ​​(E1, E2) of the corresponding chip; 8) Calculate the variances of array A, array B, array C and array D in sequence to obtain variance A, variance B, variance C and variance D respectively; 9) Substitute the variance A and array A into the formulas CP and CPK respectively. If CP>3 and CPK>1.33, and the difference between F1 and E1 is less than or equal to 5%, that is, |F1-E1| / E1≤5%, then the No. 1 station is normal, and the compensation value C1 of the No. 1 station can be obtained, C1=E1-F1; 9) If CP≤3, or CPK≤1.33, or the difference between F1 and E1>5%, i.e. |F1-E1| / E1>5%, is obtained after substituting array A, it means that there is a problem with the test hardware at station 1 and hardware maintenance is required; 10) Similarly, substitute variance B and array B into formulas CP and CPK respectively. If CP>3 and CPK>1.33, and the difference between F2 and E2 is less than or equal to 5%, that is, |F2-E2| / E2≤5%, then it means that station 1 is normal, and the compensation value C2 of station 1 can be obtained, C2=E2-F2; 11) If CP≤3, or CPK≤1.33, or the difference between F2 and E2>5%, that is, |F2-E2| / E2>5%, it means that there is a problem with the test hardware at station 1 and hardware maintenance is required; 12) Add the obtained C1 to the test program of station No. 1, add the obtained C12 to the test program of station No. 1, repeat the above process to obtain F1” and F2”. If |F1”-E1| / E1<2%, it means that the calibration of station No. 1 of the test fixture Socket is completed; if |F1”-E1| / E1≥2%, it is necessary to detect and manually adjust the test program of station No. 1, and test again after the adjustment until |F1”-E1| / E1<2%; if |F2”-E2| / E2<2%, it means that the calibration of station No. 2 of the test fixture Socket is completed; if |F2”-E2| / E2≥2%, it is necessary to detect and manually adjust the test program of station No. 2, and test again after the adjustment until |F2”-E2| / E2<2%; 13) Then, the chip No. 1 and chip No. 2 that are tested normally in the test fixture Socket are placed in the sorting machine No. 1 and sorting machine No. 2 for testing respectively; 14) When testing chip No. 1, first place chip No. 1 in the stress test mode of sorter No. 1, then start sorter No. 1, which will cycle test chip No. 1 at least 10 times; 15) Sorting machine No. 1 will record the results of each test Se1, Se2, Se3, Se4, Se5, Se6, Se7, Se8, Se9, Se10, and get array E. The average value of array E is calculated as (Se1+Se2+Se3+Se4+Se5+Se6+Se7+Se8+Se9+Se10) / 10 to get S1'; 16) Then take out chip No. 1 and put it into the stress test mode of sorter No. 2, start sorter No. 2, and sorter No. 2 will cycle test chip No. 1 at least 10 times; 17) Sorting machine No. 2 will record the results of each test Sf1, Sf2, Sf3, Sf4, Sf5, Sf6, Sf7, Sf8, Sf9, Sf10 to get array F. The average value of array F is calculated as (Sf1+Sf2+Sf3+Sf4+Sf5+Sf6+Sf7+Sf8+Sf9+Sf10) / 10 to get S2'; 18) The value of (S1'+ S2') / 2 of chip No. 1 is taken as the final test value F1' of chip No. 1; 19) After that, take out the chip No. 1 after the test, and put the chip No. 2 into the stress test mode of the sorter No.

1. Then start the sorter No. 1, and the sorter No. 1 will cycle test the chip No. 2 for at least 10 times; 20) Sorting machine No. 1 will record the results of each test Sg1, Sg2, Sg3, Sg4, Sg5, Sg6, Sg7, Sg8, Sg9, Sg10, and get array G. The average value of array G is calculated as (Sg1+Sg2+Sg3+Sg4+Sg5+Sg6+Sg7+Sg8+Sg9+Sg10) / 10 to get S11'; 21) Then take out chip No. 2 and put it into the stress test mode of sorter No. 2, start sorter No. 2, and sorter No. 2 will cycle test chip No. 2 at least 10 times; 22) The test fixture will record the results of each test Sh1, Sh2, Sh3, Sh4, Sh5, Sh6, Sh7, Sh8, Sh9, Sh10, and get array H. The average value of array H is calculated as (Sh1+Sh2+Sh3+Sh4+Sh5+Sh6+Sh7+Sh8+Sh9+Sh10) / 10 to get S22'; 23) The value of (S11'+S22') / 2 of chip No. 2 is taken as the final test value F2' of chip No. 2; 24) Calculate the variances of array E, array F, array G and array H in turn to obtain variance E, variance F, variance G and variance H respectively, and compare F1' and F2' with the EVB test values ​​(E1, E2) of the corresponding chip; Substitute the variance E and array E into the formulas CP and CPK respectively. If CP>3 and CPK>1.33, and the difference between F1' and E1 is less than or equal to 5%, that is, |F1'-E1| / E1≤5%, then the No. 1 sorter is normal, and the compensation value C1' of the No. 1 sorter can be obtained, C1'=E1-F1'; 26) If the difference between F1' and E1 is greater than 5%, it means that there is a problem with the test hardware on the No. 1 sorter, and hardware maintenance is required, and the pressure generated by the No. 1 sorter should be adjusted; 27) Similarly, substitute the variance F and array F into the formulas CP and CPK respectively. If CP>3 and CPK>1.33, and the difference between F2' and E2 is less than or equal to 5%, that is, |F2'-E2| / E2≤5%, then the No. 2 sorter is normal, and the compensation value C2' of the No. 2 sorter can be obtained, C2'=E2-F2'; 28) If the difference between F2' and E2 is greater than 5%, it means that there is a problem with the test hardware on the No. 2 sorter, and the hardware needs to be repaired and the pressure generated by the No. 2 sorter needs to be adjusted; 29) Add the obtained D1 obtained by C1'+C1 into the sorter No. 1, and add the obtained D2 obtained by C2'+C2 into the sorter No.

2. Place the chip No. 1 and chip No. 2 into the sorter No. 1 and sorter No. 2 respectively. Repeat the above process to obtain F1"" and F2"". If |F1""-E1| / E1<2%, it means that the calibration of the sorter No. 1 is completed; if |F1""-E1| / E1≥2%, it is necessary to check the test program of the sorter No. 1 and adjust it. After the adjustment is completed, test again until |F1""-E1| / E1<2%; if |F2""-E2| / E2<2%, it means that the calibration of the sorter No. 2 is completed; if |F2""-E2| / E2≥2%, it is necessary to check the test program of the sorter No. 2 and adjust it. After the adjustment is completed, test again until |F2""-E2| / E2<2%.

2. The radio frequency chip test station calibration scheme according to claim 1, characterized in that: The E1 is the standard value of chip No. 1 when it leaves the factory, and E2 is the standard value of chip No. 2 when it leaves the factory.

3. The radio frequency chip test station calibration scheme according to claim 1, characterized in that: The formula of CP is Cp=(USL-LSL) / 6sigma, where sigma is the variance value, USL is the maximum value in the array, and LSL is the minimum value in the array).

4. The radio frequency chip test station calibration scheme according to claim 1, characterized in that: The formula of CPK is CPK=min[(USL-μ), (μ-LSL)] / 3sigma, where USL is the maximum value in the array, LSL is the minimum value in the array, and μ is the mean value of the array.

Images