Lithographic Imaging Simulation Method, Apparatus, Storage Medium, and Electronic Device

Abstract

The present application discloses a lithographic imaging simulation method, apparatus, storage medium, and electronic device. Among them, the lithographic imaging simulation method includes obtaining a first simulation area of a wafer; decomposing the simulation area into a plurality of first sub-areas based on the surface topography characteristics of the wafer; extracting first electric field information of the first sub-areas from an electric field look-up table; performing electric field superposition processing and redundancy removal processing on the plurality of first electric field information to obtain second electric field information of the first simulation area; and calculating an optical imaging result of a target mask pattern based on optical system parameters and the second electric field information. This solution can improve the efficiency of lithographic imaging simulation.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of lithography technology, and particularly to a lithography imaging simulation method, device, storage medium and electronic device. Background Art

[0002] In modern semiconductor manufacturing, the wafer surface topography has an important impact on the imaging effect of the lithography process. As the process technology nodes continue to shrink, the optical effects caused by the complex structure on the wafer surface increase significantly, such as print bias and hotspot. These effects will cause a deviation between the mask design size and the actual pattern size, reduce the tolerance range of the lithography process window, and cause local imaging quality problems, thus affecting the yield of wafer manufacturing.

[0003] Existing electromagnetic field simulation technologies, such as the Finite Difference Time Domain Method (FDTD) and the Rigorous Coupled Wave Analysis (RCWA), have a huge computational amount when dealing with complex wafer topography, and it is difficult to quickly and accurately evaluate these effects, seriously affecting the efficiency of lithography imaging simulation. Summary of the Invention

[0004] Embodiments of the present application provide a lithography imaging simulation method, device, storage medium and electronic device, which can improve the efficiency of lithography imaging simulation.

[0005] In a first aspect, an embodiment of the present application provides a lithography imaging simulation method, including:

[0006] Obtain a first simulation area of the wafer;

[0007] Based on the surface topography characteristics of the wafer, decompose the simulation area into several first sub-areas;

[0008] Extract first electric field information of the first sub-areas from an electric field look-up table;

[0009] Perform electric field superposition processing and redundancy removal processing on several pieces of the first electric field information to obtain second electric field information of the first simulation area;

[0010] Based on the optical system parameters and the second electric field information, calculate the optical imaging result of the target mask pattern.

[0011] In the lithography imaging simulation method provided by the embodiment of the present application, before obtaining the first simulation area of the wafer, it further includes:

[0012] Construct an electric field look-up table.

[0013] In the lithography imaging simulation method provided by the embodiments of the present application, the construction of the electric field look-up table includes:

[0014] Obtain a plurality of second simulation regions;

[0015] Based on the surface topography characteristics of the wafer, decompose the corresponding second simulation regions into a plurality of second sub-regions;

[0016] Construct an electric field look-up table based on the third electric field information of each of the second sub-regions.

[0017] In the lithography imaging simulation method provided by the embodiments of the present application, the construction of the electric field look-up table based on the third electric field information of each of the second sub-regions includes:

[0018] Decompose each of the second sub-regions into a plurality of first boundary line segments;

[0019] Use a preset electromagnetic field algorithm to calculate the fourth electric field information of each of the first boundary line segments, and generate an electric field look-up table based on the fourth electric field information.

[0020] In the lithography imaging simulation method provided by the embodiments of the present application, the extraction of the first electric field information of the first sub-region from the electric field look-up table includes:

[0021] Divide the first sub-region into a plurality of second boundary line segments;

[0022] Extract the corresponding fifth electric field information from the electric field look-up table based on the second boundary line segments.

[0023] In the lithography imaging simulation method provided by the embodiments of the present application, the electric field superposition processing and redundancy removal processing of a plurality of the first electric field information to obtain the second electric field information of the first simulation region includes:

[0024] Perform electric field superposition processing and redundancy removal processing on the plurality of fifth electric field information of each of the first sub-regions to obtain the first electric field information of each of the first sub-regions;

[0025] Perform electric field superposition processing and redundancy removal processing on the plurality of the first electric field information to obtain the second electric field information of the first simulation region.

[0026] In the lithography imaging simulation method provided by the embodiments of the present application, the electric field superposition processing and redundancy removal processing of a plurality of the first electric field information to obtain the second electric field information of the first simulation region includes:

[0027] Perform electric field superposition processing and redundancy removal processing on a plurality of the fifth electric field information to obtain the second electric field information of the first simulation area.

[0028] In a second aspect, an embodiment of the present application provides a lithography imaging simulation device, including:

[0029] A determination unit, configured to obtain a first simulation area of a wafer;

[0030] A decomposition unit, configured to decompose the simulation area into a plurality of first sub-areas based on the surface topography characteristics of the wafer;

[0031] A search unit, configured to extract the first electric field information of the first sub-area from an electric field look-up table;

[0032] A superposition unit, configured to perform electric field superposition processing and redundancy removal processing on a plurality of the first electric field information to obtain the second electric field information of the first simulation area;

[0033] A calculation unit, configured to calculate an optical imaging result of a target mask pattern based on optical system parameters and the second electric field information.

[0034] In a third aspect, the present application provides a storage medium, which stores a plurality of instructions, and the instructions are suitable for being loaded by a processor to execute the lithography imaging simulation method described in any one of the above.

[0035] In a fourth aspect, the present application provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the lithography imaging simulation method described in any one of the above is implemented.

[0036] In summary, the lithography imaging simulation method provided by the embodiment of the present application includes obtaining a first simulation area of a wafer; decomposing the simulation area into a plurality of first sub-areas based on the surface topography characteristics of the wafer; extracting the first electric field information of the first sub-area from an electric field look-up table; performing electric field superposition processing and redundancy removal processing on a plurality of the first electric field information to obtain the second electric field information of the first simulation area; calculating an optical imaging result of a target mask pattern based on optical system parameters and the second electric field information. This solution decomposes the simulation area into a plurality of sub-areas and uses a look-up table to search for sub-area electric field information, thereby reducing the real-time calculation complexity and improving the efficiency of lithography imaging simulation. Description of the Drawings

[0037] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0038] Figure 1 It is a schematic diagram of the application scenario of the lithography imaging simulation method provided by the embodiment of the present application.

[0039] Figure 2 It is a schematic flowchart of the lithography imaging simulation method provided by the embodiment of the present application.

[0040] Figure 3 It is a schematic diagram of the electric field superposition processing and redundancy removal processing of the electric field information provided by the embodiment of the present application.

[0041] Figure 4 It is another schematic diagram of the electric field superposition processing and redundancy removal processing of the electric field information provided by the embodiment of the present application.

[0042] Figure 5 It is a schematic diagram of the structure of the lithography imaging simulation device provided by the embodiment of the present application.

[0043] Figure 6 It is a schematic diagram of the structure of the electronic device provided by the embodiment of the present application. Detailed Embodiments

[0044] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are only examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0045] It should be noted that in this document, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of additional identical elements in the process, method, article or device comprising that element. In addition, components, features, and elements with the same name in different embodiments of this application may have the same meaning or different meanings, and their specific meanings need to be determined based on their explanations in the specific embodiments or further in combination with the context of the specific embodiments.

[0046] It should be understood that the specific embodiments described herein are merely used to explain this application and are not used to limit this application.

[0047] In subsequent descriptions, the use of suffixes such as "module", "component" or "unit" to represent elements is only for the convenience of explaining this application, and they have no specific meaning in themselves. Therefore, "module", "component" or "unit" can be used interchangeably.

[0048] In the description of this application, it should be noted that the orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. In addition, terms such as "first", "second", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0049] Existing electromagnetic field simulation technologies, such as the finite-difference time-domain method of electromagnetic waves and rigorous coupled-wave analysis, have extremely large computational amounts when dealing with complex wafer topographies, making it difficult to quickly and accurately evaluate these effects, which seriously affects the efficiency of lithography imaging simulation.

[0050] Based on this, the embodiments of this application provide a lithography imaging simulation method, device, storage medium, and electronic device. Specifically, the lithography imaging simulation device can be integrated into an electronic device, which can be a server or a terminal device, etc.; among them, the terminal can include a mobile phone, a wearable intelligent device, a tablet computer, a laptop computer, and a personal computer (PC), etc.; the server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.

[0051] For example, as Figure 1 shown, after the electronic device obtains the first simulation area of the wafer, based on the surface topography characteristics of the wafer, the simulation area is decomposed into several first sub-areas; then the first electric field information of the first sub-areas is extracted from the electric field look-up table; then the electric field superposition processing and redundancy removal processing are performed on the several first electric field information to obtain the second electric field information of the first simulation area; finally, based on the optical system parameters and the second electric field information, the optical imaging result of the target mask pattern is calculated.

[0052] The following will separately describe the technical solutions shown in this application in detail through specific embodiments. It should be noted that the description order of the following embodiments does not limit the priority order of the embodiments.

[0053] Please refer to Figure 2 , Figure 2 which is a schematic flowchart of the lithography imaging simulation method provided by the embodiment of this application. The specific process of this lithography imaging simulation method can be as follows:

[0054] 101. Obtain the first simulation area of the wafer.

[0055] Among them, the wafer refers to a semiconductor wafer. The first simulation area refers to the area on the semiconductor wafer where the lithography process is to be performed. The method for obtaining the first simulation area can be through user input, system automatic recognition, or presetting, etc. For example, the user can input information such as the model, size, and position of the area to be simulated of the wafer, and the system can automatically determine the first simulation area; or, the system can also pre-store the simulation area information of multiple wafers, and the user only needs to select the corresponding wafer model, and the system can automatically obtain the corresponding first simulation area.

[0056] 102. Based on the surface topography characteristics of the wafer, decompose the simulation area into several first sub-areas.

[0057] It can be understood that when forming the wafer, the ion implantation process, lithography process, and double exposure technology will all cause changes in the topography of the wafer surface deposited inside the photoresist, such as surface topography characteristics such as flat, convex, and concave. For example, as the feature size of semiconductor devices decreases, in the multi-layer resist lithography process, the photoresist will undergo a chemical reaction after being exposed, resulting in the curing of the photoresist within a certain area, thereby causing local deformation of the photoresist.

[0058] Therefore, in the specific implementation process, the first simulation area can be decomposed into several first sub-areas according to the surface topography characteristics. It should be noted that during the decomposition process, it should be ensured that the sub-areas are as independent as possible, but small-range overlap is allowed.

[0059] 103. Extract the first electric field information of the first sub-region from the electric field look-up table.

[0060] It can be understood that the electric field look-up table is preset in advance before the simulation. That is, before step 101, it may further include the step of constructing the electric field look-up table.

[0061] Specifically, several second simulation regions can be obtained first; then, based on the surface topography characteristics of the wafer, the corresponding second simulation regions are decomposed into several second sub-regions; and then the electric field look-up table is constructed based on the third electric field information of each second sub-region.

[0062] In some embodiments, each second sub-region can be further decomposed into several first boundary line segments; then the fourth electric field information of each first boundary line segment is calculated using a preset electromagnetic field algorithm, and the electric field look-up table is generated based on the fourth electric field information.

[0063] It can be understood that in this electric field look-up table, there is a one-to-one correspondence between the electric field information and the boundary line segments.

[0064] Therefore, during the simulation process, after the simulation region is decomposed into several first sub-regions, similarly, the first sub-region can be divided into several second boundary line segments first, and then the corresponding fifth electric field information is extracted from the electric field look-up table based on the second boundary line segments.

[0065] In some embodiments, when the second boundary line segment cannot fully match the electric field information in the electric field look-up table, an interpolation method can also be used to calculate the approximate value, and the approximate value is used as the corresponding fifth electric field information.

[0066] 104. Perform electric field superposition processing and redundancy removal processing on several first electric field information to obtain the second electric field information of the first simulation region.

[0067] In one embodiment, the electric field superposition processing and redundancy removal processing can be performed on the several fifth electric field information of each first sub-region first to obtain the first electric field information of each first sub-region; then the electric field superposition processing and redundancy removal processing are performed on the several first electric field information to obtain the second electric field information of the first simulation region.

[0068] In another embodiment, the electric field superposition processing and redundancy removal processing can be directly performed on the several fifth electric field information to obtain the second electric field information of the first simulation region.

[0069] It should be noted that the results obtained by the above two methods are exactly the same. Electric field superposition processing refers to combining two electric field information together. Redundancy removal processing refers to removing the repeated parts between the electric field information. For details, reference can be made to Figure 3 and Figure 4 as shown. Among them, Figure 3It represents the process of obtaining the second electric field information through the electric field superposition process and redundancy removal process of the first electric field information. Figure 4 It represents the process of obtaining the first electric field information through the electric field superposition process and redundancy removal process of the fifth electric field information.

[0070] 105. Based on the optical system parameters and the second electric field information, calculate the optical imaging result of the target mask pattern.

[0071] In projection lithography imaging, the light intensity in a certain lithography medium is obtained by the combined action of different plane wave diffraction orders excited by the exit pupil, and the amplitude and phase of the plane wave are jointly determined by parameters such as the mask layout, illumination conditions, and objective lens properties, such as the light source incident angle, the numerical aperture NA of the objective lens, etc. Therefore, in the embodiments of the present application, the optical system parameters can be the plane wave diffraction orders.

[0072] Taking the imaging of a one-dimensional periodic dense mask layout as an example, the target mask pattern is a one-dimensional periodic dense pattern arranged along the X direction, and the 0th and 1st order plane wave diffraction orders and electric field information are used for imaging. The formula is as follows:

[0073]

[0074] Among them, is the plane wave diffraction order, is the amplitude corresponding to the plane wave diffraction order, is the final optical imaging result.

[0075] It can be understood that when the light source conditions, the objective lens properties, and the target mask pattern change, only the values of the corresponding plane wave diffraction orders and the above-mentioned electric field information need to be input to quickly obtain the final optical imaging result.

[0076] In summary, the lithography imaging simulation method provided by the embodiments of the present application includes obtaining the first simulation area of the wafer; decomposing the simulation area into several first sub-areas based on the surface topography characteristics of the wafer; extracting the first electric field information of the first sub-areas from the electric field look-up table; performing an electric field superposition process and redundancy removal process on the several first electric field information to obtain the second electric field information of the first simulation area; calculating the optical imaging result of the target mask pattern based on the optical system parameters and the second electric field information. This solution can decompose a complex simulation area into several sub-areas and use the look-up table to find the electric field information of the sub-areas, thereby reducing the real-time calculation complexity and improving the efficiency of lithography imaging simulation.

[0077] To facilitate better implementation of the lithography imaging simulation method provided by the embodiments of the present application, the embodiments of the present application also provide a lithography imaging simulation device. The meanings of the terms are the same as those in the above lithography imaging simulation method, and the specific implementation details can refer to the description in the method embodiments.

[0078] Please refer to Figure 5 , Figure 5 which is a schematic structural diagram of a lithographic imaging simulation device provided by an embodiment of the present application. The lithographic imaging simulation device may include a determination unit 201, a decomposition unit 202, a search unit 203, a top superposition unit 204, and a calculation unit 205. Among them,

[0079] The determination unit 201 is configured to obtain a first simulation area of the wafer;

[0080] The decomposition unit 202 is configured to decompose the simulation area into a plurality of first sub-areas based on the surface topography characteristics of the wafer;

[0081] The search unit 203 is configured to extract first electric field information of the first sub-area from an electric field look-up table;

[0082] The superposition unit 204 is configured to perform electric field superposition processing and redundancy removal processing on a plurality of pieces of first electric field information to obtain second electric field information of the first simulation area;

[0083] The calculation unit 205 is configured to calculate an optical imaging result of a target mask pattern based on optical system parameters and the second electric field information.

[0084] For the specific implementation manners of each of the above units, reference may be made to the embodiments of the above-mentioned lithographic imaging simulation method, which will not be elaborated herein one by one.

[0085] In summary, the lithographic imaging simulation device provided by the embodiment of the present application can obtain a first simulation area of the wafer through the determination unit 201; decompose the simulation area into a plurality of first sub-areas by the decomposition unit 202 based on the surface topography characteristics of the wafer; extract first electric field information of the first sub-area from an electric field look-up table by the search unit 203; perform electric field superposition processing and redundancy removal processing on a plurality of pieces of first electric field information by the superposition unit 204 to obtain second electric field information of the first simulation area; calculate an optical imaging result of a target mask pattern based on optical system parameters and the second electric field information by the calculation unit 205. This solution can decompose a complex simulation area into a plurality of sub-areas and use a look-up table to search for sub-area electric field information, thereby reducing the real-time calculation complexity and improving the efficiency of lithographic imaging simulation.

[0086] The embodiment of the present application further provides an electronic device, which may integrate the lithographic imaging simulation device of the embodiment of the present application. As Figure 6 shown, which shows a schematic structural diagram of the electronic device involved in the embodiment of the present application. Specifically:

[0087] The electronic device may include components such as a processor 301 with one or more processing cores and a memory 302 with one or more computer-readable storage media. Those skilled in the art can understand that Figure 6 the structure of the electronic device shown in

[0088] does not limit the electronic device, and it may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements. Among them:

[0089] The processor 301 is the control center of the electronic device, connecting various parts of the entire electronic device through various interfaces and circuits. By running or executing software programs and / or this application stored in the memory 302, and by calling the data stored in the memory 302, it executes various functions of the electronic device and processes data, thereby monitoring the electronic device as a whole. Optionally, the processor 301 may include one or more processing cores; preferably, the processor 301 may integrate an application processor and a modem processor. Among them, the application processor mainly processes operation of the storage medium, user interface, application programs, etc., and the modem processor mainly processes wireless communication. It can be understood that the above-mentioned modem processor may not be integrated into the processor 301 either.

[0090] Although not shown, the electronic device may further include a display unit, an input unit, a power supply, etc., which will not be elaborated here. Specifically in this embodiment, the processor 301 in the electronic device will, according to the following instructions, load the executable files corresponding to the processes of one or more application programs into the memory 302, and the processor 301 will run the application programs stored in the memory 302 to implement various functions as follows:

[0091] Obtain the first simulation area of the wafer;

[0092] Based on the surface topography characteristics of the wafer, decompose the simulation area into several first sub-areas;

[0093] Extract the first electric field information of the first sub-region from the electric field look-up table;

[0094] Perform electric field superposition processing and redundancy removal processing on a number of first electric field information to obtain the second electric field information of the first simulation region;

[0095] Calculate the optical imaging result of the target mask pattern based on the optical system parameters and the second electric field information.

[0096] Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructions, or by controlling related hardware through instructions. The instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0097] For this reason, an embodiment of the present application provides a storage medium, which stores multiple instructions that can be loaded by a processor to execute the steps in any one of the methods provided by the embodiments of the present application. For example, the instructions can perform the following steps:

[0098] Obtain the first simulation region of the wafer;

[0099] Based on the surface topography characteristics of the wafer, decompose the simulation region into a number of first sub-regions;

[0100] Extract the first electric field information of the first sub-region from the electric field look-up table;

[0101] Perform electric field superposition processing and redundancy removal processing on a number of first electric field information to obtain the second electric field information of the first simulation region;

[0102] Calculate the optical imaging result of the target mask pattern based on the optical system parameters and the second electric field information.

[0103] For the specific implementation of each of the above operations, reference can be made to the previous embodiments, which will not be elaborated here.

[0104] Among them, the storage medium may include: read-only memory (ROM, Read Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk, etc.

[0105] Since the instructions stored in the storage medium can execute the steps in any one of the methods provided by the embodiments of the present application, the beneficial effects that can be achieved by any one of the methods provided by the embodiments of the present application can be realized. For details, reference can be made to the previous embodiments, which will not be elaborated here.

[0106] The above has introduced in detail the lithography imaging simulation method, device, storage medium and electronic device provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A lithography imaging simulation method, characterized in that: include: Acquire a first simulation region of a wafer; Based on the surface morphology characteristics of the wafer, decomposing the first simulation area into a plurality of first sub-areas; Extracting first electric field information of the first sub-region from an electric field lookup table, wherein the construction process of the electric field lookup table includes acquiring a plurality of second simulation regions; decomposing the corresponding second simulation region into a plurality of second sub-regions based on the surface morphology characteristics of the wafer; constructing an electric field lookup table based on the third electric field information of each of the second sub-regions; Performing electric field superposition processing and redundancy removal processing on a plurality of the first electric field information to obtain second electric field information of the first simulation area; Based on the optical system parameters and the second electric field information, an optical imaging result of the target mask pattern is calculated.

2. The lithography imaging simulation method according to claim 1, characterized in that: The constructing an electric field lookup table based on the third electric field information of each of the second sub-regions comprises: decomposing each of the second sub-regions into a plurality of first boundary line segments; The fourth electric field information of each of the first boundary line segments is calculated using a preset electromagnetic field algorithm, and an electric field lookup table is generated based on the fourth electric field information.

3. The lithography imaging simulation method according to claim 2, characterized in that: The extracting the first electric field information of the first sub-area from the electric field lookup table includes: dividing the first sub-region into a plurality of second boundary line segments; Based on the second boundary line segment, corresponding fifth electric field information is extracted from the electric field lookup table.

4. The lithography imaging simulation method according to claim 3, characterized in that: The performing electric field superposition processing and redundancy removal processing on a plurality of the first electric field information to obtain the second electric field information of the first simulation area includes: Performing electric field superposition processing and redundancy removal processing on a plurality of fifth electric field information of each first sub-region to obtain first electric field information of each first sub-region; Electric field superposition processing and redundancy removal processing are performed on a plurality of the first electric field information to obtain second electric field information of the first simulation area.

5. The lithography imaging simulation method according to claim 3, characterized in that: The performing electric field superposition processing and redundancy removal processing on a plurality of the first electric field information to obtain the second electric field information of the first simulation area includes: Perform electric field superposition processing and redundancy removal processing on a plurality of the fifth electric field information to obtain the second electric field information of the first simulation area.

6. A photolithography imaging simulation device, characterized in that: include: A determination unit, configured to obtain a first simulation region of a wafer; A decomposition unit, configured to decompose the first simulation region into a plurality of first sub-regions based on the surface morphology characteristics of the wafer; A search unit, configured to extract the first electric field information of the first sub-region from an electric field lookup table, wherein the construction process of the electric field lookup table includes acquiring a plurality of second simulation regions; and decomposing the corresponding second simulation region into a plurality of second sub-regions based on the surface morphology characteristics of the wafer; constructing an electric field lookup table based on the third electric field information of each of the second sub-regions; a superposition unit, configured to perform electric field superposition processing and redundancy removal processing on a plurality of the first electric field information to obtain second electric field information of the first simulation area; A calculation unit is used to calculate the optical imaging result of the target mask pattern based on the optical system parameters and the second electric field information.

7. A storage medium, characterized in that: The storage medium stores a plurality of instructions, and the instructions are suitable for being loaded by a processor to execute the lithography imaging simulation method according to any one of claims 1 to 5.

8. An electronic device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the lithography imaging simulation method according to any one of claims 1 to 5 when executing the computer program.

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