A bidirectional loaded gate bias circuit

Abstract

The invention discloses a bidirectional gate bias circuit with load, which relates to the technical field of semiconductor integrated circuit design, including a circuit for generating a reference voltage V ref The reference circuit, N-type output power tube N1, P-type output power tube P1, comparator A1 for providing control gate voltage for P-type output power tube P1, comparator A2 for providing control gate voltage for N-type output power tube N1, resistor string and switch logic circuit, resistor string and switch logic, are used to provide resistor voltage V r And the output voltage VOUT, through the logic code to control the switch logic, so as to select different resistors in the resistor string to obtain different output voltages VOUT; thereby, a stable adjustable voltage can be generated, and it has a bidirectional load capacity, which can provide a large current for the subsequent stage, or receive a large current from the subsequent stage, to ensure that under large load conditions, the output voltage fluctuates as little as possible compared to the no-load voltage, so as to meet the different needs of the subsequent circuit.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor integrated circuit design, and in particular to a bidirectional loaded gate voltage bias circuit. Background Art

[0002] The gate bias chip is a common electronic component used to provide a stable voltage bias in integrated circuits. It plays a vital role in various electronic devices, including analog circuits, oscillators, filters, and various GaAs amplifiers, providing stable and reliable gate bias.

[0003] Currently, most of the gate bias chips on the market have only unidirectional load-carrying capabilities. However, various types of GaAs amplifiers have very high requirements for the stability of the bias voltage, and sometimes require bidirectional load-carrying capabilities. The simple use of N-type power tubes or P-type power tubes can only provide unidirectional load-carrying capabilities, which obviously cannot meet the requirements of such amplifiers. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides a bidirectional loaded gate bias circuit, including a reference circuit, an N-type output power tube N1, a P-type output power tube P1, a comparator A1, a comparator A2, a resistor string and a switch logic circuit; Reference circuit for generating reference voltage V ref , provide reference for the later stage; The comparator A1 is used to provide a control gate voltage for the P-type output power tube P1. When the output port of the bias circuit pulls out current, the comparator A1 adjusts the gate voltage of the P-type output power tube P1 through negative feedback; The comparator A2 is used to provide a control gate voltage for the N-type output power tube N1. When the output port of the bias circuit injects current, the comparator A2 adjusts the gate voltage of the N-type output power tube N1 through negative feedback. N-type output power tube N1 and P-type output power tube P1, when the output port of the bias circuit pulls out current, the current flows out from the P-type output power tube P1; when the output port of the bias circuit injects current, the current flows into the N-type output power tube N1; Resistor strings and switch logic are used to provide the resistor divider V r and the output voltage VOUT, and controls the switch logic through the logic code, thereby selecting different resistors in the resistor string to obtain different output voltages VOUT.

[0005] The technical solution further defined in the present invention is: Furthermore, the reference circuit generates a reference voltage V with a zero temperature coefficient. ref .

[0006] As described above, a bidirectional loaded gate bias circuit, the reference circuit includes a bandgap reference source and a BUFFER module, the bandgap reference source includes transistors Q1 and Q2, and the exponential ratio of the two is 1:8, and the input and output voltages of the bandgap reference source are VEE and V bg , V bg Generate a reference voltage V through the BUFFER module ref , as the reference voltage for the subsequent output circuit.

[0007] As described above, in a bidirectional gate bias circuit with load, the in-phase input terminals of comparator A1 and comparator A2 are both connected to a resistor divider voltage V r , the inverting input terminals of both are connected to the reference voltage V ref , comparator A1 and comparator A2 are used to control the gate voltage of P-type output power tube P1 and N-type output power tube N1 respectively. When the input current makes the output voltage VOUT increase toward GND, the resistor divider voltage V r The output voltage VOUT increases, and the output voltage V2 of comparator A2 increases through the negative feedback loop, and the output voltage VOUT decreases, making the resistor voltage V r Gradually equal to the reference voltage V ref When the pull current makes the output voltage VOUT decrease towards VEE, the negative feedback loop makes the resistor divider voltage V r Gradually equal to the reference voltage V ref .

[0008] In the bidirectional loaded gate bias circuit as described above, the width-to-length ratio of the N-type output power tube N1 and the P-type output power tube P1 is 17000:1.

[0009] As described above, in a bidirectional loaded gate bias circuit, comparator A1 and comparator A2 are both provided with input pair transistors M1 and input pair transistors M2, and the gates of the two are respectively connected to the reference voltage V ref And the resistor divider V r The output voltages of comparator A1 and comparator A2 are V1 and V2, which are the gate voltages of P-type output power tube P1 and N-type output power tube N1, respectively.

[0010] As described above, in a bidirectional loaded gate bias circuit, a hysteresis structure is provided in comparator A1 and comparator A2, and the input pair tube M1 and the input pair tube M2 in the same comparator have different sizes. The width-to-length ratio of the input pair tube M1 in comparator A1 is larger than that of the input pair tube M2, while the width-to-length ratio of the input pair tube M1 in comparator A2 is smaller than that of the input pair tube M2.

[0011] As described above, in the bidirectional gate bias circuit with load, in comparator A1 and comparator A2, when the signal V rWhen V is low, the output voltage of comparator A1 is low, the output voltage of comparator A2 is also low, the P-type output power tube P1 is turned on, and the N-type output power tube N1 is turned off; when V r As the voltage gradually increases, the hysteresis structure introduced in the comparator will cause V r Rising to V ref -ΔV, the output voltage of comparator A1 changes from low to high, and the P-type output power tube P1 is turned off; when V r Rising to V ref +ΔV, the output voltage of comparator A2 changes from low to high, and the N-type output power tube N1 turns on.

[0012] As described above, in a bidirectional loaded gate bias circuit, a resistor string and a switch logic, the resistor string includes a plurality of resistors connected in series, wherein the first resistor is recorded as the first resistor R s , the second resistor is recorded as the starting resistor R1, and the following 32 resistors are recorded as R2, R3, ..., R x ,...,R 32 , x is an integer from 1 to 32; the reference voltage V ref Set to -0.5V, the first resistor R s The resistance value is set to R, and the corresponding voltage is V r , equal to the reference voltage V ref , that is, V r =V ref =-0.5V; the resistance of the starting resistor R1 is A*R, A=1.6, the corresponding voltage is -1.3V, which is the starting voltage; the resistance of the resistor R2 is B*R, B=0.1, the corresponding voltage is -1.35V, and the subsequent resistors R3 to R 32 The resistance value is 0.1R, and the voltage difference across each subsequent resistor is 50mV, and the corresponding voltage value is -(25+x)*0.05V.

[0013] As described above, in the bidirectional loaded gate bias circuit, in the resistor string and the switch logic, except for the first resistor R s Any two adjacent resistors R x With R x+1There is a MOS switch tube xK in between; take the five-bit logic code D4 / D3 / D2 / D1 / D0, and the five-bit logic code generates 32 pairs of differential switch signals xN and xP after passing through the logic circuit, which are used to control the corresponding MOS switch xK respectively; the initial state xN is low level, xP is high level, and the corresponding switch tube xK is turned off, when xN is high level, xP is low level, the corresponding switch tube xK is turned on; at the same time, only one xN signal is high level, and the corresponding xP is low level, that is, only one MOS switch tube xK will be turned on, and the rest are in the off state, and the corresponding voltage value -(25+x)*0.05V is output; when the logic code input level is GND, the corresponding logic is high, that is, 1, when the logic code input level is VEE, the corresponding logic is low, that is, 0, thus forming 32 corresponding logic states.

[0014] The beneficial effects of the present invention are: (1) The present invention can generate a bias voltage with a deviation of less than 1% when no-load and has a zero temperature coefficient characteristic, and the bias voltage value can be adjusted by changing the external code; (2) In the present invention, the bias voltage has a certain bidirectional load capacity. Under high current load conditions, the bias voltage is stable within a certain fluctuation range, thereby meeting the requirements of more amplifiers. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the overall structure of the present invention; Figure 2 This is a schematic diagram of the reference source structure in an embodiment of the present invention; Figure 3 A schematic diagram of a comparator with a hysteresis structure in an embodiment of the present invention; Figure 4 This is a timing diagram of the gate voltage hysteresis of the power tube in an embodiment of the present invention; Figure 5 Schematic diagram of a resistor string and a switch logic circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0016] This embodiment provides a bidirectional loaded gate bias circuit, such as Figure 1 As shown, it includes a reference circuit, an N-type output power tube N1, a P-type output power tube P1, a comparator A1, a comparator A2, a resistor string and a switch logic circuit.

[0017] The reference circuit is used to generate the reference voltage V ref, in this embodiment, it is set to -0.5V, which provides a reference for the subsequent stage; the comparator A1 is used to provide a control gate voltage for the P-type output power tube P1. When the output port of the bias circuit pulls out current, the comparator A1 adjusts the gate voltage of the P-type output power tube P1 through negative feedback; the comparator A2 is used to provide a control gate voltage for the N-type output power tube N1. When the output port of the bias circuit injects current, the comparator A2 adjusts the gate voltage of the N-type output power tube N1 through negative feedback; when the output port of the bias circuit pulls out current, the current flows out from the P-type output power tube P1; when the output port of the bias circuit injects current, the current flows into the N-type output power tube N1; the resistor string and the switch logic are used to provide a resistor voltage divider V r The output voltage VOUT is controlled by the logic code to control the switch logic, thereby selecting different resistors in the resistor string to obtain different output voltages VOUT. The encoding logic is 5-bit encoding D4 / D3 / D2 / D1 / D0.

[0018] For various types of GaAs amplifiers, the bias voltage stability is very high, and sometimes bidirectional load capacity is required, while the simple use of N-type power tubes or P-type power tubes can only provide unidirectional load capacity. In order to solve the above problems, this embodiment uses both N-type output power tube N1 and P-type output power tube P1, and adjusts the gate voltage of P-type output power tube P1 and N-type output power tube N1 respectively through comparator A1 and comparator A2, so that the output voltage is stable within a certain fluctuation range.

[0019] Circuit framework such as Figure 1 As shown, the reference circuit consists of a bandgap reference source and a post-stage BUFFER module, where the reference source structure is as follows: Figure 2 As shown, a typical bandgap reference source structure is adopted, and the exponential ratio of transistors Q1 and Q2 is 1:8. At this time, the output voltage V bg is -1.2V, V bg Generate a reference voltage V through the BUFFER module ref It is -0.5V, which serves as the reference voltage for the subsequent output circuit.

[0020] When the P-type output power tube P1 or the N-type output power tube N1 is turned on, in order to stabilize the output voltage and not change with the load current, comparator A1 and comparator A2 are used to provide gate voltage for the output tube respectively. One end of the two comparators is connected to the resistor voltage divider V r , the other end is connected to the reference voltage V ref , the comparator controls the gate voltage of the output tubes P1 and N1. When the current is injected to increase the output voltage VOUT toward GND, V r It will increase with VOUT, and through the negative feedback loop, V2 will increase, VOUT will decrease, and finally V r The terminal voltage is stable at a value close to the reference voltage V refSimilarly, when the pull current makes the output voltage decrease toward VEE, the negative feedback loop makes V r The terminal voltage is stable at a value close to the reference voltage V ref Place.

[0021] In order to ensure the gate bias circuit's 400mA current carrying capacity, the output MOS tube's width-to-length ratio W:L is 17000:1. The MOS tube has a relatively large width-to-length ratio. If the two MOS tubes of the output stage are turned on at the same time, a short-circuit current will be generated from GND to VEE, which will increase system power consumption on the one hand and reduce working reliability on the other. Therefore, a hysteresis structure design needs to be added to comparators A1 and A2.

[0022] like Figure 3 As shown, M1 and M2 are the input pair of comparators, and their gates are connected to the reference voltage V ref And the resistor divider V r , the output voltage of comparator A1 is V1, and the output voltage of A2 is V2, which are the gate voltages of output MOS tubes P1 and N1 respectively.

[0023] Under normal circumstances, the sizes of the input pair tubes M1 and M2 of the comparator are the same. At this time, the response voltages of the comparators A1 and A2 are also the same. When the output tubes N1 and P1 flip at the same time, the two MOS tubes will be turned on at the same time. In order to avoid simultaneous conduction, a hysteresis structure design is introduced in the comparator, and the sizes of the input pair tubes M1 and M2 of the comparator are set to be different. The width-to-length ratio of M1 in comparator A1 is larger than that of M2, while the width-to-length ratio of M1 in comparator A2 is smaller than that of M2. The specific size difference can be adjusted according to the required hysteresis voltage.

[0024] The corresponding hysteresis timing is as follows Figure 4 As shown, when the signal V r When V is low, the output voltage of comparator A1 is low, the output voltage of comparator A2 is also low, P1 is turned on, and N1 is turned off; when V r As the voltage gradually increases, due to the hysteresis structure design introduced in the comparator, when V r Rising to V ref -ΔV, the output voltage of comparator A1 changes from low to high, and P1 is turned off; when V r When it rises to Vref+ΔV, the output voltage of comparator A2 changes from low to high, and tube N1 is turned on, so there is no short circuit.

[0025] The output voltage of the circuit is obtained by resistor voltage division. The resistor string includes several resistors connected in series, of which the first resistor is recorded as the first resistor R s , the second resistor is recorded as the starting resistor R1, and the following 32 resistors are recorded as R2, R3, ..., R x ,...,R 32, x is an integer from 1 to 32; when the first resistor R s The resistance value is set to R, and the corresponding voltage is V r , which is basically equal to the reference voltage, that is, V r =V ref =-0.5V, the resistance of the starting resistor R1 is A*R, A=1.6, the corresponding voltage is -1.3V, which is the starting voltage; the resistance of the resistor R2 is B*R, B=0.1, the corresponding voltage is -1.35V, the subsequent resistors R3 to R 32 The resistance value is 0.1R, and so on. The voltage difference across each subsequent resistor is 50mV, and the corresponding voltage value is -(25+x)*0.05V.

[0026] By using different external codes and selecting different resistors, the corresponding voltage value can be obtained. Take the five-bit logic code D4 / D3 / D2 / D1 / D0, and the five-bit logic code will generate 32 pairs of differential switch signals xN and xP (x is an integer from 1 to 32) after passing through the logic circuit.

[0027] The schematic diagram of the resistor string and switch logic circuit is as follows Figure 5 As shown, the left side of the figure is a logic circuit, which encodes the input five-bit logic code D4 / D3 / D2 / D1 / D0 into 32 pairs of differential signals xN and xP, which respectively control the 32 corresponding MOS switches xK on the right side of the figure. In the initial state, xN is low level and xP is high level, and the corresponding switch tube xK is turned off. When xN is high level and xP is low level, the corresponding switch tube xK is turned on. At the same time, only one xN signal will be high level and the corresponding xP will be low level, that is, only one MOS switch tube xK will be turned on, and the rest will be in the off state, and the corresponding output voltage value is -(25+x)*0.05V.

[0028] When the logic code input level is GND, the corresponding logic is high (1), and when the logic code input level is VEE, the corresponding logic is low (0). At this time, 32 corresponding logic states can be formed; when the logic code D4 / D3 / D2 / D1 / D0 is 00000, after encoding through the logic circuit, 1N is high level, 1P is low level, and the rest are initial states. At this time, the 1K switch tube is turned on, and the output voltage VOUT is -1.3V. By analogy, each time the logic code is increased by 1, the corresponding opened switch tube x is increased by 1. When the logic code is 00000, 1N is high level, 1P is low level, and the rest are initial states. At this time, the 1K switch tube is turned on, and the output voltage VOUT is -1.3V. By analogy, each time the logic code is increased by 1, the corresponding opened switch tube x is increased by 1. When the code D4 / D3 / D2 / D1 / D0 is 11111, 32N is high level, 32P is low level, and the rest are in the initial state. At this time, the 32K switch tube is turned on, and the output voltage VOUT is -2.85V. The corresponding relationship between the encoding logic and the output voltage is shown in Table 1. 32 output voltages can be obtained, with a minimum of -2.85V and a maximum of -1.3V, with a step of 50mV, and all output voltages have bidirectional load capacity. When the load current is 400mA, the output voltage fluctuation is less than 80mV.

[0029] Table 1 Correspondence between encoding logic and output voltage

[0030] The actual circuit test results show that the bidirectional loaded gate bias circuit provided in this embodiment is a negative power system, so it is powered by a -5V power supply. When the enable port SHDN is at a low level, the chip is in an off state, and the chip current is less than 10uA at this time; when SHDN is at a high level, the chip works normally, and the overall working current is less than 0.8mA at this time; assuming that the logic code is 00000 at this time, the output voltage is -1.3V, when the injection current is less than or equal to 400mA, the output voltage is always between -1.22V and -1.3V, and when the pull current is less than or equal to 400mA, the output voltage is always between -1.38V and -1.3V; and so on, the output voltage changes from -1.3V to -2.85V with the logic code, and when the load current is 400mA, the output voltage fluctuation is always less than 80mV.

[0031] In addition to the above embodiments, the present invention may also have other implementation modes. Any technical solution formed by equivalent replacement or equivalent transformation falls within the protection scope required by the present invention.

Claims

1. A bidirectional loaded gate bias circuit, characterized in that: It includes a reference circuit, an N-type output power tube N1, a P-type output power tube P1, a comparator A1, a comparator A2, a resistor string and a switch logic circuit; Reference circuit for generating reference voltage V ref , provide reference for the later stage; The comparator A1 is used to provide a control gate voltage for the P-type output power tube P1. When the output port of the bias circuit pulls out current, the comparator A1 adjusts the gate voltage of the P-type output power tube P1 through negative feedback; The comparator A2 is used to provide a control gate voltage for the N-type output power tube N1. When the output port of the bias circuit injects current, the comparator A2 adjusts the gate voltage of the N-type output power tube N1 through negative feedback. N-type output power tube N1 and P-type output power tube P1, when the output port of the bias circuit pulls out current, the current flows out from the P-type output power tube P1; when the output port of the bias circuit injects current, the current flows into the N-type output power tube N1; Resistor strings and switch logic are used to provide the resistor divider V r and the output voltage VOUT, and controls the switch logic through the logic code, thereby selecting different resistors in the resistor string to obtain different output voltages VOUT.

2. A bidirectional loaded gate bias circuit according to claim 1, characterized in that: The reference circuit generates a zero temperature coefficient reference voltage V ref .

3. A bidirectional loaded gate bias circuit according to claim 2, characterized in that: The reference circuit includes a bandgap reference source and a BUFFER module. The bandgap reference source includes transistors Q1 and Q2, and the exponential ratio of the two is 1:

8. The input and output voltages of the bandgap reference source are VEE and V bg , V bg Generate a reference voltage V through the BUFFER module ref , as the reference voltage for the subsequent output circuit.

4. The bidirectional loaded gate bias circuit according to claim 1, characterized in that: The in-phase input terminals of comparator A1 and comparator A2 are both connected to the resistor divider V r , the inverting input terminals of both are connected to the reference voltage V ref , comparator A1 and comparator A2 are used to control the gate voltage of P-type output power tube P1 and N-type output power tube N1 respectively. When the input current makes the output voltage VOUT increase toward GND, the resistor divider voltage V r The output voltage VOUT increases, and the output voltage V2 of comparator A2 increases through the negative feedback loop, and the output voltage VOUT decreases, making the resistor voltage V r Gradually equal to the reference voltage V ref When the pull current makes the output voltage VOUT decrease towards VEE, the negative feedback loop makes the resistor divider voltage V r Gradually equal to the reference voltage V ref .

5. A bidirectional loaded gate bias circuit according to claim 4, characterized in that: The width-to-length ratio of the N-type output power tube N1 and the P-type output power tube P1 is 17000:

1.

6. The bidirectional loaded gate bias circuit according to claim 1, characterized in that: The comparator A1 and the comparator A2 are both provided with an input pair of transistors M1 and an input pair of transistors M2, and the gates of the two are connected to the reference voltage V ref And the resistor divider V r The output voltages of comparator A1 and comparator A2 are V1 and V2, which are the gate voltages of P-type output power tube P1 and N-type output power tube N1, respectively.

7. A bidirectional loaded gate bias circuit according to claim 6, characterized in that: The comparator A1 and the comparator A2 are provided with a hysteresis structure. The input pair tube M1 and the input pair tube M2 in the same comparator have different sizes. The width-to-length ratio of the input pair tube M1 in the comparator A1 is larger than that of the input pair tube M2, while the width-to-length ratio of the input pair tube M1 in the comparator A2 is smaller than that of the input pair tube M2.

8. The bidirectional loaded gate bias circuit according to claim 7, characterized in that: The comparator A1 and comparator A2, when the signal V r When V is low, the output voltage of comparator A1 is low, the output voltage of comparator A2 is also low, the P-type output power tube P1 is turned on, and the N-type output power tube N1 is turned off; when V r As the voltage gradually increases, the hysteresis structure introduced in the comparator will cause V r Rising to V ref -ΔV, the output voltage of comparator A1 changes from low to high, and the P-type output power tube P1 is turned off; when V r Rising to V ref +ΔV, the output voltage of comparator A2 changes from low to high, and the N-type output power tube N1 turns on.

9. The bidirectional loaded gate bias circuit according to claim 1, characterized in that: In the resistor string and switch logic, the resistor string includes a plurality of resistors connected in series, wherein the first resistor is recorded as the first resistor R s , the second resistor is recorded as the starting resistor R1, and the following 32 resistors are recorded as R2, R3, ..., R x ,...,R 32 , x is an integer from 1 to 32; the reference voltage V ref Set to -0.5V, the first resistor R s The resistance value is set to R, and the corresponding voltage is V r , equal to the reference voltage V ref , that is, V r =V ref =-0.5V; the resistance of the starting resistor R1 is A*R, A=1.6, the corresponding voltage is -1.3V, which is the starting voltage; the resistance of the resistor R2 is B*R, B=0.1, the corresponding voltage is -1.35V, and the subsequent resistors R3 to R 32 The resistance value is 0.1R, and the voltage difference across each subsequent resistor is 50mV, and the corresponding voltage value is -(25+x)*0.05V.

10. The bidirectional loaded gate bias circuit according to claim 9, characterized in that: In the resistor string and switch logic, except for the first resistor R s Any two adjacent resistors R x With R x+1 There is a MOS switch tube xK in between; take the five-bit logic code D4 / D3 / D2 / D1 / D0, and the five-bit logic code generates 32 pairs of differential switch signals xN and xP after passing through the logic circuit, which are used to control the corresponding MOS switch xK respectively; the initial state xN is low level, xP is high level, and the corresponding switch tube xK is turned off, when xN is high level, xP is low level, the corresponding switch tube xK is turned on; at the same time, only one xN signal is high level, and the corresponding xP is low level, that is, only one MOS switch tube xK will be turned on, and the rest are in the off state, and the corresponding voltage value -(25+x)*0.05V is output; when the logic code input level is GND, the corresponding logic is high, that is, 1, when the logic code input level is VEE, the corresponding logic is low, that is, 0, thus forming 32 corresponding logic states.

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