An adjustable output precision shunt regulator circuit and chip

Abstract

This article relates to an adjustable output precision parallel regulator circuit and chip, including a first MOS tube, a second MOS tube, a third MOS tube, a first operational amplifier and a bandgap circuit. The adjustable output precision parallel regulator circuit has three ports: an anode, a cathode and a reference end; the bandgap circuit is used to generate an internal reference voltage, and the internal reference voltage is used to control the conduction or cutoff of the first MOS tube; the external reference voltage input to the reference end is used to control the conduction or cutoff of the second MOS tube; the first MOS tube and the second MOS tube control the conduction or cutoff of the third MOS tube through the first operational amplifier; the third MOS tube is connected in series between the anode and the cathode through its source and drain. The parallel regulator in this article is implemented using a BCD process or a CMOS process, and a regulator circuit is built using MOS tubes, which increases the output current, increases the output voltage range, reduces power consumption, and improves temperature stability.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to an adjustable output precision shunt regulator circuit and chip. Background Art

[0002] Adjustable shunt regulators are widely used in various power supplies and control circuits. They include three pins, namely anode, cathode and reference terminal. When in use, the cathode is connected to the output terminal of the circuit, the anode is connected to the GND terminal of the circuit, and the reference terminal is connected between two external resistors in series. Through these two external resistors, the output voltage is set to any value between the reference voltage and the maximum voltage value to achieve the voltage regulation function.

[0003] However, the current adjustable shunt regulator has a large quiescent current, resulting in high power consumption. In addition, the output current capability is limited. In applications that require a larger output current, additional power transistors may be required for expansion. The output voltage range is small. For some high-voltage or low-voltage applications, additional circuits are required for adjustment, which increases the complexity of the structure. In addition, the existing adjustable shunt regulator is implemented using a bipolar process, which has the problem of low transistor withstand voltage and poor temperature stability. Summary of the invention

[0004] To solve the problems in the prior art, the embodiments of this article provide an adjustable output precision parallel regulator circuit and chip, which are implemented using a BCD process or a CMOS process, and use MOS tubes to build a regulator circuit, thereby increasing the output current, increasing the output voltage range, reducing power consumption, and improving temperature stability.

[0005] On the one hand, an embodiment of the present specification provides an adjustable output precision shunt regulator circuit, comprising: a first MOS tube, a second MOS tube, a third MOS tube, a first operational amplifier and a bandgap circuit, wherein the adjustable output precision shunt regulator circuit has three ports, namely, an anode, a cathode and a reference terminal;

[0006] The bandgap circuit is used to generate an internal reference voltage, and the internal reference voltage is used to control the conduction or cutoff of the first MOS tube;

[0007] The external reference voltage input to the reference terminal is used to control the conduction or cutoff of the second MOS tube;

[0008] The first MOS tube and the second MOS tube control the conduction or cutoff of the third MOS tube through the first operational amplifier;

[0009] The third MOS transistor is connected in series between the anode and the cathode via its source and drain.

[0010] Furthermore, the first MOS transistor, the second MOS transistor and the third MOS transistor are all NMOS transistors.

[0011] Further, the output end of the bandgap circuit is connected to the gate of the first MOS transistor, the source of the first MOS transistor is connected to the inverting input end of the first operational amplifier, and the drain of the first MOS transistor is connected to the cathode;

[0012] The reference end is connected to the gate of the second MOS transistor, the source of the second MOS transistor is connected to the non-inverting input end of the first operational amplifier, and the drain of the second MOS transistor is connected to the cathode;

[0013] The output end of the first operational amplifier is connected to the gate of the third MOS tube;

[0014] The drain of the third MOS tube is connected to the cathode, and the source of the third MOS tube is connected to the anode.

[0015] Furthermore, when the voltage value of the cathode increases, the reference terminal voltage increases synchronously, so that the voltage value of the source of the second MOS tube increases, the voltage value of the same-direction input terminal of the first operational amplifier is higher than the voltage value of the reverse input terminal, the first operational amplifier outputs a high level, and the third MOS tube is turned on, thereby reducing the voltage value of the cathode.

[0016] Furthermore, the adjustable output precision shunt regulator circuit further includes resistors R3 and R4, and a first current source and a second current source;

[0017] The structure formed by the series connection of R3 and the first current source is connected in series between the source of the first MOS tube and the anode;

[0018] The R4 is connected in series between the source of the second MOS tube and the non-inverting input terminal;

[0019] The second current source is connected in series between the non-inverting input terminal and the anode.

[0020] Furthermore, the adjustable output precision shunt regulator circuit also includes resistors R5 and R6;

[0021] The R5 is connected in series between the drain of the first MOS tube and the cathode;

[0022] The R6 is connected in series between the drain of the second MOS tube and the cathode.

[0023] Further, the adjustable output precision shunt regulator circuit also includes resistors R7 and R8;

[0024] The R7 is connected in series between the R5 and the drain of the first MOS tube;

[0025] The R8 is connected in series between the second current source and the non-inverting input terminal.

[0026] Furthermore, the adjustable output precision shunt regulator circuit further includes a second operational amplifier, a fourth MOS tube and resistors R1 and R2, and the fourth MOS tube is a PMOS tube;

[0027] The R1 is connected in series between the drain of the fourth MOS tube and the non-inverting input terminal of the second operational amplifier, the drain of the fourth MOS tube is connected to the gate of the first MOS tube, the gate of the fourth MOS tube is connected to the output terminal of the second operational amplifier, the source of the fourth MOS tube is connected to the cathode, and the output terminal of the bandgap circuit is connected to the reverse input terminal of the second operational amplifier;

[0028] The R2 is connected in series between the non-inverting input terminal of the second operational amplifier and the anode.

[0029] On the other hand, an embodiment of the present specification further provides a chip on which the above-mentioned adjustable output precision shunt regulator circuit is formed.

[0030] The adjustable output precision shunt regulator circuit of the embodiment of this specification is implemented by BCD process or CMOS process. Compared with the shunt regulator implemented by Bipolar process in the prior art, the adjustable output precision shunt regulator of the embodiment of this specification has low power consumption and good temperature stability because the gate of the MOS tube has no current. In addition, combined with the circuit structure of the embodiment of this specification, it has a wider voltage regulation range. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of this article or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of this article. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 It is a first structural schematic diagram of an adjustable output precision shunt regulator circuit in an embodiment of this specification;

[0033] Figure 2 This is a second structural schematic diagram of the adjustable output precision shunt regulator circuit in the embodiment of this specification;

[0034] Figure 3 It is a third structural schematic diagram of the adjustable output precision shunt regulator circuit in the embodiment of this specification;

[0035] Figure 4 It is a fourth structural schematic diagram of the adjustable output precision shunt regulator circuit in the embodiment of this specification;

[0036] Figure 5 This is a fifth structural diagram of the adjustable output precision shunt regulator circuit in the embodiments of this specification;

[0037] Figure 6 This is a sixth structural diagram of the adjustable output precision shunt regulator circuit in the embodiments of this specification;

[0038] Figure 7 This is a schematic diagram of an application of an adjustable output precision shunt regulator chip in an embodiment of this specification;

[0039] Figure 8 This is another application diagram of the adjustable output precision shunt regulator chip in the embodiments of this specification.

[0040] [Description of Reference Numerals]

[0041] MN1, the first MOS tube;

[0042] MN2, the second MOS tube;

[0043] MN3, the third MOS tube;

[0044] MP1, the fourth MOS tube;

[0045] OP1, first operational amplifier;

[0046] OP2, second operational amplifier;

[0047] Bandgap, bandgap circuit;

[0048] ANODE / VA, anode;

[0049] CATHODE / VK, cathode;

[0050] VREF, reference terminal;

[0051] R1~R8, resistor;

[0052] I1, a first current source;

[0053] I2, second current source;

[0054] 1. Adjustable output precision shunt regulator chip;

[0055] Ro, Ro3, current limiting resistor;

[0056] Ro1, Ro2, external resistor. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of this article to clearly and completely describe the technical solutions in the embodiments of this article. Obviously, the described embodiments are only part of the embodiments of this article, not all of the embodiments. Based on the embodiments of this article, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this article.

[0058] In order to solve the problems of narrow voltage regulation range, poor temperature stability and high power consumption in the existing shunt regulator circuit, the embodiments of this specification provide an adjustable output precision shunt regulator circuit, such as Figure 1 As shown, it includes: a first MOS tube MN1, a second MOS tube MN2, a third MOS tube MN3, a first operational amplifier OP1 and a bandgap circuit Bandgap, and the adjustable output precision parallel regulator circuit has three ports: an anode ANODE / VA, a cathode CATHODE / VK and a reference terminal VREF;

[0059] The bandgap circuit Bandgap is used to generate an internal reference voltage, and the internal reference voltage is used to control the on or off state of the first MOS transistor MN1;

[0060] The external reference voltage inputted by the reference terminal VREF is used to control the conduction or cut-off of the second MOS transistor MN2;

[0061] The first MOS transistor MN1 and the second MOS transistor MN2 control the on or off of the third MOS transistor MN3 through the first operational amplifier OP1;

[0062] The third MOS transistor MN3 is connected in series between the anode ANODE / VA and the cathode CATHODE / VK through its source and drain.

[0063] The adjustable output precision shunt regulator of the embodiment of this specification is a three-pin shunt regulator, which can replace the existing three-pin shunt regulator in situ. Among them, CATHODE / VK is equivalent to the cathode of the diode, that is, the output voltage, ANODE / VA is equivalent to the anode of the diode, which is generally grounded when in use, and VREF is the setting end of the output voltage, which is generally connected to an external resistor divider.

[0064] The bandgap circuit Bandgap of the embodiment of the present specification can generate a stable internal reference voltage vref1, which is usually 1.2V, to control the on or off of the first MOS transistor MN1. The voltage at the VREF terminal is used to control the on or off of the second MOS transistor MN2. The first MOS transistor MN1 and the second MOS transistor MN2 control the on or off of the third MOS transistor MN3 through the first operational amplifier OP1.

[0065] When the voltage at the CATHODE / VK terminal increases, the voltage at the VREF terminal will also increase. At this time, the voltage at the source of the second MOS tube MN2 will be higher than the source voltage of the first MOS tube MN1. At this time, the first operational amplifier OP1 controls the third MOS tube MN3 to be turned on. The third MOS tube is connected in series between ANODE / VA and CATHODE / VK through its source and drain. Therefore, the conduction of the third MOS tube MN3 can reduce the output voltage of the CATHODE / VK terminal.

[0066] Preferably, the first MOS transistor MN1 , the second MOS transistor MN2 , and the third MOS transistor MN3 in the embodiments of this specification are all NMOS transistors.

[0067] Continue as Figure 1 As shown, the output end of the bandgap circuit Bandgap is connected to the gate of the first MOS transistor MN1, the source of the first MOS transistor MN1 is connected to the inverting input end of the first operational amplifier OP1, and the drain of the first MOS transistor MN1 is connected to the cathode CATHODE / VK;

[0068] The reference terminal VREF is connected to the gate of the second MOS transistor MN2, the source of the second MOS transistor MN2 is connected to the non-inverting input terminal of the first operational amplifier OP1, and the drain of the second MOS transistor MN2 is connected to the cathode CATHODE / VK;

[0069] The output end of the first operational amplifier OP1 is connected to the gate of the third MOS transistor MN3;

[0070] The drain of the third MOS tube MN3 is connected to the cathode CATHODE / VK, and the source of the third MOS tube MN3 is connected to the anode ANODE / VA.

[0071] In the embodiment of the present specification, the source voltage of the first MOS tube MN1 is the internal reference voltage Vref1-VSGMN1, wherein VSGMN1 represents the gate-source voltage difference of the first MOS tube MN1, and the source voltage of the first MOS tube MN1 is also the reverse output terminal voltage V- of the first operational amplifier OP1. The source voltage of the second MOS tube MN2 is the external reference voltage VREF-VSGMN2, wherein VSGMN2 represents the gate-source voltage difference of the second MOS tube MN2, and the source voltage of the second MOS tube MN2 is also the non-inverting output terminal voltage V+ of the first operational amplifier OP1. When the parallel regulator works normally, V+ and V- are equal, the first operational amplifier OP1 outputs a low level, and the third MOS tube MN3 is turned off. When the cathode CATHODE / VK voltage increases, the reference voltage VREF is caused to increase synchronously. At this time, V+ is greater than V-, the first operational amplifier OP1 outputs a high level, and the third MOS tube MN3 is turned on, pulling down the cathode CATHODE / VK voltage. When V+ is less than V-, MN3 is turned off. Both MN1 and MN2 are source followers.

[0072] According to an embodiment of the present specification, in order to adapt V+ and V-, so that when the parallel regulator works normally, V+ and V- are equal, when the cathode CATHODE / VK voltage increases, V+ is greater than V-, such as Figure 1 As shown, the adjustable output precision shunt regulator circuit further includes resistors R3 and R4, and a first current source I1 and a second current source I2;

[0073] The structure formed by the series connection of R3 and the first current source I1 is connected in series between the source of the first MOS transistor MN1 and the anode ANODE / VA;

[0074] The R4 is connected in series between the source of the second MOS transistor MN2 and the non-inverting input terminal;

[0075] The second current source I2 is connected in series between the non-inverting input terminal and the anode ANODE / VA.

[0076] Therefore, the voltage V+ of the non-inverting output terminal of the first operational amplifier OP1 is equal to VREF-VGSMN2-R4*I2. When the parallel regulator works normally, V+ and V- are equal, that is, VREF=Vref1-VGSMN1+VGSMN2+R4*I2. The VREF value can be adjusted by adjusting R4 and I2 to make it higher than the external power supply voltage, so as to adapt to different application environments.

[0077] In the embodiments of this specification, I1 and I2, as current sources of source follower MN1 and source follower MN2, can provide a relatively stable current, limit the range of variation of the source current, and keep the output current stable; help to determine the static operating point of the circuit, the static operating point refers to the state of the circuit when there is no input signal, and a suitable static operating point can ensure the normal amplification and following functions of the circuit; help to enhance the stability of the entire source follower circuit, etc.

[0078] According to an embodiment of the present specification, in order to further match the working states of MN1 and MN2, as shown in FIG. Figure 2 As shown, the adjustable output precision shunt regulator circuit also includes resistors R5 and R6;

[0079] The R5 is connected in series between the drain of the first MOS tube MN1 and the cathode CATHODE / VK;

[0080] The R6 is connected in series between the drain of the second MOS transistor MN1 and the cathode CATHODE / VK.

[0081] Alternatively, if Figure 3 As shown, the adjustable output precision shunt regulator circuit may further include resistors R7 and R8;

[0082] The R7 is connected in series between the R5 and the drain of the first MOS transistor MN1;

[0083] The R8 is connected in series between the second current source I2 and the non-inverting input terminal.

[0084] Reasonable setting of the resistance values ​​of R3 to R8 ensures that the working states of MN1 and MN2 are more matched, that is, the gate voltage of MN1 is VX lower than the gate voltage of MN2, the source voltage of MN1 is VX lower than the source voltage of MN2, and the drain voltage of MN1 is also VX lower than the drain voltage of MN2, where VX = VREF-Vref1, thereby increasing the stability of the circuit and avoiding signal distortion.

[0085] According to an embodiment of the present specification, in order to better match the working states of MN1 and MN2, as shown in FIG. Figure 4 As shown, the adjustable output precision shunt regulator circuit further includes a second operational amplifier OP2, a fourth MOS tube MP1, and resistors R1 and R2, and the fourth MOS tube MP1 is a PMOS tube;

[0086] The R1 is connected in series between the drain of the fourth MOS transistor MP1 and the non-inverting input terminal of the second operational amplifier OP2. The drain of the fourth MOS transistor MP1 is connected to the gate of the first MOS transistor MN1. The gate of the fourth MOS transistor MP1 is connected to the output terminal of the second operational amplifier OP2. The source of the fourth MOS transistor MP1 is connected to the cathode CATHODE / VK. The output terminal of the bandgap circuit Bandgap is connected to the inverting input terminal of the second operational amplifier OP2;

[0087] The R2 is connected in series between the non-inverting input terminal of the second operational amplifier OP2 and the anode ANODE / VA.

[0088] It can be understood that the second operational amplifier OP2, the fourth MOS transistor MP1, and the resistors R1 and R2 form a complete voltage series negative feedback circuit for amplifying the internal reference voltage Vref1, with the aim of making the gate voltage of the first MOS transistor MN1 equal to Vref1*(R1 + R2) / R2.

[0089] The voltage V- at the inverting input terminal of the first operational amplifier OP1 is Vref1*(1 + R1 / R2) - VGSMN1, and the voltage V+ at the non-inverting input terminal is VREF - VGSMN2 - R4*I2. When V+ > V-, MN3 conducts, pulling down the voltage VK; when V+ < V-, MN3 cuts off. During normal operation, V- = V+, that is: VREF = Vref1*(1 + R1 / R2) - VGSMN1 + VGSMN2 + R4*I2. The value of VREF can be adjusted by adjusting R1, R2, R4, and I2, and it can be made higher than the external power supply voltage to adapt to different application environments.

[0090] Further, in order to further match the operating states of MN1 and MN2, as Figure 5 shown, the drains of MN1 and MN2 are respectively connected to the CATHODE port through resistors R5 and R6. As Figure 6 shown, resistors R7 and R8 are further added. Reasonably setting the resistance values of R3 to R8 ensures that the operating states of MN1 and MN2 are more matched, that is: the gate voltage, source voltage, and drain voltage of MN1 are lower than those of MN2 by the same value.

[0091] Based on the same inventive concept, the embodiments of this specification also provide an adjustable output precision shunt regulator chip, on which is formed the adjustable output precision shunt regulator circuit as Figure 1-Figure 6 any one of the above.

[0092] Exemplarily, the application schematic diagram of the adjustable output precision shunt regulator chip in the embodiments of this specification is as Figure 7As shown, the adjustable output precision parallel regulator chip 1 can be equivalent to an adjustable Zener voltage regulator, with an output voltage Vo, Vo = VK = VREF * (1 + Ro1 / Ro2). Ro3 is a current limiting resistor. The principle of selecting Ro3 is to ensure that the current IK at the cathode CATHODE / VK end is within the working range. Assume that the output voltage of Vo is 5V in actual work, and the corresponding VREF is 2.5V. When Vo is greater than 5V, VREF is greater than 2.5V, MN3 is turned on, and the Vo voltage is pulled down. When Vo is less than 5V, VREF is less than 2.5V, MN3 is turned off, and the Vo voltage increases. This cycle repeats. Since the turn-on / off is a faster process, the output voltage Vo is finally stabilized.

[0093] Optionally, the application diagram may also be as follows Figure 8 As shown, the output voltage Vo is short-circuited with VREF, the output voltage Vo=VK=VREF, and Ro is the current limiting resistor.

[0094] It should be understood that in the various embodiments of this document, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this document.

[0095] It should also be understood that in the embodiments of this article, the term "and / or" is only a description of the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0096] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this article.

[0097] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0098] In the several embodiments provided herein, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, or can be electrical, mechanical or other forms of connection.

[0099] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of this article.

[0100] In addition, each functional unit in each embodiment of this invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of software functional unit.

[0101] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this article is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of this article. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0102] Specific embodiments are used in this article to illustrate the principles and implementation methods of this article. The description of the above embodiments is only used to help understand the methods and core ideas of this article. At the same time, for general technicians in this field, according to the ideas of this article, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on this article.

Claims

1. An adjustable output precision shunt regulator circuit, characterized in that: include: A first MOS tube, a second MOS tube, a third MOS tube, a first operational amplifier and a bandgap circuit, wherein the adjustable output precision shunt regulator circuit has three ports: an anode, a cathode and a reference end; The bandgap circuit is used to generate an internal reference voltage, and the internal reference voltage is used to control the conduction or cutoff of the first MOS tube; The external reference voltage input to the reference terminal is used to control the conduction or cutoff of the second MOS tube; The first MOS tube and the second MOS tube control the conduction or cutoff of the third MOS tube through the first operational amplifier; The third MOS transistor is connected in series between the anode and the cathode via its source and drain.

2. The adjustable output precision shunt regulator circuit according to claim 1, characterized in that: The first MOS tube, the second MOS tube and the third MOS tube are all NMOS tubes.

3. The adjustable output precision shunt regulator circuit according to claim 2, characterized in that: The output end of the bandgap circuit is connected to the gate of the first MOS transistor, the source of the first MOS transistor is connected to the inverting input end of the first operational amplifier, and the drain of the first MOS transistor is connected to the cathode; The reference end is connected to the gate of the second MOS transistor, the source of the second MOS transistor is connected to the non-inverting input end of the first operational amplifier, and the drain of the second MOS transistor is connected to the cathode; The output end of the first operational amplifier is connected to the gate of the third MOS tube; The drain of the third MOS tube is connected to the cathode, and the source of the third MOS tube is connected to the anode.

4. The adjustable output precision shunt regulator circuit according to claim 3, characterized in that: When the voltage value of the cathode increases, the reference terminal voltage increases synchronously, so that the voltage value of the source of the second MOS tube increases, the voltage value of the same-direction input terminal of the first operational amplifier is higher than the voltage value of the reverse input terminal, the first operational amplifier outputs a high level, and the third MOS tube is turned on, thereby reducing the voltage value of the cathode.

5. The adjustable output precision shunt regulator circuit according to claim 3, characterized in that: The adjustable output precision shunt regulator circuit also includes resistors R3 and R4, and a first current source and a second current source; The structure formed by the series connection of R3 and the first current source is connected in series between the source of the first MOS tube and the anode; The R4 is connected in series between the source of the second MOS tube and the non-inverting input terminal; The second current source is connected in series between the non-inverting input terminal and the anode.

6. The adjustable output precision shunt regulator circuit according to claim 5, characterized in that: The adjustable output precision shunt regulator circuit also includes resistors R5 and R6; The R5 is connected in series between the drain of the first MOS tube and the cathode; The R6 is connected in series between the drain of the second MOS tube and the cathode.

7. The adjustable output precision shunt regulator circuit according to claim 6, characterized in that: The adjustable output precision shunt regulator circuit also includes resistors R7 and R8; The R7 is connected in series between the R5 and the drain of the first MOS tube; The R8 is connected in series between the second current source and the non-inverting input terminal.

8. The adjustable output precision shunt regulator circuit according to claim 1, characterized in that: The adjustable output precision parallel regulator circuit also includes a second operational amplifier, a fourth MOS tube and resistors R1 and R2, and the fourth MOS tube is a PMOS tube; The R1 is connected in series between the drain of the fourth MOS tube and the non-inverting input terminal of the second operational amplifier, the drain of the fourth MOS tube is connected to the gate of the first MOS tube, the gate of the fourth MOS tube is connected to the output terminal of the second operational amplifier, the source of the fourth MOS tube is connected to the cathode, and the output terminal of the bandgap circuit is connected to the reverse input terminal of the second operational amplifier; The R2 is connected in series between the non-inverting input terminal of the second operational amplifier and the anode.

9. A chip, comprising: The chip forms the adjustable output precision shunt regulator circuit described in any one of claims 1 to 8.

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