Embedded touch substrate and display device

Abstract

The embodiment of the invention discloses an embedded touch substrate and a display device. The embedded touch substrate adopts a tri-gate technology and comprises a driving circuit layer, a pixel electrode layer and a touch layer located between the driving circuit layer and the pixel electrode layer, the pixel electrode layer comprises a plurality of pixel electrodes arranged in an array, and the driving circuit layer comprises a plurality of scanning signal lines, a plurality of data signal lines and a plurality of transistors; each transistor is connected with a scanning signal line, a data signal line and a pixel electrode; the touch layer comprises touch subareas, vertical projections of the touch subareas on the pixel electrode layer are located between the pixel electrodes in the adjacent rows, and vertical projections of the touch subareas on the driving circuit layer are not overlapped with scanning signal lines arranged on the driving circuit layer. In conclusion, according to the scheme, the touch subareas are arranged at the positions, where the scanning signal lines are arranged, between the pixel electrodes in the adjacent rows, so that the area of the black matrix used for shielding the subareas is small, and therefore the aperture ratio of the embedded touch substrate is increased.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to an embedded touch substrate and a display device. Background Art

[0002] The embedded touch screen is a device that integrates the touch screen and the display screen. The touch driving electrodes and touch sensing electrodes of the embedded touch screen are integrated into the display screen, which can realize the functions of touch control and image display at the same time, and can reduce the overall thickness of the display module, greatly reducing the production cost of the touch screen.

[0003] However, the in-cell touch screen currently manufactured using the three-gate technology will increase the black matrix blocking area when performing touch partitioning, sacrificing a large aperture ratio, thereby reducing the aperture ratio of the in-cell touch screen. Summary of the invention

[0004] Embodiments of the present invention provide an in-cell touch substrate and a display device to improve the aperture ratio of the in-cell touch substrate.

[0005] In a first aspect, an embodiment of the present invention provides an embedded touch substrate, which adopts a three-gate technology, and the embedded touch substrate includes: a driving circuit layer, a pixel electrode layer, and a touch layer located between the driving circuit layer and the pixel electrode layer;

[0006] The pixel electrode layer includes a plurality of pixel electrodes arranged in an array, and the driving circuit layer includes a plurality of scanning signal lines, a plurality of data signal lines and a plurality of transistors; each of the transistors is connected to a scanning signal line, a data signal line and a pixel electrode;

[0007] The touch layer includes a touch partition, a vertical projection of the touch partition on the pixel electrode layer is located between the pixel electrodes of adjacent rows, and a vertical projection of the touch partition on the drive circuit layer does not overlap with the scan signal line provided on the drive circuit layer.

[0008] Optionally, the pixel electrode layer includes a first pixel group consisting of a plurality of pixel electrodes arranged in three rows and two columns;

[0009] The first pixel groups in adjacent columns share three scanning signal lines, and the first pixel groups in adjacent rows share the scanning signal line whose vertical projection on the pixel electrode layer is located between the two;

[0010] The first pixel groups in adjacent rows share three data signal lines, and the area between the first pixel groups in adjacent columns is provided with two data signal lines in a vertical projection area of ​​the touch layer.

[0011] Optionally, the transistor connected to the pixel electrode of the first row of the first pixel group is connected to the scanning signal line whose vertical projection on the pixel electrode layer is located on a side of the pixel electrode of the first row of the first pixel group away from the pixel electrode of the second row;

[0012] The transistor connected to the pixel electrode of the second row of the first pixel group and the transistor connected to the first pixel electrode of the third row are both connected to the scanning signal line whose vertical projection on the pixel electrode layer is located between the pixel electrode of the second row and the pixel electrode of the third row of the first pixel group;

[0013] The transistor connected to the second pixel electrode of the third row of the first pixel group is connected to the scanning signal line whose vertical projection on the pixel electrode layer is located on the side of the pixel electrode of the third row of the first pixel group away from the pixel electrode of the second row.

[0014] Optionally, the transistor connected to the first pixel electrode of the first column of the first pixel group and the transistor connected to the second pixel electrode are both connected to the data signal line whose vertical projection on the pixel electrode layer is located on a side of the pixel electrode of the first column of the first pixel group away from the pixel electrode of the second column;

[0015] The transistor connected to the third pixel electrode in the first column of the first pixel group and the transistor connected to the first pixel electrode in the second column are both connected to the data signal line whose vertical projection on the pixel electrode layer is located between the pixel electrode in the first column and the pixel electrode in the second column of the first pixel group;

[0016] The transistor connected to the second pixel electrode of the second column of the first pixel group and the transistor connected to the third pixel electrode are both connected to the data signal line whose vertical projection of the pixel electrode layer is located on the side of the pixel electrode of the second column of the first pixel group away from the pixel electrode of the first column.

[0017] Optionally, the pixel electrode layer includes a second pixel group consisting of a plurality of adjacent rows of pixel electrodes;

[0018] Two scanning signal lines are arranged in the vertical projection area of ​​the touch layer in the area between the second pixel groups in adjacent rows.

[0019] Optionally, the transistor connected to the pixel electrode of the first row of the second pixel group is connected to the scanning signal line whose vertical projection on the pixel electrode layer is located on a side of the pixel electrode of the first row of the second pixel group away from the pixel electrode of the second row;

[0020] The transistor connected to the pixel electrode of the second row of the second pixel group is connected to the scanning signal line whose vertical projection on the pixel electrode layer is located on the side of the pixel electrode of the second row of the second pixel group away from the pixel electrode of the first row;

[0021] The transistor connected to each pixel electrode in the same column of the second pixel group is connected to the data signal line whose vertical projection on the pixel electrode layer is located on the first side or the second side of the pixel electrode in each column of the second pixel group.

[0022] Optionally, the pixel electrode layer includes a third pixel group consisting of a plurality of pixel electrodes arranged in an array, the number of rows N of the third pixel group is greater than 4, and the number of rows N is an even number;

[0023] The transistors connected to each pixel electrode in a row of the third pixel group are connected to the same data signal line;

[0024] The transistor connected to each pixel electrode in the same column of the third pixel group is connected to the same data signal line.

[0025] Optionally, the transistor connected to the pixel electrode of the first row of the third pixel group is connected to the scanning signal line whose vertical projection on the pixel electrode layer is located on a side of the pixel electrode of the first row of the third pixel group away from the pixel electrode of the second row;

[0026] The transistor connected to the pixel electrode of the second row of the third pixel group is connected to the scanning signal line whose vertical projection on the pixel electrode layer is located on the side of the pixel electrode of the second row of the third pixel group away from the pixel electrode of the first row;

[0027] The transistor connected to the pixel electrode of the N / 2th row of the third pixel group is connected to the scanning signal line whose vertical projection on the pixel electrode layer is located on a side of the pixel electrode of the N / 2th row of the third pixel group away from the pixel electrode of the first row;

[0028] The transistor connected to the pixel electrode of the N / 2+1th row of the third pixel group is connected to the scanning signal line whose vertical projection on the pixel electrode layer is located on a side of the pixel electrode of the N / 2+1th row of the third pixel group away from the pixel electrode of the Nth row;

[0029] The transistor connected to the pixel electrode of the N-1th row of the third pixel group is connected to the scanning signal line whose vertical projection on the pixel electrode layer is located on a side of the pixel electrode of the N-1th row of the third pixel group away from the pixel electrode of the Nth row;

[0030] The transistor connected to the pixel electrode of the Nth row of the third pixel group is connected to the scanning signal line whose vertical projection on the pixel electrode layer is located on a side of the pixel electrode of the Nth row of the third pixel group away from the pixel electrode of the N-1th row;

[0031] The transistor connected to each pixel electrode in the same column of the third pixel group is connected to the data signal line whose vertical projection on the pixel electrode layer is located on the first side or the second side of the pixel electrode in each column of the third pixel group.

[0032] Optionally, the touch partition includes a partition seam;

[0033] The partition seams can divide the touch layer into a plurality of touch blocks.

[0034] In a second aspect, an embodiment of the present invention further provides a display device, which includes the embedded touch substrate provided by any embodiment of the present invention.

[0035] In the embodiment of the present invention, the touch partitions are arranged correspondingly at positions where no scanning signal lines are arranged between pixel electrodes of adjacent rows. Compared with the prior art in which the touch partitions are arranged at positions where scanning signal lines are arranged between pixel electrodes of adjacent rows, the area of ​​the black matrix used for shielding the partitions in the present solution is smaller than the area of ​​the black matrix used for shielding transistors, scanning signal lines and partitions in the prior art, thereby improving the aperture ratio of the embedded touch substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 A cross-sectional view of an embedded touch substrate provided by an embodiment of the present invention;

[0038] Figure 2 A partial top view of an embedded touch control substrate provided by an embodiment of the present invention;

[0039] Figure 3 A partial top view of another embedded touch substrate provided by an embodiment of the present invention;

[0040] Figure 4 A partial top view of another embedded touch substrate provided by an embodiment of the present invention;

[0041] Figure 5 A schematic diagram of partitions of an embedded touch control substrate provided by an embodiment of the present invention;

[0042] Figure 6 A schematic diagram of partitioning of an embedded touch control substrate provided in the prior art. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0044] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0045] Figure 1 A cross-sectional view of an embedded touch substrate provided by an embodiment of the present invention, Figure 2 FIG. 1 is a partial top view of an embedded touch control substrate provided by an embodiment of the present invention. Figure 1 and Figure 2 As shown, the embedded touch substrate adopts a three-gate technology, which includes: a driving circuit layer 110, a pixel electrode layer 120, and a touch layer 130 located between the driving circuit layer 110 and the pixel electrode layer 120;

[0046] The pixel electrode layer 120 includes a plurality of pixel electrodes P arranged in an array, and the driving circuit layer 110 includes a plurality of scanning signal lines G, a plurality of data signal lines D, and a plurality of transistors T; each transistor T is connected to a scanning signal line G, a data signal line D, and a pixel electrode P;

[0047] The touch layer 130 includes a touch partition 131 , the vertical projection of the touch partition 131 on the pixel electrode layer 120 is located between the pixel electrodes P in adjacent rows, and the vertical projection of the touch partition 131 on the driving circuit layer 110 does not overlap with the scanning signal line G set in the driving circuit layer 110 .

[0048] Among them, the driving circuit layer 110 is used to control the transmission of the scanning signal and the data voltage, so as to control the designated pixel electrode P of the pixel electrode layer 120 to obtain the data voltage. The pixel electrode layer 120 and the corresponding touch layer 130 can generate an electric field under the joint action. In a liquid crystal display, when there is a voltage difference between the pixel electrode P and the corresponding touch layer 130, an electric field will be formed in the liquid crystal layer. Under the action of the electric field, the liquid crystal molecules will change their arrangement direction. For example, the liquid crystal molecules are in a twisted state when there is no electric field, and this twisted state allows light to pass through the liquid crystal layer. When a suitable voltage is applied between the pixel electrode P and the corresponding touch layer 130, the electric field generated by the pixel electrode layer 120 and the corresponding touch layer 130 will make the arrangement direction of the liquid crystal molecules orderly, thereby changing the polarization characteristics of the liquid crystal layer to light, and then controlling the amount of light transmitted. Therefore, by accurately controlling the data voltage obtained by each pixel electrode P, the brightness and darkness of each pixel point can be adjusted, thereby displaying a complex image.

[0049] Specifically, the gate of each transistor T is connected to a scanning signal line G, the first electrode of each transistor T is connected to a data signal line D, and the second electrode of each transistor T is connected to a pixel electrode P. Thus, the transistor T can control the conduction state of the first electrode and the second electrode of the transistor T according to the scanning signal transmitted by the scanning signal line G, thereby controlling the data voltage transmitted by the data signal line D to be output to the pixel electrode P.

[0050] In addition, the touch zone 131 refers to a location where the touch sensing area of ​​the touch screen can be divided into a plurality of different areas. Figure 2 It can be seen that in this solution, the touch partition 131 is set at a position where no scanning signal line G is set between pixel electrodes P in adjacent rows. Therefore, compared with the prior art that sets the touch partition 131 at a position where a scanning signal line G is set between pixel electrodes P in adjacent rows, the area of ​​the black matrix used for shielding the partition in this solution is smaller than the area of ​​the black matrix used for shielding the transistor T, the scanning signal line G and the partition in the prior art, thereby improving the aperture ratio of the embedded touch substrate.

[0051] Based on the above embodiment, optionally, continue to refer to Figure 2 , the pixel electrode layer 120 includes a first pixel group 01 consisting of a plurality of pixel electrodes P arranged in three rows and two columns;

[0052] The first pixel groups 01 in adjacent columns share three scanning signal lines G, and the first pixel groups 01 in adjacent rows share a scanning signal line G whose vertical projection on the pixel electrode layer 120 is located between the two; the first pixel groups 01 in adjacent rows share three data signal lines D, and the area between the first pixel groups 01 in adjacent columns is provided with two data signal lines D in the vertical projection area of ​​the touch layer 130.

[0053] Among them, compared with the embedded touch screen designed with three-gate technology in the prior art, the embedded touch substrate designed in this scheme reduces the scanning signal line G and increases the data signal line D, thereby reducing the number of scanning circuits set in the border area of ​​the embedded touch substrate, thereby reducing the width of the border area of ​​the control substrate, and realizing the design of a narrow border in the border area of ​​the control substrate.

[0054] Optionally, continue to refer to Figure 2 Specifically, the transistor T connected to the pixel electrode P of the first row of the first pixel group 01 is connected to the scanning signal line G located on the side of the pixel electrode P of the first row of the first pixel group 01 away from the pixel electrode P of the second row in the vertical projection of the pixel electrode layer 120;

[0055] The transistor T connected to the pixel electrode P of the second row of the first pixel group 01 and the transistor T connected to the first pixel electrode P of the third row are both connected to the scanning signal line G whose vertical projection of the pixel electrode layer 120 is located between the pixel electrode P of the second row of the first pixel group 01 and the pixel electrode P of the third row;

[0056] The transistor T connected to the second pixel electrode P in the third row of the first pixel group 01 is connected to the scanning signal line G located on the side of the pixel electrode P in the third row of the first pixel group 01 away from the pixel electrode P in the second row in the vertical projection of the pixel electrode layer 120 .

[0057] The transistor T connected to the first pixel electrode P in the first column of the first pixel group 01 and the transistor T connected to the second pixel electrode P are both connected to the data signal line D located at the side of the pixel electrode P in the first column of the first pixel group 01 away from the pixel electrode P in the second column in the vertical projection of the pixel electrode layer 120;

[0058] The transistor T connected to the third pixel electrode P in the first column of the first pixel group 01 and the transistor T connected to the first pixel electrode P in the second column are both connected to the data signal line D whose vertical projection of the pixel electrode layer 120 is located between the pixel electrode P in the first column and the pixel electrode P in the second column of the first pixel group 01;

[0059] The transistor T connected to the second pixel electrode P in the second column of the first pixel group 01 and the transistor T connected to the third pixel electrode P are both connected to the data signal line D on the side of the pixel electrode P in the second column of the first pixel group 01, which is located away from the pixel electrode P in the first column in the vertical projection of the pixel electrode layer 120.

[0060] Based on the above embodiment, optionally, Figure 3 A partial top view of another embedded touch control substrate provided by an embodiment of the present invention. Figure 3 As shown, the pixel electrode layer 120 includes a second pixel group 02 formed by a plurality of adjacent rows of pixel electrodes P; two scanning signal lines G are arranged in the vertical projection area of ​​the touch layer 130 in the area between the adjacent rows of the second pixel groups 02 .

[0061] Among them, in this scheme, the touch partition 131 can be set at a position where no scanning signal line G is set between the pixel electrodes P of adjacent rows. Therefore, compared with the prior art that sets the touch partition 131 at a position where a scanning signal line G is set between the pixel electrodes P of adjacent rows, the area of ​​the black matrix used for shielding the partition in this scheme is smaller than the area of ​​the black matrix used for shielding the transistor T, the scanning signal line G and the partition in the prior art, thereby improving the aperture ratio of the embedded touch substrate.

[0062] Specifically, the transistor T connected to the pixel electrode P of the first row of the second pixel group 02 is connected to the scanning signal line G located on the side of the pixel electrode P of the first row of the second pixel group 02 away from the pixel electrode P of the second row in the vertical projection of the pixel electrode layer 120;

[0063] The transistor T connected to the pixel electrode P of the second row of the second pixel group 02 is connected to the scanning signal line G located at the side of the pixel electrode P of the second row of the second pixel group 02 away from the pixel electrode P of the first row in the vertical projection of the pixel electrode layer 120;

[0064] The transistor T connected to each pixel electrode P in the same column of the second pixel group 02 is connected to the data signal line D located at the first side or the second side of the pixel electrode P in each column of the second pixel group 02 in a vertical projection of the pixel electrode layer 120 .

[0065] Based on the above embodiment, optionally, Figure 4 A partial top view of another embedded touch control substrate provided by an embodiment of the present invention. Figure 4 As shown, the pixel electrode layer 120 includes a third pixel group 03 composed of a plurality of pixel electrodes P arranged in an array, the number of rows N of the third pixel group 03 is greater than 4 rows, and the number of rows N is an even number;

[0066] The transistors T connected to each pixel electrode P in the same row of the third pixel group 03 are connected to the same data signal line D;

[0067] The transistors T connected to each pixel electrode P in the same column of the third pixel group 03 are all connected to the same data signal line D.

[0068] Specifically, the transistor T connected to the pixel electrode P of the first row of the third pixel group 03 is connected to the scanning signal line G located on the side of the pixel electrode P of the first row of the third pixel group 03 away from the pixel electrode P of the second row in the vertical projection of the pixel electrode layer 120;

[0069] The transistor T connected to the pixel electrode P of the second row of the third pixel group 03 is connected to the scanning signal line G located at a side of the pixel electrode P of the second row of the third pixel group 03 away from the pixel electrode P of the first row in the vertical projection of the pixel electrode layer 120;

[0070] The transistor T connected to the pixel electrode P of the N / 2th row of the third pixel group 03 is connected to the scanning signal line G located at the side of the pixel electrode P of the N / 2th row of the third pixel group 03 away from the pixel electrode P of the first row in the vertical projection of the pixel electrode layer 120;

[0071] The transistor T connected to the pixel electrode P of the N / 2+1th row of the third pixel group 03 is connected to the scanning signal line G located at the side of the pixel electrode P of the N / 2+1th row of the third pixel group 03 away from the pixel electrode P of the Nth row in the vertical projection of the pixel electrode layer 120;

[0072] The transistor T connected to the pixel electrode P of the N-1th row of the third pixel group 03 is connected to the scanning signal line G located at the side of the pixel electrode P of the N-1th row of the third pixel group 03 away from the pixel electrode P of the Nth row in the vertical projection of the pixel electrode layer 120;

[0073] The transistor T connected to the pixel electrode P of the Nth row of the third pixel group 03 is connected to the scanning signal line G located at a side of the pixel electrode P of the Nth row of the third pixel group 03 away from the pixel electrode P of the N-1th row in the vertical projection of the pixel electrode layer 120;

[0074] The transistor T connected to each pixel electrode P in the same column of the third pixel group 03 is connected to the data signal line D located at the first side or the second side of the pixel electrode P in each column of the third pixel group 03 in a vertical projection of the pixel electrode layer 120 .

[0075] Among them, in this solution, the touch partition 131 can be set correspondingly at the position where no scanning signal line G is set between the pixel electrodes P in the first row and the second row, and can also be set correspondingly at the position where no scanning signal line G is set between the pixel electrodes P in the N-1th row and the Nth row.

[0076] Based on the above embodiment, optionally, the transistor T includes an NMOS transistor and a PMOS transistor.

[0077] Specifically, when the transistor T is an NMOS tube, if the scanning signal transmitted by the scanning signal line G is at a high level, the NMOS tube can output the data voltage transmitted by the data signal line D connected to the first stage thereof to the pixel electrode P connected to the second electrode of the NMOS tube. If the scanning signal transmitted by the scanning signal line G is at a low level, the NMOS tube cannot output the data voltage transmitted by the data signal line D connected to the first stage thereof to the pixel electrode P connected to the second electrode of the NMOS tube.

[0078] When the transistor T is a PMOS tube, if the scanning signal transmitted by the scanning signal line G is at a low level, the PMOS tube can output the data voltage transmitted by the data signal line D connected to the first stage thereof to the pixel electrode P connected to the second electrode of the PMOS tube. If the scanning signal transmitted by the scanning signal line G is at a high level, the PMOS tube cannot output the data voltage transmitted by the data signal line D connected to the first stage thereof to the pixel electrode P connected to the second electrode of the PMOS tube.

[0079] Based on the above embodiment, optionally, Figure 5 FIG. 1 is a schematic diagram of partitions of an embedded touch control substrate provided by an embodiment of the present invention. Figure 5 As shown, the touch control partition 131 includes partition seams; the partition seams can divide the touch control layer 130 into a plurality of touch control blocks.

[0080] The partition seams of the present solution are only disposed between the pixel electrodes P in adjacent rows and the touch partitions 131 where no corresponding scanning signal lines G are disposed are disconnected.

[0081] However, Figure 6 A schematic diagram of a partition of an embedded touch control substrate provided by the prior art, such as Figure 6 As shown, in the prior art, partition seams are not only set at the positions where the touch layer 130 needs to be partitioned, but also need to be set between each pixel in the same column (composed of three pixel electrodes P arranged adjacent to each other in the same column) for breaking seam processing.

[0082] By comparison, it can be seen that the number of partition seams included in the touch layer 130 of the present solution is greatly reduced compared with the prior art, thereby reducing the area of ​​the black matrix used to shield the partition seams, thereby improving the aperture ratio of the embedded touch substrate.

[0083] The present invention further provides a display device, which includes an embedded touch substrate provided by any embodiment of the present invention, and thus has the beneficial effects of the embedded touch substrate provided by any embodiment of the present invention, which will not be described in detail in this case.

[0084] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0085] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An embedded touch substrate, using triple-gate technology, characterized in that: include: A driving circuit layer, a pixel electrode layer, and a touch control layer located between the driving circuit layer and the pixel electrode layer; The pixel electrode layer includes a plurality of pixel electrodes arranged in an array, and the driving circuit layer includes a plurality of scanning signal lines, a plurality of data signal lines and a plurality of transistors; each of the transistors is connected to a scanning signal line, a data signal line and a pixel electrode; The touch layer includes a touch partition, a vertical projection of the touch partition on the pixel electrode layer is located between the pixel electrodes of adjacent rows, and a vertical projection of the touch partition on the drive circuit layer does not overlap with the scan signal line provided on the drive circuit layer.

2. The embedded touch substrate according to claim 1, characterized in that: The pixel electrode layer includes a first pixel group consisting of a plurality of pixel electrodes arranged in three rows and two columns; The first pixel groups in adjacent columns share three scanning signal lines, and the first pixel groups in adjacent rows share the scanning signal line whose vertical projection on the pixel electrode layer is located between the two; The first pixel groups in adjacent rows share three data signal lines, and the area between the first pixel groups in adjacent columns is provided with two data signal lines in a vertical projection area of ​​the touch layer.

3. The embedded touch substrate according to claim 2, characterized in that: The transistor connected to the pixel electrode of the first row of the first pixel group is connected to the scanning signal line whose vertical projection on the pixel electrode layer is located on the side of the pixel electrode of the first row of the first pixel group away from the pixel electrode of the second row; The transistor connected to the pixel electrode of the second row of the first pixel group and the transistor connected to the first pixel electrode of the third row are both connected to the scanning signal line whose vertical projection on the pixel electrode layer is located between the pixel electrode of the second row and the pixel electrode of the third row of the first pixel group; The transistor connected to the second pixel electrode of the third row of the first pixel group is connected to the scanning signal line whose vertical projection on the pixel electrode layer is located on the side of the pixel electrode of the third row of the first pixel group away from the pixel electrode of the second row.

4. The embedded touch substrate according to claim 2, characterized in that: The transistor connected to the first pixel electrode of the first column of the first pixel group and the transistor connected to the second pixel electrode are both connected to the data signal line whose vertical projection on the pixel electrode layer is located on the side of the pixel electrode of the first column of the first pixel group away from the pixel electrode of the second column; The transistor connected to the third pixel electrode in the first column of the first pixel group and the transistor connected to the first pixel electrode in the second column are both connected to the data signal line whose vertical projection on the pixel electrode layer is located between the pixel electrode in the first column and the pixel electrode in the second column of the first pixel group; The transistor connected to the second pixel electrode of the second column of the first pixel group and the transistor connected to the third pixel electrode are both connected to the data signal line whose vertical projection of the pixel electrode layer is located on the side of the pixel electrode of the second column of the first pixel group away from the pixel electrode of the first column.

5. The embedded touch substrate according to claim 1, characterized in that: The pixel electrode layer includes a second pixel group consisting of a plurality of adjacent rows of pixel electrodes; Two scanning signal lines are arranged in the vertical projection area of ​​the touch layer in the area between the second pixel groups in adjacent rows.

6. The embedded touch substrate according to claim 5, characterized in that: The transistor connected to the pixel electrode of the first row of the second pixel group is connected to the scanning signal line whose vertical projection on the pixel electrode layer is located on the side of the pixel electrode of the first row of the second pixel group away from the pixel electrode of the second row; The transistor connected to the pixel electrode of the second row of the second pixel group is connected to the scanning signal line whose vertical projection on the pixel electrode layer is located on the side of the pixel electrode of the second row of the second pixel group away from the pixel electrode of the first row; The transistor connected to each pixel electrode in the same column of the second pixel group is connected to the data signal line whose vertical projection on the pixel electrode layer is located on the first side or the second side of the pixel electrode in each column of the second pixel group.

7. The embedded touch substrate according to claim 1, characterized in that: The pixel electrode layer includes a third pixel group consisting of a plurality of pixel electrodes arranged in an array, the number of rows N of the third pixel group is greater than 4, and the number of rows N is an even number; The transistors connected to each pixel electrode in a row of the third pixel group are connected to the same data signal line; The transistor connected to each pixel electrode in the same column of the third pixel group is connected to the same data signal line.

8. The embedded touch substrate according to claim 7, characterized in that: The transistor connected to the pixel electrode of the first row of the third pixel group is connected to the scanning signal line whose vertical projection on the pixel electrode layer is located on the side of the pixel electrode of the first row of the third pixel group away from the pixel electrode of the second row; The transistor connected to the pixel electrode of the second row of the third pixel group is connected to the scanning signal line whose vertical projection on the pixel electrode layer is located on the side of the pixel electrode of the second row of the third pixel group away from the pixel electrode of the first row; The transistor connected to the pixel electrode of the N / 2th row of the third pixel group is connected to the scanning signal line whose vertical projection on the pixel electrode layer is located on a side of the pixel electrode of the N / 2th row of the third pixel group away from the pixel electrode of the first row; The transistor connected to the pixel electrode of the N / 2+1th row of the third pixel group is connected to the scanning signal line whose vertical projection on the pixel electrode layer is located on a side of the pixel electrode of the N / 2+1th row of the third pixel group away from the pixel electrode of the Nth row; The transistor connected to the pixel electrode of the N-1th row of the third pixel group is connected to the scanning signal line whose vertical projection on the pixel electrode layer is located on a side of the pixel electrode of the N-1th row of the third pixel group away from the pixel electrode of the Nth row; The transistor connected to the pixel electrode of the Nth row of the third pixel group is connected to the scanning signal line whose vertical projection on the pixel electrode layer is located on a side of the pixel electrode of the Nth row of the third pixel group away from the pixel electrode of the N-1th row; The transistor connected to each pixel electrode in the same column of the third pixel group is connected to the data signal line whose vertical projection on the pixel electrode layer is located on the first side or the second side of the pixel electrode in each column of the third pixel group.

9. The embedded touch substrate according to claim 1, characterized in that: The touch partition includes a partition seam; The partition seams can divide the touch layer into a plurality of touch blocks.

10. A display device, characterized in that: The invention comprises the embedded touch control substrate as claimed in any one of claims 1 to 9.

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