Cache management method and device, cluster, medium and product

Abstract

The embodiment of the invention relates to a cache management method and device, a cluster, a medium and a product. The cache management method is characterized by being applied to a storage system comprising a host and a storage device, an application program runs on the host, the host comprises a host-side cache, and the storage device comprises a device-side cache and a storage medium. The method comprises the step of respectively mapping a virtual address space of data to a host end cache, a device end cache and a storage medium based on the access frequency of the data. The method further comprises the step of obtaining a target virtual address space of target data in the data based on an I / O request of byte granularity from an application program. The method further includes accessing the target data from the host-side cache, the device-side cache, or the storage medium at byte granularity based on the target virtual address space. In this way, flexible mapping based on access frequency can be provided, and collaborative cache management and byte access between the host side and the device side can be supported.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of storage, and more specifically to a cache management method, apparatus, computing device cluster, computer-readable storage medium, and computer program product. Background Art

[0002] Solid-state drive (SSD), also known as solid-state drive, is a high-bandwidth, low-latency storage device that uses non-volatile memory flash memory (NAND-Flash). Unlike traditional mechanical hard disks (HDDs) that use rotating platters and moving read-write heads for data access, SSDs use solid-state electronic storage chips to store and read and write data. SSDs are usually composed of a control unit and a storage unit (Flash chip, DRAM chip).

[0003] With the continuous advancement of storage technology, SSD has gradually become a mainstream storage device. Compared with traditional HDD, SSD can achieve many advantages. For example, SSD can achieve faster data access speed because it adopts a design without mechanical parts and can directly read the data in the storage chip, thereby greatly shortening the startup time and file transfer time. At the same time, since SSD does not require mechanical moving parts (such as motors and moving parts), it is more resistant to vibration and impact and is not easily disturbed by magnetic fields, so it has more reliable data storage performance and lower energy consumption. These advantages make SSD more and more popular and widely used in computers, servers, mobile devices and other fields, providing users with faster, more efficient and reliable data storage solutions. However, the current SSD-based data storage solutions still have technical problems that need to be overcome. Summary of the invention

[0004] The embodiments of the present disclosure provide a cache management solution. Through the cache management solution according to the embodiments of the present disclosure, it is possible to provide a byte access granularity abstraction for collaboration between the host and the device to implement data access and cache management of different granularities.

[0005] In a first aspect of the present disclosure, a method for cache management is provided, characterized in that it is applied to a storage system including a host and a storage device, wherein an application is running on the host and includes a host-side cache, and the storage device includes a device-side cache and a storage medium. The method includes mapping the virtual address space of the data to the host-side cache, the device-side cache, and the storage medium respectively based on the access frequency of the data. The method also includes obtaining a target virtual address space of target data in the data based on a byte-granular I / O request from the application. The method also includes accessing the target data from the host-side cache, the device-side cache, or the storage medium at a byte granularity based on the target virtual address space. In this way, a flexible mapping based on access frequency can be provided, and collaborative cache management and byte access between the host and device sides can be supported.

[0006] In some embodiments, the host-side cache, the device-side cache, and the storage medium can be managed by the host. In this way, the storage device (device-side) can be exposed to the host (host-side). In other words, the host-side can perceive the device-side, so that they can operate in coordination without causing, for example, caching the same data multiple times, resulting in a waste of cache space.

[0007] In some embodiments, the method further includes dividing the data into a plurality of parts with a predetermined unit size, and determining an access frequency for each of the plurality of parts of the data. In this way, the access frequency is determined for each part of the predetermined unit size, and customized cache management is performed on each part according to the access frequency of each part.

[0008] In some embodiments, data is to be written to a storage device, and determining the access frequency may include determining a location to which each of a plurality of portions of data is to be written based on an I / O request for the data, and determining a frequency at which the determined location was accessed in a previous time step as the access frequency. In this way, even if the data is new data to be written to the storage device, the access frequency of each portion can be estimated based on the historical access frequency of the location to which each portion is to be written in the storage device.

[0009] In some embodiments, the data has been written to the storage device, and determining the access frequency may include determining the frequency at which each of the plurality of parts of the data was accessed in the last time step as the access frequency. In this way, when the data has been written to the storage device, the parts can be redistributed according to the historical access frequency of each part, so that cache management can be performed dynamically in the storage system, thereby improving the access performance of the storage system.

[0010] In some embodiments, the device-side cache may include a cache part and an exchange part, and mapping the virtual address space of the data to the host-side cache, the device-side cache, and the storage medium based on the access frequency of the data may also include: mapping the virtual address space of the part of the data whose access frequency is higher than the first frequency threshold to the host-side cache; mapping the virtual address space of the part of the data whose access frequency is lower than the first frequency threshold and higher than the second frequency threshold to the cache part in the device-side cache; and mapping the virtual address space of the part of the data whose access frequency is lower than the second frequency threshold to the storage medium via the exchange part in the device-side cache, wherein the first frequency threshold is greater than the second frequency threshold. In this way, the virtual memory is flexibly mapped according to the access frequency of each part, that is, according to the access heat of each part, its virtual address space is mapped to the host-side cache, the device-side cache, and the storage medium respectively, and such a data hot and cold separation cache technology stores data of different hot and cold degrees in different cache levels. The separation of data in the cache medium is realized.

[0011] In some embodiments, based on the target virtual address space, accessing the target data from the host-side cache, the device-side cache, or the storage medium at a byte granularity may include, in response to the target virtual address space including a first virtual address space mapped to the host-side cache, directly accessing the first data corresponding to the first virtual address space from the host-side cache at a first byte granularity. In this way, the hottest data can be accessed directly from the host-side cache at a byte granularity without accessing the storage device side via a peripheral component interconnect express (PCIe) protocol. As a result, data interaction between the host side and the device side is reduced, while PCIe traffic is reduced.

[0012] In some embodiments, based on the target virtual address space, accessing the target data from the host-side cache, the device-side cache, or the storage medium at a byte granularity may include, in response to the target virtual address space including a second virtual address space mapped to the cache portion, accessing the second data corresponding to the second virtual address space from the cache portion via the PCIe protocol at a second byte granularity. In this way, the less hot data can be accessed from the device-side cache on the storage device side via the PCIe protocol at a smaller byte granularity.

[0013] In some embodiments, based on the target virtual address space, accessing the target data from the host-side cache, the device-side cache, or the storage medium at a byte granularity may include, in response to the target virtual address space including a third virtual address space mapped to the storage medium, transferring the third data corresponding to the third virtual address space from the storage medium by utilizing the exchange portion, and accessing the third data from the storage medium via the PCIe protocol at a third byte granularity. In this way, the coldest data can be accessed from the storage medium on the storage device side via the PCIe protocol at a byte granularity, wherein the device-side cache on the storage device side does not cache the coldest data, but transfers the coldest data from the storage medium for access. Since the coldest data does not need to be accessed frequently, the interaction with the storage cutoff does not bring high latency.

[0014] In some embodiments, the second byte granularity may correspond to the granularity of the CPU L3 cache exchange. In this way, the less hot data can be accessed with a smaller byte granularity corresponding to the granularity of the CPU L3 cache exchange, avoiding the degradation of read-write amplification.

[0015] In some embodiments, the cache portion may be configured to merge multiple byte-granularity I / O requests from an application into a single page-granularity I / O request, and based on the single page-granularity I / O request, cache corresponding data from the storage medium at the page granularity. In this way, the number of reads and writes to the storage medium can be reduced, and delays caused by repeated reads and writes to the storage medium can be avoided.

[0016] In some embodiments, the host-side cache can be configured to perform cache replacement based on a least recently used strategy. The cache portion can be configured to perform cache replacement based on a write-back strategy and multi-way set associative management. In addition, the exchange portion can be configured to perform cache replacement based on a write-through strategy.

[0017] According to a second aspect of the present disclosure, a cache management device is provided, characterized in that it is applied to a storage system including a host and a storage device, wherein an application is run on the host and includes a host-side cache, and the storage device includes a device-side cache and a storage medium. The device includes a mapping module, which is configured to map the virtual address space of the data to the host-side cache, the device-side cache, and the storage medium respectively based on the access frequency of the data. The device also includes an acquisition module, which is configured to acquire the target virtual address space of the target data in the data based on the byte-granular I / O request from the application. The device also includes an access module, which is configured to access the target data from the host-side cache, the device-side cache, or the storage medium at a byte granularity based on the target virtual address space. In this way, flexible mapping based on access frequency can be provided, and collaborative cache management and byte access between the host and device ends can be supported.

[0018] According to a third aspect of the present disclosure, a computing device is provided, which includes a processor and a memory, wherein the memory stores instructions, and when the instructions are executed by the processor, the computing device executes the method according to the first aspect of the present disclosure.

[0019] According to a fourth aspect of the present disclosure, a computing device cluster is provided. The computing device cluster includes at least one computing device, each computing device including a processor and a memory. The processor of the at least one computing device is used to execute instructions stored in the memory of the at least one computing device, so that the computing device cluster executes the method described in the first aspect of the present disclosure. In some embodiments, the computing device cluster includes one computing device. In other embodiments, the computing device cluster includes multiple computing devices. In some embodiments, the computing device can be a server, such as a central server, an edge server, or a local server in a local data center. In some embodiments, the computing device can also be a terminal device such as a desktop, a laptop, or a smart phone.

[0020] According to a fifth aspect of the present disclosure, a computer-readable storage medium is provided. The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a computing device cluster, the computing device cluster executes the method according to the first aspect of the present disclosure.

[0021] According to a sixth aspect of the present disclosure, a computer program product is provided. The computer program product includes instructions, and when these instructions are executed by a computing device cluster, the computing device cluster performs the method according to the first aspect of the present disclosure. In some embodiments, the program product may include one or more software installation packages, and when it is necessary to use the method provided by the aforementioned first aspect or its possible variations, the software installation packages can be downloaded or copied and executed on the computing device.

[0022] Please note that the invention summary is provided to introduce a series of concepts in a simplified form, which will be further described in the detailed description below. The invention summary is not intended to identify key features or essential features of the present disclosure, nor is it intended to limit the scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other purposes, features and advantages of the present disclosure will become more clearly understood by describing the embodiments of the present disclosure in more detail in conjunction with the accompanying drawings, in which:

[0024] Figure 1 is a schematic diagram schematically illustrating an exemplary storage system in which the method and / or process according to an embodiment of the present disclosure may be implemented;

[0025] Figure 2 is a flowchart schematically illustrating a method for cache management according to an embodiment of the present disclosure;

[0026] Figure 3 An exemplary diagram schematically illustrates a cache management process according to an embodiment of the present disclosure;

[0027] Figure 4 A flowchart schematically illustrates a process for determining access frequency according to an embodiment of the present disclosure;

[0028] Figure 5 A flowchart schematically illustrates another determination process of access frequency according to an embodiment of the present disclosure;

[0029] Figure 6 A diagram schematically illustrates a cache management framework according to an embodiment of the present disclosure;

[0030] Figure 7 A diagram schematically illustrates granularity configuration and protocol configuration in a cache management process according to an embodiment of the present disclosure;

[0031] Figure 8 A diagram schematically illustrates a policy configuration in a cache management process according to an embodiment of the present disclosure;

[0032] Fig. 9 A schematic block diagram schematically shows a cache management device according to an embodiment of the present disclosure;

[0033] Fig.10 A schematic block diagram schematically illustrates an example device that can be used to implement an example implementation of the present disclosure;

[0034] Fig.11 A schematic block diagram schematically illustrates an example device cluster that can be used to implement an example implementation of the present disclosure; and

[0035] Fig.12 A schematic block diagram of another example device that can be used to implement an example implementation of the present disclosure is schematically shown.

[0036] Throughout the drawings, same or similar reference numbers generally refer to same or similar elements. DETAILED DESCRIPTION

[0037] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0038] In the description of the embodiments of the present disclosure, the term "including" and its variations should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects, unless explicitly indicated to be different.

[0039] As mentioned above, a solid-state drive (SSD) is a high-bandwidth, low-latency hard drive. SSD uses solid-state electronic storage chips to store and read and write data. The current mainstream SSD storage chip is a non-volatile memory flash (NAND-Flash) chip. As a high-performance storage device, SSD usually uses flash memory (Flash) as a storage medium, such as NAND-Flash. Compared with past storage technologies, SSD has faster read and write speeds and lower latency, and due to the non-volatility of SSD storage chips, it can save data in the event of a power outage.

[0040] The NAND-Flash mentioned above has the advantages of high density, low power consumption and persistence, which makes it widely used in various storage devices. SSDs using NAND-Flash media perform read and write operations in units of pages (i.e., at page granularity), and the size of each page is usually 4KB or 8KB. However, due to the erase-and-write characteristics of Flash media, performing small-granularity read and write operations on SSDs requires reading the entire page where the data is located before performing small-granularity read and write operations on it. In other words, small-granularity read and write requests are not friendly to SSDs, because such read and write operations require the consumption of additional or extra storage resources and time costs. The minimum memory access granularity of traditional SSDs is usually 512B or 4KB.

[0041] Since there are more and more small-granularity (e.g., byte-granularity) access requests to SSDs, such as application programs accessing the cache of storage devices in byte-granularity, it is necessary to provide a byte-granularity access interface for reading and writing. Some storage devices provide such an access interface. In some existing storage devices, improvements on the host side enable read and write operations in bytes, but since the existing interface of the SSD limits the granularity of read and write (e.g., 4KB), and the granularity of the central processing unit (CPU) read and write cache is usually smaller (usually exchanging data with the cache at the third-layer cache (L3 cache) granularity of 64B), such a difference will bring about a more serious read-write amplification problem.

[0042] In other existing storage devices, improvements on the storage device side enable read and write operations in bytes. However, since the host needs to go through the PCIe protocol to directly access the SSD cache, the access latency is higher and the bandwidth is limited compared to the cache on the host side, which directly affects the execution efficiency of the application. In addition, the cache on the host side and the cache on the SSD cannot work together, and the SSD device does not expose the cache management interface to the host, so the host has no perception of the device cache layer. The host side usually also has read and write caches from the storage device, so there may be multiple cache copies of the same data on the host side and the storage device side, resulting in a waste of cache space. In addition, the cache on the host side and the cache on the storage device side have different granularity, which may also cause read and write amplification problems.

[0043] In order to solve at least some of the above problems and other potential problems, a method for cache management according to an embodiment of the present disclosure is proposed, characterized in that it is applied to a storage system including a host and a storage device, the host runs an application and includes a host-side cache, and the storage device includes a device-side cache and a storage medium. The method includes mapping the virtual address space of the data to the host-side cache, the device-side cache, and the storage medium respectively based on the access frequency of the data. The method also includes obtaining the target virtual address space of the target data in the data based on the byte-granular I / O request from the application. The method also includes accessing the target data from the host-side cache, the device-side cache, or the storage medium at a byte granularity based on the target virtual address space. In this way, flexible mapping based on access frequency can be provided, and collaborative cache management and byte access between the host and device sides can be supported.

[0044] Reference below Figures 1 to 12 It should be understood that these exemplary embodiments are provided only to enable those skilled in the art to better understand and implement the embodiments of the present disclosure, and are not intended to limit the scope of the present disclosure in any way.

[0045] Figure 1 is a schematic diagram illustrating an exemplary storage system 100 in which methods and / or processes according to embodiments of the present disclosure may be implemented. Figure 1 As shown in , the storage system 100 includes a host 110 and storage devices 120, 121, 122, wherein in addition to being able to perform read and write operations in units of pages (i.e., page granularity) between the host 110 and the storage devices 120, 121, 122, it is also possible to perform read and write operations in units of bytes (i.e., byte granularity). Figure 1 The host 100 and the storage device 120 in the embodiment can perform access with a 64B granularity or, for example, a 4KB granularity. The access between the host 100 and the storage devices 121 and 122 is also the same or similar. It should be noted that Figure 1 The 64B and 4KB shown in are only examples of byte granularity and page granularity, and the embodiments of the present disclosure are not limited thereto. For example, the byte granularity may also include 32B, etc., and the page granularity may also include 8KB, etc. Other values ​​determined according to specific needs are also possible.

[0046] According to an embodiment of the present disclosure, the host 110 may be a processing device with computing capabilities, on which an application may be run, such as an application for accessing or managing the storage devices 120, 121, 122, or an application whose operation is based on data on the storage devices 120, 121, 122, etc. The host 110 may send an access request to the storage devices 120, 121, 122 to perform a read and write operation. For example, the application on the host 110 may send a request to the storage devices 120, 121, 122 for retrieving target data due to its operation needs.

[0047] By way of example and not limitation, the host 110 may include a computer, a server, a mobile device, a wearable device, a console, a player, a reader, a personal digital assistant, or a combination thereof, etc. It should be noted that the examples of the host 110 and the application described herein are only exemplified for the purpose of facilitating understanding, and the embodiments of the present disclosure are not limited to these examples, and may also include other devices and applications of different types or versions, etc.

[0048] According to an embodiment of the present disclosure, the storage devices 120, 121, 122 may be configured to store data, such as from an application running on the host 110. The storage devices 120, 121, 122 may be or include an SSD. The SSD-based storage devices 120, 121, 122 may include storage media such as NAND-Flash to provide faster read and write speeds, lower latency, and data reliability, etc. The storage devices 120, 121, 122 may write new data or cache data in response to a request from the host 100. It should be noted that the embodiments of the present disclosure do not specifically limit the version, size, etc. of the storage devices 120, 121, 122.

[0049] The host 110 and the storage devices 120, 121, 122 in the storage system 100 may be coupled together, for example, via a bus, a network, or directly connected together through a physical interface such as a USB interface, an eSATA interface, etc. The host 110 and the storage devices 120, 121, 122 may be arranged locally, or may be arranged in a distributed manner, for example, the storage device 120 may be arranged locally and the storage devices 121, 122 may be arranged in the cloud, such as Figure 1 As shown in . When the host 110 and the storage storage devices 120, 121, 122 are arranged locally, the data transmission distance is short and the delay is therefore low. This is very beneficial for applications that require fast response (such as real audio and video streaming, etc.). In addition, since the data is mainly processed and stored locally, user privacy and sensitive data can be better protected.

[0050] When the host 110 and the storage devices 120, 121, 122 are distributedly arranged, a distributed storage system 100 is formed. Such a cloud arrangement makes it easy to add more hosts or storage devices, and the load can be distributed to all of these hosts or storage devices, thereby improving the overall performance and throughput of the storage system 100. Further, the host 110 and the storage devices 120, 121, 122 can all be arranged in one region, or they can be arranged in multiple regions respectively. The arrangement in multiple regions allows the other regions to continue to operate even if a device in one region fails, thereby improving the availability and stability of the storage system 100.

[0051] It should be understood that for ease of explanation and illustration purposes, Figure 1Only one host (i.e., host 110) and three storage devices (i.e., storage devices 120, 121, 122) are shown in the figure. However, this is only exemplary, and there may be other different numbers of hosts and storage devices, which can be customized as described above according to specific usage scenarios and needs, and the same is true in the following. Figure 1 Describes an example environment in which the methods and / or processes according to embodiments of the present disclosure may be implemented. Figure 2 A method 200 for cache management according to an embodiment of the present disclosure is described.

[0052] Figure 2 FIG. 2 is a flow chart schematically illustrating a method 200 for cache management according to an embodiment of the present disclosure. Figure 2 The described method 200 can provide flexible mapping based on access frequency and support coordinated cache management and byte access between the host side and the device side. In the following, for the purpose of ease of illustration and explanation, a host (i.e., host 110) and a storage device (i.e., storage device 120) are described, and it should be understood that multiple hosts and multiple storage devices are also possible, and the same Figure 2 The situation is the same or similar to that described in .

[0053] The cache management method 200 according to the embodiment of the present disclosure is applied to a storage system 100 including a host 110 and a storage device 120. The host 110 runs an application and includes a host-side cache, and the storage device 120 includes a device-side cache and a storage medium. Under such a storage architecture, both the cache on the host 110 side and the cache on the storage device 120 side will be enabled, and the joint use of such a host-side cache and a device-side cache will reduce the number of accesses to the storage medium, thereby improving the overall I / O performance.

[0054] At 210, the virtual address space of the data is mapped to the host cache, the device cache, and the storage medium based on the access frequency of the data. Through this operation, the virtual memory address of the data can be flexibly mapped to different locations on the host 110 side and the storage device 120 side, so that the data can be distinguished in the system based on the access popularity of the data. In this way, for frequently accessed data, fast reading and writing can be achieved through the cache, and for infrequently accessed data, it will be mapped to the storage medium to save cache space.

[0055] At 220, based on the byte-granularity I / O request from the application, the target virtual address space of the target data in the data is obtained. When the application is running on the host 110, it will generate I / O requests for reading and writing the target data, wherein these I / O requests indicate the target virtual address space of the target data, and these I / O requests will then be sent to the storage device 120. After receiving these I / O requests, the storage device 120 will parse these I / O requests to determine the target virtual address space of the target data, thereby completing the addressing. Here, the byte-granularity I / O request indicates that the read and write operation is in bytes, or the target data to be accessed is in byte order.

[0056] At 230, based on the target virtual address space, the target data is accessed from the host cache, the device cache, or the storage medium at byte granularity. By introducing the joint use of the host cache and the device cache, not only can the byte granularity access between the host 110 side and the storage device 120 side be achieved, but also the data reading and writing speed and reliability can be improved, and unnecessary data transmission and storage medium access times can be reduced.

[0057] According to the cache management method 200 of the embodiment of the present disclosure, in addition to the page-granularity access interface, a byte-granularity access interface can also be provided between the source unit 110 and the target unit 120. In this way, the memory access interface in the system is enriched, for example, it is beneficial to the writing of application programs. At the same time, since byte-granularity access between the source unit 110 and the target unit 120 is implemented, the difference in granularity of exchange with the CPU L3 cache is guaranteed, avoiding the problem of read-write amplification. In addition, data of different hotness and coldness are grouped and cached, that is, a customized cache management strategy is used, so that the problem of frequent cache replacement is solved. Next, we will combine Figure 3 Cache management according to an embodiment of the present disclosure is described in further detail.

[0058] Figure 3 FIG. 3 schematically illustrates an exemplary diagram of a cache management process 300 according to an embodiment of the present disclosure. Figure 3As shown in , the host 110 side includes an application 310 running thereon, from which an I / O request for accessing target data, such as an I / O request with byte granularity, can be sent. An I / O request with byte granularity means that a read or write operation is performed with one or more bytes, or the size of the target data to be accessed is a number of bytes. According to an embodiment of the present disclosure, in addition to data exchange at the page level (e.g., 4K granularity), data exchange at the byte level (e.g., 64B granularity) can also be performed between the host 110 and the storage device 120. This is because a byte-granular access interface is provided through the joint interaction between the two-sided caches, which is very important for simplifying storage management and performance optimization of applications.

[0059] According to an embodiment of the present disclosure, the host 110 side includes a host-side cache 320, which can be part of the host 110 side memory. By way of example and not limitation, the host 110 side memory may include a dynamic random access memory (DRAM), which is a semiconductor memory that is typically used as a main memory to store running programs and data. DRAM is characterized by fast access speed, large capacity, etc., and is therefore widely used. It should be noted that DRAM is only an exemplary implementation of the host 110 side memory, and the embodiments of the present disclosure may also include other different implementations or improved implementations.

[0060] The host-side cache 320 can be used to cache frequently accessed or frequently used data so that it can be accessed faster by the host 110. This cache strategy can improve the read and write speed of data, thereby improving the performance of the entire storage system 100. The size of the host-side cache 320 can be configured according to specific application scenarios and device resources. In some cases, a larger cache can improve the data read and write speed of the system, but it also requires more memory resources. A smaller cache can reduce memory resource usage, but it causes an increase in memory access latency, thereby affecting the response speed and throughput of the system. Therefore, in order to strike a balance between the two, the size of the host-side cache 320 can be selected depending on the specific purpose and requirements, as well as the overall performance and resource limitations of the host 110.

[0061] like Figure 3As shown in , the storage device 120 includes a device-side cache 330 and a storage medium 340. By way of example and not limitation, the storage device 120 may be a storage device based on an SSD, and may generally include a DRAM chip and a Flash chip. The device-side cache 330 may be part of the memory on the side of the storage device 120. By way of example and not limitation, the memory on the side of the storage device 120 may include a dynamic random access memory (DRAM). Similarly, DRAM is only an exemplary implementation of the memory on the side of the storage device 120, and the embodiments of the present disclosure may also include other different implementations or improved implementations. The device-side cache 330 may be used to cache data that is accessed from time to time or sometimes used so that it can be accessed faster by the host 110. When setting the size of the device-side cache 330, it is also necessary to consider such as the purpose, the resource configuration of the storage device (such as the overall performance and resource limitations of the storage device 120), etc. In addition, the access mode of the data, the update strategy of the cache, etc. will also affect the size configuration of the device-side cache 330.

[0062] The storage medium 340 may store data that is infrequently accessed or seldom used. Data with low access frequency or popularity may not be cached, whether on the host 110 side or the storage device 120 side, but may be stored in the storage medium 340, and transferred via a cache (e.g., a device-side cache 330) when needed. The advantage of this approach is that it can avoid the situation where excessive memory resources are occupied due to caching these data. In an illustrative and non-restrictive manner, the storage medium 340 may include a storage medium based on a Flash medium, and the embodiments of the present disclosure may of course also include other different implementations or improved implementations. It should be noted that the size of the storage medium 340 may also be customized based on various factors, and the present disclosure does not limit this.

[0063] Because the application's access to the memory is byte-granular, the dual-side cache joint mechanism of the host-side cache 320 and the device-side cache 330 enables fine-grained data exchange between the host 110 and the storage device 120, solving the problem of mismatch between the medium (e.g., Flash medium) and the byte memory access granularity. At the same time, the transmission traffic of such smaller-grained read and write requests on the data transmission link is reduced, and a richer memory access interface is provided for the system. In addition, dynamic mapping based on access frequency or heat improves the complex cache management on the host 110 side and the storage device 120 side, providing a more efficient and flexible customized storage solution.

[0064] According to an embodiment of the present disclosure, the host-side cache 320, the device-side cache 330 and the storage medium 340 can be managed by the host 110. In this way, the storage device 120 (device side) can be exposed to the host 110 (host side). In other words, the host side can perceive the device side so that they can operate in coordination without causing, for example, caching the same data multiple times, resulting in a waste of cache space. As described above, the virtual address space or virtual memory address of the data can be mapped to different locations in the system, i.e., the host-side cache 320, the device-side cache 330 and the storage medium 340, depending on its popularity. The management of these parts by the host 110 can ensure that there is no duplication between the host-side and device-side caches.

[0065] As described above, the popularity of the data (i.e., the frequency of being accessed) determines to which of the host-side cache 320, the device-side cache 330, and the storage medium 340 the virtual address space of the data is mapped. In order to facilitate the determination of the access frequency of the data, according to an embodiment of the present disclosure, the data can be divided into multiple parts with a predetermined unit size, and the access frequency can be determined for each of the multiple parts of the data. In this way, the access frequency is determined for each part of the predetermined unit size, and then customized cache management is performed on each part according to the access frequency of each part. This flexible management method can better meet the access requirements of different parts, thereby improving the overall performance of the system. Next, we will combine Figure 4 and Figure 5 The access frequency determination process according to the embodiment of the present disclosure is further described in detail.

[0066] Figure 4 A flow chart of a determination process 400 of access frequency according to an embodiment of the present disclosure is schematically illustrated. As described above, data can be divided into a plurality of parts having a predetermined unit size, and the access frequency can be determined for each such part. Such a division enables more accurate results to be obtained by detecting and analyzing the access frequency of each part. The embodiment of the present disclosure will consider at least two situations, one is that the data is about to be written to the storage device 110, and the other is that the data has been written to the storage device 110. It should be noted that, in addition to these two situations, other situations based on access history are also possible, and the determination process may be the same or similar to that described below.

[0067] Figure 4 Schematically shows the situation where data is about to be written into the storage device 110. Figure 4As shown in , at 410, based on the I / O request for data, the location where each of the multiple parts of the data is to be written can be determined. The I / O request for data can indicate the location where the data is to be written in the storage system 110 (hereinafter, also referred to as the target location), that is, it contains positioning information related to the location or identifier of the data. In addition, the I / O request can also indicate the read and write mode, size and type of the data, the start and end time of data transmission, consistency or backup requirements, etc.

[0068] At 420, the frequency with which the determined location was accessed in the last time step is determined. These parts of the data have not yet been written to the storage device 110. For example, through statistical methods such as sampling of the host-side operating system, the frequency with which these parts were accessed in the target location in the storage system 110 in the past (i.e., the historical access frequency of the target location) is determined and estimated as the access frequency of each of these parts. The last time step at 420 may include the previous hour, yesterday, last week, and other past times, and may be predetermined according to specific needs, and the embodiments of the present disclosure are not limited to this.

[0069] At 430, the determined frequency is used as the estimated access frequency of each part. Figure 4 The described access frequency determination process 400 can estimate the access frequency of each part according to the historical access popularity of the target location where each part is to be written, even if the data is new data to be written to the storage device 110, so that the data can be subdivided based on historical access conditions.

[0070] Figure 5 A flow chart schematically illustrates another process 500 for determining access frequency according to an embodiment of the present disclosure. Figure 5 The schematic diagram shows the situation where data already exists in the storage device 110. Figure 5 As shown in , at 510, the frequency at which each of the multiple parts of the data was accessed in the previous time step (i.e., the historical access frequency) is determined. For example, the frequency at which these parts were accessed in the past time period or time interval is determined by a statistical method such as sampling of the host-side operating system. Similarly, the previous time step at 510 may include the previous hour, yesterday, last week, and other past times, and may be predetermined according to specific needs, and the embodiments of the present disclosure are not limited to this.

[0071] At 520, the determined frequency is used as the access frequency of each part. Figure 5The access frequency determination process 500 described above can redistribute the data according to the historical access frequency of each part in the storage device 110, so that the cache management can be dynamically performed in the storage system 110, thereby improving the access performance of the storage system. For example, when the cache is full, we can decide which part should be replaced from the cache according to the access popularity of each part. If the access popularity of a part is very high, it should be kept in the cache, and if the access popularity of a part is very low, it should be replaced from the cache. Figure 5 The cache management framework according to the embodiments of the present disclosure is described in further detail.

[0072] Figure 6 Schematically illustrates a diagram of a cache management framework 600 according to an embodiment of the present disclosure. Figure 6 As shown in FIG. 6 , the cache management framework 600 includes a virtual memory space 621 in which a virtual address space or a virtual memory address of data can be allocated based on its access frequency (e.g., by combining Figure 4 and Figure 5 The access frequency determination process described in the above description is mapped to different cache layers or storage layers, i.e., Figure 6 In the segmented memory map 621. In addition, the device-side cache 330 may include a cache part 640 and a swap part 650 to further subdivide its functions to meet different cache requirements.

[0073] According to an embodiment of the present disclosure, the virtual address space of a portion of data whose access frequency is higher than a first frequency threshold can be mapped to a host-side cache 320, the virtual address space of a portion of data whose access frequency is lower than the first frequency threshold and higher than a second frequency threshold can be mapped to a cache portion 640 in a device-side cache 330, and the virtual address space of a portion of data whose access frequency is lower than the second frequency threshold can be mapped to a storage medium 340 via a swap portion 650 in the device-side cache 330, wherein the first frequency threshold is greater than the second frequency threshold.

[0074] The first frequency threshold may refer to high access frequency and heat, and being higher than the first frequency threshold may indicate that this part of the data is frequently accessed or frequently used. Cache frequently accessed or frequently used data to the host-side cache 320, so that the host 110 can access these data faster, improve the read and write speed of hot data, and thus improve the performance of the entire storage system 100. The host 110 can directly access the host-side cache 320, and the access from the host 100 to the host-side cache 320 supports byte-granular data exchange. Compared with the storage device 120 side, such a caching strategy can achieve faster speeds and maintain relatively low data transmission traffic. In other words, it can reduce the number of accesses to the storage device 120 side, that is, reduce the delay caused by the PCIe protocol, Flash media reading and writing, etc. when accessing memory, and at the same time reduce the load of the storage device 120 and extend its service life.

[0075] The second frequency threshold may refer to low access frequency and heat, and being lower than the first frequency threshold and higher than the second frequency threshold may indicate that this portion of data is accessed from time to time or is sometimes used. The data that is accessed from time to time or is sometimes used is cached in the cache portion 640 in the device-side cache 330, so that the host 110 can access these sub-hot data at a faster speed through the PCIe protocol, thereby improving access performance, wherein the host 110 accesses the cache portion 640 at a byte granularity. At the same time, such a cache strategy can also save the memory resources of the host 110. Because the memory resources of the host 110 are limited, if all data is stored in the host-side cache 320, it will result in a waste of memory resources.

[0076] The frequency lower than the second frequency threshold may indicate that this part of data is infrequently accessed or rarely used. The infrequently accessed or rarely used data (i.e., cold data) is stored in the storage medium 340 without being cached, and can be transferred via the exchange part 650 in the device-side cache 330 only when needed to complete the reading, wherein the transfer through the exchange part 650 can provide a fine-grained access interface with byte granularity to the host 110 side. Such a cache strategy can save precious cache resources and reduce the cost of cache expiration and replacement, while being able to solve problems caused by cache overflow or data loss, thereby effectively optimizing the performance and efficiency of the storage system.

[0077] By performing cache management according to the cache management framework 600 of the embodiment of the present disclosure, it is possible to avoid the need to repeatedly interact with the storage device 120 for data when the hottest data is needed, thereby significantly reducing PCIe traffic. Under the cache management framework 600, the second hot data is cached in the cache part 640 of the memory on the storage device side 120, avoiding the delay caused by repeated reading and writing of the storage medium 340. At the same time, the cached second hot data can support smaller granularity access, ensuring the consistency of the granularity of the CPUL3 cache exchange, avoiding the occurrence of read-write amplification problems. In addition, cold data is transferred through the exchange part 650 of the memory on the storage device 120 side as an indirect layer, providing a byte-granularity access interface, and since frequent access is not required, interaction with the storage medium 340 will not cause high latency. Overall, this mechanism provides a byte-granularity interface for SSD data access while also ensuring high efficiency.

[0078] Furthermore, this mechanism provides three different cache management modes, which can effectively provide different memory access strategies for data of different hot and cold granularities, thereby improving the flexibility of cache management and SSD data access. Combined with statistical methods such as sampling of the host operating system (such as memory access and sampling technologies in the Linux kernel, for example, for determining the access frequency, etc.), data of different hot and cold degrees are stored in different cache levels, thereby realizing the separation of data in the cache medium, wherein the data corresponding to different cache levels do not intersect with each other. Grouping and caching data of different hot and cold degrees effectively solves problems such as data read and write amplification and frequent cache replacement. It should be understood that the embodiments of the present disclosure divide data into three types based on the access frequency of the data, namely, hot, sub-hot, and cold, but more types can be divided more finely as needed, and other factors other than the access frequency can also be considered when dividing, and the embodiments of the present disclosure do not limit this.

[0079] Figure 7 Schematically illustrates a diagram of granularity and protocol configuration 700 in a cache management process according to an embodiment of the present disclosure. For ease of illustration and explanation, Figure 7 exemplarily shows that the virtual address space or virtual memory address of data is divided into three segments, namely, segment 1 701, segment 2 702, and segment 3 703. Using the virtual memory system, the address space of the data to be operated can be mapped to the host cache 320, the device cache 330 (cache part 640) and the storage medium 340 respectively, and the data corresponding to these parts are complementary and intersecting. It should be understood that this is only exemplary and not restrictive, and more or fewer segments are also possible.

[0080] According to an embodiment of the present disclosure, in response to the target virtual address space of the data including the first virtual address space mapped to the host cache 320, the first data corresponding to the first virtual address space can be directly accessed from the host cache 320 at a first byte granularity. The virtual address space of one or more portions of the data is mapped to the host cache 320, for example, Figure 7 The mapping between segment 3 703 and the host-side cache 320 shown in , which may mean that the data of one or more parts is frequently accessed or frequently used data, and its hotness and coldness are high. The data of one or more parts can be cached in the host-side cache 320, so that the host 110 can access the data faster. As shown at 710, access to hot data in the host-side cache 320 can be at byte granularity. For access that falls into the host-side cache 320, it is the same as ordinary direct memory access. From the application level, it is at byte granularity. If data needs to be evicted, it is evicted at page granularity. In addition, as shown at 710, the access to hot data in the host-side cache 320 is the same as ordinary direct memory access. Figure 7 As shown at 740 in FIG. 1 , data exchange between the host-side cache 630 and the storage medium 340 in the storage device may be via the PCIe protocol and may be page-granular.

[0081] According to an embodiment of the present disclosure, in response to the target virtual address space of the data including the second virtual address space mapped to the cache portion 640, the second data corresponding to the second virtual address space can be accessed from the cache portion 640 via the PCIe protocol at a second byte granularity. The virtual address space of one or more portions of the data is mapped to the cache portion 640, for example, Figure 7 The mapping between segment 2 702 and cache portion 640 shown in FIG. 1 may mean that the data in the one or more portions is accessed or used from time to time and has a high degree of coldness and heat. The one or more portions of data may be cached in cache portion 640 in the storage device, so that the host 110 can access the less hot data at a faster speed through the PCIe protocol.

[0082] In some embodiments, the second byte granularity of accessing the cache portion 640 may correspond to or be consistent with the granularity of the CPU L3 cache interaction, such as an access granularity of 64B. Since the CPU L3 cache line size is 64B, this granularity does not cause read-write amplification problems when exchanging data with the SSD. As shown at 720, the access to the cache portion 640 may be at a byte granularity, more specifically, at a granularity corresponding to the granularity of the CPU L3 cache interaction, such as 64B.

[0083] In addition, in some embodiments, the cache portion 640 may be configured to merge multiple byte-granularity I / O requests from the application 310 into a single page-granularity I / O request, and based on the single page-granularity I / O request, cache corresponding data from the storage medium 340 at the page granularity. In this way, the number of reads and writes to the storage medium 340 can be reduced, and delays caused by repeated reads and writes to the storage medium 340 can be avoided. Figure 7 As shown at 760, data exchange between the cache portion 640 and the storage medium 340 may be at a page granularity.

[0084] According to an embodiment of the present disclosure, in response to the target virtual address space of the data including the third virtual address space mapped to the storage medium 340, the third data corresponding to the third virtual address space can be transferred from the storage medium 340 via the PCIe protocol at a third byte granularity by using the exchange part 650. The virtual address space of one or more parts of the data is mapped to the storage medium instead of the cache on both sides, for example Figure 7 The mapping between segment 1 701 and storage medium 340 shown in FIG. 1 may mean that the data of the one or more portions are infrequently accessed or rarely used data, and the hotness and coldness of the data of the one or more portions may be stored in the storage medium 340 in the storage device 120 without being cached on both sides, and may be transferred via the exchange part 650 to complete the reading only when necessary. In addition, as shown in FIG. Figure 7 As shown at 750 in FIG. 1 , the transfer between the exchange portion and the storage medium can be page-granular.

[0085] In an illustrative but not restrictive manner, when the system starts, there is no distinction between hot and cold data, and all data is exchanged with the SSD at a page granularity in a manner where only the host-side cache 320 is used up. After the application 310 runs for a period of time, the host-side cache 320 is exhausted, and the operating system also records the corresponding page access frequency. At this time, the relatively cold data mapping is modified to the cache part 640 of the SSD, and this part of the data will also be evicted from the host-side cache 320.

[0086] Assuming that the size of the host-side cache 630 used to cache SSD data on the host 110 side is x, and the size of the cache part 640 of the SSD is y, the data of size x with the highest access frequency is cached in the host-side cache 630, and the data of size y with the second highest access frequency is cached in the cache part 640 of the SSD. The remaining memory of the SSD can be used as the swap part 650 to provide a byte-granularity memory access interface to the host 110.

[0087] When the physical memory corresponding to the virtual memory address of the data is located in the host cache 630, the memory access may be no different from the ordinary memory access, and the host 110 uses a combination of page counting and the least recently used LRU strategy to perform cache replacement. When the physical memory corresponding to the virtual memory address of the data is located in the cache part 640 of the SSD, the memory access can be swapped into the CPU cache at a 64B granularity, and is only flushed when the cache part 640 of the SSD is evicted. When the memory access misses the above two memory segments, the SSD internally pulls the data to the swap part 650, and then completes the data reading and writing.

[0088] Figure 8 Schematically illustrates a diagram of a policy configuration 800 in a cache management process according to an embodiment of the present disclosure. For ease of illustration and explanation, Figure 8 , three segments are shown as cold data, sub-hot data and hot data. It should be understood that this is only exemplary and not restrictive, and more or less number or type of segments are also possible, and the embodiments of the present disclosure are not limited to this.

[0089] like Figure 8 As shown in FIG. 8 , at 810, a least recently used (LRU) strategy can be configured between hot data and the host cache 320. The LRU strategy is a cache elimination strategy that determines the validity of data based on the time of recent use, and considers that recently used data is useful, while data that has not been used for a long time is useless. When the cache space is full and data needs to be eliminated, the LRU strategy selects the data that has not been accessed for the longest time for elimination.

[0090] At 820, a write-back strategy can be configured between the second hot data and the cache portion 640, and multi-way group associative management can be performed. The write-back strategy is a cache replacement strategy that replaces infrequently accessed data in the cache instead of immediately writing it to the disk (i.e., storage medium). When the cache is full, some of the data will be selected for replacement to make room for storing new data. The write-back strategy usually selects which data to replace based on a certain algorithm, such as a FIFO algorithm. In addition, multi-way group associative management is a cache management strategy used to improve the performance and efficiency of the storage system. In this strategy, multiple cache blocks are organized into different groups, and each group has its own direct mapping table.

[0091] At 830, a write-through strategy can be configured between the cold data and the exchange portion 650. When the data in the cache is modified, the write-through strategy will write the data to the cache and the disk at the same time. In this way, even if the cache fails or crashes, the data can still be accessed in the disk to ensure that the data is not lost. In addition, the data access between the storage medium 340 can be configured with an in-disk processing address mapping, as shown at 840.

[0092] According to the cache management solution of the embodiment of the present disclosure, dynamic customized memory access strategies can be provided for different data. Such flexible mapping and collaborative cache management can enrich the system's memory access interface and realize byte-granular access, thereby simplifying data operations of applications, for example. In addition, such a storage management solution can reduce the transmission pressure within the system and provide a more efficient and flexible customized storage solution.

[0093] Fig. 9 The apparatus 900 for cache management according to some embodiments of the present disclosure is shown. The apparatus 900 for cache management according to an embodiment of the present disclosure is applied to a storage system including a host and a storage device, wherein an application is running on the host and includes a host-side cache, and the storage device includes a device-side cache and a storage medium. Fig. 9 As shown in , the cache management device 900 includes a mapping module 910, an acquisition module 920 and an access module 930.

[0094] According to an embodiment of the present disclosure, the mapping module 910 is configured to map the virtual address space of the data to the host-side cache, the device-side cache, and the storage medium respectively based on the access frequency of the data. The acquisition module 920 is configured to acquire the target virtual address space of the target data in the data based on the byte-granular input / output I / O request from the application. Moreover, the access module 930 is configured to access the target data from the host-side cache, the device-side cache, or the storage medium at the byte granularity based on the target virtual address space. It should be understood that for the purpose of ease of illustration and ease of explanation, Fig. 9 The device 900 is shown to include only a mapping module 910, an acquisition module 920 and an access module 930, but the device 900 may also include other different modules, such as a partitioning module, a determination module, a merging module and a cache module, etc. These modules will be described in further detail below.

[0095] In some embodiments, the host-side cache, the device-side cache, and the storage medium can be managed by the host. In this way, the storage device (device-side) can be exposed to the host (host-side). In other words, the host-side can perceive the device-side, so that they can operate in coordination without causing, for example, caching the same data multiple times, resulting in a waste of cache space.

[0096] In some embodiments, the cache management device 900 may further include a partitioning module and a determination module. The partitioning module is configured to partition the data into a plurality of parts with a predetermined unit size, and the determination module is configured to determine the access frequency for each of the plurality of parts of the data. In this way, the access frequency is determined for each part of the predetermined unit size, and customized cache management is then performed on each part according to the access frequency of each part.

[0097] In some embodiments, data is to be written to a storage device, and the determination module may be configured to determine the location to which each of the plurality of portions of data is to be written based on an I / O request for the data, and determine the frequency at which the determined location was accessed in the previous time step as the access frequency. In this way, even if the data is new data to be written to the storage device, the access frequency of each portion can be estimated based on the historical access frequency of the location to which each portion is to be written in the storage device.

[0098] In some embodiments, the data has been written to the storage device, and the determination module can be configured to determine the frequency at which each of the multiple parts of the data was accessed in the previous time step as the access frequency. In this way, when the data has been written to the storage device, the parts can be redistributed according to the historical access frequency of each part, so that cache management can be dynamically performed in the storage system, thereby improving the access performance of the storage system.

[0099] In some embodiments, the device-side cache may include a cache part and an exchange part, and the mapping module 910 may be configured to: map the virtual address space of the part of the data whose access frequency is higher than the first frequency threshold to the host-side cache; map the virtual address space of the part of the data whose access frequency is lower than the first frequency threshold and higher than the second frequency threshold to the cache part in the device-side cache; and map the virtual address space of the part of the data whose access frequency is lower than the second frequency threshold to the storage medium via the exchange part in the device-side cache, wherein the first frequency threshold is greater than the second frequency threshold. In this way, the virtual memory is flexibly mapped according to the frequency of access of each part, that is, according to the access heat of each part, its virtual address space is mapped to the host-side cache, the device-side cache, and the storage medium respectively. Such data hot and cold separation cache technology stores data of different hot and cold degrees in different cache levels. The separation of data in the cache medium is realized.

[0100] In some embodiments, the access module 930 can be configured to access the first data corresponding to the first virtual address space directly from the host-side cache at a first byte granularity in response to the target virtual address space including the first virtual address space mapped to the host-side cache. In this way, the hottest data can be accessed directly from the host-side cache at a byte granularity without accessing the storage device side via the PCIe protocol. As a result, the data interaction between the host side and the device side is reduced, while the PCIe traffic is reduced.

[0101] In some embodiments, the access module 930 may be configured to access the second data corresponding to the second virtual address space from the cache portion via the PCIe protocol at a second byte granularity in response to the target virtual address space including the second virtual address space mapped to the cache portion. In this way, the less hot data can be accessed from the device-side cache on the storage device side via the PCIe protocol at a smaller byte granularity.

[0102] In some embodiments, the access module 930 can be configured to access the third data from the storage medium via the PCIe protocol at a third byte granularity by transferring the third data corresponding to the third virtual address space from the storage medium using the exchange part in response to the target virtual address space including the third virtual address space mapped to the storage medium. In this way, the coldest data can be accessed from the storage medium on the storage device side via the PCIe protocol at a byte granularity, wherein the device-side cache on the storage device side does not cache the coldest data, but transfers the coldest data from the storage medium for access. Since the coldest data does not need to be accessed frequently, the interaction with the storage cutoff does not bring high latency.

[0103] In some embodiments, the second byte granularity may correspond to the granularity of the CPU L3 cache exchange. In this way, the less hot data can be accessed with a smaller byte granularity corresponding to the granularity of the CPU L3 cache exchange, avoiding the degradation of read-write amplification.

[0104] In some embodiments, the cache management device 900 may further include a merging module and a caching module. The merging module is configured to merge multiple byte-granularity I / O requests from the application into a single page-granularity I / O request, and the caching module is configured to cache corresponding data from the storage medium at a page granularity based on the single page-granularity I / O request. In this way, the number of read and write times to the storage medium can be reduced, avoiding delays caused by repeated read and write to the storage medium.

[0105] In some embodiments, the host-side cache can be configured to perform cache replacement based on a least recently used strategy. The cache portion can be configured to perform cache replacement based on a write-back strategy and multi-way set associative management. In addition, the exchange portion can be configured to perform cache replacement based on a write-through strategy.

[0106] As an example of a software functional unit, the mapping module 910 may include code running on a computing instance. Among them, the computing instance may include at least one of a physical host (computing device), a virtual machine, and a container. Further, the above-mentioned computing instance may be one or more. For example, the mapping module 910 may include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the code can be distributed in the same region (region) or in different regions. Furthermore, the multiple hosts / virtual machines / containers used to run the code can be distributed in the same availability zone (AZ) or in different AZs, each AZ including a data center or multiple data centers with close geographical locations. Among them, usually a region can include multiple AZs.

[0107] Similarly, multiple hosts / virtual machines / containers used to run the code can be distributed in the same virtual private cloud (VPC) or in multiple VPCs. Usually, a VPC is set up in a region. For cross-region communication between two VPCs in the same region and between VPCs in different regions, a communication gateway needs to be set up in each VPC to achieve interconnection between VPCs through the communication gateway.

[0108] As an example of a hardware functional unit, the mapping module 910 may include at least one computing device, such as a server, etc. Alternatively, the mapping module 910 may also be a device implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD may be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0109] The multiple computing devices included in the mapping module 910 can be distributed in the same region or in different regions. The multiple computing devices included in the mapping module 910 can be distributed in the same AZ or in different AZs. Similarly, the multiple computing devices included in the mapping module 910 can be distributed in the same VPC or in multiple VPCs. The multiple computing devices can be any combination of computing devices such as servers, ASICs, PLDs, CPLDs, FPGAs, and GALs.

[0110] It should be noted that, in other embodiments, the mapping module 910 can be used to execute any step in the method for cache management according to the embodiment of the present disclosure, the acquisition module 920 can be used to execute any step in the method for cache management according to the embodiment of the present disclosure, and the access module 930 can be used to execute any step in the method for cache management according to the embodiment of the present disclosure. In addition, the above-mentioned division module, determination module, merging module and cache module can also be used to execute any step in the method for cache management according to the embodiment of the present disclosure.

[0111] The steps that the mapping module 910, the acquisition module 920, the access module 930, the partitioning module, the determination module, the merging module and the cache module are responsible for implementing can be specified as needed. The mapping module 910, the acquisition module 920, the access module 930, the partitioning module, the determination module, the merging module and the cache module respectively implement different steps in the cache management method according to the embodiment of the present disclosure to realize all the functions of the cache management device 900.

[0112] The present disclosure also provides a computing device 1000 . Fig.10 1 shows a schematic block diagram of an example computing device 1000 that can be used to implement an example implementation of the present disclosure. Fig.10 As shown in , the computing device 1000 includes: a bus 1002, a processor 1004, a memory 1006, and a communication interface 1108. The processor 1004, the memory 1006, and the communication interface 1108 communicate through the bus 1002. The computing device 1000 can be a server or a terminal device. It should be understood that the present disclosure does not limit the number of processors and memories in the computing device 1000.

[0113] The bus 1002 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.10 The bus 1002 may include a path for transmitting information between various components of the computing device 1000 (eg, the memory 1006, the processor 1004, and the communication interface 1008).

[0114] The processor 1004 may include any one or more processors such as a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0115] The memory 1006 may include a volatile memory, such as a random access memory (RAM). The processor 1004 may also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid state drive (SSD).

[0116] The memory 1006 stores executable program codes, and the processor 1004 executes the executable program codes to respectively implement the functions of the aforementioned mapping module 910, acquisition module 920, access module 930 and other modules, thereby implementing the cache management method according to the embodiment of the present disclosure. That is, the memory 1006 stores instructions for executing the cache management method according to the embodiment of the present disclosure.

[0117] Alternatively, the memory 1006 stores executable codes, and the processor 1004 executes the executable codes to respectively implement the functions of the aforementioned cache management apparatus 900, thereby implementing the cache management method according to the embodiment of the present disclosure. That is, the memory 1006 stores instructions for executing the cache management method according to the embodiment of the present disclosure.

[0118] The communication interface 1008 uses a transceiver module such as, but not limited to, a network interface card or a transceiver to implement communication between the computing device 1000 and other devices or a communication network.

[0119] The disclosed embodiment also provides a computing device cluster. Fig.11 A schematic block diagram of an example computing device cluster 1100 that can be used to implement an exemplary implementation of the present disclosure is shown. The computing device cluster 1100 includes at least one computing device. The computing device can be a server, such as a central server, an edge server, or a local server in a local data center. In some embodiments, the computing device can also be a terminal device such as a desktop computer, a laptop computer, or a smart phone.

[0120] like Fig.11 As shown in , the computing device cluster 1100 includes at least one computing device 1000. The memory 1006 in one or more computing devices 1000 in the computing device cluster 1100 may store the same instructions for executing the cache management method according to the embodiment of the present disclosure.

[0121] In some possible implementations, the memory 1006 of one or more computing devices 1000 in the computing device cluster 1100 may also respectively store partial instructions for executing the cache management method according to the embodiment of the present disclosure. In other words, the combination of one or more computing devices 1000 may jointly execute the instructions for executing the cache management method according to the embodiment of the present disclosure.

[0122] It should be noted that the memory 1006 in different computing devices 1000 in the computing device cluster 1100 may store different instructions, which are respectively used to execute part of the functions of the cache management apparatus 900. That is, the instructions stored in the memory 1006 in different computing devices 1000 may implement the functions of one or more modules of the mapping module 910, the acquisition module 920, the access module 930, and the like.

[0123] In some possible implementations, one or more computing devices in the computing device cluster 1100 may be connected via a network, which may be a wide area network or a local area network. Fig.12A possible implementation is shown. Fig.12 As shown, two computing devices 1000A and 1000B are connected via a network. Specifically, the network is connected via a communication interface in each computing device. In this type of possible implementation, the memory 1006 in the computing device 1000A stores instructions for executing the functions of the mapping module 910. At the same time, the memory 1006 in the computing device 1000B stores instructions for executing the functions of the acquisition module 920 and the access module 930.

[0124] Fig.12 The connection method between the computing device cluster 1100 shown in the figure may be considered to be that the cache management method provided by the present disclosure may be aimed at distributed storage devices, so it is considered to hand over the functions implemented by the acquisition module 920 and the access module 930 to the computing device 1000B for execution.

[0125] It should be understood that Fig.12 The functions of the computing device 1000A shown in FIG. 1000A may also be completed by multiple computing devices 1000. Similarly, the functions of the computing device 1000B may also be completed by multiple computing devices 1000.

[0126] The present disclosure also provides another computing device cluster 1100. The connection relationship between the computing devices in the computing device cluster 1100 can be similar to that of Fig.12 and Fig.12 The connection mode of the computing device cluster 1100. The difference is that the memory 1006 in one or more computing devices 1000 in the computing device cluster 1100 may store the same instructions for executing the cache management method according to the embodiment of the present disclosure.

[0127] In some possible implementations, the memory 1006 of one or more computing devices 1000 in the computing device cluster 1100 may also respectively store partial instructions for executing the cache management method according to the embodiment of the present disclosure. In other words, the combination of one or more computing devices 1000 may jointly execute the instructions for executing the cache management method according to the embodiment of the present disclosure.

[0128] The embodiment of the present disclosure also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that can be stored by a computing device or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk). The computer-readable storage medium includes instructions that instruct the computing device to execute the cache management method according to the embodiment of the present disclosure.

[0129] The present disclosure also provides a computer program product including instructions. The computer program product may be software or a program product including instructions that can be run on a computing device or stored in any available medium. When the computer program product is run on at least one computing device, the at least one computing device executes the cache management method according to the present disclosure.

[0130] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of the present invention.

Claims

1. A cache management method, characterized in that: The method is applied to a storage system including a host and a storage device, wherein the host runs an application and includes a host-side cache, and the storage device includes a device-side cache and a storage medium. The method includes: Mapping the virtual address space of the data to the host-side cache, the device-side cache, and the storage medium respectively based on the access frequency of the data; Based on a byte-granularity input / output I / O request from the application, obtaining a target virtual address space of target data in the data; and Based on the target virtual address space, the target data is accessed from the host-side cache, the device-side cache, or the storage medium at the byte granularity.

2. The method according to claim 1, characterized in that The host-side cache, the device-side cache, and the storage medium are managed by the host.

3. The method according to claim 1 or 2, characterized in that: Also includes: dividing the data into a plurality of parts with a predetermined unit size; as well as For each of the plurality of portions of the data, the access frequency is determined.

4. The method according to claim 3, characterized in that The data is to be written into the storage device, and determining the access frequency includes: determining, based on an I / O request for the data, a location where each of the plurality of portions of the data is to be written; and The frequency with which the determined location was visited in the previous time step is determined as the visit frequency.

5. The method according to claim 3, characterized in that: The data has been written to the storage device, and determining the access frequency includes: A frequency at which each of the plurality of portions of the data was accessed in a previous time step is determined as the access frequency.

6. The method according to claim 3, characterized in that The device-side cache includes a cache part and a swap part, and maps the virtual address space of the data to the host-side cache, the device-side cache, and the storage medium based on the access frequency of the data, and further includes: Mapping a virtual address space of a portion of the data whose access frequency is higher than a first frequency threshold to the host-side cache; Mapping the virtual address space of a portion of the data whose access frequency is lower than the first frequency threshold and higher than the second frequency threshold to the cache portion in the device-side cache; and mapping the virtual address space of the portion of the data whose access frequency is lower than the second frequency threshold to the storage medium via the exchange portion in the device-side cache, The first frequency threshold is greater than the second frequency threshold.

7. The method according to claim 6, characterized in that Based on the target virtual address space, accessing the target data from the host-side cache, the device-side cache, or the storage medium at the byte granularity includes: In response to the target virtual address space comprising a first virtual address space mapped to the host-side cache, first data corresponding to the first virtual address space is directly accessed from the host-side cache at a first byte granularity.

8. The method according to claim 6, characterized in that Based on the target virtual address space, accessing the target data from the host-side cache, the device-side cache, or the storage medium at the byte granularity includes: In response to the target virtual address space including a second virtual address space mapped to the cache portion, second data corresponding to the second virtual address space is accessed from the cache portion via a peripheral component interconnect express (PCIe) protocol at a second byte granularity.

9. The method according to claim 6, characterized in that Based on the target virtual address space, accessing the target data from the host-side cache, the device-side cache, or the storage medium at the byte granularity includes: In response to the target virtual address space including a third virtual address space mapped to the storage medium, third data corresponding to the third virtual address space is transferred from the storage medium by utilizing the exchange part, and the third data is accessed from the storage medium via the PCIe protocol at a third byte granularity.

10. The method according to claim 8, characterized in that The second byte granularity corresponds to a granularity of a third layer L3 cache exchange of a central processing unit CPU.

11. The method according to claim 6, characterized in that The cache section is configured as: Merging multiple byte-granularity I / O requests from the application into a single page-granularity I / O request; and Based on the I / O request of the single page granularity, corresponding data is cached from the storage medium at the page granularity.

12. The method according to claim 6, It is characterized by: The host-side cache is configured to perform cache replacement based on a least recently used policy; The cache portion is configured to perform cache replacement based on a write-back policy and multi-way set associativity management; and The exchange portion is configured to perform cache replacement based on a write-through policy.

13. A device for cache management, characterized in that: The device is applied to a storage system including a host and a storage device, wherein the host runs an application and includes a host-side cache, and the storage device includes a device-side cache and a storage medium, and the device includes: A mapping module, configured to map the virtual address space of the data to the host-side cache, the device-side cache, and the storage medium respectively based on the access frequency of the data; an acquisition module configured to acquire a target virtual address space of target data in the data based on a byte-granularity input / output (I / O) request from the application program; and The access module is configured to access the target data from the host-side cache, the device-side cache, or the storage medium at the byte granularity based on the target virtual address space.

14. A computing device cluster, comprising at least one computing device, each computing device comprising a processor and a memory, the processor of the at least one computing device being configured to execute instructions stored in the memory of the at least one computing device, so that the computing device cluster executes the method according to any one of claims 1 to 12.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores instructions, which, when executed by a computing device, cause the computing device to perform the method according to any one of claims 1 to 12.

16. A computer program product, characterized in that The computer program product comprises instructions which, when executed by a computing device, cause the computing device to perform the method according to any one of claims 1 to 12.

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