Techniques for interleaving data emergencies across channels

Abstract

The invention relates to techniques for interleaving data emergencies across channels. The memory system may offset data transfer events on a plurality of lanes with timing delays between data transfers on respective lanes. For example, the memory system may initiate a first data transfer on a first channel at a first time and implement a timing delay prior to a second data transfer on a second channel at a second time such that the second time occurs after the first time. In some cases, the memory system may initiate one data transfer on each respective channel at a time, and in some cases, the memory system may initiate two or more data transfers on respective channels simultaneously. In some cases, each channel may be associated with a respective timing delay.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 18 / 771,609 filed by Yu et al. on July 12, 2024, entitled “TECHNIQUES FOR STAGGERING DATA BURST EVENTS ACROSS CHANNELS” and U.S. Provisional Patent Application No. 63 / 588,237 filed by Yu et al. on October 5, 2023, entitled “TECHNIQUES FOR STAGGERING DATA BURST EVENTS ACROSS CHANNELS”, each of which has been assigned to its assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to techniques for staggering data bursts across channels. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, any of which can be stored. To access stored information, a memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to a memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selection memory, chalcogenide memory technology, NOR and NAND memory devices, etc. Memory cells can be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration can maintain a stored logic state for a long time even in the absence of an external power source. Memory cells configured in a volatile configuration may lose a stored state when disconnected from an external power source. Summary of the invention

[0006] An apparatus is described. The apparatus may include: a memory device; and a controller coupled to the memory device and configured to cause the apparatus to: receive a respective command to process respective data for each memory array in a set of memory arrays of a memory system, each memory array being associated with a channel in a set of channels of the memory system; determine a respective timing delay based at least in part on a respective current value associated with each respective channel in the set of channels of the memory system to process the respective data for each memory array in the set of memory arrays of the memory system and on each respective channel; and process the respective data for each respective memory array and on each respective channel based at least in part on the respective timing delay associated with each respective channel.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a respective command to process respective data for each memory array in a set of memory arrays of a memory system, each memory array being associated with a channel in a set of channels of the memory system; determine a respective timing delay based at least in part on a respective current value associated with each respective channel in the set of channels of the memory system to process the respective data for each memory array in the set of memory arrays of the memory system and on each respective channel; and process the respective data for each respective memory array and on each respective channel based at least in part on the respective timing delay associated with each respective channel.

[0008] A method is described. The method may include: receiving a respective command to process respective data for each memory array in a set of memory arrays of a memory system, each memory array being associated with a channel in a set of channels of the memory system; determining a respective timing delay based at least in part on a respective current value associated with each respective channel in the set of channels of the memory system to process the respective data for each memory array in the set of memory arrays and on each respective channel of the memory system; and processing the respective data for each respective memory array and on each respective channel based at least in part on the respective timing delay associated with each respective channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting techniques for staggering data bursts across channels according to examples as disclosed herein is presented.

[0010] Figure 2A and 2B An example of a timing diagram is shown supporting techniques for staggering data bursts across lanes according to examples as disclosed herein.

[0011] Figure 3 An example of a timing diagram is shown supporting techniques for staggering data bursts across lanes according to examples as disclosed herein.

[0012] Figure 4 An example of a system diagram is shown supporting techniques for staggering data bursts across channels according to examples as disclosed herein.

[0013] Figure 5 An example of a process flow supporting techniques for staggering data bursts across channels according to examples as disclosed herein is presented.

[0014] Figure 6 A block diagram showing a memory system supporting techniques for interleaving data bursts across channels according to examples as disclosed herein.

[0015] Figure 7 Flowcharts illustrating one or several methods supporting techniques for staggering data bursts across channels are shown according to examples as disclosed herein. DETAILED DESCRIPTION

[0016] The memory system may support data transfers that may be associated with a corresponding standard or protocol for operation of the memory system and a corresponding channel (e.g., an open NAND flash interface (ONFI) channel, a DRAM channel, a compute fast link (CXL) channel, or any combination thereof). For example, the memory system may support transferring data from a first page to a second page on a corresponding channel. In some cases, the memory system may be configured to support simultaneous or at least partially overlapping (concurrent) data transfer events on multiple channels (e.g., four channels). In some cases, the number of channels that may be active simultaneously may be static and may not be adjusted by the memory system. However, data transfer events on multiple channels may result in high transient currents on the channels, which may negatively affect power delivery to the channels, as well as other issues.

[0017] Various aspects of the present disclosure relate to techniques for interleaving (e.g., arranging, queuing, processing, assigning, sorting) data bursts across multiple channels. For example, a memory system may utilize timing delays between data transfers on corresponding channels to offset data transfer events across multiple channels (e.g., ONFI channels, DRAM channels, CXL channels, or any combination thereof). For example, a memory system may initiate a first data transfer on a first channel at a first time, and implement a timing delay before a second data transfer on a second channel at a second time, so that the second time occurs after the first time. In some cases, a memory system may initiate one data transfer on each corresponding channel at a time, and in some cases, a memory system may initiate two or more data transfers on corresponding channels at the same time. In some cases, each channel may be associated with a corresponding timing delay (e.g., a different delay). By utilizing timing delays associated with one or more channels to interleave data transfer events on multiple channels, a memory system may reduce transient currents, which may also reduce power budget requirements affecting power delivery of the channels, as well as other benefits.

[0018] In addition to applicability in memory systems as described herein, techniques for interleaving data bursts across channels may also be implemented generally to improve the performance of various electronic devices and systems. Some electronic device applications, including high-performance applications (e.g., artificial intelligence (AI) applications, augmented reality (AR) applications, virtual reality (VR) applications, and gaming applications) may be associated with relatively high processing requirements while also benefiting from relatively fast response times to improve the user experience. Thus, it may be desirable to increase processing speed, reduce response time, or otherwise improve the performance of electronic devices. Implementation of the techniques described herein may improve the performance of electronic devices by improving power delivery during transfer and access operations, which may improve response time and power usage, among other benefits.

[0019] refer to Figure 1 , initially describe features of the present disclosure in the context of systems, devices, and circuits. Figures 2A to 5 , features of the present disclosure are described in the context of sequence diagrams, system diagrams, and process flows. Figure 6 and 7 , these and other features of the present disclosure are further illustrated by and described in the context of device diagrams and flow diagrams involving techniques for staggering data bursts across channels.

[0020] Figure 1 An example of a system 100 supporting techniques for interleaving data bursts across channels according to examples as disclosed herein is shown. The system 100 includes a host system 105 coupled to a memory system 110. The system 100 includes a host system 105 coupled to a memory system 110. The system 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked business device), or any other computing device including a memory and a processing device.

[0021] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM) or a non-volatile DIMM (NVDIMM), among other devices.

[0022] System 100 may include a host system 105, which may be coupled to a memory system 110. In some examples, such coupling may include an interface with a host system controller 106, which may be an example of a controller or control component configured to cause the host system 105 to perform various operations according to examples as described herein. The host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a peripheral component interconnect express (PCIe) controller, a serial advanced technology attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to the memory system 110 and read data from the memory system 110. Although Figure 1 One memory system 110 is shown in FIG. 1 , but the host system 105 may be coupled to any number of memory systems 110 .

[0023] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 may be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise communicate control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces may include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR-capable DIMM slot interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces may be included in or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled to the memory system 110 via a respective physical host interface of each memory device 130 included in the memory system 110 or via a respective physical host interface of each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0024] Memory system 110 may include a memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells, such as non-volatile memory cells, volatile memory cells, or any combination thereof. Figure 1 , two memory devices 130-a and 130-b are shown in the example of , but the memory system 110 may include any number of memory devices 130. Furthermore, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0025] The memory system controller 115 may be coupled and communicate with the host system 105 (e.g., via a physical host interface), and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples as described herein. The memory system controller 115 may also be coupled and communicate with the memory devices 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory devices 130—as well as other such operations—which may generally be referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to perform such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access of the memory devices 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with commands from the host system 105). For example, the memory system controller 115 may convert responses associated with the memory devices 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0026] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations (e.g., error detection operations or error correction operations), encryption operations, cache operations, media management operations, background refreshes, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0027] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0028] The memory system controller 115 may also include a local memory 120. In some cases, the local memory 120 may include a read-only memory (ROM) or other memory that may store operating codes (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include a static random access memory (SRAM) or other memory that may be used by the memory system controller 115, such as for internal storage or computations related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 may act as a cache for the memory system controller 115. For example, if data is read from or written to the memory device 130, the data may be stored in the local memory 120, and the data may be available within the local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory device 130).

[0029] although Figure 1 The example of the memory system 110 in has been illustrated as including the memory system controller 115, but in some cases, the memory system 110 may not include the memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135 (which may each be internal to the memory device 130) to perform the functions attributed herein to the memory system controller 115. In general, in some cases, one or more functions attributed herein to the memory system controller 115 may instead be performed by the host system 105, the local controller 135, or any combination thereof. In some cases, the memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] The memory device 130 may include one or more arrays of non-volatile memory cells. For example, the memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric random access memory (FeRAM), magnetically controlled RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, the memory device 130 may include one or more arrays of volatile memory cells. For example, the memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some examples, the memory devices 130 may include a local controller 135 (e.g., on the same die or within the same package) that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115 or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1 As illustrated in FIG. 1 , memory device 130 - a may include a local controller 135 - a and memory device 130 - b may include a local controller 135 - b.

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a die 160 (e.g., a memory die). For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a piece of electronic grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as single-level cells (SLCs). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each, which may be referred to as multi-level cells (MLCs) if configured to store two bits of information each, three-level cells (TLCs) if configured to store three bits of information each, four-level cells (QLCs) if configured to store four bits of information each, or more generally, multi-level memory cells. Relative to SLC memory cells, multi-level memory cells may provide greater storage density, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0034] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, concurrent operations may be performed on different planes 165. For example, concurrent operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and a virtual block 180 may refer to a group of blocks 170 within which concurrent operations may occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as a virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, and so on). In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0035] In some cases, block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share (e.g., be coupled to) a common word line, and memory cells in the same string may share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0036] For some NAND architectures, memory cells may be read and programmed (e.g., written) at a first granularity (e.g., at a page granularity or portions thereof), but may be erased at a second granularity (e.g., at a block granularity). That is, a page 175 may be the smallest unit of memory (e.g., a group of memory cells) that may be independently programmed or read (e.g., concurrently programmed or read as part of a single programming or reading operation), while a block 170 may be the smallest unit of memory (e.g., a group of memory cells) that may be independently erased (e.g., concurrently erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells may be erased before they are overwritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing the page 175 has been erased.

[0037] In some cases, to update some data within a block 170 while retaining other data within the block 170, the memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages of the new block 170. The memory device 130 (e.g., the local controller 135) or the memory system controller 115 may mark or otherwise designate the data remaining in the old block 170 as invalid or obsolete, and may update a logical-to-physical (L2P) mapping table to associate the logical address (e.g., LBA) of the data with the new valid block 170 rather than the old invalid block 170. In some cases, such copying and remapping may be performed rather than erasing and rewriting the entire old block 170, for example due to latency or wear considerations. In some cases, one or more copies of the L2P mapping table may be stored within a memory unit of the memory device 130 (e.g., stored within one or more blocks 170 or planes 165) for use (e.g., reference and update) by the local controller 135 or the memory system controller 115.

[0038] In some cases, an L2P mapping table may be maintained and data may be marked as valid or invalid at a page granularity level, and a page 175 may contain valid data, invalid data, or no data. Invalid data may be outdated data, which may be due to a more recent or updated version of the data being stored in a different page 175 of the memory device 130. Invalid data may have been previously programmed to an invalid page 175, but may no longer be associated with a valid logical address (e.g., a logical address referenced by the host system 105). Valid data may be the most recent version of this data stored on the memory device 130. A page 175 that does not contain data may be a page 175 that has never been written to or has been erased.

[0039] In some cases, the memory system controller 115 or the local controller 135 may perform operations (e.g., as part of one or more media management algorithms) for the memory device 130, such as wear leveling, background flushing, trash collection, scrubbing, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, a block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. In order to avoid waiting for all pages 175 in a block 170 to have invalid data in order to erase and reuse the block 170, an algorithm called "trash collection" may be invoked to allow the block 170 to be erased and released as a free block for subsequent write operations. Trash collection may refer to a set of media management operations including, for example, selecting a block 170 containing valid and invalid data, selecting a page 175 in the block containing valid data, copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected page 175 as invalid, and erasing the selected block 170. Thus, the number of blocks 170 that have been erased may be increased so that more blocks 170 are available to store subsequent data (eg, data subsequently received from the host system 105).

[0040] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller, such as local controller 135. An example of a managed memory system is a managed NAND (MNAND) system.

[0041] The system 100 may include any number of non-transitory computer-readable media that support techniques for interleaving data bursts across channels. For example, the host system 105 (e.g., host system controller 106), the memory system 110 (e.g., memory system controller 115), or the memory device 130 (e.g., local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media storing instructions (e.g., firmware, logic, code) for performing the functions attributed herein to the host system 105, the memory system 110, or the memory device 130. For example, such instructions, if executed by the host system 105 (e.g., by the host system controller 106), by the memory system 110 (e.g., by the memory system controller 115), or by the memory device 130 (e.g., by the local controller 135), may cause the host system 105, the memory system 110, or the memory device 130 to perform the associated functions as described herein.

[0042] The memory system 110 may support data transfers, which may be associated with a corresponding standard or protocol for operation of the memory system 110 and a corresponding channel (e.g., an ONFI channel, a DRAM channel, a CXL channel, etc.). For example, the memory system 110 may support transferring data from a first page 175 to a second page 175 on a corresponding channel (e.g., a first ONFI channel, a first DRAM channel, a first CXL channel). In some cases, the memory system 110 may be configured to support simultaneous or at least partially overlapping data transfer events on multiple channels (e.g., four channels). In some cases, the number of channels that may be simultaneously active may be static and may not be adjusted by the memory system 110. However, data transfer events on multiple channels may result in unwanted transient currents on the channels, which may negatively affect power delivery to the channels.

[0043] The memory system 110 may utilize a timing delay between data transfers on respective channels to offset data transfer events on multiple channels. For example, the memory system 110 may initiate a first data transfer on a first channel (e.g., a first ONFI channel) at a first time, and implement a timing delay before a second data transfer on a second channel (e.g., a second ONFI channel) at a second time, so that the second time occurs after the first time. In some cases, the memory system 110 may initiate one data transfer on each respective channel at a time, and in some cases, the memory system 110 may initiate two or more data transfers on respective channels (e.g., a first ONFI channel, a second ONFI channel) at the same time. In some cases, each channel may be associated with a respective timing delay. By utilizing a timing delay associated with one or more channels to stagger data transfer events on multiple channels (e.g., arrange, sort, assign, allocate, process), the memory system 110 may reduce transient currents, which may also reduce power budget requirements affecting power delivery of the channels.

[0044] Figure 2A An example of a timing diagram 200-a supporting a technique for staggering data bursts across channels according to an example as disclosed herein is shown. One or more aspects of the timing diagram 200-a may be implemented by one or more aspects of the system 100. For example, the timing diagram 200-a may be associated with the number of channels 205-a (e.g., ONFI channels, DRAM channels, CXL channels, or any combination thereof) used for data transfer. For example, as described in reference Figure 1As described, the memory system 110 may include four channels 205-a (e.g., channel 205-a1, channel 205-a2, channel 205-a3, and channel 205-a4). As the speed of the memory system 110 increases, the current on the channels 205-a and the power rails associated with the memory system may also increase. Additionally or alternatively, if all channels 205-a are active at the same time, the power delivery network (e.g., power rails) associated with the memory system 110 may observe an increase in current, and in some cases, an increase in noise associated with the power. In some cases, the increased current may negatively affect the memory system 110. In some cases, if all channels 205-a are permitted to be active at the same time, the memory system 110 may reserve a power budget sufficient to enable all four channels 205-a to be active. In some cases, reserving a significant power budget may affect the power allocation to other aspects of the memory system 110, and may cause the memory system 110 to require more time to allocate the power budget.

[0045] To reduce the negative impact of current on the channels 205-a, the memory system 110 may interleave (e.g., process, order, arrange, queue) channel 205-a activities (e.g., associated with data transfers) by implementing timing delays 215-a, which may reduce peak current associated with the channels 205-a and reduce noise associated with power. For example, each channel 205-a may be associated with a respective memory array (e.g., a NAND array) of the memory system 110, and the memory system 110 may receive a command to process data of each memory array (e.g., transfer data). For example, the command (e.g., an external transfer command) may indicate a data transfer event 210-a to be performed by the memory system 110 for each channel 205-a, wherein each data transfer event 210-a includes a transfer of a page. In some cases, the memory system 110 may transfer data from a first memory array of the memory system 110 to a second memory array of the memory system 110. The memory system 110 may determine a respective timing delay 215-a (e.g., a timing delay 215-a associated with each channel 205-a and / or the memory array). In some cases, the timing delay 215-a may be based on or responsive to a current value associated with each respective channel. Based on the timing delay 215-a associated with each channel 205-a, the memory system 110 may process data on each channel 205-a (e.g., by executing a respective data transfer event 210-a).

[0046] In some cases, such as Figure 2A, the memory system 110 may implement timing delays 215-a so that the channels 205-a may be activated one at a time. For example, the memory system 110 may first activate channel 205-a1 and may begin executing data transfer event 210-a. In some cases, channel 205-a1 may not be associated with a timing delay 215-a or may be associated with a timing delay 215-a of zero. Next, the memory system 110 may activate channel 205-a2, then channel 205-a3, and then channel 205-a4. Each channel 205-a may be associated with an increasing number of timing delays 215-a or timing delays 215-a of increasing duration so that the channels 205-a are activated one by one. For example, the timing delay 215-a associated with channel 205-a2 may be different from the timing delay 215-a associated with channel 205-a3.

[0047] In some cases, the timing delay 215-a may consist of a preconfigured duration (e.g., Δt), and each channel 205-a may be associated with a number of timing delays 215-a. For example, channel 205-a2 may be associated with two timing delays 215-a. In some cases, the preconfigured duration (e.g., Δt) may be associated with a response time of a power management integrated circuit (PMIC) of the memory system 110. For example, the preconfigured duration may be no less than a target PMIC response time. In some cases, the memory system 110 may receive a timing delay 215-a configuration from a host system. For example, the memory system 110 may receive an indication of the preconfigured duration from the host system. In some cases, the preconfigured duration may be configured by firmware.

[0048] In some cases, the memory system 110 may configure the timing delays 215-a to reduce the number of data transfer events 210-a that are concurrent (e.g., at least partially overlapping in time). For example, there may be a threshold number of channels 205-a that may be active and processing data (e.g., performing data transfer events 210-a) at the same time. For example, the threshold number of channels 205-a that may be active at the same time may be three channels 205-a, and the memory system 110 may configure the duration and number of timing delays 215-a so that no more than three channels 205-a are active at the same time. For example, channel 205-a4 may be associated with three timing delays 215-a so that channel 205-a4 is activated and a data transfer event 210-a associated with channel 205-a4 occurs after channel 205-a1 is no longer active (e.g., inactive). For example, just before activating channel 205-a4, three channels (e.g., channel 205-a1, channel 205-a2, and channel 205-a3) are active, and just after activating channel 205-a4, three channels (e.g., channel 205-a2, channel 205-a3, and channel 205-a4) are active.

[0049] In some cases, the memory system 110 may configure the timing delay 215-a based on an activity (e.g., a data transfer event 210-a). For example, the data transfer event 210-a may be associated with a duration associated with one page transfer on the channel 205-a, and the timing delay 215-a may be configured to match the duration associated with one page transfer. For example, after the first data transfer event 210-a on the channel 205-a1 is completed, the first data transfer event 210-a on the channel 205-a2 may be initiated so that the second data transfer event 210-a starts at the same time as the first data transfer event 210-a on the channel 205-a2. If the timing delay 215-a is associated with a PMIC response time (e.g., Δt), the timing delay 215-a may be rounded up to match a duration associated with an integer number of activities (e.g., 1, 2, or 3 activities). The memory system 110 may implement the configured timing delay 215-a to reduce the number of events occurring in parallel (eg, at least partially overlapping in time). In some cases, the timing delay 215-a duration may be based on a read time, a write time, or any combination thereof.

[0050] In some cases, a timing delay 215 - a may be implemented, rather than a data transfer event 210 - a , before data is read on channel 205 - a or written to an associated memory array.

[0051] Figure 2BAn example of a timing diagram 200-b is shown that supports a technique for staggering data bursts across channels according to an example as disclosed herein. One or more aspects of the timing diagram 200-a may be implemented by one or more aspects of the system 100. For example, as described in reference Figure 1 As described, the memory system 110 may implement timing delays 215-b to stagger (e.g., order, time, process, queue, etc.) data transfer events 210-b so that two or more channels 205-b initiate data transfer events 210-b simultaneously. For example, the memory system 110 may first activate channel 205-b1 and channel 205-b2 simultaneously and initiate data transfer events 210-b. After the timing delay 215-b, the memory system 110 may activate channel 205-b3 and channel 205-b4 and perform additional data transfer events 210-b. The timing delay 215-b may include one or more timing delays 215-b and may be a preconfigured duration (e.g., Δt), may be associated with a duration of one or more events associated with the channel 205-b (e.g., a duration of the data transfer event 210-b, a read time, a write time, or any combination thereof), or any combination thereof. In some cases, memory system 110 may implement an amount of timing delay 215-b such that data transfer events 210-b associated with channels 205-bl and 205-b2 complete before initiating data transfer events 210-b associated with channels 205-b3 and 205-b4.

[0052] Figure 3 An example of a system diagram 300 supporting techniques for interleaving data bursts across channels according to examples as disclosed herein is shown. One or more aspects of the system diagram 300 may be implemented by one or more aspects of the system 100. For example, the memory system 305 may be as described in reference Figure 1 305. The memory system 305 may dynamically configure the timing delay configuration according to power feedback associated with the memory system 305. The memory system 305 may include a power rail 310, which may be used to power an application specific integrated circuit (ASIC) 335, which may include a core linear voltage regulator 315, a firmware configuration 320, a timing delay control 330, an ONFI 340, and a voltage detector 325. The memory system 305 may also include a channel 345 (e.g., an ONFI channel) and an associated memory array 350. The voltage detector 325 may be a voltage detector 325 configured to detect a voltage for determining the timing delay configuration, or a shared voltage detector 325 that may be used for other purposes within the memory system 305.

[0053] In some cases, the memory system 305 may implement a default timing delay configuration (e.g., from the firmware configuration 320), but may use the voltage detector 325 to determine whether the noise or power level associated with the power rail 310 meets a threshold. For example, if the noise associated with the power rail 310 meets (e.g., is equal to or greater than) a threshold, the voltage detector 325 may provide feedback to the timing delay control 330. The timing delay control 330 may then adjust (e.g., increase) the timing delay. For example, the timing delay control 330 may increase the timing delay or several timing delays associated with ONFI 340-a and the corresponding ONFI channel 345-a, ONFI 340-b and the corresponding ONFI channel 345-b, ONFI 340-c and the corresponding ONFI channel 345-c, and ONFI 340-d and the corresponding ONFI channel 345-d while performing data transfer to the memory array 350-a, the memory array 350-b, the memory array 350-c and the memory array 350-d.

[0054] In some cases, the timing delay control 330 may increase the number of timing delays or may increase the duration of the timing delays. In some cases, the timing delay control 330 may continue to adjust the timing delays until the voltage detector 325 indicates that the noise associated with the power rail 310 no longer meets the threshold. In some cases, the memory system 305 may implement dynamic timing delay configuration as part of a training design within the system.

[0055] Figure 4 An example of a system diagram 400 supporting techniques for interleaving data bursts across channels according to examples as disclosed herein is shown. One or more aspects of the system diagram 400 may be implemented by one or more aspects of the system 100. For example, the memory system 405 may be as described in reference Figure 1 4. An example of a memory system 110 is described. The memory system 405 can dynamically configure a timing delay configuration based on current detector feedback associated with the memory system 405. The memory system 405 can include a power rail 410, which can be used to power an ASIC 440, which can include a core linear voltage regulator 415, a firmware configuration 420, a timing delay control 435, an ONFI 445, and an operational amplifier 430. The memory system 405 can also include a resistor 425, a channel 450 (e.g., an ONFI channel), and a memory array 455. The resistor 425 can be coupled to the power rail 410 to detect a voltage drop across the resistor 425. The timing delay control 435 can determine a current amplitude or noise associated with the power rail 410 based on the voltage drop across the resistor 425 detected by the operational amplifier 430.

[0056] The timing delay control 435 may adjust the timing delay associated with the channel 450 according to the current amplitude or noise associated with the power rail 410. For example, if the current amplitude or noise associated with the power rail 410 meets (e.g., is greater than or equal to) a threshold, the timing delay control 435 may adjust (e.g., increase) a number of timing delays associated with ONFI 445-a and corresponding ONFI channel 450-a, ONFI 445-b and corresponding ONFI channel 450-b, ONFI 445-c and corresponding ONFI channel 450-c, and ONFI 445-d and corresponding ONFI channel 450-d while performing data transfer to the memory arrays 455-a, 455-b, 455-c, and 455-d. In some cases, the resistor 425 may be a low resistance (e.g., 5 mOhm) resistor 425 to reduce the impact on the power rail margin.

[0057] Figure 5 An example of a process flow 500 supporting techniques for staggering data bursts across channels according to examples as disclosed herein is shown. In some cases, the process flow 500 may be implemented by a processor as described in reference to Figure 1 In some cases, the process flow 500 may be implemented as described in the respective embodiments of the system 100. Figure 2A and 2B In some other cases, the process flow 500 may be implemented as described in the timing diagram 200-a and the timing diagram 200-b. Figure 3 and 4 500. In the following description of process flow 500, operations may be performed in an order different from that shown. Some operations may also be omitted from process flow 500, or other operations may be added to process flow 500. Although some operations or communications may be shown as occurring at different times for discussion purposes, these operations may occur simultaneously. Process flow 500 may include resource manager 505, read handler 510, dynamic power switch 515, near field communicator 520, and channel 530.

[0058] Aspects of process flow 500 may be implemented by a controller and other components. Additionally or alternatively, aspects of process flow 500 may be implemented as instructions stored in a memory (e.g., firmware stored in a memory coupled to a timing delay control). For example, the instructions, when executed by a controller (e.g., a timing delay control), may cause the controller to perform the operations of process flow 500.

[0059] At 535, requests may be exchanged (e.g., transmitted, received). For example, the read handler 510 may transmit and the dynamic power switch 515 may receive a request to process data. The request to process data may include a request to perform one or more data transfers (e.g., page transfers), read operations, write operations, or any combination thereof. In some cases, the request to process data may be associated with one or more channels 530 (e.g., ONFI channels, DRAM channels, CXL channels, or any combination thereof).

[0060] At 540, power allocations may be exchanged (e.g., transmitted, received). For example, dynamic power switch 515 may transmit and resource manager 505 may receive power allocations to execute the request at 535. Based on the power allocations, resource manager 505 may determine a power budget and a corresponding timing delay configuration for channel 530, as described in reference to FIG. Figure 2A and 2B described.

[0061] At 545, a command (e.g., a write command, an access command, a read command) may be received. For example, based on the power allocation received at 540, the resource manager 505 may transmit and the dynamic power switch 515, the near field communicator 520, and the channel 530 may receive a command to process data. In some cases, the command to process data may include a command to process respective data for each memory array in a set of memory arrays of the memory system, wherein each memory array is associated with a channel in a set of channels 530. The data may be processed according to the timing delay configuration. In some cases, the memory system may adjust the timing delay configuration while executing the command to process data, as described in reference to FIG. Figure 3 and 4 In some cases, resource manager 505 may ensure that the command to process data at 545 is executed by channel 530 such that the command to process data is executed to meet a timing delay after a set of one or more previous data transfers or completion indications associated with previous data transfers.

[0062] At 550, once the channel 530 has executed the command to process the data, the channel can transmit and the near field communicator 520 can receive a completion indication. At 555, based on the completion indication at 550, the near field communicator 520 can transmit and the resource manager 505 can receive a power deallocation and can deallocate power.

[0063] Figure 6 A block diagram 600 is shown of a memory system 620 supporting techniques for interleaving data bursts across channels according to examples as disclosed herein. The memory system 620 may be a memory system as described in reference to Figures 1 to 560, a memory system 620, or various components thereof, may be examples of means for performing various aspects of the techniques for interleaving data bursts across channels as described herein. For example, the memory system 620 may include a command component 625, a timing delay component 630, a processing component 635, a power level component 640, a configuration component 645, a detection component 650, a threshold component 655, a write component 660, a read component 665, or any combination thereof. Each of these components may communicate with each other, directly or indirectly (e.g., via one or more buses).

[0064] The memory system 620 may support operating the memory system according to examples as disclosed herein. The command component 625 may be configured to or otherwise support means for receiving respective commands to process respective data for each memory array in a set of memory arrays of the memory system, each memory array being associated with a channel in a set of channels of the memory system. The timing delay component 630 may be configured to or otherwise support means for determining respective timing delays based at least in part on respective current values ​​associated with each respective channel in the set of channels of the memory system to process the respective data for each memory array in the set of memory arrays of the memory system and on each respective channel. The processing component 635 may be configured to or otherwise support means for processing the respective data for each respective memory array and on each respective channel based at least in part on the respective timing delays associated with each respective channel.

[0065] In some examples, the timing delay component 630 may be configured or otherwise support means for determining the respective timing delays based at least in part on a threshold number of channels of the set of channels of the memory system that process the respective data during the same time.

[0066] In some examples, to support processing the respective data for each respective memory array and on each respective channel, the processing component 635 may be configured to or otherwise support means for processing the respective data for a first memory array and on the first channel in response to a first timing delay associated with the first channel. In some examples, to support processing the respective data for each respective memory array and on each respective channel, the processing component 635 may be configured to or otherwise support means for processing the respective data for a second memory array and on the second channel based at least in part on processing the respective data for the first memory array and in response to a second timing delay associated with the second channel, wherein the first timing delay is different from the second timing delay.

[0067] In some examples, to support processing the respective data for each respective memory array and on each respective channel, the processing component 635 may be configured to or otherwise support means for processing the respective data for a first memory array and on the first channel in response to the respective timing delay associated with the first channel. In some examples, to support processing the respective data for each respective memory array and on each respective channel, the processing component 635 may be configured to or otherwise support means for processing the respective data for a second memory array and on the second channel in response to the respective timing delay associated with the second channel, wherein the respective timing delay associated with the first channel and the respective timing delay associated with the second channel are the same.

[0068] In some examples, the respective timing delays include a preconfigured duration and each channel of the set of channels of the memory system is associated with a number of timing delays.

[0069] In some examples, the preconfigured duration is based at least in part on a response time of a power management integrated circuit of the memory system.

[0070] In some examples, power level component 640 may be configured or otherwise support means for determining a power level associated with a power rail of the memory system. In some examples, timing delay component 630 may be configured or otherwise support means for determining the respective timing delays based at least in part on the power level associated with the power rail of the memory system.

[0071] In some examples, threshold component 655 may be configured or otherwise support means for determining whether the power level associated with the power rail of the memory system satisfies a threshold. In some examples, timing delay component 630 may be configured or otherwise support means for adjusting the corresponding timing delay based at least in part on determining that the power level associated with the power rail of the memory system satisfies the threshold.

[0072] In some examples, the configuration component 645 can be configured or otherwise support means for receiving a configuration indicating a threshold number of channels in the set of channels of the memory system that are active during a certain duration. In some examples, the timing delay component 630 can be configured or otherwise support means for determining the corresponding timing delay based at least in part on the configuration.

[0073] In some examples, to support receiving the respective commands to process the respective data for each memory array in the set of memory arrays of the memory system, the command component 625 may be configured as or otherwise support means for receiving the respective commands to transfer data from a first memory array in the set of memory arrays of the memory system to a second memory array in the set of memory arrays of the memory system.

[0074] In some examples, to support receiving the respective commands to process the respective data for each memory array in the set of memory arrays of the memory system, the command component 625 may be configured as or otherwise support means for receiving the respective commands to write the respective data to each memory array in the set of memory arrays of the memory system.

[0075] In some examples, to support processing the respective data for each respective memory array and on each respective channel, write component 660 can be configured or otherwise support means for writing the respective data to each respective memory array.

[0076] In some examples, to support receiving the respective commands to process the respective data for each memory array in the set of memory arrays of the memory system, the command component 625 may be configured as or otherwise support means for receiving the respective commands to read the respective data from each memory array in the set of memory arrays of the memory system.

[0077] In some examples, to support processing the respective data for each respective memory array and on each respective channel, the read component 665 can be configured or otherwise support means for reading the respective data from each respective memory array.

[0078] In some examples, the respective timing delay for processing the respective data for each memory array in the set of memory arrays of the memory system and on each respective channel in the set of channels of the memory system is less than or equal to the respective duration associated with performing a respective external transfer of a respective page for each memory array in the set of memory arrays of the memory system and on each respective channel in the set of channels of the memory system.

[0079] In some examples, the set of memory arrays includes a set of NAND arrays, a set of DRAM arrays, or any combination thereof. In some examples, the set of channels includes a set of ONFI channels, a set of DRAM channels, a set of CXL channels, or any combination thereof.

[0080] In some examples, the detection component 650 may be configured or otherwise support means for detecting one or more of a voltage, a current, or any combination thereof. In some examples, the timing delay component 630 may be configured or otherwise support means for determining the corresponding timing delay based at least in part on one or more of the voltage, the current, or any combination thereof.

[0081] In some examples, the corresponding command comprises an external transfer command. In some examples, the corresponding data comprises a page.

[0082] Figure 7 A flowchart illustrating a method 700 for supporting techniques for interleaving data bursts across channels according to an example as disclosed herein is shown. The operations of the method 700 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 700 may be implemented by a memory system or components thereof as described herein. Figures 1 to 6 The memory system described herein performs. In some examples, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0083] At 705, the method may include receiving a respective command to process respective data for each memory array in a set of memory arrays of a memory system, each memory array being associated with a channel in a set of channels of the memory system. The operations of 705 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 705 may be described by reference to Figure 6 The command component 625 described here executes.

[0084] At 710, the method may include determining a respective timing delay based at least in part on a respective current value associated with each respective channel in the set of channels of the memory system to process the respective data for each memory array in the set of memory arrays of the memory system and on each respective channel. The operations of 710 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 710 may be performed as described in reference to Figure 6 The timing delay component 630 is described to perform.

[0085] At 715, the method may include processing the respective data for each respective memory array and on each respective channel based at least in part on the respective timing delay associated with each respective channel. The operations of 715 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 715 may be described by reference to Figure 6 The described processing component 635 performs.

[0086] In some examples, an apparatus as described herein may perform one or several methods, such as method 700. The apparatus may include operations, features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0087] Aspect 1: A method, apparatus, or non-transitory computer-readable medium, comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: receiving a respective command to process respective data for each memory array in a set of memory arrays of a memory system, each memory array being associated with a channel in a set of channels of the memory system; determining a respective timing delay based at least in part on a respective current value associated with each respective channel in the set of channels of the memory system to process the respective data for each memory array in the set of memory arrays of the memory system and on each respective channel; and processing the respective data for each respective memory array and on each respective channel based at least in part on the respective timing delay associated with each respective channel.

[0088] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of aspect 1, wherein determining the respective timing delays is based at least in part on a threshold number of channels in the set of channels of the memory system that process the respective data during the same time.

[0089] Aspect 3: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 2, wherein processing the respective data for each respective memory array and on each respective channel includes operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: processing the respective data for a first memory array and on the first channel in response to a first timing delay associated with the first channel; and processing the respective data for a second memory array and on the second channel based at least in part on processing the respective data for the first memory array and in response to a second timing delay associated with the second channel, wherein the first timing delay is different from the second timing delay.

[0090] Aspect 4: A method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 2, wherein processing the respective data for each respective memory array and on each respective channel includes operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: processing the respective data for a first memory array and on the first channel in response to the respective timing delay associated with the first channel; and processing the respective data for a second memory array and on the second channel in response to the respective timing delay associated with the second channel, wherein the respective timing delay associated with the first channel and the respective timing delay associated with the second channel are the same.

[0091] Aspect 5: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 to 4, wherein the respective timing delays include a preconfigured duration and each channel of the set of channels of the memory system is associated with a number of timing delays.

[0092] Aspect 6: The method, apparatus, or non-transitory computer-readable medium of aspect 5, wherein the preconfigured duration is based at least in part on a response time of a power management integrated circuit of the memory system.

[0093] Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 6, further comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for determining a power level associated with a power rail of the memory system, wherein determining the corresponding timing delay is based at least in part on the power level associated with the power rail of the memory system.

[0094] Aspect 8: The method, apparatus, or non-transitory computer-readable medium of Aspect 7, further comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: determining whether the power level associated with the power rail of the memory system satisfies a threshold; and adjusting the corresponding timing delay based at least in part on determining that the power level associated with the power rail of the memory system satisfies the threshold.

[0095] Aspect 9: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 8, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving a configuration indicating a threshold number of channels in the set of channels of the memory system that are active during a certain duration, wherein determining the corresponding timing delay is based at least in part on the configuration.

[0096] Aspect 10: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 9, wherein receiving the corresponding command to process corresponding data for each memory array in the set of memory arrays of the memory system includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving the corresponding command to transfer data from a first memory array in the set of memory arrays of the memory system to a second memory array in the set of memory arrays of the memory system.

[0097] Aspect 11: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 10, wherein receiving the corresponding command to process the corresponding data for each memory array in the set of memory arrays of the memory system includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for receiving the corresponding command to write the corresponding data to each memory array in the set of memory arrays of the memory system.

[0098] Aspect 12: The method, apparatus, or non-transitory computer-readable medium of aspect 11, wherein processing the respective data for each respective memory array and on each respective channel comprises operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: writing the respective data to each respective memory array.

[0099] Aspect 13: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 10, wherein receiving the corresponding command to process the corresponding data for each memory array in the set of memory arrays of the memory system includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving the corresponding command to read the corresponding data from each memory array in the set of memory arrays of the memory system.

[0100] Aspect 14: A method, apparatus, or non-transitory computer-readable medium according to Aspect 13, wherein processing the respective data for each respective memory array and on each respective channel includes operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: reading the respective data from each respective memory array.

[0101] Aspect 15: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 14, wherein the respective timing delay for processing the respective data for each memory array in the set of memory arrays of the memory system and on each respective channel in the set of channels of the memory system is less than or equal to the respective duration associated with performing a respective external transfer of a respective page for each memory array in the set of memory arrays of the memory system and on each respective channel in the set of channels of the memory system.

[0102] Aspect 16: A method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 15, wherein the set of memory arrays includes a set of NAND arrays, a set of DRAM arrays, or any combination thereof, and the set of channels includes a set of ONFI channels, a set of DRAM channels, a set of CXL channels, or any combination thereof.

[0103] Aspect 17: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 16, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: detecting one or more of a voltage, a current, or any combination thereof, wherein determining the corresponding timing delay is based at least in part on one or more of the voltage, the current, or any combination thereof.

[0104] Aspect 18: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 to 17, wherein the corresponding command comprises an external transfer command and the corresponding data comprises a page.

[0105] It should be noted that the described techniques include possible implementations, and that operations and steps may be rearranged or otherwise modified, and other implementations are possible. In addition, portions from two or more methods may be combined.

[0106] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have a variety of bit widths.

[0107] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports signal flow between the components. Components are considered to be in electronic communication (or conductive contact or connected or coupled) with each other if there is any conductive path between the components that can readily support signal flow between the components. At any given time, the conductive path between components that are in electronic communication (or conductive contact or connected or coupled) with each other may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, the signal flow between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0108] The term "coupled" (e.g., "electrically coupled") may refer to a condition that moves from an open circuit relationship between components (where signals cannot currently be communicated between components via conductive paths) to a closed circuit relationship between components (where signals can be communicated between components via conductive paths). If a component (e.g., a controller) couples other components together, the component initiates a change that allows signals to flow between other components via conductive paths that previously did not permit signal flow.

[0109] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. If an open circuit exists between the components, then the components are isolated from each other. For example, if a switch positioned between the components is open, then the two components separated by the switch are isolated from each other. If a controller isolates two components, then the controller causes a change that prevents a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0110] The terms "if", "when", "based on", or "based at least in part on" are used interchangeably. In some instances, the terms "if", "when", "based on", or "based at least in part on" may be interchangeable if they are used to describe a connection between conditional actions, conditional processes, or parts of processes.

[0111] The term "responsive to" may refer to a condition or action that occurs at least in part, if not entirely, as a result of a prior condition or action. For example, a first condition or action may be performed and a second condition or action may occur at least in part as a result of the prior condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions that occur after the first condition or action).

[0112] In addition, the term "directly in response to or in direct response to" may refer to a condition or action that occurs as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of the occurrence of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of the occurrence of a previous condition or action, so that no other intermediate conditions or actions occur between an earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between an earlier condition or action and the second condition or action. Any condition or action described herein as "based on", "at least partially based on" or "in response to" some other step, action, event or condition and performed may be performed in addition or alternatively (e.g., in an alternative instance) "directly in response to (in direct response to or directly in response to)" this other condition or action, unless otherwise specified.

[0113] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping means.

[0114] The switch components or transistors discussed herein may represent field effect transistors (FETs) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0115] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "superior to other examples". The detailed description includes specific details to provide an understanding of the described technology. However, these technologies may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0116] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that distinguishes the similar components. When only the first reference label is used in the specification, the description applies to any of the similar components with the same first reference label, regardless of the second reference label.

[0117] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the described functions may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features that implement the functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations.

[0118] For example, the various illustrative blocks and components described in connection with the present disclosure may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0119] As used herein (including in the claims), "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, so that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an example step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0120] Computer-readable media include both non-transitory computer storage media and communication media, and the communication media include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage device, magnetic disk storage device or other magnetic storage device, or may be used to carry or store desired program code components in the form of instructions or data structures and any other non-transitory media that can be accessed by a general or special computer or a general or special processor. Moreover, any connection is appropriately referred to as computer-readable media. For example, if coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) is used to transmit software from a website, server or other remote source, then coaxial cable, fiber optic cable, twisted pair, DSL or wireless technology (such as infrared, radio and microwave) are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of these are also included within the scope of computer-readable media.

[0121] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: Memory device; and a controller coupled to the memory device and configured to cause the apparatus to: receiving a respective command to process respective data for each memory array of a set of memory arrays of a memory system, each memory array being associated with a channel of a set of channels of the memory system; determining a respective timing delay based at least in part on a respective current value associated with each respective channel in the set of channels of the memory system to process the respective data for each memory array in the set of memory arrays of the memory system and on each respective channel; and The respective data is processed for each respective memory array and on each respective channel based at least in part on the respective timing delay associated with each respective channel. 2 . The apparatus of claim 1 , wherein determining the respective timing delays is based at least in part on a threshold number of channels in the set of channels of the memory system that process the respective data during a same time.

3. The apparatus of claim 1 , wherein to process the respective data for each respective memory array and on each respective channel, the controller is configured to cause the apparatus to: processing the corresponding data on a first channel for a first memory array in response to a first timing delay associated with the first channel; and processing the corresponding data for a second memory array and on the second channel based at least in part on processing the corresponding data for the first memory array and in response to a second timing delay associated with a second channel, The first timing delay is different from the second timing delay.

4. The apparatus of claim 1 , wherein to process the respective data for each respective memory array and on each respective channel, the controller is configured to cause the apparatus to: processing the respective data for a first memory array and on the first channel in response to the respective timing delay associated with the first channel; and processing the corresponding data on a second channel for a second memory array in response to the corresponding timing delay associated with the second channel, Wherein the corresponding timing delay associated with the first channel and the corresponding timing delay associated with the second channel are the same.

5. The apparatus of claim 1, wherein the respective timing delays comprise a preconfigured duration and each channel of the set of channels of the memory system is associated with a number of timing delays. 6 . The apparatus of claim 5 , wherein the preconfigured duration is based at least in part on a response time of a power management integrated circuit of the memory system.

7. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: determining a power level associated with a power rail of the memory system, Wherein determining the respective timing delays is based at least in part on the power levels associated with the power rails of the memory system.

8. The apparatus of claim 7, wherein the controller is further configured to cause the apparatus to: determining whether the power level associated with the power rail of the memory system satisfies a threshold; and The respective timing delays are adjusted based at least in part on determining that the power level associated with the power rail of the memory system satisfies the threshold.

9. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: receiving a configuration indicating a threshold number of channels of the set of channels of the memory system that are active during a certain duration, Wherein determining the corresponding timing delay is based at least in part on the configuration.

10. The apparatus of claim 1, wherein to receive the respective command to process respective data for each memory array in the set of memory arrays of the memory system, the controller is configured to cause the apparatus to: The corresponding command is received to transfer data from a first memory array in the set of memory arrays in the memory system to a second memory array in the set of memory arrays in the memory system.

11. The apparatus of claim 1 , wherein to receive the respective command to process respective data for each memory array in the set of memory arrays of the memory system, the controller is configured to cause the apparatus to: The respective commands are received to write the respective data to each memory array of the set of memory arrays of the memory system.

12. The apparatus of claim 11, wherein to process the respective data for each respective memory array and on each respective channel, the controller is configured to cause the apparatus to: The respective data is written to each respective memory array.

13. The apparatus of claim 1 , wherein to receive the respective command to process respective data for each memory array in the set of memory arrays of the memory system, the controller is configured to cause the apparatus to: The respective commands are received to read the respective data from each memory array of the set of memory arrays of the memory system.

14. The apparatus of claim 13, wherein to process the respective data for each respective memory array and on each respective channel, the controller is configured to cause the apparatus to: The respective data is read from each respective memory array.

15. The apparatus of claim 1 , wherein the respective timing delay for processing the respective data for each memory array in the set of memory arrays of the memory system and on each respective channel in the set of channels of the memory system is less than or equal to the respective duration associated with performing a respective external transfer of a respective page for each memory array in the set of memory arrays of the memory system and on each respective channel in the set of channels of the memory system.

16. The apparatus of claim 1, wherein the set of memory arrays comprises a set of NAND (NAND) arrays, a set of dynamic random access memory (DRAM) arrays, or any combination thereof, and the set of channels comprises a set of Open NAND Flash Interface (ONFI) working group (ONFI) channels, a set of DRAM channels, a set of Compute Express Link (CXL) channels, or any combination thereof.

17. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: detecting one or more of voltage, current, or any combination thereof, Wherein determining the respective timing delay is based at least in part on one or more of the voltage, the current, or any combination thereof.

18. The apparatus of claim 1, wherein the corresponding command comprises an external transfer command and the corresponding data comprises a page.

19. A non-transitory computer-readable medium storing code, the code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving a respective command to process respective data for each memory array of a set of memory arrays of a memory system, each memory array being associated with a channel of a set of channels of the memory system; determining a respective timing delay based at least in part on a respective current value associated with each respective channel in the set of channels of the memory system to process the respective data for each memory array in the set of memory arrays of the memory system and on each respective channel; and The respective data is processed for each respective memory array and on each respective channel based at least in part on the respective timing delay associated with each respective channel.

20. A method for operating a memory system, comprising: receiving a respective command to process respective data for each memory array of a set of memory arrays of a memory system, each memory array being associated with a channel of a set of channels of the memory system; determining a respective timing delay based at least in part on a respective current value associated with each respective channel in the set of channels of the memory system to process the respective data for each memory array in the set of memory arrays of the memory system and on each respective channel; and The respective data is processed for each respective memory array and on each respective channel based at least in part on the respective timing delay associated with each respective channel.

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